Fault locating method, device, equipment and storage medium

Abstract

The present disclosure provides a fault positioning method, device, equipment and storage medium. The method comprises: selecting a first mapping circuit, writing preset data to a to-be-tested storage area in a storage module, and reading the to-be-tested storage area to obtain first read data; if the first read data is consistent with the preset data, selecting a second mapping circuit, reading the to-be-tested storage area to obtain second read data; if the second read data is consistent with the first read data, it indicates that the first mapping circuit and the second mapping circuit are fault-free; if the second read data is inconsistent with the first read data, it indicates that at least one of the first mapping circuit and the second mapping circuit is faulty. The present disclosure determines whether the storage unit and the data transmission path exist faults according to the consistency of read and write data; detects whether the address mapping circuit exists faults according to the consistency of read data under multiple mapping rules, and realizes the positioning of the fault position on the storage chip in the access system.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a fault location method, apparatus, device, and storage medium. Background Technology

[0002] After a memory chip is connected to a system, it is typically controlled by providing commands, addresses, and clock signals. These signals, addresses, and clock signals can be provided, for example, by a memory controller. Commands control the semiconductor memory chip to perform various operations; for example, a read command is used to read data from the memory chip, and a write command is used to write data to the memory chip.

[0003] The operation of such systems is typically very complex, and the system program cannot be modified. For example, the timing and time intervals for sending activation commands, write commands, precharge commands, and refresh commands are basically fixed after the memory chip is connected to the system. If a read / write fault is discovered after the memory chip is connected to the system, it is not easy to locate the instruction or location where the error occurred.

[0004] Therefore, how to locate the error in the system is a problem that needs to be solved. Summary of the Invention

[0005] This disclosure provides a fault location method, apparatus, device, and storage medium for locating the location of an error in a system.

[0006] In a first aspect, embodiments of this disclosure provide a fault location method applied to a storage system, the storage system including an address mapping module; the address mapping module is used to generate an internal address based on an external address, the internal address pointing to a storage area of ​​the storage module; the address mapping module includes a first mapping circuit and a second mapping circuit, the method including: selecting the first mapping circuit to write preset data into a storage area to be tested in the storage module, and reading the storage area to be tested to obtain first read data; if the first read data is consistent with the preset data, then selecting the second mapping circuit to read the storage area to be tested to obtain second read data; if the second read data is consistent with the first read data, it indicates that the first mapping circuit and the second mapping circuit are fault-free; if the second read data is inconsistent with the first read data, it indicates that at least one of the first mapping circuit and the second mapping circuit is faulty.

[0007] In some embodiments, the mapping rule of the first mapping circuit includes: external address bits and internal address bits are mapped in the same position.

[0008] In some embodiments, the mapping rules of the second mapping circuit include: performing out-of-bit mapping for at least two external address bits and at least two internal address bits; and performing in-bit mapping for other address bits in the external and internal addresses, excluding those that are out-of-bit mapped.

[0009] In some embodiments, the mapping rule of the second mapping circuit includes: forcibly setting any one or more internal address bits to a first logic level or a second logic level.

[0010] In some embodiments, after obtaining the first read data, the method further includes: selecting a first mapping circuit to perform multiple refreshes on the first storage row of the storage area, and not refreshing other storage rows in the storage area besides the first storage row; wherein the number of refreshes is greater than the number of refreshes required to cause the row hammer effect; reading the storage area to obtain third read data; determining whether a row hammer effect has occurred and the storage row in which the row hammer effect has occurred based on the first read data and the third read data; if there is no storage row in which the row hammer effect has occurred, then the refresh instruction is determined to be incorrect; if there is a storage row in which the row hammer effect has occurred, then the refresh instruction is determined to be correct; if the storage row in which the row hammer effect has occurred is adjacent to the word line of the first storage row, then the first mapping circuit is determined to be fault-free; if the storage row in which the row hammer effect has occurred is not adjacent to the word line of the first storage row, then the first mapping circuit is determined to be faulty.

[0011] In some embodiments, the storage system further includes an input / output module; the method further includes: if the first read data is empty, determining that the read instruction is incorrect, or that the input / output module is faulty; if the first read data is not empty, determining that the read instruction is correct, and that the input / output module is fault-free.

[0012] In some embodiments, the storage area includes word lines, bit lines, and storage capacitors; the method further includes: if the first read data is inconsistent with preset data, then a fault determination is made based on the distribution of faulty units; wherein, the faulty unit is a storage unit in which the first read data is inconsistent with the preset data; if all storage units corresponding to the same word line are faulty units, then the word line is determined to be faulty; otherwise, the word line is not faulty; if all storage units corresponding to the same bit line are faulty units, then the bit line is determined to be faulty; otherwise, the bit line is not faulty; if both the word line and the bit line corresponding to the faulty unit are not faulty, then the storage capacitor of the faulty unit is determined to be faulty.

[0013] Secondly, embodiments of this disclosure provide a fault location device applied to a storage system, the storage system including an address mapping module; the address mapping module is used to generate an internal address based on an external address, the internal address pointing to a storage area of ​​the storage module; the address mapping module includes a first mapping circuit and a second mapping circuit; the device includes: a first processing module, used to select the first mapping circuit, write preset data to a storage area to be tested in the storage module, and read the storage area to be tested to obtain first read data; a second processing module, used to select the second mapping circuit if the first read data is consistent with the preset data, and read the storage area to be tested to obtain second read data; a fault determination module, used to indicate that the first mapping circuit and the second mapping circuit are fault-free if the second read data is consistent with the first read data; the fault determination module is also used to indicate that at least one of the first mapping circuit and the second mapping circuit is faulty if the second read data is inconsistent with the first read data.

[0014] In some embodiments, the mapping rule of the first mapping circuit includes: external address bits and internal address bits are mapped in the same position.

[0015] In some embodiments, the mapping rules of the second mapping circuit include: performing out-of-bit mapping for at least two external address bits and at least two internal address bits; and performing in-bit mapping for other address bits in the external and internal addresses, excluding those that are out-of-bit mapped.

[0016] In some embodiments, the mapping rule of the second mapping circuit includes: forcibly setting any one or more internal address bits to a first logic level or a second logic level.

[0017] In some embodiments, after obtaining the first read data, the first processing module is further configured to select the first mapping circuit to perform multiple refreshes on the first storage row of the storage area, and not to perform refreshes on other storage rows in the storage area besides the first storage row; wherein, the number of refreshes is greater than the number of refreshes required to cause the row hammer effect; the first processing module is further configured to read the storage area to obtain the third read data; the fault determination module is further configured to determine whether the row hammer effect has occurred and the storage row in which the row hammer effect has occurred based on the first read data and the third read data; the fault determination module is further configured to determine that the refresh instruction is incorrect if there is no storage row in which the row hammer effect has occurred; and determine that the refresh instruction is correct if there is a storage row in which the row hammer effect has occurred; the fault determination module is further configured to determine that the first mapping circuit is fault-free if the storage row in which the row hammer effect has occurred is adjacent to the word line of the first storage row; and determine that the first mapping circuit is faulty if the storage row in which the row hammer effect has occurred is not adjacent to the word line of the first storage row.

[0018] In some embodiments, the storage system further includes an input / output module; a fault determination module is further configured to determine that the read instruction is incorrect or that the input / output module is faulty if the first read data is empty; the fault determination module is further configured to determine that the read instruction is correct and that the input / output module is fault-free if the first read data is not empty.

[0019] In some embodiments, the storage area includes word lines, bit lines, and storage capacitors; the fault determination module is further configured to determine a fault based on the distribution of faulty units if the first read data is inconsistent with preset data; wherein, the faulty unit is a storage unit in which the first read data is inconsistent with the preset data; the fault determination module is further configured to determine that the word line is faulty if all storage units corresponding to the same word line are faulty units; otherwise, the word line is not faulty; the fault determination module is further configured to determine that the bit line is faulty if all storage units corresponding to the same bit line are faulty units; otherwise, the bit line is not faulty; the fault determination module is further configured to determine that the storage capacitor of the faulty unit is faulty if both the word line and the bit line corresponding to the faulty unit are not faulty.

[0020] Thirdly, embodiments of this disclosure provide an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method as described in the first aspect.

[0021] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method as described in the first aspect.

[0022] Fifthly, this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the method of the first aspect.

[0023] The fault location method, apparatus, device, and storage medium disclosed herein are applied to a storage system, which includes an address mapping module. The address mapping module generates an internal address based on an external address, the internal address pointing to a storage area of ​​the storage module. The address mapping module includes a first mapping circuit and a second mapping circuit. The method includes: selecting the first mapping circuit to write preset data to a storage area under test in the storage module, and reading the storage area under test to obtain first read data; if the first read data matches the preset data, then selecting the second mapping circuit to read the storage area under test to obtain second read data; if the second read data matches the first read data, it indicates that the first and second mapping circuits are fault-free; if the second read data does not match the first read data, it indicates that at least one of the first and second mapping circuits is faulty. This disclosure determines whether a storage unit and data transmission path are faulty based on the consistency of read and write data; and detects whether an address mapping circuit is faulty based on the consistency of read data under multiple mapping rules, thereby achieving fault location on the storage chip in the access system. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0025] Figure 1 A flowchart of a fault location method provided in an embodiment of this disclosure;

[0026] Figure 2 This is a schematic diagram of the structure of an address mapping module provided in an embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram of a mapping rule provided in an embodiment of this disclosure;

[0028] Figure 4 This is a schematic diagram of another mapping rule provided in an embodiment of the present disclosure;

[0029] Figure 5 This is a schematic diagram illustrating another mapping rule provided in an embodiment of the present disclosure;

[0030] Figure 6 This is a schematic diagram of yet another mapping rule provided in an embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of the structure of a fault location device provided in an embodiment of the present disclosure;

[0032] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0033] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0035] After a memory chip is connected to a system, it is typically controlled by providing commands, addresses, and clock signals. These signals, addresses, and clock signals can be provided, for example, by a memory controller. Commands control the semiconductor memory chip to perform various operations; for example, a read command is used to read data from the memory chip, and a write command is used to write data to the memory chip.

[0036] The operation of such systems is typically very complex, and the system program cannot be modified. This can be understood as the timing and time intervals of commands sent by the storage controller, such as activation, write, precharge, and refresh commands, becoming essentially fixed after the storage chip is connected to the system. If a read / write fault is discovered after the storage chip is connected, it is difficult to pinpoint the instruction or location where the error occurred. Therefore, locating the source of the error in the system is a problem that needs to be solved.

[0037] The access process of a memory chip generally includes address resolution, data buffering, and data transfer. Address resolution refers to the process where, after a command is issued, the external address is transmitted to the address decoder via the command bus and address bus to obtain the bank address, row address, and column address, which are then used to locate the corresponding memory cell. Data buffering involves writing data from the row buffer to the memory cell or reading data from the memory cell into the row buffer. Data transfer involves transmitting data to the data port (DQ) via the data bus. Errors in either the data buffering process or the data transfer process can manifest as inconsistencies between the written data and the actual read data. However, inconsistencies between written and read data cannot effectively pinpoint address mapping errors in the address resolution process.

[0038] Specifically, both writing and reading data use the same address mapping rule. Under normal circumstances, an external address `a` will generate an internal address `a` pointing to memory cell `a`; and an external address `b` will generate an internal address `b` pointing to memory cell `b`. When a mapping error occurs, an internal address `b` pointing to memory cell `b` might also be generated based on external address `a`. Therefore, when reading or writing data using external address `a`, it is actually reading and writing data to memory cell `b`. Although the written and read data are identical, the corresponding memory cell is incorrect. Furthermore, when multiple external addresses correspond to the same memory cell, data loss and errors are likely to occur.

[0039] The fault location method, apparatus, device, and storage medium provided in this disclosure, after determining that the storage unit and data transmission path are fault-free based on the consistency of read and write data, detects whether there is a fault in the address mapping circuit based on the consistency of read data under multiple mapping rules, thereby realizing the location of the fault on the storage chip in the access system.

[0040] The technical solutions of this disclosure and how they solve the aforementioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0041] Example 1

[0042] Figure 1 This is a flowchart illustrating a fault location method provided in an embodiment of this disclosure. The method is applied to fault detection in a storage system. The executing entity can be a fault location device. This device can be implemented through a computer program, such as application software; or it can be implemented as a medium storing relevant computer programs, such as a USB flash drive or cloud storage; or it can be implemented through a physical device integrating or installing relevant computer programs, such as a computer. The following description uses a fault location device as the executing entity as an example.

[0043] The storage system includes an address mapping module; the address mapping module is used to generate an internal address based on an external address, and the internal address points to the storage area of ​​the storage module; the address mapping module includes a first mapping circuit and a second mapping circuit. Figure 2 This is a schematic diagram of the structure of an address mapping module provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, a control signal selects either a first mapping circuit or a second mapping circuit to convert the input external address into an internal address. The mapping rules for the first and second mapping circuits are different.

[0044] like Figure 1As shown, the method may include the following steps:

[0045] S100: Select the first mapping circuit, write preset data to the storage area to be tested in the storage module, and read the storage area to be tested to obtain the first read data;

[0046] S200. If the first read data is consistent with the preset data, then the second mapping circuit is selected to read the storage area to be tested and obtain the second read data.

[0047] S300. If the second read data is consistent with the first read data, it indicates that the first mapping circuit and the second mapping circuit are fault-free.

[0048] S400. If the second read data is inconsistent with the first read data, it indicates that at least one of the first mapping circuit and the second mapping circuit is faulty.

[0049] In step S100, the preset data is used for testing and is usually arranged according to certain rules to improve testing efficiency. Optionally, the preset data can be all 0s or all 1s. Data that flips during data reading indicates that the stored unit may be faulty, which helps improve testing efficiency. Optionally, the preset data can also be data containing both 0s and 1s arranged according to preset rules, such as 010101... arranged at intervals.

[0050] Optionally, the storage area to be tested can be a storage cell-level storage area, or a storage row-level storage area, or a storage array (mat)-level storage area, or a storage bank-level storage area, or a larger storage area.

[0051] Furthermore, in step S200, the consistency between the first read data and preset data is checked to determine whether the data transmission path and the accessed storage unit are faulty. If the first read data is consistent with the preset data, it can be determined that the data transmission path has transmitted the data correctly with a high probability, and that the accessed storage unit has stored the data correctly with a high probability. Otherwise, the data transmission path and the accessed storage unit may be faulty.

[0052] In some embodiments, there may be instances where two flips occur in the data transmission path, resulting in the final read and write data being identical, or where data storage errors occur in the storage unit, and the final read and write data are identical due to flips in the data transmission path. To avoid this extreme situation from causing errors in the test results, the accuracy of the test can be improved by increasing the number of tests, repeatedly writing and reading preset data to perform write and read consistency checks, and by using preset data with different arrangement rules to perform write and read consistency checks.

[0053] Furthermore, if it is determined that the transmission path and the accessed storage unit are essentially fault-free, the address mapping module is further checked for faults. As in the previous example, both writing and reading data use the same address mapping rule. Under normal circumstances, an internal address a pointing to storage unit a is generated based on the external address a. When a mapping error occurs, an internal address b pointing to storage unit b is generated based on the external address a. Therefore, when reading or writing is performed using the external address a, it is actually reading and writing to storage unit b. Although the written and read data are consistent, the corresponding storage unit is incorrect. Therefore, in step S200, the control signals in the address mapping module are adjusted to select the second mapping circuit to convert the external address to an internal address.

[0054] Specifically, the external address used to generate the internal address 'a' will differ depending on the mapping rule. Under normal circumstances, to generate the internal address 'a' based on the first mapping circuit, an external address 'a' needs to be provided to the first mapping circuit; to generate the internal address 'a' based on the second mapping circuit, an external address 'b' needs to be provided to the second mapping circuit. If the data read based on the second mapping circuit and external address 'b' is consistent with the data read based on the first mapping circuit and external address 'a', it indicates that both mapping circuits have a high probability of generating the same internal address 'a', and therefore both mapping circuits are functioning correctly. Conversely, if the data read based on the second mapping circuit and external address 'b' is inconsistent with the data read based on the first mapping circuit and external address 'a', it indicates that the two mapping circuits have not generated the same internal address, meaning one or both mapping circuits have a mapping error.

[0055] There's a possibility that two mapping circuits might have the same data in their corresponding memory cells under incorrect mapping as they do under correct mapping, resulting in identical read and write data. Specifically, this can be mitigated by increasing the number of tests, using multiple sets of different external addresses for each mapping circuit. This reduces the probability of identical internal addresses or identical data in the corresponding memory cells due to both external addresses being incorrect. Furthermore, repeated mapping detection can be performed by writing preset data with different arrangement patterns. Different arrangement patterns refer to data at different memory locations having different characteristics; for example, data between different banks may have different arrangement characteristics, and / or data between different sections may have different arrangement characteristics. This ensures that in the case of incorrect mapping, if the internal address is different, the data in the corresponding memory cell will differ significantly. It's understandable that the difficulty of identifying errors caused by different arrangement patterns under the same mapping rule varies. Therefore, the aforementioned arrangement pattern can be set based on the first and second mapping rules.

[0056] In this embodiment, after determining that the storage unit and data transmission path are fault-free based on the consistency of read and write data, the address mapping circuit is checked for mapping errors based on the consistency of read data under various mapping rules, thus conducting a more comprehensive fault diagnosis of the storage chip in the access system.

[0057] Figure 3 This is a schematic diagram of a mapping rule provided in an embodiment of this disclosure. For example... Figure 3 As shown, the mapping rule of the first mapping circuit includes: external address bits and internal address bits are mapped to each other. For example, both the external address and the internal address are composed of multiple digits, where the first bit of the external address corresponds to the first bit of the internal address; the second bit of the external address corresponds to the second bit of the internal address, and so on.

[0058] In some embodiments, the mapping rules of the second mapping circuit include: at least two external address bits are mapped to at least two internal address bits in a different position; and the other address bits in the external and internal addresses, except for those mapped in a different position, are mapped in the same position. Figure 4 This is a schematic diagram illustrating another mapping rule provided for an embodiment of this disclosure. For example... Figure 4 As shown, the example illustrates the swapping and mapping of internal address bits corresponding to two sets of external address bits. Here, ExAdr[n] represents the nth bit of the external address, and similarly, InAdr[n] represents the nth bit of the internal address.

[0059] Specifically, the nth bit of the external address (Ex Adr[n]) and the (n+m)th bit of the external address (Ex Adr[n+m]) were swapped and mapped out of order. For example... Figure 4 As shown, Ex Adr[n] is mapped to In Adr[n+m], and Ex Adr[n+m] is mapped to In Adr[n]. Similarly, the (n+1)th bit of the external address (Ex Adr[n+1]) and the (n+m+1)th bit of the external address (Ex Adr[n+m+1]) are mapped separately. Figure 4 As shown, Ex Adr[n+1] is mapped to In Adr[n+m+1], and Ex Adr[n+m+1] is mapped to In Adr[n+1]. In this embodiment, the external address bits of the swapped out-of-place mapping can be a single set, or three or more sets.

[0060] Understandably, in Figure 4 In the illustrated embodiment, at least two external addresses are considered as a group. The second mapping circuit performs out-of-place mapping on different groups of external addresses. The address that comes first in the same group of external addresses remains the first address after out-of-place mapping, which is called out-of-group mapping. For example, Ex Adr[n] comes first compared to Ex Adr[n+1]. After out-of-place mapping, the corresponding internal address In Adr[n+m] still comes first compared to In Adr[n+m+1]. In other embodiments, at least two external addresses can also be considered as a group, and each group of external addresses can be internally out-of-place mapped, which is called intra-group mapping. For example, external address Ex Adr[n] is mapped to internal address In Adr[n+1], or external address Ex Adr[n+1] is mapped to internal address In Adr[n]. Similarly, external address Ex Adr[n+m] is mapped to internal address In Adr[n+m+1], or external address Ex Adr[n+m+1] is mapped to internal address In Adr[n]. Adr[n+m], thus, the same set of external addresses, the address before the internal address, becomes the address after the external address after the external address mapping.

[0061] It is understandable that the two mapping methods mentioned above (intergroup mapping and intragroup mapping) can also be combined. For example, at least two external addresses can be considered as a group, and the second mapping circuit can perform inter-group mapping on external addresses in different groups. While mapping different groups, it can also perform intra-group inter-group mapping within the same group. In this way, external address Ex Adr[n] can be mapped to internal address In Adr[n+m+1], for example, external address Ex Adr[n+1] can be mapped to internal address In Adr[n+m]. Similarly, external address Ex Adr[n+m] can be mapped to internal address In Adr[n+1], for example, external address Ex Adr[n+m+1] can be mapped to internal address In Adr[n].

[0062] In other embodiments, the mapping rule of the second mapping circuit may also be: an external address and an internal address bit are mapped out of position, and other external addresses and other internal addresses are mapped in the same position.

[0063] Figure 5 This is a schematic diagram illustrating another mapping rule provided in an embodiment of this disclosure. For example... Figure 5 As shown, this example illustrates how each external address bit is shifted by one bit in its own position and mapped to an internal address bit. Specifically, taking a downward shift of one bit as an example, Ex Adr[0] is mapped to In Adr[1], Ex Adr[1] is mapped to In Adr[2], and so on, with Ex Adr[n-1] mapped to In Adr[n] and Ex Adr[n] mapped to In Adr[0]. In this embodiment, the number of bits shifted sequentially can also be two, three, or more bits.

[0064] In addition, in this embodiment, the direction of movement can be forward. Taking moving one position upward as an example, Ex Adr[0] maps to In Adr[n], Ex Adr[1] maps to In Adr[0], and so on, with Ex Adr[n] mapping to In Adr[n-1]. It is easy to understand that moving one position forward has the same effect as moving n-1 positions backward.

[0065] In addition, when each group of external addresses in the intra-group mapping contains at least three external addresses, the intra-group mapping rule can also be adjusted from swap mapping to shift mapping. That is, each external address bit is shifted by one bit in its own bit position, or the shift is performed in groups, with each group containing at least two external addresses. In this case, each time the number of external addresses contained in each group is shifted up or down, the first address in the group remains the first address after the shift mapping.

[0066] Using the above Figure 4 or Figure 5 After misalignment mapping, to generate the target internal address, the external address needs to be changed. Optionally, during implementation, a target internal address is first determined, and a first external address is derived based on the same-position mapping relationship in the first mapping circuit, and a second external address is derived based on the misalignment mapping relationship in the second mapping circuit. First read data is obtained by providing the first external address to the first mapping circuit; second read data is obtained by providing the second external address to the second mapping circuit.

[0067] The detection results fall into three categories: (1) If the first read data is consistent with the preset data written, and the first read data is consistent with the second read data, it indicates that both mapping circuits have generated the target internal address with a high probability. Therefore, both mapping circuits are fault-free and the transmission path and storage unit are normal. (2) If the first read data is consistent with the preset data written, but the first read data is inconsistent with the second read data, it indicates that at least one of the two mapping circuits has not generated the target internal address. Correspondingly, it indicates that one of the two mapping circuits has a mapping error, or both have mapping errors. (3) If the first read data is inconsistent with the preset data written, but the first read data is consistent with the second read data, it is highly likely that there is a storage unit failure and a data transmission failure. It is also possible that the two mapping circuits generated the same internal address but not the target internal address. Based on this, it can be inferred that both mapping circuits have made mapping errors and have incorrectly mapped to the same internal address.

[0068] When a mapping circuit has a mapping fault, multiple external addresses may actually access the same memory cell, and some memory cells may not be accessible. This embodiment improves the probability of each memory cell in the memory area being accessed by selecting different mapping circuits, thereby making it easier to find faulty memory cells.

[0069] Furthermore, if the first read data is consistent with the written data, the distribution pattern of the inconsistent data between the first and second read data can be used to further determine the address bit where the mapping fault occurred, thus narrowing down the scope of troubleshooting. For example, if the second address bit of the internal address corresponding to the memory cell where the two read data are inconsistent is the same (both are 1), it can be understood that when the second bit of the internal address is 1, the two read data are inconsistent, indicating that one of the address mapping circuits cannot generate an accurate second internal address bit.

[0070] In some embodiments, the storage area to be tested can be divided into multiple parts, and faults can be checked one by one to continuously narrow down the scope of fault investigation and help locate the fault location.

[0071] Combination Figure 4 and Figure 5 As can be seen, the commonality between the above-mentioned heterogeneous mapping method and the homogeneous mapping method lies in the fact that each external address bit and each internal address bit are in a one-to-one correspondence. Under normal, fault-free conditions, each memory cell on the memory chip can be accessed by changing the external address.

[0072] It should be noted that the mapping rules for the first mapping circuit and the second mapping circuit in this embodiment need to be different. Considering that the mapping circuits corresponding to the same mapping rules are the same, the probability of the same fault occurring is relatively high. Therefore, the effect of troubleshooting is not good when comparing read data.

[0073] This embodiment does not limit the specific mapping rules for the first and second mapping circuits. Optional combinations include the first mapping circuit using same-position mapping and the second mapping circuit using different-position mapping; or, the second mapping circuit using same-position mapping and the first mapping circuit using different-position mapping. Further, different-position mapping includes swapping different-position mapping (e.g.,...). Figure 4 (as shown) and shift mapping (such as) Figure 5 As shown), therefore, the possible combinations include the first mapping circuit using exchange-based out-of-position mapping and the second mapping circuit using shift-based out-of-position mapping; or, the second mapping circuit using exchange-based out-of-position mapping and the first mapping circuit using shift-based out-of-position mapping.

[0074] In some embodiments, the swapped out-of-bit mapping further includes multiple swapping forms. On the one hand, it may include swapping one or more groups of external address bits; on the other hand, it may include swapping two bits as a group, swapping three bits as a group, and so on. Therefore, optionally, the two mapping circuits can be swapped out-of-bit mappings using different swapping forms. In some embodiments, the shifted out-of-bit mapping further includes multiple shifting forms, such as shifting backward by one or more bits, or shifting forward by one or more bits. Therefore, optionally, the two mapping circuits can be shifted out-of-bit mappings using different shifting forms.

[0075] In some embodiments, the mapping rule of the second mapping circuit includes: forcibly setting any one or more internal address bits to a first logic level or a second logic level. Figure 6 This is a schematic diagram illustrating yet another mapping rule provided in an embodiment of this disclosure. For example... Figure 6 As shown, taking the example of forcibly setting the (n-1)th bit of the internal address to a high level (Vcc) and the nth bit of the internal address to a low level (Vss), all external address bits except the forcibly set address bits are mapped to the internal address bits. Assume that eight memory arrays are represented by three binary digits: 000, 001, 010, 011, 100, 101, 110, and 111. If three address bits are forcibly set, only one memory array can be accessed; if two address bits are forcibly set, two memory arrays can be accessed; and if one address bit is forcibly set, four memory arrays can be accessed. In this embodiment, the address bit forcibly set to a fixed logic level can be one or more bits, without limitation.

[0076] Specifically, the memory area accessible by the second mapping circuit is referred to as the first region. The data corresponding to the first region in the first read data is compared with the second read data. If they match, it indicates that the two mapping circuits are functioning correctly; if they do not match, a similarity comparison can be performed between the second read data and the first read data. If there is data in the first read data that matches the second read data, but the corresponding region is not the first region, it indicates that the first mapping rule is incorrect in mapping the external address corresponding to the forced internal address.

[0077] In some embodiments, after obtaining the first read data in step S100, the method further includes:

[0078] S110. Select the first mapping circuit to perform multiple refreshes on the first storage row of the storage area, and do not perform refreshes on other storage rows in the storage area other than the first storage row; wherein, the number of refreshes is greater than the number of refreshes required to cause the row hammer effect.

[0079] S120: Read the storage area to obtain the third read data;

[0080] S130. Based on the first read data and the third read data, determine whether a row hammer effect has occurred and the storage row in which the row hammer effect has occurred;

[0081] S140. If there is no storage row where a row hammer effect occurs, the refresh instruction is determined to be incorrect; if there is a storage row where a row hammer effect occurs, the refresh instruction is determined to be correct.

[0082] S150. If the storage row where the row hammer effect occurs is adjacent to the word line of the first storage row, then the first mapping circuit is determined to be fault-free.

[0083] S160. If the storage row where the row hammer effect occurs is not adjacent to the word line of the first storage row, then the first mapping circuit is determined to be faulty.

[0084] Specifically, in step S100, in one feasible implementation, the first mapping circuit uses same-position mapping or different-position mapping, and achieves multiple refreshes of only the first storage row by repeatedly sending the same external address to the first mapping circuit. In another feasible implementation, the second mapping circuit is configured to force the internal address to the mapping rule of the first storage row, and achieves multiple refreshes of the first storage row by continuously sending multiple external addresses to the second mapping circuit. Since the internal address is forced to point to the first storage row, the external addresses sent multiple times do not need to be the same external address.

[0085] It should be noted that the row hammer effect refers to the phenomenon where, in a given bank, repeatedly activating a given storage row can cause the values ​​of certain bits in physically adjacent rows to be reversed. This embodiment simulates the row hammer effect in the first storage row, and then obtains the third read data, including three detection results such as steps S140, S150, and S160. Under normal, fault-free conditions, the row hammer effect will occur in storage rows adjacent to the word lines of the first storage row.

[0086] Specifically, in step S140, if no row hammer effect occurs in the memory row, the refresh instruction may be incorrect, resulting in no refresh of the first memory row; or the external address may be lost, causing some refresh instructions not to be executed, and the refresh count is too low to cause a row hammer effect. If a row hammer effect occurs, it is further determined whether the memory row experiencing the row hammer effect is adjacent to the word line of the first memory row. If they are adjacent, it indicates that the first memory row can be accessed according to the external address, and the first mapping circuit is not faulty. If they are not adjacent, it indicates that the memory row accessed according to the external address is not the first memory row, a mapping error has occurred, i.e., the first mapping circuit is faulty.

[0087] Furthermore, after step S160, the address bit where the mapping error occurred can be determined based on the difference between the internal address of the storage row where the row hammer effect occurred and the internal address of the first storage row, which helps to narrow down the scope of troubleshooting.

[0088] In some embodiments, the storage system further includes an input / output module; the fault location method provided in this embodiment further includes: if the first read data is empty, then it is determined that the read instruction is incorrect, or that the input / output module is faulty; if the first read data is not empty, then it is determined that the read instruction is correct, and that the input / output module is fault-free.

[0089] Specifically, when there are timing problems with the read instruction and clock, or timing problems with the read instruction and address resolution, the first data read may fail, which is reflected in the data output port (DQ) being empty; circuit failures such as a break in the data transmission path may also cause the first data read to be empty.

[0090] Furthermore, if the first read data is not empty, it proves that the read command was correct and that the data transmission path is not broken, allowing data transmission to proceed. Additionally, data typically needs to travel a data transmission path after being read from the memory bank before being output to the data port. Voltage loss along the data transmission path can degrade data quality, potentially causing data output to flip. Further comparison of the first read data with the pre-written preset data confirms that the data transmission path is functioning correctly.

[0091] In some embodiments, the location of the fault can be further determined based on the distribution pattern of the inconsistent first read data and written data. Specifically, the memory cell where the first read data is inconsistent with the preset data is referred to as the fault cell. Fault determination is performed based on the distribution of the fault cells; if all memory cells corresponding to the same word line are fault cells, the word line is determined to be faulty; otherwise, the word line is not faulty; if all memory cells corresponding to the same bit line are faulty, the bit line is determined to be faulty; otherwise, the bit line is not faulty; if both the word line and the bit line corresponding to the fault cell are not faulty, the memory capacitor of the fault cell is determined to be faulty.

[0092] The fault location method, apparatus, device, and storage medium disclosed herein are applied to a storage system, which includes an address mapping module. The address mapping module generates an internal address based on an external address, the internal address pointing to a storage area of ​​the storage module. The address mapping module includes a first mapping circuit and a second mapping circuit. The method includes: selecting the first mapping circuit to write preset data to a storage area under test in the storage module, and reading the storage area under test to obtain first read data; if the first read data matches the preset data, then selecting the second mapping circuit to read the storage area under test to obtain second read data; if the second read data matches the first read data, it indicates that the first and second mapping circuits are fault-free; if the second read data does not match the first read data, it indicates that at least one of the first and second mapping circuits is faulty. This disclosure determines whether a storage unit and data transmission path are faulty based on the consistency of read and write data; and detects whether an address mapping circuit is faulty based on the consistency of read data under multiple mapping rules, thereby achieving fault location on the storage chip in the access system.

[0093] The following describes the apparatus, electronic device, and computer-readable storage medium corresponding to the fault location method provided in the embodiments of this disclosure. The effects can be referred to the foregoing description of the fault location method.

[0094] Figure 7 This disclosure provides a schematic diagram of a fault location device according to an embodiment. Applied to a storage system, the storage system includes an address mapping module; the address mapping module generates an internal address based on an external address, the internal address pointing to a storage area of ​​the storage module; the address mapping module includes a first mapping circuit and a second mapping circuit; as shown... Figure 7As shown, the device includes: a first processing module 10, used to select a first mapping circuit to write preset data to the storage area to be tested in the storage module, and read the storage area to be tested to obtain first read data; a second processing module 20, used to select a second mapping circuit to read the storage area to be tested to obtain second read data if the first read data is consistent with the preset data; a fault determination module 30, used to indicate that the first mapping circuit and the second mapping circuit are fault-free if the second read data is consistent with the first read data; the fault determination module 30 is also used to indicate that at least one of the first mapping circuit and the second mapping circuit is faulty if the second read data is inconsistent with the first read data.

[0095] In some embodiments, the mapping rule of the first mapping circuit includes: external address bits and internal address bits are mapped in the same position.

[0096] In some embodiments, the mapping rules of the second mapping circuit include: performing out-of-bit mapping for at least two external address bits and at least two internal address bits; and performing in-bit mapping for other address bits in the external and internal addresses, excluding those that are out-of-bit mapped.

[0097] In some embodiments, the mapping rule of the second mapping circuit includes: forcibly setting any one or more internal address bits to a first logic level or a second logic level.

[0098] In some embodiments, after obtaining the first read data, the first processing module 10 is further configured to select the first mapping circuit to perform multiple refreshes on the first storage row of the storage area, and not to perform refreshes on other storage rows of the storage area besides the first storage row; wherein, the number of refreshes is greater than the number of refreshes required to cause the row hammer effect; the first processing module 10 is further configured to read the storage area to obtain the third read data; the fault determination module 30 is further configured to determine whether the row hammer effect has occurred and the storage row in which the row hammer effect has occurred based on the first read data and the third read data; the fault determination module 30 is further configured to determine that the refresh instruction is incorrect if there is no storage row in which the row hammer effect has occurred; and determine that the refresh instruction is correct if there is a storage row in which the row hammer effect has occurred; the fault determination module 30 is further configured to determine that the first mapping circuit is fault-free if the storage row in which the row hammer effect has occurred is adjacent to the word line of the first storage row; and determine that the first mapping circuit is faulty if the storage row in which the row hammer effect has occurred is not adjacent to the word line of the first storage row.

[0099] In some embodiments, the storage system further includes an input / output module; the fault determination module 30 is further configured to determine that the read instruction is incorrect or that the input / output module is faulty if the first read data is empty; the fault determination module 30 is further configured to determine that the read instruction is correct and that the input / output module is fault-free if the first read data is not empty.

[0100] In some embodiments, the storage area includes word lines, bit lines, and storage capacitors; the fault determination module 30 is further configured to determine a fault based on the distribution of faulty units if the first read data is inconsistent with preset data; wherein, the faulty unit is a storage unit in which the first read data is inconsistent with the preset data; the fault determination module 30 is further configured to determine that the word line is faulty if all storage units corresponding to the same word line are faulty units; otherwise, the word line is not faulty; the fault determination module 30 is further configured to determine that the bit line is faulty if all storage units corresponding to the same bit line are faulty units; otherwise, the bit line is not faulty; the fault determination module 30 is further configured to determine that the storage capacitor of the faulty unit is faulty if both the word line and the bit line corresponding to the faulty unit are not faulty.

[0101] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure, such as... Figure 8 As shown, the electronic device includes:

[0102] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke logical instructions stored in the memory 292 to execute the methods provided in the foregoing embodiments.

[0103] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0104] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, thereby implementing the methods in the above-described method embodiments.

[0105] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory.

[0106] This disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided in the foregoing embodiments.

[0107] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0108] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A fault location method, applied to a storage system, characterized in that, The storage system includes an address mapping module; the address mapping module is used to generate an internal address based on an external address, the internal address pointing to the storage area of ​​the storage module; the address mapping module includes a first mapping circuit and a second mapping circuit; The mapping rules of the first mapping circuit and the second mapping circuit are different; The method includes: The first mapping circuit is selected to write preset data into the storage area to be tested in the storage module and read the storage area to be tested to obtain the first read data. If the first read data is consistent with the preset data, then the second mapping circuit is selected to read the storage area to be tested and obtain the second read data; If the second read data is consistent with the first read data, it indicates that the first mapping circuit and the second mapping circuit are fault-free; if the second read data is inconsistent with the first read data, it indicates that at least one of the first mapping circuit and the second mapping circuit is faulty.

2. The fault location method according to claim 1, characterized in that, The mapping rule of the first mapping circuit includes: the external address bits and the internal address bits are mapped in the same position.

3. The fault location method according to claim 2, characterized in that, The mapping rules of the second mapping circuit include: performing out-of-position mapping between at least two external address bits and at least two internal address bits; and performing in-position mapping between the external address bits and the internal address bits other than those performing out-of-position mapping.

4. The fault location method according to claim 2, characterized in that, The mapping rules of the second mapping circuit include: forcibly setting any one or more internal address bits to the first logic level or the second logic level.

5. The fault location method according to claim 1, characterized in that, After obtaining the first read data, the process also includes: The first mapping circuit is selected to perform multiple refreshes on the first storage row of the storage area, while no refreshes are performed on other storage rows of the storage area besides the first storage row; wherein the number of refreshes is greater than the number of refreshes required to cause the row hammer effect. Read the storage area to obtain the third read data; Based on the first read data and the third read data, determine whether a row hammer effect has occurred and the storage row in which the row hammer effect has occurred; If no row hammer effect occurs, the refresh instruction is determined to be incorrect; if a row hammer effect occurs, the refresh instruction is determined to be correct; if the row hammer effect occurs adjacent to the word line of the first row, the first mapping circuit is determined to be fault-free; if the row hammer effect occurs not adjacent to the word line of the first row, the first mapping circuit is determined to be faulty.

6. The fault location method according to claim 1, characterized in that, The storage system further includes an input / output module; the method further includes: If the first read data is empty, then the read instruction is determined to be incorrect, or the input / output module is faulty; If the first read data is not empty, then the read instruction is correct, and the input / output module is fault-free.

7. The fault location method according to claim 1, characterized in that, The storage area includes word lines, bit lines, and storage capacitors; The method further includes: If the first read data is inconsistent with the preset data, a fault determination is made based on the distribution of the fault units; wherein, the fault unit is a storage unit where the first read data is inconsistent with the preset data; If all memory cells corresponding to the same word line are the erroneous cells, then the word line is determined to be faulty; otherwise, the word line is not faulty. If all memory cells corresponding to the same bit line are the faulty cells, then the bit line is determined to be faulty; otherwise, the bit line is not faulty. If the word line and bit line corresponding to the faulty unit are both fault-free, then the storage capacitor of the faulty unit is determined to be faulty.

8. A fault location device, applied to a storage system, characterized in that, The storage system includes an address mapping module; the address mapping module is used to generate an internal address based on an external address, the internal address pointing to the storage area of ​​the storage module; the address mapping module includes a first mapping circuit and a second mapping circuit; The mapping rules of the first mapping circuit and the second mapping circuit are different; The device includes: The first processing module is used to select the first mapping circuit, write preset data into the storage area to be tested in the storage module, and read the storage area to be tested to obtain the first read data. The second processing module is used to select the second mapping circuit to read the storage area to be tested and obtain the second read data if the first read data is consistent with the preset data. The fault determination module is used to indicate that the first mapping circuit and the second mapping circuit are fault-free if the second read data is consistent with the first read data. The fault determination module is further configured to indicate that at least one of the first mapping circuit and the second mapping circuit is faulty if the second read data is inconsistent with the first read data.

9. The fault location device according to claim 8, characterized in that, The mapping rule of the first mapping circuit includes: the external address bits and the internal address bits are mapped in the same position.

10. The fault location device according to claim 9, characterized in that, The mapping rules of the second mapping circuit include: performing out-of-position mapping between at least two external address bits and at least two internal address bits; and performing in-position mapping between the external address bits and the internal address bits other than those performing out-of-position mapping.

11. The fault location device according to claim 9, characterized in that, The mapping rules of the second mapping circuit include: forcibly setting any one or more internal address bits to the first logic level or the second logic level.

12. The fault location device according to claim 8, characterized in that, After obtaining the first read data, the first processing module is further configured to select the first mapping circuit to perform multiple refreshes on the first storage row of the storage area, and not to perform refreshes on other storage rows of the storage area other than the first storage row; wherein, the number of refreshes is greater than the number of refreshes required to cause the row hammer effect; The first processing module is further configured to read the storage area to obtain third read data; The fault determination module is further configured to determine whether a row hammer effect has occurred and the storage row in which the row hammer effect has occurred based on the first read data and the third read data. The fault determination module is further configured to determine that the refresh instruction is incorrect if there is no storage row with a row hammer effect, and to determine that the refresh instruction is correct if there is a storage row with a row hammer effect. The fault determination module is further configured to determine that the first mapping circuit is fault-free if the storage row in which the row hammer effect occurs is adjacent to the word line of the first storage row. The fault determination module is further configured to determine that the first mapping circuit is faulty if the storage row in which the row hammer effect occurs is not adjacent to the word line of the first storage row.

13. The fault location device according to claim 8, characterized in that, The storage system also includes an input / output module; The fault determination module is also used to determine that if the first read data is empty, the read instruction is incorrect, or the input / output module is faulty. The fault determination module is further configured to determine that the read instruction is correct and that the input / output module is fault-free if the first read data is not empty.

14. The fault location device according to claim 8, characterized in that, The storage area includes word lines, bit lines, and storage capacitors; The fault determination module is further configured to determine a fault based on the distribution of error units if the first read data is inconsistent with the preset data; wherein, the error unit is a storage unit in which the first read data is inconsistent with the preset data. The fault determination module is further configured to determine that the word line is faulty if all the memory cells corresponding to the same word line are the faulty cells; otherwise, the word line is not faulty. The fault determination module is further configured to determine that the bit line is faulty if all the memory cells corresponding to the same bit line are the faulty cells; otherwise, the bit line is not faulty. The fault determination module is further configured to determine that the storage capacitor of the fault unit is faulty if there are no faults in the word line and bit line corresponding to the fault unit.

15. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-7.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-7.

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