High speed peripheral component interconnect device and method of operation thereof

Abstract

The present invention relates to a method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port, the method comprising: performing a first link training operation to link a first host with a first link of the first port; operating in a single-port mode when the first link training operation is completed; performing a lane reduction operation to reduce lanes corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link a second host with a second link of the second port when a state of the first link is an L0 state.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0067690, filed with the Korean Intellectual Property Office on May 26, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to an electronic device, and more particularly, to a high-speed peripheral component interconnect (PCIe) device and a method of operating thereof. Background Technology

[0004] High-speed peripheral component interconnect (PCIe) refers to an interface with serial configuration for data communication. PCIe-based storage devices can support multiple ports and multiple functions. PCIe-based storage devices can be virtualized or non-virtualized and implement Quality of Service (QoS) for host I / O commands through at least one PCIe function.

[0005] Storage devices can store data under the control of host devices such as computers or smartphones. Storage devices may include memory devices for storing data and memory controllers for controlling the memory devices. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0006] Volatile memory devices retain data as long as there is power, but may lose stored data if there is no power. Types of volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0007] Non-volatile memory devices do not lose data even when there is no power supply. Types of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0008] Various embodiments of this disclosure relate to a method of operating an improved PCIe device by changing the port mode.

[0009] According to an embodiment, a high-speed peripheral component interconnect (PCIe) device may include: a first port, connected to a first host via a first link; a second port, connected to a first host or a second host via a second link; and a port mode controller, controlling the first port and the second port to change the operating mode from a dual-port mode in which the first port and the second port operate independently of each other to a single-port mode in which only the first port operates, wherein the port mode controller controls the second port to reset the second link while the first link is connected.

[0010] According to an embodiment, a high-speed peripheral component interconnect (PCIe) device may include: a first port, connected to a first host via a first link; a second port, connected to either the first host or a second host via a second link; and a port mode controller, controlling the first port and the second port to change the operating mode from a single-port mode where only the first port operates to a dual-port mode where the first port and the second port operate independently of each other, wherein the port mode controller controls the second port to perform a link training operation to connect the second link while the first link is connected.

[0011] According to an embodiment, a method of operating a high-speed peripheral component interconnect (PCIe) device including a first port and a second port may include: performing a first link training operation to link a first host to a first link of the first port; operating in single-port mode when the first link training operation is completed; performing a channel reduction operation to reduce the number of channels corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link a second host to a second link of the second port when the state of the first link is L0.

[0012] According to an embodiment, a method of operating a high-speed peripheral component interconnect (PCIe) device including a first port and a second port may include: performing a first link training operation to link a first host to a first link of the first port, and performing a second link training operation to link a second host to a second link of the second port; operating in a dual-port mode where the first link and the second link operate independently of each other when the first link training operation and the second link training operation are completed; deactivating the second link in response to a mode change request received from the first host or the second host; and performing a channel addition operation to add a channel corresponding to the first link when the deactivation of the second link is completed. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating a PCIe computing system according to an embodiment of the present disclosure.

[0014] Figure 2 This is a diagram illustrating a PCIe device according to an embodiment of the present disclosure.

[0015] Figure 3 This is a diagram illustrating a PCIe interface according to an embodiment of the present disclosure.

[0016] Figure 4 This is a diagram illustrating a transmitter, receiver, and channel according to an embodiment of the present disclosure.

[0017] Figure 5 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0018] Figure 6 This is a diagram illustrating the link status of a PCIe device according to an embodiment of the present disclosure.

[0019] Figure 7 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0020] Figure 8 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0021] Figure 9 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0022] Figure 10 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0023] Figure 11 This is a diagram illustrating the configuration of a PCIe device according to an embodiment of the present disclosure.

[0024] Figure 12 This is a diagram illustrating a method for changing a PCIe device from single-port mode to dual-port mode according to an embodiment of the present disclosure.

[0025] Figure 13 This is a diagram illustrating a method for changing a PCIe device from a dual-port mode to a single-port mode according to an embodiment of the present disclosure. Detailed Implementation

[0026] The specific structural or functional descriptions of examples of embodiments of the concept disclosed in this specification are for illustrative purposes only. Examples of embodiments of the concept may be implemented in various forms; however, the description is not limited to the examples of the embodiments described in this specification.

[0027] Various modifications and changes can be applied to the example embodiments based on this concept, thus providing examples of embodiments shown in the accompanying drawings and described in the specification. However, embodiments based on the concept of this disclosure are not to be construed as limited to the specific disclosure, but rather include all changes, equivalents, or alternatives without departing from the spirit and scope of this disclosure. In describing those embodiments, descriptions of techniques well-known in the art to which this disclosure pertains and not directly related to this disclosure will be omitted. This is intended to more clearly disclose the spirit of this disclosure by omitting unnecessary descriptions.

[0028] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a diagram illustrating a PCIe computing system according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The PCIe computing system 100 may include a central processing unit (CPU) 110, a root complex 120, a memory 130, a switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and a PCIe to PCI / PCI-X bridge 170.

[0031] PCIe computing system 100 can be an electronic device that supports communication using a PCIe interface. PCIe computing system 100 can be a personal computer (PC), a laptop computer, or a mobile computing device. PCIe computing system 100 may include expansion cards, expansion boards, adapter cards, insert cards, or accessory cards. Additionally, PCIe computing system 100 may include a printed circuit board (PCB) that inserts into an electrical connector or expansion slot on the motherboard of PCIe computing system 100 to provide additional functionality to PCIe computing system 100 via an expansion bus. Furthermore, PCIe computing system 100 may include storage devices such as solid-state drives (SSDs) and may include graphics cards, network cards, or USB cards.

[0032] The CPU 110 can be electrically connected to each component of the PCIe computing system 100 and can control various operations of the PCIe computing system 100. More specifically, the CPU 110 can drive an operating system or application to control the hardware or software components connected to the CPU 110 and can perform various types of data processing and operations. In addition, the CPU 110 can execute software or applications for controlling the operation of the PCIe computing system 100.

[0033] Root union 120 can be a root hub, controller hub, or root controller in a PCIe interconnect architecture. For example, root union 120 may include a chipset, memory controller hub (MCH), northbridge, interconnect controller hub (ICH), southbridge, and root controller / hub. Additionally, root union 120 can connect CPU 110 and memory 130 to the I / O hierarchy. Root union 120 can support peer-to-peer (P2P) routing. Root union 120 may include at least one master bridge and root port. Root union 120 can support at least one PCIe port.

[0034] The memory 130 can store data, commands, or program code required for the operation of the PCIe computing system 100. According to an embodiment, the memory 130 can store program code operable to run one or more operating systems (OS) and virtual machines (VMs), as well as program code running a virtualization intermediary (VI) for managing the virtual machines (VMs). Alternatively, the memory 130 can be implemented as a volatile memory device such as DRAM or SRAM.

[0035] Switch 140 can route packets or messages upstream or downstream. More specifically, switch 140 can route packets or messages upwards along the hierarchy from a PCIe endpoint (e.g., 150_1) to root union 120. Alternatively, switch 140 can route packets or messages downwards along the hierarchy from root union 120 to a PCIe endpoint (e.g., 150_2).

[0036] Switch 140 may be referred to as a logical component of multiple virtual PCI-to-PCI bridge devices. Examples of devices connected to switch 140 may include any internal or external devices or components to be connected to an electronic system, such as I / O devices, network interface controllers (NICs), plug-in cards, audio processors, network processors, hard disk drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, FireWire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices.

[0037] Each of PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can act as a requester or completer of a PCIe transaction. Transaction Layer Packets (TLPs) sent or received by PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 may provide a configuration space header. Additionally, each of PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 may provide a configuration request as a completer. Under certain conditions, Transaction Layer Packets (TLPs) sent or received by PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 must provide a configuration space header. Furthermore, each of PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 must provide a configuration request as a completer.

[0038] PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can be classified according to the possible size of memory transactions. For example, when a memory transaction may exceed 4GB, the endpoints can be PCIe endpoints (150_1 to 150_3). On the other hand, when a memory transaction is unlikely to exceed 4GB, the endpoints can be traditional endpoints (160_1 and 160_2). Although PCIe endpoints 150_1 to 150_3 are not allowed to generate I / O requests, traditional endpoints 160_1 and 160_2 can provide or generate I / O requests. Additionally, PCIe endpoint 150_3 can send TLPs to or receive TLPs from root union 120. Furthermore, PCI / PCI-X can send TLPs to or receive TLPs from root union 120 via PCIe to PCI / PCI-X bridge 170. In addition, PCIe endpoints 150_1 and 150_2, along with traditional endpoints 160_1 and 160_2, can send TLPs to or receive TLPs from switch 140.

[0039] Figure 2 This is a diagram illustrating a PCIe device according to an embodiment of the present disclosure.

[0040] Reference Figure 2 A PCIe device may include a PCIe interface and may be an electronic device that supports sending and receiving using a PCIe interface. For example, the first PCIe device 200-1 or the second PCIe device 200-2 may include, for example, a PCIe interface. Figure 1The root union 120, switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and one of the PCIe to PCI / PCI-X bridges 170 are shown.

[0041] Furthermore, the first PCIe device 200-1 or the second PCIe device 200-2 can perform communication using the first PCIe interface 210-1 or the second PCIe interface 210-2, respectively. More specifically, the first PCIe device 200-1 can convert data to be sent to the second PCIe device 200-2 into a communication-suitable protocol using the first PCIe interface 210-1. Additionally, the first PCIe device 200-1 and the second PCIe device 200-2 can form a link. The first PCIe device 200-1 and the second PCIe device 200-2 can communicate through the link. For example, the first PCIe device 200-1 or the second PCIe device 200-2 can send or receive data packets through the link.

[0042] Figure 3 This is a diagram illustrating a PCIe interface according to an embodiment of the present disclosure.

[0043] Figure 3 It shows Figure 2 The first PCIe interface 210-1 and the second PCIe interface 210-2 are described. The first PCIe interface 210-1 and the second PCIe interface 210-2 can have the same structure. Therefore, the following description of the first PCIe interface 210-1 can also be applied to the second PCIe interface 210-2.

[0044] The PCIe layer included in the first PCIe interface 210-1 may include three separate logical layers. For example, the first PCIe interface 210-1 may include a PCIe kernel 211, a transaction layer 212, a data link layer 213, and a physical layer 214. Each of the layers (212, 213, and 214) may include two parts. More specifically, one part, TX, can handle outbound information (or information to be sent), while the other part, RX, can handle inbound information (or received information). Additionally, the first PCIe interface 210-1 can communicate with other PCIe interfaces using data packets.

[0045] PCIe core 211 can control the entire first PCIe interface 210-1. More specifically, PCIe core 211 may include a software layer for operating the interface. Additionally, PCIe core 211 can transmit addresses, transaction types, and data to or receive addresses, transaction types, and data from transaction layer 212.

[0046] Transaction layer 212 can be an upper layer in the PCIe interface architecture. Transaction layer 212 can assemble and decompose Transaction Layer Packets (TLPs). Additionally, transaction layer 212 can implement split transactions, i.e., transactions that allow other traffic to be sent to the link while the target system assembles data for a response. For example, transaction layer 212 can implement transactions where requests and responses are time-separated. According to embodiments, the four transaction address spaces can consist of a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions can include at least one of read requests and write requests for sending data from or to a memory-mapped location. According to embodiments, memory space transactions can use two different address formats, such as a short address format like a 32-bit address or a long address format like a 64-bit address. Configuration space transactions can be used to access the configuration space of a PCIe device. Transactions involving the configuration space can include read requests and write requests. Message space transactions (or messages) can be defined to support in-band communication between PCIe devices.

[0047] Transaction layer 212 can store link configuration information received from PCIe kernel 211. In addition, transaction layer 212 can generate TLPs requested by PCIe kernel 211 or convert received TLPs into payloads or status information.

[0048] In the PCIe interface architecture, the intermediate layer can be the data link layer 213. The data link layer 213 can serve as an intermediate level between the transaction layer 212 and the physical layer 214. The primary responsibilities of the data link layer 213 can include link management and data integrity, including error detection and correction. More specifically, the sending side of the data link layer 213 can accept the TLP assembled by the transaction layer 212, apply data protection codes, or calculate the TLP sequence number. Additionally, the sending side of the data link layer 213 can send data protection codes and TLP sequence numbers to the physical layer 214. The receiving side of the data link layer 213 can check the integrity of the TLP received from the physical layer 214 and send the TLP to the transaction layer 212 for further processing.

[0049] Physical layer 214 may include circuitry for interface operation. Physical layer 214 may include drivers, input buffers, serial-to-parallel conversion circuitry, parallel-to-serial conversion circuitry, phase-locked loops (PLLs), and impedance matching circuitry.

[0050] Additionally, physical layer 214 may include logical subblocks and electrical subblocks that physically transmit data packets to external PCIe devices. Logical subblocks can be used to perform the "digital" functions of physical layer 214. More specifically, logical subblocks may include a transmitting section that prepares information for transmission via the physical subblocks, and a receiving section that identifies and prepares received information before passing it to data link layer 213. Physical layer 214 may include a transmitter Tx and a receiver Rx. The transmitter Tx can transmit symbols serialized by the logical subblocks to external devices. Additionally, the receiver Rx can receive serialized symbols from external devices and convert the received signals into a bit stream. The bit stream can be deserialized and provided to the logical subblocks. In other words, physical layer 214 can convert TLPs received from data link layer 213 into a serialized format and data packets received from external devices into a deserialized format. Furthermore, physical layer 214 may include logic functions related to interface initialization and maintenance.

[0051] Figure 3 The architecture of the first PCIe interface 210-1 and the second PCIe interface 210-2 is shown. However, the PCIe interface architecture in other embodiments may include any architecture, such as a high-speed channel interconnect architecture, a next-generation high-performance computing interconnect architecture, or other hierarchical architecture.

[0052] Figure 4 This is a diagram illustrating a transmitter, receiver, and channel according to an embodiment of the present disclosure.

[0053] Figure 4 A first transmitter TX1, a second transmitter TX2, a first receiver RX1, and a second receiver RX2 are shown. A channel may include paths comprising differential drive signal pairs, such as transmit path pairs configured for transmitting and receive path pairs configured for receiving. A PCIe device may include transmit logic for sending data to another PCIe device and receive logic for receiving data from another PCIe device. For example, a PCIe device may include two transmit paths coupled to the first transmitter TX1 and two receive paths coupled to the first receiver RX1.

[0054] The transmitting path can refer to any path used for data transmission, such as a transmit line, copper wire, wireless communication channel, infrared communication link, or other communication path. Furthermore, the receiving path can be implemented in the same way as the transmitting path, and the receiving path can be used for receiving data.

[0055] For example Figure 2The connection between the two PCIe devices, the first PCIe device 200-1 and the second PCIe device 200-2 shown, can be referred to as a link. A link can support at least one channel. Furthermore, each channel can be represented by a set of differential signal pairs (one pair for transmitting and another for receiving). A differential signal pair can refer to two signals with the same frequency and amplitude but opposite phases. For example, while the first signal has a rising edge switching from 0 to a voltage level V+, the second signal can have a falling edge switching from 0 to a voltage level V-. For example, PCIe devices can utilize signal integrity features such as cross-connection, voltage overshoot / undershoot, and ringing electrical characteristics, and can control the transmission frequency more quickly by using differential signals. Additionally, PCIe devices can include multiple channels to control bandwidth. For example, two PCIe devices can form a link consisting of 1, 2, 4, 8, 12, 16, or 64 channels.

[0056] Figure 5 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0057] Reference Figure 5 The PCIe device 1000 can be linked to a first PCIe host 2000-1 and a second PCIe host 2000-2. A link can refer to the state of establishing a connection to enable logical data communication. Compared to the PCIe device 1000, the first PCIe host 2000-1 and the second PCIe host 2000-2 can be located at an upper layer. Furthermore, data movement and transmission to the upper layer can be referred to as "upstream," and the port supporting the upstream can be referred to as an "upstream port." On the other hand, data movement and transmission to the lower layer can be referred to as "downstream," and the port supporting the downstream can be referred to as a "downstream port." For example, refer to... Figure 1 Switch 140 can support downstream and upstream routing. More specifically, upstream can refer to routing upwards along the hierarchy from a PCIe endpoint (e.g., 150_1) to root union 120, and downstream can refer to routing downwards along the hierarchy from root union 120 to a PCIe endpoint (e.g., 150_2).

[0058] PCIe device 1000 may include a first upstream port 1100 and a second upstream port 1200. Additionally, PCIe device 1000 may perform data communication with a first PCIe host 2000-1 and a second PCIe host 2000-2 in a dual-port mode, wherein the first upstream port 1100 and the second upstream port 1200 operate independently of each other.

[0059] More specifically, the first upstream port 1100 included in the PCIe device 1000 can be linked to the first PCIe host 2000-1 via the first link 10. Additionally, the second upstream port 1200 included in the PCIe device 1000 can be linked to the second PCIe host 2000-2 via the second link 20. The first upstream port 1100 can be linked to the first downstream port 2100-1 of the first PCIe host 2000-1. The second upstream port 1200 can be linked to the second downstream port 2100-2 of the second PCIe host 2000-2. The link width of each of the first link 10 and the second link 20 can include channels such as x1, x2, x4, x8, x12, x16, x32, and x64.

[0060] According to an embodiment, when the PCIe device 1000 operates in dual-port mode, an error (e.g., a clock error) occurring in the first link 10 between the first upstream port 1100 and the first downstream port 2100-1 may not affect the second link 20 between the second upstream port 1200 and the second downstream port 2100-2.

[0061] According to an embodiment, each of the first upstream port 1100 and the second upstream port 1200 may include a PCIe interface and a Link Training State Machine (LTSSM) (also referred to as a link training module). In other words, the PCIe interface and LTSSM of the first upstream port 1100 and the second upstream port 1200 can be independent of each other. More specifically, the first upstream port 1100 may include a first LTSSM1, and the second upstream port 1200 may include a second LTSSM2. In addition, the first LTSSM1 and the second LTSSM2 can independently perform link training for the first link 10 and link training for the second link 20.

[0062] Figure 6 This is a diagram illustrating the link status of a PCIe device according to an embodiment of the present disclosure.

[0063] like Figure 6 As shown, the link status of a PCIe device can include detection, polling, configuration, hot reset, disabled, and L0 status.

[0064] The detection state can refer to the initial state after power-on or reset. It can be entered from the following states, as described below: configuration state, hot reset state, disabled state, polling state, L2 state, loopback state, and recovery state. In the detection state, all logic, ports, and registers can be reset, and the links connected to the PCIe interface can be detected. In other words, a PCIe device in the detection state can search for physically connected channels.

[0065] In polling mode, channels with enabled data communication can be distinguished from detected channels. For example, in polling mode, the clocks at both ends of the PCIe interface can be synchronized, and the channel polarity (D+ or D-) can be confirmed. Additionally, the available data transmission rate for the channel can be checked. In other words, polarity reversal can be checked in polling mode. Furthermore, a link in polling mode can enter either detection or configuration mode.

[0066] In configuration mode, the connection status of the channels can be checked. More specifically, in configuration mode, the channel width for enabling data communication can be determined. Additionally, in configuration mode, channel reversal can be checked. Configuration mode can be entered from polling mode. However, optionally, after entering L0 mode, configuration mode can be entered again if the number of channels decreases or the channel width increases.

[0067] The recovery state can be used to reconfigure link bandwidth. In recovery state, the link bandwidth of the established link can be changed, and bit locking, symbol locking, and lane-to-lane de-skew can be reset. When an error occurs in L0 state, the system can enter recovery state. After recovering from the error in recovery state, the state can be changed back to L0 state. Additionally, according to an embodiment, link equalization operations can be performed in recovery state.

[0068] The L0 state can be a normal operating state, in which data and packets are sent and received via the link. More specifically, the L0 state can be an operating state of the physical bus interface capable of sending and receiving data and control packets. The L0 state can also be a fully active state.

[0069] L0s state can refer to the state in which the physical bus interface can quickly enter a power-saving state and recover from it without going through a recovery state. L0s state can be a power-saving state. L0s state can also refer to the idle or standby state of certain functions within the interface.

[0070] L1 state can be a power-saving state. L1 state can refer to a power-saving state that allows for additional power saving compared to L0s state. L1 state can also be a low-power standby state.

[0071] L2 state can be an active power-saving state. Most transmitters and receivers can be turned off. Although main power and clock are not guaranteed, auxiliary power can be provided. L2 state can also be a low-power sleep state that does not power most functions.

[0072] Loopback mode can be used for testing and fault isolation. Loopback mode can operate on a per-channel basis, and the loopback receive channel must be selected and configured.

[0073] The disabled state allows an established link to be disabled until indicated. The hot reset state can be triggered solely by the downstream port. The downstream port can propagate a hot reset using a training sequence (e.g., TS1 or TS2). The training sequence TS can consist of an ordered set used to initialize bit alignment, sign alignment, and exchange physical layer parameters.

[0074] Figures 7 to 10 This is a diagram illustrating a dual-port mode and a single-port mode according to embodiments of the present disclosure.

[0075] exist Figures 7 to 10 In PCIe Physics, interface speed is designed to maximize performance in challenging system environments found in high-performance computing. PCIe Physics is a low-power, area-optimized, silicon-proven IP designed with a system-oriented approach to maximize flexibility and ease of customer integration. A multiplexer (Mux) is a combinational logic circuit designed to switch one of several input lines to a single common output line by applying control signals. Multiplexers operate like very fast multi-position rotary switches, connecting or controlling multiple input lines, called "channels," to the output at once.

[0076] Reference Figures 7 to 10 The PCIe device 1000 (not shown) may include a first upstream port 1100 and a second upstream port 1200. Additionally, the first upstream port 1100 may be linked to a first downstream port 2100-1, and the second upstream port 1200 may be linked to a second downstream port 2100-2 via a link independent of the first upstream port 1100. Each of the first upstream port 1100 and the second upstream port 1200 may include an LTSSM that controls the state of links physically or logically connected to the LTSSM.

[0077] According to an embodiment, the PCIe device 1000 can change its operating mode from single-port mode to dual-port mode while a link is connected. Optionally, the PCIe device 1000 (specifically, its port mode controller) can change its operating mode from dual-port mode to single-port mode while at least one link is connected. The port mode controller can, in response to a mode change request from a first host to change from dual-port mode to single-port mode, control a second port to reset the second link.

[0078] Reference Figure 7The dual-port mode can be configured such that the first upstream port 1100 and the second upstream port 1200 of the PCIe device 1000 are respectively connected to the first downstream port 2100-1 and the second downstream port 2100-2. According to an embodiment, the first downstream port 2100-1 and the second downstream port 2100-2 can be included in a single host and implemented as independent ports. However, alternatively, the first downstream port 2100-1 and the second downstream port 2100-2 can be included in different hosts. (See also...) Figure 7 Links connected to the first upstream port 1100 and the second upstream port 1200 can logically enable data communication.

[0079] Reference Figure 8 The first upstream port 1100 and the second upstream port 1200 of the PCIe device 1000 can be configured in a single-port mode, where data communication can be performed using only the first upstream port 1100. More specifically, when the operating mode of the PCIe device 1000 changes from dual-port mode to single-port mode, the link state of the first upstream port 1100 can be in the L0 state, while the link state of the second upstream port 1200 can be in a reset state where the link connection is initialized (e.g., cold reset, warm reset, or hot reset), or a disabled state where the link connection is disabled. However, when the operating mode of the PCIe device 1000 changes from single-port mode to dual-port mode, the link state of the first upstream port 1100 can be in the L0 state, while the link state of the second upstream port 1200 can be in a state where link training is being performed for the link connection. For example, the link state of the second upstream port 1200 can be one of a detection state, a polling state, and a configuration state. According to the embodiment, since the link state of the first upstream port 1100 is L0, the PCIe device 1000 can maintain data communication with the first downstream port 2100-1 using the first upstream port 1100 regardless of the link state of the second upstream port 1200.

[0080] Reference Figure 9The first upstream port 1100 and the second upstream port 1200 of the PCIe device 1000 can operate in a single-port mode, where data communication can be performed using only the first upstream port 1100. More specifically, when the operating mode of the PCIe device 1000 changes from dual-port mode to single-port mode, the first upstream port 1100 (or LTSSM 1) can perform an up-configuration operation in response to the control of the port mode controller to increase the channel width of the configured link. For example, the first upstream port 1100 can increase the channel width of the link connected to the first upstream port 1100 from X2 channels to X4 channels. More specifically, in order to configure the link of the first upstream port 1100 to have the maximum channel width, the first LTSSM1 can sequentially change the link state of the first upstream port 1100 to L0 state, recovery state, and configuration state, and can perform an up-configuration operation to increase the channel width in each state.

[0081] On the other hand, when the operating mode of the PCIe device 1000 changes from single-port mode to dual-port mode, the first upstream port 1100 can perform a channel reduction operation to reduce the channel width of the configured link. For example, the first upstream port 1100 can reduce the channel width of the link connected to the first upstream port 1100 from X4 channels to X2 channels. More specifically, the PCIe device 1000 can reduce the channel width of the first upstream port 1100 to change the operating mode from a single-port mode in which only the first upstream port 1100 operates to a dual-port mode in which the first upstream port 1100 and the second upstream port 1200 operate independently of each other. The first LTSSM1 can sequentially change the link state of the first upstream port 1100 to L0 state, recovery state, and configuration state, and can perform a channel reduction operation to reduce the channel width in each state.

[0082] Reference Figure 10 The first upstream port 1100 and the second upstream port 1200 of the PCIe device 1000 can be configured in a single-port mode, where data communication can be performed using only the first upstream port 1100. According to an embodiment, the link connected to the first downstream port 2100-1 can be implemented with the maximum channel width. However, according to an embodiment, when the first upstream port 1100 and the second upstream port 1200 are connected to the same host, if an error occurs in the link or data communication connected to the second upstream port 1200, the PCIe device 1000 can use only the first upstream port 1100 to accelerate data communication until the error is recovered.

[0083] Reference Figures 7 to 10The PCIe device 1000 can receive an operating mode change request from the host to change from dual-port mode to single-port mode. Additionally, in response to the operating mode change request from the host, the PCIe device 1000 can sequentially change the state of the links connected to the first upstream port 1100 and the second upstream port 1200 to the same state. Figure 8 , Figure 9 and Figure 10 The link status corresponding to the link status in the diagram.

[0084] However, refer to Figures 7 to 10 The PCIe device 1000 can receive an operating mode change request from the host to change from dual-port mode to single-port mode. Additionally, in response to the operating mode change request from the host, the PCIe device 1000 can sequentially change the state of the links connected to the first upstream port 1100 and the second upstream port 1200 to the same state. Figure 10 , Figure 9 , Figure 8 and Figure 7 The link status corresponding to the link status in the diagram.

[0085] Figure 11 This is a diagram illustrating the configuration of a PCIe device according to an embodiment of the present disclosure.

[0086] Reference Figure 11 The PCIe device 1000 may include a first upstream port (also referred to as the first port) 1100, a second upstream port (also referred to as the second port) 1200, and a port mode controller 1300. The PCIe device 1000 may perform data communication in single-port mode using only the first upstream port 1100. More specifically, the PCIe device 1000 may link the first upstream port 1100 to an external device by using at least one of the first to fourth channels. Figure 11 A PCIe device 1000 with four channels is shown; however, the PCIe device contemplated in this disclosure may include more than four channels.

[0087] When the PCIe device 1000 operates in single-port mode using the first through fourth channels, the port mode controller 1300 can control the first multiplexer 1010 such that the same reference clock can be input to each circuit. More specifically, when the PCIe device 1000 operates in single-port mode, the port mode controller 1300 can control the first multiplexer (MUX 1) 1010 such that the first reference clock Refclk#1 can be input to each circuit between the first reference clock Refclk#1 and the second reference clock Refclk#2 input to the first multiplexer 1010. Additionally, when the PCIe device 1000 operates in single-port mode, the port mode controller 1300 can control the second multiplexer (MUX 2) 1020 such that signals transmitted from the third and fourth channels can be sent to the first PCIe interface 1.

[0088] Additionally, the PCIe device 1000 can perform data communication in dual-port mode using both the first upstream port 1100 and the second upstream port 1200. The PCIe device 1000 can connect to at least one host using the first upstream port 1100 and the second upstream port 1200.

[0089] When the PCIe device 1000 operates in dual-port mode, the PCIe device 1000 can use the port mode controller 1300 to control its internal circuitry. More specifically, when the PCIe device 1000 operates in dual-port mode, the port mode controller 1300 can control the first multiplexer 1010 to provide a first reference clock Refclk#1 to the first upstream port 1100, and can provide a second reference clock Refclk#2, different from the first reference clock Refclk#1, to the second upstream port 1200. Additionally, when the PCIe device 1000 operates in dual-port mode, the port mode controller 1300 can control the second multiplexer 1020 to send signals transmitted from the third and fourth channels to the second PCIe interface 2.

[0090] PCIe device 1000 can reset the PCIe interfaces included in the first upstream port 1100 and the second upstream port 1200 respectively in response to a first PCIe reset signal PERST#1 and a second PCIe reset signal PERST#2 received from the host. Additionally, PCIe device 1000 can change its operating mode to single-port mode or dual-port mode in response to a dual-port enable signal DualPortEn# received from the host. More specifically, port mode controller 1300 can reset the first PCIe interface 1 and LTSSM included in the first upstream port 1100 in response to the first PCIe reset signal PERST#1. Port mode controller 1300 can reset the second PCIe interface 2 and LTSSM included in the second upstream port 1200 in response to the second PCIe reset signal PERST#2.

[0091] Figure 12 This is a diagram illustrating a method for changing a PCIe device from single-port mode to dual-port mode according to an embodiment of the present disclosure.

[0092] exist Figure 12 The diagram sequentially illustrates a method for operating a PCIe device 1000. More specifically, the PCIe device 1000 may include a first port and a second port. Additionally, in step S1210, the PCIe device 1000 may connect the first port to a first host and operate in single-port mode. More specifically, the PCIe device 1000 may perform a first link training operation to link the first host to the first port via a first link. Single-port mode may refer to a mode where only the first port operates between the first port and the second port.

[0093] Additionally, when the PCIe device 1000 receives a mode change request from the host ("Yes" in S1220), in step S1230, the PCIe device 1000 may perform a channel reduction operation on the first link. The channel reduction operation may refer to reducing the channel width (or link width) corresponding to the first link.

[0094] In step S1240, when the state of the first link on the first port becomes L0, the PCIe device 1000 can begin linking the second port. More specifically, when the channel reduction operation on the first port is completed and the state of the first link on the first port returns to L0, the PCIe device 1000 (specifically, the port mode controller therein) can perform a second link training operation to link the second link.

[0095] Furthermore, when the second link training operation is complete, the PCIe device 1000 can operate in a dual-port mode where the first and second ports operate independently of each other. In other words, data communication performed or errors occurring in one of the first and second ports will not affect the operation of the other port. For operation in dual-port mode, each of the first and second ports may include an LTSSM, a PCIe interface, etc. The PCIe interface may refer to an interface comprising the transaction layer, data link layer, and physical layer that operates in link state according to the PCIe standard, responding to separate controls of each of LTSSM1 and LTSSM2.

[0096] Figure 13 This is a diagram illustrating a method for changing a PCIe device from a dual-port mode to a single-port mode according to an embodiment of the present disclosure.

[0097] Reference Figure 13 The method of operating a PCIe device 1000 is illustrated sequentially. More specifically, the PCIe device 1000 may include a first port and a second port. Additionally, in step S1310, the PCIe device 1000 may link the first port and the second port and operate in dual-port mode. More specifically, the PCIe device 1000 may link the first port to a first host and the second port to a second host. In other words, the PCIe device 1000 can independently perform a first link training operation linking the first host to the first port and a second link training operation linking the second host to the second port. A link can refer to the operation of logically connecting a link to a host to enable data communication with the host. A link training operation can refer to controlling the settings associated with the corresponding link to perform the overall operation of the link.

[0098] Additionally, when the PCIe device 1000 receives a mode change request from the host ("Yes" in S1320), in step S1330, the PCIe device 1000 (specifically, its port mode controller) can control LTSSM 2 to reset or disable the second link. Resetting or disabling can refer to physically or logically disconnecting the link from the host. Furthermore, according to an embodiment, when the PCIe device 1000 (specifically, its port mode controller) can control the second port to reset or disable the second link, the first link can remain connected (e.g., in L0 state).

[0099] Additionally, when the reset or deactivation of the second link is completed, in step S1340, the PCIe device 1000 (specifically, its port mode controller) can control LTSSM 1 to perform a channel increase operation to increase the channel width of the first link. When the PCIe device 1000 performs the channel increase operation on the first link, the state of the first link can sequentially change to L0 state, recovery state, configuration state, and back to L0 state. Since data communication is logically possible during the channel increase operation on the first link, the first link can be considered to be in a linked state.

[0100] In addition, when the channel addition operation on the first link is completed, the PCIe device 1000 can operate in a single-port mode with only the first port operating, and the PCIe device 1000 can set the channel width of the first link to the maximum channel width.

[0101] According to this disclosure, a method for operating an improved PCIe device by changing the port mode can be provided.

[0102] In the embodiments discussed above, all steps may be selectively performed or skipped. Furthermore, the steps in each embodiment may not always be performed in the usual order. Moreover, the embodiments disclosed in this specification and accompanying drawings are intended to help those skilled in the art to better understand this disclosure, and are not intended to limit the scope of this disclosure. In other words, those skilled in the art will be able to readily understand that various modifications can be made based on the technical scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made to the above exemplary embodiments of this disclosure without departing from the spirit or scope of the invention. Therefore, this disclosure is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A high-speed peripheral component interconnect (PCIe) device, comprising: The first port uses the first link to connect to the first host; The second port is connected to the first host or the second host using a second link; as well as A port mode controller controls the first port and the second port to change the operating mode from a dual-port mode where the first port and the second port operate independently of each other to a single-port mode where only the first port operates. The port mode controller controls the second port to reset the second link when the first link is communicating between the first port and the first host.

2. The PCIe device of claim 1, wherein the first port includes a first link training module for changing the state of the first link, and The second port includes a second link training module that changes the state of the second link.

3. The PCIe device of claim 2, wherein when the first link is communicating between the first port and the first host, the port mode controller controls the second link training module to reset the second link, and when the reset of the second link is completed, controls the first link training module to expand the channel width of the first link.

4. The PCIe device of claim 3, wherein the first link training module performs an upconfiguration operation in response to the control of the port mode controller to increase the channel width of the first link.

5. The PCIe device according to claim 3, wherein the first link training module sequentially changes the state of the first link to L0 state, recovery state, configuration state and L0 state, wherein the L0 state is a normal operating state for sending and receiving data and data packets through the first link.

6. The PCIe device of claim 2, wherein each of the first port and the second port includes a PCIe interface, the PCIe interface including a transaction layer, a data link layer and a physical layer, the transaction layer, the data link layer and the physical layer operating in link state in response to the respective control of each of the first link training module and the second link training module, according to the PCIe standard.

7. The PCIe device of claim 1, wherein the port mode controller controls the second port to reset the second link in response to a mode change request from the first host to change from the dual-port mode to the single-port mode.

8. A high-speed peripheral component interconnect (PCIe) device, comprising: The first port uses the first link to connect to the first host; The second port is connected to the first host or the second host using a second link; as well as A port mode controller controls the first port and the second port to change the operating mode from a single-port mode where only the first port operates to a dual-port mode where the first port and the second port operate independently of each other. The port mode controller controls the second port to perform a link training operation to link the second link when the first link is communicating between the first port and the first host.

9. The PCIe device of claim 8, wherein the first port includes a first link training module for changing the state of the first link, and The second port includes a second link training module that changes the state of the second link.

10. The PCIe device of claim 9, wherein the port mode controller controls the first link training module to perform a channel reduction operation to reduce the channels corresponding to the first link when the first link is linked, and controls the second link training module to perform the link training operation when the channel reduction operation is completed.

11. The PCIe device of claim 10, wherein the first link training module, in response to the control of the port mode controller, sequentially changes the state of the first link to L0 state, recovery state, configuration state, and L0 state, wherein the L0 state is a normal operating state for sending and receiving data and data packets through the first link.

12. The PCIe device of claim 9, wherein each of the first port and the second port includes a PCIe interface, the PCIe interface including a transaction layer, a data link layer and a physical layer, the transaction layer, the data link layer and the physical layer operating in link state in response to the respective control of each of the first link training module and the second link training module, according to the PCIe standard.

13. The PCIe device of claim 8, wherein the second port performs the link training operation on the second link in response to a mode change request from the first host to change from the single-port mode to the dual-port mode.

14. A method of operating a high-speed peripheral component interconnect (PCIe) device, the PCIe device including a first port and a second port, the method comprising: Perform a first link training operation to link the first host with the first link of the first port; When the first link training operation is completed, it operates in single-port mode; In response to a mode change request received from the first host, a channel reduction operation is performed to reduce the number of channels corresponding to the first link; and When the state of the first link is L0, a second link training operation is performed to link the second host with the second link of the second port, wherein the L0 state is a normal operating state for sending and receiving data and packets through the first link.

15. The method of claim 14, further comprising: It operates in a dual-port mode where the first port and the second port operate independently of each other.

16. The method of claim 14, wherein when performing the second link training operation, the second link training operation is performed when the state of the first link is L0.

17. The method of claim 14, wherein performing the channel reduction operation comprises: The state of the first link is changed sequentially to L0 state, recovery state, configuration state, and L0 state.

18. The method of claim 14, wherein each of the first port and the second port includes a PCIe interface, the PCIe interface including a transaction layer, a data link layer and a physical layer operating according to the PCIe standard.

19. A method of operating a high-speed peripheral component interconnect (PCIe) device, the PCIe device including a first port and a second port, the method comprising: Perform a first link training operation to link the first host to the first link of the first port, and perform a second link training operation to link the second host to the second link of the second port; When the first link training operation and the second link training operation are completed, the operation is carried out in a dual-port mode in which the first link and the second link operate independently of each other. In response to a mode change request received from the first host or the second host, the second link is disabled; and When the second link is deactivated, a channel addition operation is performed to add a channel corresponding to the first link.

20. The method of claim 19, further comprising: When the channel addition operation is completed, the first port is used to operate in single-port mode.

21. The method of claim 19, wherein when the state of the first link corresponds to the L0 state, the second link is deactivated, wherein the L0 state is a normal operating state for sending and receiving data and data packets through the first link.

22. The method of claim 19, wherein performing the channel addition operation comprises: The state of the first link is changed sequentially to L0 state, recovery state, configuration state, and L0 state, wherein the L0 state is the normal operating state of sending and receiving data and data packets through the first link.

23. The method of claim 19, wherein each of the first port and the second port includes a PCIe interface, the PCIe interface including a transaction layer, a data link layer and a physical layer operating according to the PCIe standard.

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