A system, method, and apparatus for non-volatile memory read operation optimization

Abstract

The application discloses a nonvolatile memory read operation optimization system, method and device, and the system comprises a storage unit, a real-time frequency detection circuit, a read instruction unit and a system control module. The system control module receives a real-time clock frequency sent by the real-time frequency detection circuit, obtains a current clock frequency range, and adjusts internal circuits of the nonvolatile memory according to the current clock frequency range. The read instruction unit is used for identifying instruction information of reading memory and applying high voltage to the storage unit gate. The application detects the clock frequency of a read instruction in real time through an internal real-time frequency detection circuit, obtains a current clock frequency range, then adjusts internal related circuits to reduce power consumption, improve reliability, improve the precision of distinguishing between the storage unit current and the reference current, and improve the reliability of using a chip at a low frequency.

Description

Technical Field

[0001] This application relates to the field of non-volatile memory, and in particular to a non-volatile memory read operation optimization system, method and apparatus. Background Technology

[0002] Non-volatile storage (NVS), also known as non-volatile random access memory (NVRAM), is a form of static random access memory that retains its contents when the computer is powered off or loses its external power. NVS typically uses different clock frequencies (generally ranging from a few kHz to several hundred MHz) for read instruction interface timing, depending on the specific application environment. Higher frequency circuits often have more demanding requirements than lower frequency circuits, so internal circuit designs are typically based on high-frequency requirements. This often results in some performance and reliability sacrifices for lower-frequency applications.

[0003] Therefore, the aforementioned technical problems in the relevant technologies urgently need to be solved. Summary of the Invention

[0004] This application aims to solve one of the technical problems in related technologies. To this end, embodiments of this application provide a non-volatile memory read operation optimization system, method, and apparatus, which can optimize non-volatile memory read operations and save energy.

[0005] According to one aspect of the embodiments of this application, a non-volatile memory read operation optimization system is provided, the system comprising: a memory unit, a real-time frequency detection circuit, a read instruction unit, and a system control module;

[0006] The system control module receives the real-time clock frequency sent by the real-time frequency detection circuit, obtains the current clock frequency range, and adjusts the internal circuit of the non-volatile memory according to the current clock frequency range.

[0007] The read instruction unit is used to identify the instruction information for reading memory and apply high voltage to the storage unit gate.

[0008] In one embodiment, the system further includes: a sensitive amplification comparator and a charge pump, and the system control module adjusts the internal circuitry of the non-volatile memory according to the current clock frequency range, including:

[0009] When the current clock frequency is lower than a first preset value, the system control module shuts down the BOOST circuit during the non-operation phase of the sensitive amplifier comparator.

[0010] In one embodiment, the system further includes a charge pump, a reference voltage circuit, and a reference current circuit. When the current clock frequency is lower than a second preset value, the system control module shuts down the charge pump, the reference voltage circuit, and the reference current circuit during the non-operation phase of the sensitive amplifier comparator.

[0011] In one embodiment, when the current clock frequency is lower than a third preset value, the system control module adjusts the operating timing of the sensitive amplifier comparator module to increase the operating duration of the sensitive amplifier comparator at low frequencies.

[0012] According to one aspect of the embodiments of this application, the system control module is provided to select and shut down different modules to reduce power consumption based on the read instruction I / O time frequency obtained by the real-time frequency detection circuit, the chip communication protocol interface, and the restart establishment time of each power source module.

[0013] According to one aspect of the embodiments of this application, a method for optimizing non-volatile memory read operations is provided, applied to a non-volatile memory read operation optimization system described in the preceding embodiments, the method comprising:

[0014] The system receives the real-time clock frequency sent by the real-time frequency detection circuit, obtains the current clock frequency range, and adjusts the internal circuitry of the non-volatile memory according to the current clock frequency range.

[0015] Apply high voltage to the gate of the storage unit.

[0016] In one embodiment, adjusting the internal circuitry of the non-volatile memory according to the current clock frequency range includes:

[0017] When the current clock frequency is lower than the first preset value, the BOOST circuit is turned off during the non-operation phase of the sensitive amplifier comparator.

[0018] In one embodiment, the method further includes:

[0019] When the current clock frequency is lower than the second preset value, the charge pump, the reference voltage circuit, and the reference current circuit are turned off during the non-operation phase of the sensitive amplifier comparator.

[0020] In one embodiment, the method further includes:

[0021] When the current clock frequency is lower than the third preset value, the operating timing of the sensitive amplifier comparator module is adjusted to increase the operating duration of the sensitive amplifier comparator at low frequencies.

[0022] According to one aspect of an embodiment of this application, a non-volatile memory read operation optimization apparatus is provided, the apparatus comprising:

[0023] The first module is used to receive the real-time clock frequency sent by the real-time frequency detection circuit, obtain the current clock frequency range, and adjust the internal circuit of the non-volatile memory according to the current clock frequency range.

[0024] The second module is used to apply high voltage to the gate of the storage unit.

[0025] According to one aspect of an embodiment of this application, a non-volatile memory read operation optimization apparatus is provided, the apparatus comprising:

[0026] At least one processor;

[0027] At least one memory for storing at least one program;

[0028] When at least one of the programs is executed by at least one of the processors, a non-volatile memory read operation optimization method as described in the preceding embodiments is implemented.

[0029] The beneficial effects of the non-volatile memory read operation optimization system, method, and apparatus provided in this application are as follows: The system of this application includes: a memory unit, a real-time frequency detection circuit, a read instruction unit, and a system control module; the system control module receives the real-time clock frequency sent by the real-time frequency detection circuit to obtain the current clock frequency range, and adjusts the internal circuitry of the non-volatile memory according to the current clock frequency range; the read instruction unit is used to identify the instruction information for reading memory and apply high voltage to the gate of the memory unit. This application uses the internal real-time frequency detection circuit to detect the clock frequency of the read instruction in real time, obtain the current clock frequency range, and then adjusts the relevant internal circuitry to reduce power consumption, improve reliability, improve the accuracy of distinguishing between the memory unit current and the reference current, and improve the reliability of the chip when used at low frequencies.

[0030] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a non-volatile memory read operation optimization system provided in an embodiment of this application;

[0033] Figure 2 A flowchart of a non-volatile memory read operation optimization method provided in an embodiment of this application;

[0034] Figure 3 A complete operation flowchart of the non-volatile memory read operation optimization method provided in the embodiments of this application;

[0035] Figure 4 A schematic diagram of a non-volatile memory read operation optimization device provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of another non-volatile memory read operation optimization device provided in an embodiment of this application. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0038] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0039] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] Non-volatile storage (NVS), also known as non-volatile random access memory (NVRAM), is a form of static random access memory that retains its contents when the computer is powered off or loses its external power. NVS typically uses different clock frequencies (generally ranging from a few kHz to several hundred MHz) for read instruction interface timing, depending on the specific application environment. Higher frequency circuits often have more demanding requirements than lower frequency circuits, so internal circuit designs are typically based on high-frequency requirements. This often results in some performance and reliability sacrifices for lower-frequency applications.

[0041] To address the aforementioned issues, this application proposes a non-volatile memory read operation optimization system, method, and apparatus. This application uses an internal real-time frequency detection circuit to detect the clock frequency of the read command in real time, obtaining the current clock frequency range. Then, it adjusts related internal circuits to reduce power consumption and improve reliability. For example, regarding power consumption: when the frequency is lower than a set value A, the relevant BOOST circuit is shut down during the non-operating phase of the sensitive amplifier comparator. When the frequency is lower than a set value B, the relevant charge pump, reference voltage, and reference current circuits are shut down during the non-operating phase of the sensitive amplifier comparator. The specific circuits shut down can be determined based on the actual frequency detection point and module setup time. Regarding reliability: when the frequency is lower than a set value C, the operating timing of the sensitive amplifier comparator module is adjusted to increase the operating time of the sensitive amplifier comparator at low frequencies, thereby improving the accuracy of distinguishing between the memory cell current and the reference current, and improving the reliability of the chip at low frequencies.

[0042] like Figure 1 As shown, the non-volatile memory read operation optimization system, method, and apparatus proposed in this application specifically include: a memory unit, a real-time frequency detection circuit, a read instruction unit, and a system control module; the system control module receives the real-time clock frequency sent by the real-time frequency detection circuit, obtains the current clock frequency range, and adjusts the internal circuit of the non-volatile memory according to the current clock frequency range; the read instruction unit is used to identify the instruction information for reading memory and apply high voltage to the gate of the memory unit.

[0043] Optionally, the system in this embodiment further includes: a sensitive amplifier comparator and a charge pump. The system control module adjusts the internal circuitry of the non-volatile memory according to the current clock frequency range, including: when the current clock frequency is lower than a first preset value, the system control module shuts down the BOOST circuit during the non-operating phase of the sensitive amplifier comparator. The system further includes: a charge pump, a reference voltage circuit, and a reference current circuit. When the current clock frequency is lower than a second preset value, the system control module shuts down the charge pump, the reference voltage circuit, and the reference current circuit during the non-operating phase of the sensitive amplifier comparator.

[0044] When the current clock frequency is lower than a third preset value, the system control module adjusts the working timing of the sensitive amplifier comparator module to increase the working duration of the sensitive amplifier comparator at low frequencies.

[0045] Furthermore, in this embodiment, the system control module selects to shut down different modules to reduce power consumption based on the read instruction I / O time frequency obtained from the real-time frequency detection circuit, the chip communication protocol interface, and the restart establishment time of each power source module.

[0046] In this embodiment, reading instructions require applying high voltage to the memory cell gate: the word line decoder is boosted to the charge pump voltage after passing through a high-voltage conversion circuit; then, a boost circuit (BOOST) further increases the voltage based on the charge pump voltage, which serves as the gate voltage for the WL direction high-voltage switch to transmit the word line high voltage to the memory cell gate; reading instructions also require applying high voltage to the BL direction decoding high-voltage switch gate: the bit line decoder is boosted to the charge pump voltage after passing through a high-voltage conversion circuit; a sensitive amplifier comparator is used to compare the reference current with the memory cell current and outputs the comparison value; a parameter configuration register is used to configure its operating time; the reference voltage is input to the charge pump, which then checks whether it has reached its operating voltage.

[0047] The power consumption during instruction read operations in this embodiment originates from the following sources: a sensitive amplifier comparator (whose operating time is determined by the parameter configuration register), a bit line charge pump (ensuring the BL high-voltage switch is on when the sensitive amplifier comparator is operating), a BOOST boost circuit (ensuring the word line high voltage is transmitted to each memory cell gate when the sensitive amplifier comparator is operating), a word line charge pump (ensuring the read operation gate high voltage value is reached when the sensitive amplifier comparator is operating), a reference current (provided to the sensitive amplifier comparator), and a reference voltage (provided to the charge pump). Based on the read instruction I / O time frequency obtained from the clock detection circuit (determined by the specific chip application), the chip communication protocol interface (SPI, DPI, QPI, DTR, etc.), and the restart setup time of each power-consuming module (determined by circuit design), relevant modules are selected to be shut down to reduce power consumption. Different operating durations are configured for the sensitive amplifier comparator based on the read instruction I / O time frequency obtained from the clock detection circuit (determined by the specific chip application); lower frequencies can be configured with longer operating times to increase module accuracy and improve chip reliability.

[0048] Specifically, during clock detection, the clock signal is the external read instruction clock for the chip, and the enable signal is the detection circuit switch signal. The output signal of each module is the check result: 1 indicates that the n clock times are less than the pulse circuit duration; 0 indicates that the n clock times are greater than the pulse circuit duration. Taking the modules in the box below as examples, assuming the pulse circuit duration is 30ns, then when the output is 1, 3 clocks < 30ns, that is, one clock < 10ns, and the frequency is greater than 100MHz; conversely, when the output is 0, the frequency is less than 100MHz. Different detection modules can be set with different pulse circuit durations and the number of clocks. The following figures show circuit diagrams for 3 clocks and 4 clocks, respectively.

[0049] Furthermore, this application also proposes an optimization method for non-volatile memory read operations, such as... Figure 2 As shown, a non-volatile memory read operation optimization system applied to the preceding embodiments of claims, the method includes:

[0050] S201. Receive the real-time clock frequency sent by the real-time frequency detection circuit, obtain the current clock frequency range, and adjust the internal circuit of the non-volatile memory according to the current clock frequency range.

[0051] S202, Apply high voltage to the gate of the storage unit.

[0052] The adjustment of the internal circuitry of the non-volatile memory according to the current clock frequency range includes: when the current clock frequency is lower than a first preset value, disabling the BOOST circuit during the non-operating phase of the sensitive amplifier comparator; when the current clock frequency is lower than a second preset value, disabling the charge pump, the reference voltage circuit, and the reference current circuit during the non-operating phase of the sensitive amplifier comparator; and when the current clock frequency is lower than a third preset value, adjusting the operating timing of the sensitive amplifier comparator module to increase the operating duration of the sensitive amplifier comparator at low frequencies.

[0053] like Figure 3 As shown, the specific workflow of the operation optimization method provided in this application is as follows:

[0054] (1) The memory chip activates the clock detection circuit after receiving the read command;

[0055] (2) The clock detection circuit judges the signal output by the detection module and divides it into external clock frequency lower than the set value B, external clock frequency higher than the set value A, external clock frequency lower than the set value A but higher than the set value B, and external clock frequency higher than the set value C or lower than the set value C.

[0056] (3) If the external clock frequency is lower than the set value B, the working flag of the sensitive amplifier is determined, and the BOOST circuit, charge pump, reference voltage, reference current and other circuits are turned on or off according to the working flag of the sensitive amplifier.

[0057] (4) If the external clock frequency is lower than the set value A but higher than the set value B, the BOOST circuit will be turned on or off according to the sensitive amplifier working flag.

[0058] (5) If the external clock frequency is higher than the set value A, no action will be taken;

[0059] (6) If the external clock frequency is higher than the set value C, no action will be taken;

[0060] (7) If the external clock frequency is lower than the set value C, adjust the setting to increase the working time of the sensitive amplifier comparator.

[0061] Furthermore, this application also proposes a non-volatile memory read operation optimization device, such as... Figure 4 As shown, the device includes:

[0062] The first module is used to receive the real-time clock frequency sent by the real-time frequency detection circuit, obtain the current clock frequency range, and adjust the internal circuit of the non-volatile memory according to the current clock frequency range.

[0063] The second module is used to apply high voltage to the gate of the storage unit.

[0064] Furthermore, this application also proposes a non-volatile memory read operation optimization device, such as... Figure 5 As shown, the device includes:

[0065] At least one processor;

[0066] At least one memory for storing at least one program;

[0067] When at least one of the programs is executed by at least one of the processors, a non-volatile memory read operation optimization method as described in the preceding embodiments is implemented.

[0068] Similarly, the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0069] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0070] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0071] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0073] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0074] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0075] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0076] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A non-volatile memory read operation optimization system, characterized in that, The system includes: a storage unit, a real-time frequency detection circuit, a read instruction unit, and a system control module; The system control module receives the real-time clock frequency sent by the real-time frequency detection circuit, obtains the current clock frequency range, and adjusts the internal circuit of the non-volatile memory according to the current clock frequency range. The read instruction unit is used to identify the instruction information for reading memory and apply high voltage to the storage unit gate; The system also includes a sensitive amplifier comparator, a charge pump, a reference voltage circuit, and a reference current circuit. The system control module adjusts the internal circuitry of the non-volatile memory according to the current clock frequency range, including: When the current clock frequency is lower than the first preset value, the system control module shuts down the BOOST circuit during the non-working phase of the sensitive amplifier comparator. When the current clock frequency is lower than the second preset value, the system control module shuts down the charge pump, the reference voltage circuit, and the reference current circuit during the non-operation phase of the sensitive amplifier comparator.

2. The non-volatile memory read operation optimization system according to claim 1, characterized in that, When the current clock frequency is lower than the third preset value, the system control module adjusts the operating timing of the sensitive amplifier comparator and increases the operating duration of the sensitive amplifier comparator at low frequencies.

3. The non-volatile memory read operation optimization system according to claim 1, characterized in that, The system control module selects to shut down different modules to reduce power consumption based on the read instruction I / O time frequency obtained from the real-time frequency detection circuit, the chip communication protocol interface, and the restart establishment time of each power source module.

4. A method for optimizing read operations of non-volatile memory, characterized in that, The method, applied to a non-volatile memory read operation optimization system according to any one of claims 1 to 3, comprises: The system receives the real-time clock frequency sent by the real-time frequency detection circuit, obtains the current clock frequency range, and adjusts the internal circuitry of the non-volatile memory according to the current clock frequency range. Increase the height of the gate of the storage unit; The internal circuitry for adjusting the non-volatile memory according to the current clock frequency range includes: When the current clock frequency is lower than the first preset value, the BOOST circuit is turned off during the non-operating phase of the sensitive amplifier comparator. When the current clock frequency is lower than the second preset value, the charge pump, the reference voltage circuit, and the reference current circuit are turned off during the non-operation phase of the sensitive amplifier comparator.

5. The method for optimizing non-volatile memory read operations according to claim 4, characterized in that, The method further includes: When the current clock frequency is lower than the third preset value, the operating timing of the sensitive amplifier comparator is adjusted to increase the operating duration of the sensitive amplifier comparator at low frequencies.

6. A non-volatile memory read operation optimization device, characterized in that, The apparatus employs the method of claim 4; the apparatus comprises: The first module is used to receive the real-time clock frequency sent by the real-time frequency detection circuit, obtain the current clock frequency range, and adjust the internal circuit of the non-volatile memory according to the current clock frequency range. The second module is used to apply high voltage to the gate of the storage unit; The internal circuitry for adjusting the non-volatile memory according to the current clock frequency range includes: When the current clock frequency is lower than the first preset value, the BOOST circuit is turned off during the non-operating phase of the sensitive amplifier comparator. When the current clock frequency is lower than the second preset value, the charge pump, the reference voltage circuit, and the reference current circuit are turned off during the non-operation phase of the sensitive amplifier comparator.

7. A non-volatile memory read operation optimization device, characterized in that, The device includes: At least one processor; At least one memory for storing at least one program; When at least one of the programs is executed by at least one of the processors, a non-volatile memory read operation optimization method as described in any one of claims 4-5 is implemented.

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