Semiconductor memory device

Abstract

A semiconductor memory device capable of low power consumption and high integration is provided. A nonvolatile semiconductor memory of the present invention includes a memory cell array formed on a substrate with a NOR type array having a NOR type flash memory structure and a resistance change type array having a resistance change type memory structure. An access gate is formed between the NOR type array and the resistance change type array, and separates the resistance change type array from the NOR type array when the NOR type array is accessed.

Description

Technical Field

[0001] This invention relates to a semiconductor storage device that combines NOR flash memory and resistance-varying memory. Background Technology

[0002] NOR flash memory is a non-volatile memory that uses a storage cell between the bit line and the source line, allowing random access to the storage cell.

[0003] On the other hand, as a non-volatile memory to replace NOR-type flash memory, a resistance-varying type memory with a variable resistance element is used. The resistance-varying type memory stores data by applying a pulse voltage to the variable resistance element, causing the variable resistance element to reversibly and non-volatilely change to a high resistance state or a low resistance state. Summary of the Invention

[0004] Unlike NOR flash memory, resistive variable memory does not require erasure, so data can be rewritten at low voltage. However, the cell size of resistive variable memory is smaller than that of NOR flash memory. If the integration density is increased, the cost-performance ratio will decrease.

[0005] The purpose of this invention is to provide a semiconductor memory device that can achieve low power consumption and high integration.

[0006] [Technical means to solve the problem]

[0007] The semiconductor memory device of the present invention includes a memory cell array, wherein a first memory cell array having a resistance-varying memory structure and a second memory cell array having a NOR flash memory structure are formed on the same substrate, and the first memory cell array or the second memory cell array can be accessed.

[0008] In one embodiment, a plurality of global bit lines extending along the column direction of a memory cell array are formed. These global bit lines are shared by a first memory cell array and a second memory cell array. At the boundary between the first and second memory cell arrays, a first connection member is formed to selectively connect the global bit lines to the first memory cell array. In one embodiment, when accessing the second memory cell array, the first connection member separates the first memory cell array from the global bit lines; when accessing the first memory cell array, it connects the first memory cell array to the global bit lines. In one embodiment, the second memory cell array includes a plurality of sectors along the column direction, each sector including a second connection member that selectively connects the sector to the global bit lines. In one embodiment, the semiconductor memory device further includes a sector selection member that selects sectors based on address information. The second connection member connects the sectors selected by the sector selection member to the global bit lines and disconnects unselected sectors from the global bit lines. In one embodiment, a first connecting component divides a global bit line into a plurality of local bit lines with a first spacing, and a second connecting component divides a global bit line into a plurality of local bit lines with a spacing equal to half the first spacing. In one embodiment, the first connecting component includes S transistors connected in parallel between a global bit line and S sacrificial local bit lines, and forms S / 2 local bit lines by short-circuiting adjacent sacrificial local bit lines. The second connecting component includes S transistors connected in parallel between a global bit line and S local bit lines. The transistors of the first connecting component and the transistors of the second connecting component have the same size. In one embodiment, the semiconductor memory device further includes: a word line selection component for selecting word lines of a memory cell array; a bit line selection component for selecting global bit lines of the memory cell array; and a read / write control component for reading and writing memory cells selected by the word line selection component and the bit line selection component.

[0009] [The effects of the invention]

[0010] According to the present invention, the memory cell array includes a first memory cell array having a resistance-varying memory structure and a second memory cell array having a NOR flash memory structure, thereby enabling high integration and low power consumption of semiconductor memory devices. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating the overall structure of a non-volatile memory according to an embodiment of the present invention;

[0012] Figure 2A , Figure 2B This is a schematic diagram illustrating the structure of a storage cell array according to an embodiment of the present invention;

[0013] Figure 3This is a circuit diagram of a portion of a NOR-type memory cell array according to an embodiment of the present invention;

[0014] Figure 4 This is a circuit diagram of a portion of a resistance-varying memory cell array according to an embodiment of the present invention;

[0015] Figure 5 This is a schematic partial cross-sectional view of a NOR-type memory cell array according to an embodiment of the present invention;

[0016] Figure 6 This is a schematic partial cross-sectional view of a resistance-varying memory cell array according to an embodiment of the present invention.

[0017] [Explanation of Symbols]

[0018] 100: Non-volatile memory

[0019] 110: Storage Cell Array

[0020] 110A: NOR array (first memory cell array)

[0021] 110B: Resistance Variation Array (Second Storage Cell Array)

[0022] 110C: Entering the gate

[0023] 110D: Sector Selection Grille

[0024] 120: Address Buffer

[0025] 130: Gate Selection Circuit

[0026] 140: Word Line Decoder

[0027] 150: Y Decoder

[0028] 160: Input / Output Circuit

[0029] 170: Read / Write Control Department Detailed Implementation

[0030] The present invention integrates a memory cell array with a NOR flash memory structure and a memory cell array with a resistance-varying memory structure on a common substrate.

[0031] Next, the non-volatile memory of an embodiment of the present invention will be described in detail. Figure 1This is a block diagram showing the overall structure of the non-volatile memory 100 of this embodiment. As shown in this figure, the non-volatile memory 100 is constructed, for example, by integrating a memory cell array 110, an address buffer 120, a sector / gate selection circuit 130, a word line decoder 140, a Y decoder 150, an input / output circuit 160, and a read / write control unit 170 on a substrate such as silicon. Each component is connected via an internal bus capable of transmitting and receiving address, data, control signals, etc. The main structure is shown in this figure; voltage generation circuits, etc., are omitted.

[0032] The memory cell array 110 includes: a first memory cell array (hereinafter referred to as the NOR array) 110A having a NOR flash memory structure; and a second memory cell array (hereinafter referred to as the resistance-varying array) 110B having a resistance-varying memory structure. Compared with the resistance-varying array 110B, the NOR array 110A can achieve high integration, and compared with the NOR array 110A, the resistance-varying array 110B can achieve low-power operation.

[0033] Figure 2A This is a schematic plan view illustrating the structure of the memory cell array. The memory cell array 110 includes a NOR-type array 110A and a resistance-variable array 110B along the column direction. The memory size of the NOR-type array 110A or the resistance-variable array 110B is not particularly limited; for example, the NOR-type array 110A is 16MB and the resistance-variable array 110B is 1Mb.

[0034] NOR array 110A includes multiple sectors (or blocks) 0, 1, ... P along the column direction as erase units. Each sector includes an LBL selection gate 110D, which selects a local bit line LBL extending along the column direction within the sector. An entry gate 110C is formed between the last sector P of NOR array 110A and resistance-varying array 110B. The entry gate 110C selects a local bit line extending along the column direction within resistance-varying array 110B and, when NOR array 110A is accessed, causes resistance-varying array 110B to separate from NOR array 110A.

[0035] Multiple global bit lines GBL0, GBL1, GBL2, ..., GBLm (collectively referred to as global bit lines GBL) are formed along the column direction of the storage cell array 110. The global bit lines GBL are connected to the LBL selection gate 110D of each sector of the NOR array 110A and to the entry gate 110C. That is, the global bit lines GBL are shared by the NOR array 110A and the resistance-varying array 110B.

[0036] Figure 2B Is Figure 2A The plan view shows the word lines and select signal lines. Multiple word lines are formed along the row direction of the memory cell array 110. Word lines WL00 to WL0n are formed along the row direction of sector 0, word lines WL10 to WL1n are formed along the row direction of sector 1, similarly, word lines WLP0 to WLPn are formed along the row direction of sector P, and word lines WLQ0 to WLQj are formed along the row direction of the resistance variation array 110B.

[0037] For the LBL select gate 110D of sector 0, a 4-bit select signal line SEL_0[0:3] is supplied from the sector / gate select circuit 130; for the LBL select gate 110D of sector 1, a select signal line SEL_1[0:3] is supplied; similarly, for the LBL select gate 110D of sector P, a select signal line SEL_P[0:3] is supplied; and for the entry gate 110C, a select signal line SEL_Q[0:3] is supplied. As described later, the sector / gate select circuit 130 selects a sector of the NOR array 110A or a resistance-variable array 110B by a portion of the row address (the upper bit), supplying a select signal line to the LBL select gate 110D corresponding to the selected sector or resistance-variable array 110B, or supplying a select signal line to the entry gate 110C.

[0038] Figure 3 The circuit structure representing a portion of sector 0. Figure 4 This represents the circuit structure of a portion of the gate 110C and the resistance-varying array 110B. For example... Figure 3 As shown, the LBL selection gate 110D extends along the row direction to divide a global bit line GBL into four local bit lines LBL0 to LBL3. That is, m global bit lines GBL are divided into m×4 lines by the LBL selection gate 110D.

[0039] Four NMOS transistors Q0, Q1, Q2, and Q3 are connected in parallel between a global bit line GBL and four local bit lines LBL0 to LBL3. A row-extending select signal line SEL0 is connected to the gates of transistors Q0, SEL1 to SEL2 to SEL3 to SEL3 to SEL3 to SEL4 to Q3.

[0040] The sector / gate selection circuit 130 selects a sector according to the upper bit of the row address, and drives any one of the selection signal lines SEL_0[0:3] connected to the LBL selection gate 110D of the sector selected according to the column address to H level, and drives the remaining selection signal lines to L level. For example, the selection signal line SEL0 is driven to H level, and the remaining selection signal lines SEL1 to SEL3 are driven to L level. As a result, m transistors Q0 of the LBL selection gate 110D are turned on, and m global bit lines GBL are selectively connected to the corresponding m local bit lines LBL0. On the other hand, transistors Q1 to Q3 are turned off, and local bit lines LBL1 to LBL3 are separated from the global bit lines.

[0041] Within each sector, multiple memory cells are formed in a matrix configuration. The drain regions of adjacent memory cells along the column direction are connected together and connected to a local bit line. Furthermore, the gates of memory cells along the row direction are connected to a word line along the row direction, and the source regions of memory cells along the row direction are connected to a source line along the row direction. For example, the gates of memory cells MC0 and MC1 are connected to word lines WL00 and WL01, respectively; the common drain region of memory cells MC0 and MC1 is connected to a local bit line LBL0; the source region of memory cell MC0 is connected to source line SL00; and the source region of memory cell MC1 is connected to source line SL01. The sector / gate selection circuit 130 selects the source line of the sector selected according to the column address and applies an operating voltage to the source line selected under the control of the read / write control unit 170.

[0042] Storage cells, for example, comprise an oxide-nitride-oxide (ONO) film on the substrate surface that functions as an accumulation region for trapping charge. A conductive gate, such as polysilicon or a metal, is then present on this ONO film. Data can be programmed by trapping hot electrons generated when current flows between the source and drain regions into the ONO film. However, alternatively, charge can also be trapped into the ONO film via Fowler-Nordheim (FN) tunneling. The trapped charge can be erased, for example, via FN tunneling or hot hole injection.

[0043] Figure 5This diagram shows a schematic cross-section of memory cells MC0 and MC1 along the column direction. Within a P-type silicon substrate or P-well region 200, memory cells MC0 and MC1 are formed in an active region formed by field oxide or trench isolation. The gates of memory cells MC0 and MC1 constitute word lines WL00 and WL01 in the row direction. The drain regions of memory cells MC0 and MC1 are shared and are electrically connected to the local bit line LBL0 in the column direction via a via contact V0. The source regions of memory cells MC0 and MC1 are electrically connected to the source lines SL00 and SL01 in the row direction via a via contact V1. In this example, the source lines are formed by a conductive layer on the substrate, but this is not a limitation; they can also be formed by an embedded diffusion region within the substrate. In this case, the source regions of the memory cells in the row direction are interconnected.

[0044] Furthermore, in the active region adjacent to the storage cell MC0, a transistor Q0 is formed as the LBL select gate 110D. The gate of transistor Q0 constitutes the row-direction select signal line SEL0, the drain region is electrically connected to the column-direction global bit line GBL0 via the contact via V2, and the source region is electrically connected to the local bit line LBL0 via the contact via V0.

[0045] The multiple local bit lines LBL0 to LBL3 formed by the LBL selection gate 110D are connected to the common drain region of the last memory cell WL0n-1 and memory cell WL0n in sector 0, and terminate here. Other sectors 1 to P are constructed in the same way as sector 0.

[0046] Next, the entry gate 110C will be described. The entry gate 110C is as follows... Figure 2A , Figure 2B As shown, the last sector P of the NOR array 110A forms the boundary with the resistance variation array 110B. The gate 110C is constructed by transistors Q0 to Q3 of the same size as the gate width and gate length of the LBL select gate 110D. However, unlike the LBL select gate 110D, it is connected to the global bit line GBL by dividing a global bit line GBL into two local bit lines LBL0 and LBL1.

[0047] Figure 4This represents the circuit structure of the entry gate 110C and a portion of the resistance-varying array 110B. The entry gate 110C includes transistors Q0 to Q3 connected in parallel between a global bit line GBL and four sacrificial local bit lines S_LBL0 to S_LBL3. At the gates of transistors Q0 to Q3, select signal lines SEL_Q[0:3] from the sector / gate select circuit 130 are connected.

[0048] Local bit line LBL0 is formed by short-circuiting the sacrificial local bit line S_LBL0 and its adjacent sacrificial local bit line S_LBL1, and local bit line LBL1 is formed by short-circuiting the sacrificial local bit line S_LBL2 and its adjacent sacrificial local bit line S_LBL3.

[0049] With this structure, the spacing between local bit lines LBL0 / LBL1 in the resistance-varying array 110B is twice that of the spacing between local bit lines LBL0 / LBL1 and LBL2 / LBL3 in the NOR array 110A. Furthermore, two transistors are connected in parallel on each local bit line at the gate 110C, thus the current that can be supplied to a local bit line of the resistance-varying array 110B is twice that that can be supplied to a local bit line of the NOR array 110A. The reason for making the spacing between local bit lines in the resistance-varying array 110B larger than that in the NOR array 110A is that the size of a resistance-varying memory cell is difficult to reduce to the size of a NOR memory cell. Moreover, the reason for increasing the current supplied to the local bit lines of the resistance-variable array 110B is that the maximum current flowing through the resistance-variable memory cell may be nearly twice that of the maximum current flowing through the NOR-type memory cell (e.g., tunneling hot electron current).

[0050] In the resistance-variable array 110B, multiple memory cells are formed in a matrix. Each memory cell comprises an access transistor and a variable resistor. The gates of the access transistors in the row direction are connected to the word line in the row direction, and the source regions of a pair of adjacent access transistors in the column direction are connected to the corresponding source line. One electrode of the variable resistor is connected to the drain region of the access transistor, and the other electrode of the variable resistor is connected to the local bit line. For example, the gates of memory cells MC0 and MC1 are connected to word lines WLQ0 and WLQ1, the common source region of memory cells MC0 and MC1 is connected to the source line SLQ0, the drain region of memory cell MC0 is connected to the local bit line LBL0 via the variable resistor, and the drain region of memory cell MC1 is connected to the local bit line LBL0 via the variable resistor.

[0051] The variable resistance element, for example, is a thin-film oxide containing transition elements such as hafnium oxide (HfOx), and is set or reset according to the polarity and magnitude of the write pulse voltage. For example, the variable resistance element is set to a low resistance state when current flows from the bit line side to the source line side, and reset to a high resistance state when current flows from the source line side to the bit line side.

[0052] Figure 6 This is a schematic cross-section of memory cells MC0 and MC1 along the column direction. Within a P-type silicon substrate or P-well region 200, memory cells MC0 and MC1 are formed in an active region isolated by a field oxide film or trench. The gates of the access transistors in memory cells MC0 and MC1 form word lines WLQ0 and WLQ1 in the row direction, respectively. The common source region of the access transistors is electrically connected to the source line SLQ0 in the row direction via a contact via V1. The drain region of the access transistor in memory cell MC0 is connected to a variable resistor element VR0 via a contact via V1, and furthermore, the variable resistor element VR0 is electrically connected to the local bit line LBL0 in the column direction via a contact via V3. The drain region of the access transistor in memory cell MC1 is connected to the variable resistor element VR1 via a contact via V1, and furthermore, the variable resistor element VR1 is electrically connected to the local bit line LBL0 via a contact via V3.

[0053] In the active region adjacent to the storage cell MC0, a transistor Q0 is formed that enters the gate 110C. The gate of transistor Q0 forms the row direction selection signal line SEL0, the drain region is electrically connected to the global bit line GBL0 via the contact via V2, and the source region is electrically connected to the local bit line LBL0 via the contact via V0.

[0054] The storage cell array 110 is formed by a multi-layer wiring structure, but as Figure 5 , Figure 6 As shown, it is understood that the resistance variation array 110B and the entry gate 110C are structures compatible with the NOR array 110A.

[0055] Refer again Figure 1 Address buffer 120 receives addresses from the address bus (not shown) and provides the received row and column addresses to sector / gate selection circuit 130 and Y decoder 150. Sector / gate selection circuit 130 selects a sector or entry gate 110C based on the row address, driving the selection signal lines SEL0 to SEL3 of the sector or entry gate 110C selected based on the column address to H or L levels. Furthermore, sector / gate selection circuit 130 applies an operating voltage to the source lines of the sector or resistance-varying array 110B selected according to the column address. This operating voltage is controlled by read / write control unit 170.

[0056] The Y decoder 150 selects global bit lines GBL0 to GBLm based on the column address. For the selected global bit line GBL, the read voltage, programming voltage, erase voltage, etc. are applied according to the control of the read / write control unit 150.

[0057] The word line decoder 140 receives the row address from the address buffer 120 and selects the word line WL based on the decoding result of the received row address. For word line selection, read voltage, programming (write) voltage, erase voltage, etc., are supplied according to the control of the read / write control unit 170. Furthermore, when all data in the memory cells within a sector of the NOR array 110A is erased, all word lines within the sector are selected.

[0058] The input / output circuit 160 outputs data read from the memory cell array 110 to an external terminal, or writes data received from the external terminal to the memory cell. Furthermore, it provides the address received from the external terminal to the address buffer 120 and provides commands to the read / write control unit 170.

[0059] The read / write control unit 170 includes, for example, a state machine or microcontroller, a read amplifier, a write amplifier, etc., and controls the overall operation of the non-volatile memory 100. The read / write control unit 170 interprets the commands received from the input / output circuit 160 and performs read, write, and erase operations based on the interpretation results.

[0060] The read / write control unit 170 can also control the read and write operations of the resistance-varying array 110B based on commands used for the NOR flash memory. However, in a resistance-varying memory, there is no concept of erasure. Therefore, the read / write control unit 170 recognizes access to the resistance-varying array 110B from a row address, and upon receiving an erase command, the resistance-varying array 110B performs a data overwrite that sets all memory cells to data "1". Of course, the user can also input the commands used when accessing the NOR array 110A and the commands used when accessing the resistance-varying array 110B separately into the non-volatile memory 100.

[0061] Next, the operation of the non-volatile memory 100 in this embodiment will be described.

[0062] [Read the action]

[0063] When commands and addresses are read from external terminals, the word line decoder 140 selects the word line according to the row address, and the sector / gate selection circuit 130 selects the sector or the entry gate 110C based on the row address. It drives the selection signal lines SEL0 to SEL3 of the LBL selection gate 110D or the selection signal lines SEL0 to SEL3 of the entry gate 110C for the selected sector, and selects the source SL according to the column address. The Y decoder 150 selects the global bit line according to the column address. During access to the NOR array 110A, the sector / gate selection circuit 130 sets the entry gate 110C to non-select (all selection signal lines SEL0 to SEL3 are at L level), thus separating the resistance-varying array 110B from the NOR array 110A.

[0064] For example, in Figure 3 When the storage cell Ma is selected, a readout voltage is applied to the select word line WL01, and GND is supplied to the source line SL01. Furthermore, the LBL select gate 110D drives the select signal line SEL2 to a high level, turning on transistor Q2. The Y decoder 150 selects the global bit line GBL0, and the read / write control unit 170 applies a readout voltage to the global bit line GBL0. The storage cell Ma is turned on / off by a threshold corresponding to the stored data, and the readout amplifier senses the voltage or current of the global bit line GBL0.

[0065] Moreover, in Figure 4 When the memory Mb shown is selected, a read voltage is applied to the select word line WLQ1, the access transistor is turned on, and GND is supplied to the source line SLQ0 selected by the sector / gate selection circuit 130. Furthermore, the sector / gate selection circuit 130 drives the select signal line SEL2 entering the gate 110C to a high level, turning on transistor Q2. The Y decoder 150 selects the global bit line GBL0, and the read / write control unit 170 applies a read voltage to the global bit line GBL0. Depending on whether the variable resistor element is in a low-resistance state or a high-resistance state, the current flowing from the global bit line GBL0 to the source line SLQ0 differs, and this voltage or current is sensed by the read amplifier.

[0066] [Write action]

[0067] When writing data "0" to memory cell Ma of NOR array 110A, read / write control unit 170 applies a write voltage to select word line WL02, applies a write voltage to the selected global bit line GBL0, and applies GND to the selected source line SL01. Conversely, when writing data "0" to memory cell Mb of resistivity-varying array 110B, write voltage is applied to select word line WLQ2 to turn on the access transistor, a write voltage is applied to the selected global bit line GBL0, and GND is applied to the selected source line SL01.

[0068] [Erase action]

[0069] When erasing a sector of the NOR array 110A, all word lines of the selected sector are selected, and GND is applied to the selected word lines. Furthermore, the sector / gate selection circuit 130 turns off all transistors Q0 to Q3 of the selected LBL selection gate 110D, sets local bit lines LBL0 to LBL3 to a floating state, and applies an erase voltage to all source lines within the selected sector. As a result, a high voltage is applied between the gate and source regions of all memory cells within the sector, causing electrons in the memory cells to escape to the source side, lowering the threshold of the memory cell, and changing the data to "1".

[0070] On the other hand, in the case of the resistance-variable array 110B, the word line decoder 140 selects all word lines of the resistance-variable array 110B, turning on all access transistors. The gate 110C turns on all transistors Q0 to Q3, connecting all local bit lines LBL0 and LBL1 to the global bit line GBL. The read / write control unit 170 applies GND to the global bit line GBL to write the data "1" to all variable resistance elements, and the sector / select gate 130 applies a write voltage to the source lines SLQ1 to SLQk.

[0071] Thus, according to this embodiment, when the NOR array 110A and the resistance-varying array 110B are integrated on the memory cell array 110, by setting an entry gate 110C at the boundary between the NOR array 110A and the resistance-varying array 110B, it is possible to prevent stress caused by unwanted voltage from affecting the resistance-varying array 110B via the global bit line GBL, etc., when the NOR array 110A is running.

[0072] Moreover, by incorporating both the NOR array 110A and the resistance variation array 110B, it is possible to combine the advantages of high integration offered by the NOR array 110A with the advantages of low-power operation offered by the resistance variation array 110B.

[0073] In the described embodiment, the LBL select gate 110D divides a global bit line into four local bit lines, but this is just one example; the number of local bit lines divided from a global bit line is arbitrary. Furthermore, the spacing between the local bit lines divided by the entry gate 110C is set to be twice the spacing between the local bit lines divided by the LBL select gate 110D, but this is just one example; the spacing between the local bit lines divided by the entry gate 110C only needs to be greater than the spacing between the local bit lines divided by the LBL select gate 110D. Furthermore, the size of the transistor entering the gate 110C is made equal to the size of the transistor in the LBL select gate, but this is just one example; the gate width of the transistor entering the gate 110C can also be greater than the gate width of the transistor in the LBL select gate 110D.

[0074] Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments. Various modifications and alterations can be made within the scope of the spirit of the present invention as set forth in the claims.

Claims

1. A semiconductor memory device, characterized in that, The system includes a memory cell array, wherein a first memory cell array having a resistance-varying memory structure and a second memory cell array having a NOR flash memory structure are formed on the same substrate. Furthermore, it can access either the first storage cell array or the second storage cell array. Multiple global bit lines are formed, extending along the column direction of the storage cell array. The second storage cell array includes multiple sectors along the column direction, and each sector includes a second connection component that selectively connects the sector to the global bit line. The first connecting component divides a global bit line into a plurality of local bit lines with a first spacing, and the second connecting component divides a global bit line into a plurality of local bit lines with a spacing of half the first spacing.

2. The semiconductor memory device according to claim 1, characterized in that, The multiple global bit lines are shared by the first storage cell array and the second storage cell array. At the boundary between the first memory cell array and the second memory cell array, a first connection component is formed to selectively connect the global bit line to the first memory cell array.

3. The semiconductor memory device according to claim 2, characterized in that, When the first connection component accesses the second storage cell array, it separates the first storage cell array from the global bit line; when it accesses the first storage cell array, it connects the first storage cell array to the global bit line.

4. The semiconductor memory device according to claim 1, characterized in that, The semiconductor memory device also includes a sector selection component for selecting sectors based on address information. The second connection component connects the sector selected by the sector selection component to the global bit line and disconnects the unselected sector from the global bit line.

5. The semiconductor memory device according to claim 1, characterized in that, The first connection component includes S transistors connected in parallel between one global bit line and S sacrificial local bit lines, and forms S / 2 local bit lines by short-circuiting adjacent sacrificial local bit lines. The second connection component includes S transistors connected in parallel between one global bit line and S local bit lines. The transistor in the first connection component has the same size as the transistor in the second connection component.

6. The semiconductor memory device according to any one of claims 1 to 3, characterized in that, The semiconductor memory device further includes: The word line selection component selects the word line of the storage cell array; The bit line selection component selects the global bit lines of the storage cell array; and The read / write control unit performs read and write operations on the memory cells selected by the word line selection unit and the bit line selection unit.

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