Drift-aware read operation

Abstract

Embodiments of the present disclosure relate to drift-aware read operations. Systems, methods, and apparatus to read a target memory cell having an associated reference memory cell configured to represent a drift or change in a threshold voltage of the target memory cell. The reference cell is programmed to a predetermined threshold level while the target cell is programmed to store data. In response to a command to read the target memory cell, an estimate of the drift in the threshold voltage of the reference is performed in parallel with the application of an initial voltage pulse to read the target cell. Based on the results of the drift estimate, the voltage pulse used to read the target cell can be modified and / or added to account for the drift estimated using the reference cell.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein relate generally to memory systems, and more precisely, but not limited to, techniques for reading memory cells to retrieve data. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices.

[0003] A memory device may include a memory integrated circuit having one or more arrays of memory cells formed on an integrated circuit die of semiconductor material. A memory cell is the smallest unit of memory that can be individually used or operated to store data. Generally, a memory cell can store one or more data bits.

[0004] Different types of memory cells have been developed for memory integrated circuits, such as random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and flash memory.

[0005] Some integrated circuit memory cells are volatile and require power to maintain the data stored in the cells. Examples of volatile memory include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).

[0006] Some integrated circuit memory cells are non-volatile and retain stored data even when no power is supplied. Examples of non-volatile memories include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). Flash memory includes NAND flash memory and NOR flash memory. NAND memory cells are based on NAND logic gates; and NOR memory cells are based on NOR logic gates.

[0007] Crosspoint memory (e.g., 3D XPoint memory) uses an array of non-volatile memory cells. The memory cells in crosspoint memory are transistorless. Each of these memory cells may have selector devices and optionally phase-change memory devices stacked together as columns in an integrated circuit. Such columns of memory cells are connected in the integrated circuit via two layers of wires extending in mutually perpendicular directions. One layer is above the memory cell; and the other layer is below the memory cell. Therefore, each memory cell can be individually selected at the intersection of the two wires extending in different directions in the two layers. Crosspoint memory devices are fast and non-volatile and can be used as a general-purpose memory pool for processing and storage.

[0008] During a programming / writing operation, a non-volatile integrated circuit memory cell is programmed to store data by applying a voltage or a pattern of voltage to the memory cell. The programming / writing operation sets the memory cell in a state corresponding to the data being programmed / stored into the memory cell. Data stored in the memory cell can be retrieved during a read operation by checking the state of the memory cell. The read operation determines the state of the memory cell by applying a voltage and determining whether the memory cell becomes conductive at a voltage corresponding to a predefined state. Summary of the Invention

[0009] According to one embodiment of this disclosure, an apparatus is provided. The apparatus includes: a memory cell; a voltage driver connected to the memory cell; and a controller coupled to the voltage driver and configured to operate on the memory cell using the voltage driver. The memory cell includes a first set of memory cells and at least one second memory cell. In response to a command to write data items to the first set of memory cells, the controller is configured to use the voltage driver to program a threshold voltage of the first memory cell according to the data items, and to program a threshold voltage of the second memory cell to a level within a predetermined voltage range. In response to a command to read the first set of memory cells, the controller is configured to estimate a drift of the threshold voltage of the second memory cell in parallel with applying a first read voltage to the first memory cell, and to modify the operation of reading the first memory cell using the voltage driver based on the drift estimated during the application of the first read voltage to the first memory cell.

[0010] According to another embodiment of this disclosure, a method is provided. The method includes: receiving a first command for writing data items into a first set of memory cells in a memory device; in response to the first command: driving one or more voltage pulses on the first memory cells to program a threshold voltage of the first memory cells according to the data items; and driving one or more voltage pulses on a second memory cell associated with the first set of memory cells in the memory device to program the threshold voltage of the second memory cell into a predetermined voltage region recognizable by a first read voltage; receiving a second command for reading the first set of memory cells; and in response to the second command: driving a voltage applied to the first memory cell to reach a first read voltage; and identifying a first memory cell having a threshold voltage lower than the first read voltage. A subset; driving a voltage applied to a second memory cell to a second read voltage in parallel with driving a voltage applied to a first memory cell to a first read voltage; determining, in parallel with identifying the first subset, that a threshold voltage of the second memory cell has drifted into a voltage region between the first read voltage and the second read voltage; and, in response to the threshold voltage of the second memory cell being between the first read voltage and the second read voltage, applying a third read voltage to the first memory cell, the magnitude of the third voltage being based on the second read voltage; and identifying a second subset of the first memory cells having a threshold voltage lower than the first read voltage; and determining, based on the identification of the second subset, the result of reading the first memory cell as a response to a second command.

[0011] According to another embodiment of this disclosure, an integrated circuit is provided. The integrated circuit includes: a bit line layer; a word line layer; memory cells disposed between the bit line layer and the word line layer, each of the memory cells being connected to a bit line among the bit lines and a word line among the word lines; a bit line driver connected to the bit line; a word line driver connected to the word line; and a controller coupled to the bit line driver and the word line driver, and configured to, in response to a command for retrieving data from a first memory cell among the memory cells, simultaneously detect a drift in a threshold voltage of a second memory cell associated with the first memory cell by applying a first read voltage to the first memory cell via the bit line driver and the word line driver; if no drift is detected in the threshold voltage of the second memory cell, determine a value programmed into the first memory cell based on whether the first memory cell is conductive under the first read voltage; and if a drift having a scale represented by a second read voltage is detected in the threshold voltage of the second memory cell, apply a third read voltage based on the second read voltage to determine a value programmed into the first memory cell based on whether the first memory cell is conductive under the third read voltage. Attached Figure Description

[0012] The embodiments are illustrated in the accompanying drawings by way of example rather than limitation, and similar reference numerals indicate similar elements in the drawings.

[0013] Figure 1 A memory device configured to have a read manager is shown according to one embodiment.

[0014] Figure 2 A memory cell having a bit line driver and a word line driver configured to apply voltage pulses is shown according to one embodiment.

[0015] Figure 3 This demonstrates a technique for executing a read command according to one embodiment.

[0016] Figure 4 and 5 This demonstrates a drift-aware reading operation according to one embodiment.

[0017] Figure 6 A method for reading a memory cell is shown according to one embodiment.

[0018] Figure 7 This describes an example computing system having a memory subsystem according to some embodiments of the present disclosure.

[0019] Figure 8 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0020] At least some aspects of this disclosure relate to a memory subsystem configured to estimate drift in the state of memory cells in parallel with reading memory cells. Based on the estimation results, additional optional operations can be selected and performed to obtain data from the memory cells with improved accuracy.

[0021] The memory subsystem can be used as a storage device and / or memory module. (The following text is in conjunction with...) Figure 7 Describe examples of storage devices, memory modules, and memory devices. A host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0022] Integrated circuit memory cells, such as memory cells in flash memory or memory cells in cross-point memory, can be programmed to store data by means of their state under voltage applied across the memory cell.

[0023] For example, if a memory cell is configured or programmed to be in such a state that allows a large current to pass through the memory cell at a voltage within a predefined voltage range, then the memory cell is considered to be configured or programmed to store a first bit value (e.g., one); and otherwise, the memory cell stores a second bit value (e.g., zero).

[0024] Optionally, the memory cell may be configured or programmed to store more than one data bit by being configured or programmed to have a threshold voltage in one of more than two separate voltage regions.

[0025] A threshold voltage for a memory cell causes it to rapidly or abruptly change, jump, or hop from a non-conductive state to a conductive state when the voltage applied across the memory cell increases above the threshold voltage. The non-conductive state allows a small leakage current to pass through the memory cell; conversely, the conductive state allows current greater than the threshold amount to pass through. Therefore, a memory device can use sensors to detect changes in or determine the conductive / non-conductive state of the memory device under one or more applied voltages to assess the level of the threshold voltage of the memory cell and thus the data stored therein.

[0026] Threshold voltages of memory cells configured / programmed in different voltage regions can be used to represent different data values ​​stored in the memory cell. For example, the threshold voltage of a memory cell can be programmed in any of four predefined voltage regions; and each region can be used to represent the bit value of a different two-bit data item. Therefore, given a two-bit data item, one of the four voltage regions can be selected based on the mapping between the two-bit data item and the voltage region; and the threshold voltage of the memory cell can be adjusted, programmed, or configured to represent or store the given two-bit data item in the selected voltage region. To retrieve, identify, or read a data item from a memory cell, one or more read voltages can be applied across the memory cell to determine which of the four voltage regions contains the threshold voltage of the memory cell. Identification of the voltage region containing the threshold voltage of the memory cell provides information about two-bit data items that have been stored, programmed, or written to the memory cell.

[0027] For example, a memory cell can be configured or programmed to store one data item in a single-level cell (SLC) mode, two data items in a multi-level cell (MLC) mode, three data items in a three-level cell (TLC) mode, four data items in a four-level cell (QLC) mode, or five data items in a five-level cell (PLC) mode.

[0028] The threshold voltage of a memory cell can change or drift over time, during use, and / or read operations, and in response to certain environmental factors, such as temperature changes. As memory cells age, the rate of change or drift can increase. This change or drift can lead to errors in determining, retrieving, or reading data items from the memory cell.

[0029] Redundancy information can be used to detect and correct random errors when reading memory cells. Data to be stored in a memory cell can be encoded to include redundancy information to facilitate error detection and recovery. When data encoded with redundancy information is stored in the memory subsystem, the memory subsystem can detect errors in the data represented by a voltage region of the threshold voltage of the memory cell and / or recover the original data used to generate the threshold voltage for programming the memory cell. Recovery operations can be successful (or have a high probability of success) when the data represented by the threshold voltage of the memory cell and therefore retrieved directly from the memory cell in the memory subsystem contains fewer errors or has a low bit error rate, and / or when the amount of redundancy information is high. For example, techniques such as error-correcting codes (ECC), low-density parity-check (LDPC) codes, etc., can be used to perform error detection and data recovery.

[0030] When data retrieved from a memory cell in the memory subsystem contains too many errors to be successfully decoded, the memory subsystem may retry the execution of the read command. This can cause considerable delays when retrieving data from the memory cell and degrade the overall read performance of the memory subsystem.

[0031] Several techniques have been developed to estimate the state drift of memory cells and to use these estimates to calibrate the read voltage of a voltage region used for testing and classifying memory cells. Using a calibrated read voltage improves the accuracy of determining the data represented by the threshold voltage of the memory cell. However, the calibration operation can increase the latency of the read operation (e.g., in cases where the drift is small and calibration is therefore optional).

[0032] At least some aspects of this disclosure address the above and other drawbacks by performing read operations on memory cells in parallel with evaluating the drift of the state of a memory cell using a reference cell. The reference cell is configured to have a drift similar to that of the memory cell. When the drift in the reference cell is small, the drift evaluation has no effect on the reads of the memory cell, and therefore no effect on the latency of reading the memory cell. When the drift in the reference cell is large, the results of the drift evaluation can be used to adjust the read operations performed on the memory cell to resolve the drift, as further discussed below.

[0033] Figure 1 A memory device 130 configured to have a read manager 113 is shown according to one embodiment.

[0034] exist Figure 1 In this memory device 130, there is an array 133 of memory cells (e.g., memory cells 101). The array 133 may be referred to as a tile; and the memory device (e.g., 130) may have one or more tiles. Different tiles may operate in parallel in the memory device (e.g., 130).

[0035] For example, Figure 1 The memory device 130 described herein may have a cross-point memory with an array 133 having at least memory cells (e.g., 101).

[0036] In some implementations, the cross-point memory uses a memory cell 101 having an element that acts as both a selector device and a memory device (e.g., a unique element). For example, the memory cell 101 may use a monolithic alloy with variable threshold capability. Read / write operations on such a memory cell 101 may be based on thresholding the memory cell 101 while suppressing other cells in a subthreshold bias, similar to read / write operations on a memory cell having a first element that acts as a selector device and a second element that acts as a phase-change memory device, the memory cells being stacked together in a column. The selector device that can be used to store information may be referred to as a selector / memory device.

[0037] Figure 1 The memory device 130 includes a controller 131 that operates a bit line driver 137 and a word line driver 135 to access individual memory cells (e.g., 101) in the array 133.

[0038] For example, it can be achieved through methods such as Figure 2 The pair of bit line drivers 147 and word line drivers 145 described herein drive voltages to access each memory cell (e.g., 101) in array 133.

[0039] Controller 131 includes a drift-aware read manager 113. Read manager 113 may be implemented, for example via logic circuitry and / or microcode / instructions, to estimate the state drift of the target memory cell set being addressed for data retrieval using reference cells associated with the target memory cell set. Drift estimation / evaluation is performed in parallel with reading the target memory cell set such that, when the drift is small, the drift estimation / evaluation has no effect on the latency of reading the target memory cells. If the drift is large, read manager 113 can immediately initiate the read operation using a read voltage adjusted according to the drift (e.g., before the decoder reports an error recovery failure).

[0040] In one embodiment, the reference cell may also be a typical memory cell 101 in array 133. Optionally, the target memory cells and reference cells are configured on separate arrays or tiles. For example, a reference tile or array may be configured to provide multiple reference cells. Each set of target memory cells in a target tile configured to store codewords encoded to support error detection and data recovery using error correction techniques may be assigned a reference cell in the reference tile. When the target memory cell set is programmed to store codewords, the reference cell is programmed to a predetermined reference state. The drift of the threshold voltage of the reference cell can be used as an estimate of the drift of the threshold voltage in the target memory cell. Based on the result of detecting / evaluating the drift in the reference cell, the drift-aware read manager 113 determines whether to perform additional optional read operations using word line driver 135 and bit line driver 137.

[0041] Figure 2 A memory cell 101 according to one embodiment is shown, having a bit line driver 147 and a word line driver 145 configured to apply voltage pulses. For example, the memory cell 101 may be... Figure 1 Typical memory cell 101 in memory cell array 133.

[0042] Figure 2 The bit line driver 147 and word line driver 145 are controlled by the read manager 113 of the controller 131 to selectively apply one or more voltage pulses to the memory cell 101, which may be a typical target memory cell or a typical reference cell.

[0043] Bit line driver 147 and word line driver 145 can apply voltages of different polarities to memory cell 101.

[0044] For example, when a voltage of a polarity (e.g., positive polarity) is applied, bit line driver 147 drives a positive voltage relative to ground on bit lines 141 connected to rows of memory cells in array 133; and word line driver 145 drives a negative voltage relative to ground on word lines 143 connected to columns of memory cells in array 133.

[0045] When a voltage of opposite polarity (e.g., negative polarity) is applied, bit line driver 147 drives a negative voltage on bit line 141; and word line driver 145 drives a positive voltage on word line 143.

[0046] Memory cell 101 is located in a row connected to bit line 141 and a column connected to word line 143. Therefore, memory cell 101 experiences a voltage difference between the voltage driven by bit line driver 147 on bit line 141 and the voltage driven by word line driver 145 on word line 143.

[0047] Generally, when the voltage driven by the bit line driver 147 is higher than the voltage driven by the word line driver 145, the memory cell 101 experiences a voltage of one polarity (e.g., positive); and when the voltage driven by the bit line driver 147 is lower than the voltage driven by the word line driver 145, the memory cell 101 experiences a voltage of the opposite polarity (e.g., negative).

[0048] In some embodiments, memory cell 101 is a selectable memory cell implemented using a selector / memory device. The selector / memory device has a chalcogenide (e.g., a chalcogenide material and / or a chalcogenide alloy). For example, the chalcogenide material may comprise a chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). The chalcogenide material may primarily comprise selenium (Se), arsenic (As), and germanium (Ge) and is referred to as a SAG alloy. The SAG alloy may comprise silicon (Si) and is referred to as a SiSAG alloy. In some embodiments, the chalcogenide glass may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form. The selector / memory device has a top side and a bottom side. A top electrode is formed on the top side of the selector / memory device for connection to bit line 141; and a bottom electrode is formed on the bottom side of the selector / memory device for connection to word line 143. For example, the top and bottom electrodes may be formed of carbon material. For example, the chalcogenide material of memory cell 101 may be in a crystalline or amorphous atomic configuration. The threshold voltage of memory cell 101 may depend on the ratio of the material in the crystalline configuration to the material in the amorphous configuration within memory cell 101. This ratio may vary under various conditions (e.g., allowing current of different magnitudes and directions to pass through memory cell 101).

[0049] The selector / memory unit 101, having a selector / memory device, can be programmed to have a threshold voltage window. The threshold voltage window can be generated by applying programming pulses of opposite polarity to the selector / memory device. For example, the memory unit 101 can be biased to have a positive voltage difference between the two sides of the selector / memory device, and alternatively, to have a negative voltage difference between the same two sides of the selector / memory device. When a positive voltage difference is considered positive polarity, a negative voltage difference is considered negative polarity. Reads can be performed with a given / fixed polarity. During programming, the memory unit has a low threshold (e.g., lower than a reset unit, or a unit already programmed to have a high threshold) such that during a read operation, the read voltage can cause the programmed unit to jump and thus become conductive, while the reset unit remains non-conductive.

[0050] For example, to program the voltage threshold of memory cell 101, bit line driver 147 and word line driver 145 can drive voltage pulses to memory cell 101 with one polarity (e.g., positive polarity) to jump memory cell 101, making memory cell 101 conductive. Although memory cell 101 is conductive, bit line driver 147 and word line driver 145 continue to drive programming pulses to change the threshold voltage of memory cell 101 toward the voltage region representing the data or bit value to be stored in memory cell 101.

[0051] Controller 131 may be configured in an integrated circuit having multiple stacks of memory cells. Each stack may be sandwiched between bit line layers and word line layers; and the memory cells in the stack may be arranged as array 133. The stack may have one or more arrays or tiles. Adjacent stacks of memory cells may share a bit line layer (e.g., 141) or a word line layer (e.g., 143). Bit lines are arranged to extend parallel in one direction within their layers; and word lines are arranged to extend parallel in another direction orthogonal to the bit line direction within their layers. Each bit line is connected to a row of memory cells in an array; and each word line is connected to a column of memory cells in an array. Bit line driver 137 is connected to the bit lines in the stack; and word line driver 135 is connected to the word lines in the stack. Thus, a typical memory cell 101 is connected to bit line driver 147 and word line driver 145.

[0052] The threshold voltage of a typical memory cell 101 is configured high enough that when only one of its bit line drivers 147 and word line drivers 145 is driven with a voltage of either polarity, while the other voltage driver keeps the corresponding line grounded, the magnitude of the voltage applied across the memory cell 101 is insufficient to make the memory cell 101 conductive. Therefore, addressing of the memory cell 101 can be performed via both its bit line drivers 147 and word line drivers 145, which are driven with voltages of opposite polarity relative to ground, for operating / selecting the memory cell 101. Other memory cells connected to the same word line driver 145 can be deselected by their respective bit line drivers keeping the corresponding bit lines grounded; and other memory cells connected to the same bit line driver can be deselected by their respective word line drivers keeping the corresponding word lines grounded.

[0053] A group of memory cells (e.g., 101) connected to a common word line driver 145 can be selected by their respective bit line drivers (e.g., 147) for parallel operation, the respective bit line drivers being driven upwards by a voltage of one polarity, while the word line driver 145 is also driven upwards by a voltage of the opposite polarity. Similarly, a group of memory cells connected to a common bit line driver 147 can be selected by their respective word line drivers (e.g., 145) for parallel operation, the respective word line drivers being driven by a voltage of one polarity, while the bit line driver 147 is also driven by a voltage of the opposite polarity.

[0054] At least some examples of crosspoint memory with selectable memory cells are disclosed herein. Other types of memory cells and / or memories may also be used. For example, in at least some embodiments, memory cells and / or flash memory cells, each having a selector device and a phase-change memory device, may also be used.

[0055] Figure 3 This demonstrates a technique for executing a read command according to one embodiment. For example, Figure 3 The technology can be used Figure 1 and 2 The read manager 113 described herein shall be used for implementation.

[0056] exist Figure 3 In this process, read command 151 identifies target memory cell 153 to retrieve a data item represented by a threshold voltage of memory cell 153. In response to read command 151, read manager 113 identifies a corresponding reference memory cell 154 pre-associated with target memory cell 153.

[0057] For example, target memory cell 153 may be one of a set of memory cells having threshold voltages programmed to represent codewords available in error detection and recovery. Reference memory cell 154 may be pre-associated with memory cells via a predetermined mapping.

[0058] In one embodiment, the target memory cell 153 and the reference memory cell 154 are configured in separate arrays or tiles to simplify parallel but distinct operations on the target memory cell 153 and the reference memory cell 154. Alternatively, the target memory cell 153 and the reference memory cell 154 may be configured in the same array 133 or tile, wherein a pair of voltage drivers connected to the target memory cell 153 and a pair of voltage drivers connected to the reference memory cell 154 are configured to perform parallel operations on the target memory cell 153 and the reference memory cell 154 in a distinct manner.

[0059] In response to read command 151, read manager 113 performs read operation 155 by instructing voltage driver of target memory cell 153 to apply one or more read voltages to target memory cell 153 when determining the voltage range of threshold voltage of target memory cell 153. However, one or more read voltages are applied in read operation 155 without taking into account the drift of threshold voltage of target memory cell 153.

[0060] In parallel with the read operation 155, the read manager 113 performs the drift detection 157 operation by instructing the voltage driver of the reference memory cell 154 to apply one or more read voltages to the target memory cell 153 when a change in the threshold voltage of the target memory cell 153 is detected. The threshold voltage of the reference memory cell 154 has been previously programmed to a predetermined voltage range when the target memory cell 153 is programmed to store data.

[0061] A drift is detected when the threshold voltage of the reference memory cell 154 moves outside the predetermined voltage region; and it can be inferred that the target memory cell 153 has a similar drift.

[0062] The read operation 155 produces a read result 161 of a data item represented by a voltage region of the threshold voltage of the target memory cell 153, without taking into account the drift of the threshold voltage of the target memory cell.

[0063] The operation of detection 157 generates a drift estimate indicating the drift in the threshold voltage of the reference memory cell 154 and therefore the corresponding drift in the threshold voltage of the target memory cell 153.

[0064] If the read manager 113 determines that the drift estimate 162 indicates that the threshold voltage of the target memory cell 153 has not drifted (e.g., remains within a previously known region), then the read result 161 is acceptable and provided as or for generating a response to the read command 151.

[0065] If the read manager 113 determines that the drift estimate 162 indicates that the threshold voltage of the target memory cell 153 has drifted (e.g., moved outside a previously known region), a read retry 165 can be initiated immediately on the target memory cell 153 based on the voltage region adjusted for the drift.

[0066] Figure 4 and 5 This demonstrates a drift-aware reading operation according to one embodiment. For example, Figure 3 The technology can be used Figure 4 or Figure 5 The operations described herein are implemented using self-selected memory units. In a system with... Figure 1 and 2Under the control of the controller 131 of the read manager 113 described herein, voltage pulses can be applied to the select memory cell 101 using the bit line driver 147 and the word line driver 145; and the select memory cell 101 can be the target memory cell 153 or the reference memory cell 154.

[0067] exist Figure 4 and 5 In response to read command 151, read manager 113 begins to use voltage driver to apply voltage to target memory cell 153 and reference memory cell 154 in parallel.

[0068] Prior to read command 151, the threshold voltage of reference memory cell 154 has been previously programmed to a known state represented by a lower voltage region. The threshold voltage of target memory cell 153 has been previously programmed to a state represented by a voltage region associated with a value written, programmed, or stored in memory cell 153. For example, the voltage region of the threshold voltage of target memory cell 153 may be in a lower voltage region representing a first value (e.g., a), or in a higher voltage region representing a second value (e.g., zero).

[0069] After the target memory cell 153 is programmed to store a first or second value, the read voltage V1 181 distinguishes the lower voltage region from the higher voltage region. If the target memory cell 153 becomes conductive when the voltage applied across it is driven to the read voltage V1, then the threshold voltage of the target memory cell 153 is below V1 and therefore in the lower voltage region. Thus, the read manager 113 can conclude that the target memory cell 153 has stored, programmed, or written to a first value (e.g., a). Otherwise, it is determined that the target memory cell 153 has a second value (e.g., zero).

[0070] However, the threshold voltage of the target memory cell 153 may be initially programmed in a lower voltage region, but has drifted above the read voltage V1. After such a drift, the target memory cell 153 may remain non-conductive after the read voltage V1 is applied; and reading the memory cell using the read voltage V1 may result in erroneous results.

[0071] exist Figure 4 and 5In response to read command 151, the voltage driver of target memory cell 153 and the voltage driver of reference memory cell 154 are used in parallel to drive voltages across target memory cell 153 and reference memory cell 154, respectively. While the voltage applied across target memory cell 153 drives upward toward read voltage V1 181, the voltage applied across reference memory cell 154 can drive upward toward alternative read voltage V2 182 to test whether the threshold voltage of reference memory cell 154 has drifted toward alternative read voltage V2.

[0072] Since the reference memory cell 154 is known to be programmed to a lower voltage region, the drift-free reference memory cell 154 can become conductive when driven upwards across its applied voltage toward the read voltage V1. However, if the reference memory cell 154 remains non-conductive when reaching the read voltage V1 across its applied voltage, but becomes conductive when driven upwards across its applied voltage toward the alternative read voltage V2, then the threshold voltage of the reference memory cell 154 has drifted into the voltage region between the read voltage V1 and the alternative read voltage V2. If a drift is detected in the reference memory cell 154, it can be inferred that the target memory cell 153 has a similar drift; and the result of reading the target memory cell 153 using the read voltage V1 181 may be erroneous.

[0073] exist Figure 4 In response to the detection of a drift in the reference memory cell 154, the read manager 113 may instruct the voltage driver of the target memory cell 153 to increase the applied voltage from the read voltage V1 to a higher read voltage V3. For example, the higher read voltage V3 may be equal to an alternative read voltage V2, or another voltage determined based on a test of the threshold voltage of the reference memory cell 154 at the time of drift detection.

[0074] exist Figure 4 and 5 If no drift is detected in the reference memory cell 154, the read manager 113 instructs the voltage driver of the target memory cell 153 to reverse the polarity of the applied voltage and drive a voltage of opposite polarity to the read voltage 185 (e.g., read the memory cell from the opposite polarity and / or apply the read voltage to eliminate the effects introduced by the read voltage V1). For example, read voltages 181 and 185 may have the same magnitude but opposite polarities.

[0075] However, if a drift is detected in the reference memory cell 154, the read manager 113 instructs the voltage driver of the target memory cell 153 to move across the voltage it applies from... Figure 4V1 in the voltage range increases to V3. If the target memory cell 153 becomes conductive during a voltage drive toward V3, the read manager 113 concludes that the target memory cell 153 has a threshold voltage in the lower voltage region and therefore has a first value (e.g., one); otherwise, the memory cell 153 has a second value (e.g., zero) corresponding to the higher voltage region.

[0076] exist Figure 4 In the process of reading the target memory cell 153 by increasing the applied voltage to V3, the read manager 113 instructs the voltage driver of the target memory cell 153 to reverse the polarity of the applied voltage and drive a voltage of opposite polarity to the read voltage 187 (e.g., reading the memory cell from the opposite polarity and / or applying a read voltage to eliminate the effects introduced by the read voltage V1 181). The read voltage 187 is also adjusted from the corresponding voltage 185 based on the drift detected in the reference memory cell 154. For example, read voltages 183 and 187 may have the same magnitude but opposite polarities.

[0077] exist Figure 4 In the context of reference memory cell 154, when no drift is detected, drift detection has no effect on the latency when reading target memory cell 153. When drift is detected, the latency increases slightly as V1 increases to V3 and the duration of determining whether the target memory cell is conductive or non-conductive at the higher read voltage V3 is determined.

[0078] exist Figure 5 If a drift is detected in reference memory cell 154, read manager 113 instructs the voltage driver of target memory cell 153 to use a read voltage 187 having a value greater than that of the opposite polarity read voltage 185, instead of... Figure 4 The direct increase across the applied voltage is from V1 to V3, as described in the diagram. Read voltages 181 and 185 can have the same magnitude but opposite polarities.

[0079] For example, if the target memory cell 153 is initially programmed in a higher voltage region with positive polarity to be tested by the read voltage V1, then the target memory cell 153 has a threshold voltage in a lower voltage region with negative polarity. Before the target memory cell 153 drifts, a voltage 185 applied with reverse polarity can be used to determine whether the negative threshold voltage of the target memory cell 153 is in the higher voltage region or in the lower voltage region in terms of magnitude. If the target memory cell 153 becomes conductive during a voltage drive towards the read voltage 185, the read manager 113 concludes that the target memory cell 153 has a negative threshold voltage in the lower voltage region, which corresponds to a positive threshold voltage in the higher voltage region and is therefore a second value (e.g., zero). Otherwise, the target memory cell 153 has a first value (e.g., one).

[0080] exist Figure 5 In the process, after reading the target memory cell 153 with the opposite polarity using a read voltage 187 adjusted from the read voltage 185 according to the detected drift, the manager 113 can further instruct the voltage driver of the target memory cell 153 to further reverse the polarity of the applied voltage, and use an additional voltage pulse 189 to drive the voltage of the original polarity to the read voltage V3. As in Figure 4 In this context, the read voltage V3 can be adjusted based on the drift detected in the reference memory cell 154, and has the same magnitude as the read voltage 187 but with the opposite polarity.

[0081] Optionally, in some examples or implementations, the additional voltage pulse 189 may be omitted.

[0082] exist Figure 5 When no drift is detected in the reference memory cell 154, drift detection has no effect on the latency of reading the target memory cell 153. When drift is detected and the result is read using the adjusted read voltage 187 in the opposite polarity, there is no effect on the latency of reading the target memory cell 153. When the result of reading the target memory cell 153 using the additional voltage pulse 189 is used, the latency is increased by using the additional voltage pulse 189.

[0083] exist Figure 4 and 5In this context, the adjusted read voltages V3 183 and V187 can be considered as read retries 165 implemented in a manner integrated into the read operation initiated under the assumption of no drift. This tight integration reduces the latency caused by read retries 165 because the time period of read retries 165 at least partially overlaps with the time period of a drift-free read. Without tight integration, read retries 165 could be initiated after the use of read voltage 185 has been completed with reverse polarity.

[0084] exist Figure 4 and 5 In this process, after the reference memory cell 154 becomes conductive during drift detection, the read manager 113 may further instruct the voltage driver of the reference memory cell 154 to apply a voltage pulse 184 to refresh the drift in the reference memory cell 154. The voltage and / or current applied to the reference memory cell 154 while it is conductive during drift detection can alter the drift in the reference memory cell 154. The voltage pulse 184 can be applied to refresh the drift in the reference memory cell 154 such that the drift in the reference memory cell 154 accurately tracks the drift in the target memory cell 153.

[0085] The set of target memory cells (e.g., 101) in array 133 can be used to store codewords with redundant information for error detection and recovery. The set of target memory cells can be connected to common word line driver 145 for parallel operation in conjunction with its respective bit line driver (e.g., 147), or connected to common word line driver 147 for parallel operation in conjunction with its respective bit line driver (e.g., 145).

[0086] One or more reference memory cells can be used to estimate the drift in the threshold voltage of the target memory cell set used to store codewords. One or more reference memory cells may be in the same array 133 and connected to a common word line driver 145, wherein their bit line drivers (e.g., 147) are instructed and / or configured to operate in a manner different from the bit line drivers of the respective target memory cells. Alternatively, when the target memory cells are connected to the common bit line driver 147 for parallel operation, one or more reference memory cells may also be connected to the common bit line driver 147, wherein their word line drivers (e.g., 145) are instructed and / or configured to operate in a manner different from the word line drivers of the respective target memory cells (e.g., implementing different voltage pulses applied to the target cells and reference cells, such as...). Figure 4 and Figure 5 (as explained in the text).

[0087] Generally, different target memory cells may have different drift rates for their threshold voltage (e.g., due to their different positions in array 133 and / or their electrical distance to their voltage drivers); and a reference memory cell of the set of target memory cells may be selected with a drift rate similar to the fastest drifting target memory cell in the set used to store codewords.

[0088] Alternatively, to avoid different driver configurations within the array, the reference memory cells can be in a separate array from the array 133 of the target memory cell set. Furthermore, the placement and routing of the reference memory cells in the target memory cell set can be configured to simulate the drift behavior of the fastest drifting target memory cell in the set used to store codewords, and thus improve the accuracy of drift estimation in the target memory cells.

[0089] Discuss in conjunction with a customizable memory cell programmed to store one bit per memory cell. Figure 4 and 5 The technology can be similarly extended to custom memory cells programmed to store more than one bit per memory cell. In some implementations, more than one reference memory cell can be used to detect different drifts in the threshold voltage programmed at different voltage levels / zones.

[0090] Generally, techniques for detecting drift in a reference memory cell in parallel with reading the target memory cell, assuming no drift, can be applied to other types of memory cells, such as flash memory cells, memory cells using different elements as selector devices, and phase-change memory devices. Reads of the target memory cell can be modified in response to the detection of drift in the reference memory cell to minimize read retry latency.

[0091] Figure 6 A method for reading a memory cell is illustrated according to one embodiment. For example, Figure 6 The method can be used Figure 3 Technical implementation in Figure 1 In the memory device 130, the memory device has a controller 131 with a read manager 113, such as Figure 1 and 2 As explained in the text.

[0092] At block 201, controller 131 receives a first command to write data items (e.g., codewords) into a first set of memory cells in memory device 130. In response, the operations at blocks 203 and 205 can be performed in parallel.

[0093] At block 203, a voltage driver (e.g., bit line driver 137 and word line driver 135) controlled by controller 131 drives one or more voltage pulses on the first memory cell to program the threshold voltage of the first memory cell according to the data item.

[0094] At block 205, a voltage driver controlled by controller 131 drives one or more voltage pulses on a second memory cell associated with a first set of memory cells in memory device 130 to program the threshold voltage of the second memory into a predetermined voltage region that can be identified using a first read voltage (e.g., V1).

[0095] For example, the first memory unit may include the target memory unit 153; and the second memory unit may be the reference memory unit 154.

[0096] For example, a second memory cell may be configured in memory device 130 to have a threshold drift rate representing the fastest drifting memory cell in the first set of memory cells.

[0097] For example, the first memory cell may be configured in a first memory cell array; and the second memory cell may be configured in a second memory cell array separate from the first memory cell array. Alternatively, the first memory cell and the second memory cell may be connected to a common bit line driver 147 or a common word line driver 145 in the same memory cell array 133.

[0098] At block 207, controller 131 receives a second command to read the first set of memory cells. In response, the operations at blocks 209 and 211 can be performed in parallel; and the operations at blocks 213 and 215 can be performed in parallel.

[0099] At box 209, read manager 113 uses a voltage driver to drive the voltage applied to the first memory cell to a first read voltage (e.g., ...). Figure 5 and 6 V1 as described in the document.

[0100] At box 211, read manager 113 uses a voltage driver to drive the voltage applied to the second memory cell to a second read voltage (e.g., Figure 5 and 6 V2 as described in the document.

[0101] At block 213, controller 131 identifies a first subset of memory cells that have a threshold voltage lower than a first read voltage (e.g., V1). The memory cells in the first subset become conductive at the first read voltage (e.g., V1).

[0102] At box 215, read manager 113 determines whether the threshold voltage of the second memory cell has drifted into the voltage range between the first read voltage (e.g., V1) and the second read voltage (e.g., V2).

[0103] If the read manager 113 determines that the threshold voltage of the second memory cell 163 has drifted into the voltage range between the first read voltage (e.g., V1) and the second read voltage (e.g., V2), then the operations at blocks 219 to 223 are performed; otherwise, the operations at block 217 are performed.

[0104] At box 217, controller 131 determines the result of reading the first memory cell based on the identification of the first subset.

[0105] At box 219, read manager 113 applies a third read voltage to the first memory cell based on a magnitude identified based on the second read voltage (e.g., V2).

[0106] At box 221, read manager 113 identifies a second subset of the first memory cells that have a threshold voltage lower than the third read voltage.

[0107] At box 223, controller 131 determines the result of reading the first memory cell based on the identification of the second subset.

[0108] For example, the third read voltage could be Figure 4 V3 as described herein. The read manager 113 can instruct the voltage driver to increase from the first read voltage V1 to the third voltage V3 before decreasing the voltage applied to the first memory cell and / or before reversing the polarity of the voltage applied to the first memory cell. After identifying the second subset, the voltage driver is instructed to reverse the polarity and will have the same voltage as the third read voltage (e.g., ...). Figure 4 The fourth voltage (e.g., the voltage opposite to the polarity of the reading voltage 183) in the reading voltage (read voltage 183) Figure 4 The read voltage 187) is driven onto the first memory cell. The fourth voltage (e.g., Figure 4 The magnitude of the read voltage 183 is different from the corresponding read voltage (e.g., 185) applied when there is no drift. The fourth voltage (e.g., Figure 4 The value of the read voltage (183) is determined based on the second read voltage (e.g., V2) and the threshold voltage of the second memory cell between the first read voltage and the second read voltage.

[0109] In another example, the third read voltage could be Figure 5The read voltage 187 is described in the diagram. In such embodiments, the third read voltage 187 has a polarity opposite to that of the first read voltage 181; and the application of the third read voltage 187 to the first memory cell includes switching from the voltage applied to the first memory cell with the polarity of the first read voltage 181 to the polarity of the third read voltage 187, independent of whether the threshold voltage of the second memory cell has drifted into the voltage region between the first read voltage V1 and the second read voltage V2. Therefore, before applying the third read voltage 187, the controller is configured to instruct the voltage driver to perform the same operation on the first memory cell independently of whether a drift is detected. Subsequent operations for reading the first memory cell can be modified based on the result of the drift estimation. Optionally, after identifying the second subset, the voltage has a polarity opposite to that of the first read voltage (e.g., Figure 5 The fourth voltage (e.g., V1) of the same polarity as V1) Figure 5 The fourth voltage (V3) is applied to the first memory cell. The magnitude of the fourth voltage can be identified or determined based on the second read voltage (e.g., V2).

[0110] like Figure 4 and 5 As described herein, if the second memory cell becomes conductive during the operation of detecting or estimating drift, the controller 131 is further configured to instruct the bit line driver and word line driver of the second memory cell to apply voltage pulses (e.g., 184) to the second memory cell to refresh the drift, such that the drift in the second memory cell remains representative of the drift in the first memory cell.

[0111] Figure 7 This describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., ... Figure 1 (memory device 130), or a combination thereof.

[0112] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0113] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or a networked business device), or such a computing device containing memory and processing devices.

[0114] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. Figure 7 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0115] Host system 120 may include a processor chipset (e.g., processing unit 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0116] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS) interfaces, Dual Data Rate (DDR) memory bus interfaces, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR) interfaces, Low Power Dual Data Rate (LPDDR) interfaces, or any other interfaces. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize NVM High Speed ​​(NVMe) interface access components (e.g., Figure 1 (Memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 7The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0117] The processing unit 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processor core, an execution unit, etc. In some examples, the controller 116 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one instance, the controller 116 controls communication via a bus coupled between the host system 120 and the memory subsystem 110. Generally, the controller 116 may send commands or requests to the memory subsystem 110 to request access to memory devices 130, 140. The controller 116 may further include an interface circuitry for communicating with the memory subsystem 110. The interface circuitry may translate responses received from the memory subsystem 110 into information for the host system 120.

[0118] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading, writing, or erasing data at memory devices 130, 140, and other such operations. In some examples, the controller 116 is integrated within the same package as the processing device 118. In other examples, the controller 116 is packaged separately from the processing device 118. The controller 116 and / or the processing device 118 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or combinations thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0119] Memory devices 130 and 140 may include different types of non-volatile memory components and / or any combination of volatile memory components. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0120] Some examples of non-volatile memory components include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0121] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0122] Although non-volatile memory devices, such as 3D crosspoint type and NAND type memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0123] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading, writing, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus by controller 116). Controller 115 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic that performs the operations described herein. Controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0124] Controller 115 may include processing device 117 (e.g., processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of memory subsystem 110, including communication between memory subsystem 110 and host system 120.

[0125] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 7 The instance memory subsystem 110 in the present disclosure is described as including controller 115, but in another embodiment of the present disclosure, memory subsystem 110 does not include controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0126] Generally, controller 115 may receive commands or operations from host system 120 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory device 130. Controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. Controller 115 may further include host interface circuitry for communicating with host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into instructions for accessing memory device 130 and responses associated with memory device 130 into information for host system 120.

[0127] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0128] In some embodiments, memory device 130 includes a local media controller 131 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 131) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0129] The controller 115 and / or memory device 130 may include a read manager 113, such as those described above. Figures 1 to 6 The read manager 113 discussed herein. In some embodiments, a controller 115 in the memory subsystem 110 includes at least a portion of the read manager 113. In other embodiments, or in combination, a controller 116 and / or a processing device 118 in the host system 120 includes at least a portion of the read manager 113. For example, controller 115, controller 116, and / or processing device 118 may include a logic circuitry implementing the read manager 113. For example, the controller 115 or processing device 118 (e.g., a processor) of the host system 120 may be configured to execute instructions stored in memory for performing operations of the read manager 113 described herein. In some embodiments, the read manager 113 is implemented in an integrated circuit chip (e.g., memory device 130) mounted in the memory subsystem 110. In other embodiments, the read manager 113 may be part of the firmware of the memory subsystem 110, the operating system of the host system 120, a device driver, or an application, or any combination thereof.

[0130] Figure 8 An example machine is described as representing computer system 300, within which an instruction set for causing the machine to perform any or more of the methods discussed herein is executable. In some embodiments, computer system 300 may correspond to a host system (e.g., Figure 7The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 7 The memory subsystem 110) or can be used to perform operations of the read manager 113 (e.g., execute instructions to perform operations corresponding to the reference). Figure 1-6 The operation of the described read manager 113 is described. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0131] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0132] The example computer system 300 includes a processing device 302, a main memory 304 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 318, which communicate with each other via a bus 330 (which may include multiple buses).

[0133] Processing device 302 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 302 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 302 is configured to execute instructions 326 for performing the operations and steps discussed herein. Computer system 300 may further include a network interface device 308 for communication via network 320.

[0134] Data storage system 318 may include machine-readable medium 324 (also referred to as computer-readable medium) on which one or more instruction sets 326 or software embodying any or more of the methods or functions described herein are stored. Instructions 326 may also reside wholly or at least partially in main memory 304 and / or processing device 302 during execution by computer system 300, the main memory 304 and processing device 302 also constituting machine-readable storage media. Machine-readable medium 324, data storage system 318, and / or main memory 304 may correspond to... Figure 7 The memory subsystem 110.

[0135] In one embodiment, instruction 326 includes instructions for implementing a function corresponding to read manager 113 (e.g., reference 113). Figure 1-6 The instructions for the function of the described read manager 113). Although the machine-readable medium 324 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0136] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. Algorithms here and generally are considered as a self-consistent sequence of operations that produce the desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0137] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0138] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0139] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices for performing the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0140] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0141] In this description, for the sake of simplicity, various functions and operations may be described as being executed or caused by computer instructions. However, those skilled in the art will recognize that such expressions are intended to mean that the functions originate from one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems with or without software instructions, such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Embodiments may be implemented using wired circuit systems without software instructions or in combination with software instructions. Therefore, the technology is not limited to any specific combination of hardware circuit systems and software, nor to any particular source of instructions executed by a data processing system.

[0142] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. An apparatus comprising: A memory cell comprising: First set of memory cells; as well as At least one second memory unit; A voltage driver connected to the memory cell; as well as A controller coupled to the voltage driver and configured to operate on the memory cell using the voltage driver; In response to a command to write a data item to the first set of memory cells, the controller is configured to perform the following programming using the voltage driver: The threshold voltage of the first memory cell is programmed according to the data item, and The threshold voltage of the second memory cell is programmed to a level within a predetermined voltage region; and In response to a command to read the first set of memory cells, the controller is configured to: Estimating the drift of the threshold voltage of the second memory cell in parallel with applying a first read voltage to the first memory cell, and The operation of reading the first memory cell using the voltage driver is modified based on the drift estimated during the application of the first read voltage to the first memory cell.

2. The apparatus of claim 1, wherein the controller is configured to: In parallel with applying the first read voltage to the first memory cell, the voltage driver is used to apply the second read voltage to the second memory cell; and Determine whether the threshold voltage of the second memory cell is within the voltage range between the first read voltage and the second read voltage to estimate the drift.

3. The apparatus of claim 2, wherein the threshold voltage in response to the second read voltage is lower than the second read voltage, the controller is further configured to use the voltage driver to increase the second read voltage applied to the second memory cell to a voltage higher than the second read voltage when the second memory cell is in a conductive state.

4. The apparatus of claim 3, wherein in response to the determination of the threshold voltage of the second read voltage between the first read voltage and the second read voltage, the controller is further configured to use the voltage driver to increase the first read voltage applied to the first memory cell to a third read voltage identified based on the second read voltage, and to determine which of the first memory cells has a threshold voltage lower than the third read voltage.

5. The apparatus of claim 4, wherein the third read voltage is of a first polarity; and in response to the determination that the threshold voltage of the second read voltage is between the first read voltage and the second read voltage, the controller is further configured to apply a fourth read voltage of a second polarity opposite to the first polarity to the first memory cell after determining which of the first memory cells has a threshold voltage lower than the third read voltage.

6. The apparatus of claim 3, wherein the first read voltage is of a first polarity; and in response to the determination of the threshold voltage of the second read voltage between the first read voltage and the second read voltage, the controller is further configured to apply a third read voltage of a second polarity opposite to the first polarity to the first memory cell using the voltage driver, wherein the third read voltage is based on the second read voltage.

7. The apparatus of claim 6, wherein after reading the first memory cell using the third read voltage of the second polarity, the controller is further configured to apply a voltage of the first polarity using the voltage driver in response to the command for reading the first set of memory cells and the determination of the threshold voltage of the second read voltage between the first read voltage and the second read voltage.

8. The apparatus of claim 3, wherein the second memory cell is configured in the apparatus to have a threshold drift rate representing the fastest drifting memory cell in the first set of memory cells.

9. The apparatus of claim 8, wherein the first memory cell is configured in a first memory cell array; and the second memory cell is configured in a second memory cell array separate from the first memory cell array.

10. The apparatus of claim 8, wherein the first memory cell and the second memory cell are connected in a memory cell array to a common bit line driver or a common word line driver.

11. A method comprising: Receive a first command for writing data items into a first set of memory cells in a memory device; In response to the first command: One or more voltage pulses are driven on the first memory cell to program the threshold voltage of the first memory cell according to the data item; as well as One or more voltage pulses are driven on a second memory cell associated with the first set of memory cells in the memory device to program the threshold voltage of the second memory to a predetermined voltage region that can be identified using the first read voltage; Receive a second command for reading the first set of memory cells; as well as In response to the second command: The voltage applied to the first memory cell is driven to reach the first read voltage; Identify a first subset of the first memory cells that has a threshold voltage lower than the first read voltage; The voltage applied to the second memory cell is driven to reach the second read voltage in parallel with the drive that applies the voltage to the first memory cell to reach the first read voltage; In parallel with identifying the first subset, it is determined that the threshold voltage of the second memory cell has drifted into the voltage range between the first read voltage and the second read voltage; as well as In response to the threshold voltage of the second memory cell being between the first read voltage and the second read voltage, A third read voltage is applied to the first memory cell, the magnitude of which is based on the second read voltage; as well as Identify a second subset of the first memory cells that has a threshold voltage lower than the first read voltage; as well as The result of reading the first memory cell is determined based on the identification of the second subset as a response to the second command.

12. The method of claim 11, wherein the application of the third read voltage to the first memory cell comprises, before reducing the voltage applied to the first memory cell, increasing the voltage applied to the first memory cell and driven to the first read voltage to further reach the third read voltage.

13. The method of claim 12, further comprising: After the second subset is identified, a fourth voltage with the opposite polarity to the third read voltage is driven onto the first memory cell, the magnitude of which is determined based on the second read voltage and the threshold voltage of the second memory cell between the first read voltage and the second read voltage.

14. The method of claim 11, wherein the third read voltage has a polarity opposite to that of the first read voltage; and the application of the third read voltage to the first memory cell includes switching from the voltage applied to the first memory cell with the polarity of the first read voltage to the polarity of the third read voltage during timing between the first read voltage and the second read voltage, independent of the threshold voltage of the second memory cell.

15. The method of claim 14, further comprising: Following the identification of the second subset, a fourth voltage having the same polarity as the first read voltage is driven onto the first memory cell, the magnitude of which is based on the second read voltage.

16. An integrated circuit, comprising: Bitline layer; Word line layer; A memory cell is disposed between the bit line layer and the word line layer, each of the memory cells being connected to a bit line in the bit line and to a word line in the word line; Bit line driver, which is connected to the bit line; A word line driver, which is connected to the word line; as well as A controller, coupled to the bit line driver and the word line driver, is configured to respond to a command for retrieving data from a first memory cell among the memory cells. The drift in the threshold voltage of the second memory cell associated with the first memory cell is detected in parallel with the application of a first read voltage to the first memory cell via a bit line driver and a word line driver. If no drift is detected in the threshold voltage of the second memory cell, the value programmed into the first memory cell is determined based on whether the first memory cell is conductive at the first read voltage. and If a drift with a scale represented by a second read voltage is detected in the threshold voltage of the second memory cell, a third read voltage is applied based on the second read voltage to determine the value programmed into the first memory cell based on whether the first memory cell is conductive under the third read voltage.

17. The integrated circuit of claim 16, wherein if the drift is detected in the threshold voltage of the second memory cell via the second read voltage, the controller is configured to instruct the bit line driver and the word line driver to raise the first read voltage to a third read voltage having an amount greater than the first read voltage and having the same polarity as the first read voltage.

18. The integrated circuit of claim 17, wherein if the drift is detected in the threshold voltage of the second memory cell via the second read voltage, the controller is configured to, after the application of the third read voltage, further instruct the bit line driver and the word line driver to apply a fourth read voltage having a polarity opposite to that of the third read voltage.

19. The integrated circuit of claim 16, wherein before applying the third read voltage having a polarity opposite to that of the first read voltage, the controller is configured to instruct the bit line driver and the word line driver to perform the same operation independently of whether the drift is detected; If no drift is detected, the controller is configured to instruct the bit line driver and the word line driver to apply a fourth read voltage with the same polarity as the third read voltage but with the same magnitude as the first read voltage; Furthermore, if the drift is detected in the threshold voltage of the second memory cell via the second read voltage, the controller is configured to instruct the bit line driver and the word line driver to apply another read voltage with the same polarity as the first read voltage after the application of the third read voltage.

20. The integrated circuit of claim 16, wherein the controller is configured to identify the second read voltage based on an operation of detecting a drift in the threshold voltage of the second memory cell; and if the second memory cell becomes conductive during the operation of detecting the drift, the controller is further configured to instruct the bit line driver and word line driver to apply voltage pulses to the second memory cell to refresh the drift.

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