Anti-io interference nonvolatile memory read operation method, device and storage medium

Abstract

The application discloses an IO interference prevention nonvolatile memory reading operation method, device and storage medium, and the method comprises the following steps: starting a comparator module, and making the current of a storage unit play to the input end of the comparator module within a first preset time; outputting the comparison result of the comparator module, starting a latch after the fixed delay ends, and locking the result; and closing the comparator module. The application reasonably designs the working time sequence of the reading operation core circuit module according to the time sequence of IO output data, and effectively avoids IO interference.

Description

Technical Field

[0001] This application relates to the field of non-volatile memory, and in particular to methods, apparatus and storage media for reading non-volatile memory that are resistant to I / O interference. Background Technology

[0002] Non-volatile storage (NVS), also known as non-volatile random access memory (NVRAM), is a form of static random access memory that retains its contents when the computer is turned off or loses its external power. Non-volatile memory read operations output data from I / O. During the input process, internal circuitry reads data from subsequent addresses. However, I / O outputs generate power-to-ground interference, and the more I / O operations there are, the greater the interference.

[0003] Therefore, the aforementioned technical problems in the relevant technologies urgently need to be solved. Summary of the Invention

[0004] This application aims to solve one of the technical problems in related technologies. To this end, embodiments of this application provide a method, apparatus, and storage medium for non-volatile memory read operations that prevent I / O interference, which can reduce interference caused by I / O output.

[0005] According to one aspect of an embodiment of this application, a method for reading a non-volatile memory with I / O interference prevention is provided, the method comprising:

[0006] The comparator module is turned on, and the current of the memory cell is projected to the input terminal of the comparator module within a first preset time.

[0007] After the comparator module outputs the comparison result and a fixed delay is completed, the latch is activated to latch the result.

[0008] The comparator module is turned off.

[0009] In one embodiment, before activating the enable comparator module, the method further includes:

[0010] When the read module is enabled, the corresponding memory unit is selected based on the address decoding.

[0011] The storage unit is charged so that it reaches a preset voltage value within a second preset time.

[0012] In one embodiment, when the read module is enabled, the method further includes:

[0013] Sample the start signal;

[0014] Enable pre-charge only after sampling is complete.

[0015] In one embodiment, sampling the start signal includes:

[0016] The start signal is sampled using the rising edge of the IO clock signal.

[0017] In one embodiment, after latching the result, the method further includes:

[0018] Sample the latch signal;

[0019] After sampling is complete, latch enable is enabled to ensure that the latch enable is always active before the falling edge of the I / O operation.

[0020] In one embodiment, sampling the latch signal includes:

[0021] The latch signal is sampled using the rising edge of the IO clock signal.

[0022] In one embodiment, after the fixed delay ends, opening the latch includes:

[0023] Obtain the duration of the fixed delay;

[0024] After the fixed delay period, it is checked whether the current latch enable signal duration is less than the IO clock signal. If so, the latch is enabled and the result is latched.

[0025] According to one aspect of an embodiment of this application, a read operation apparatus for non-volatile memory that prevents I / O interference is provided, the apparatus comprising:

[0026] The first module is used to enable the comparator module and project the current of the storage cell to the input terminal of the comparator module within a first preset time.

[0027] The second module is used to output the comparison result in the comparator module, and after the fixed delay, to open the latch and latch the result.

[0028] The third module is used to disable the comparator module.

[0029] According to one aspect of an embodiment of this application, a read operation apparatus for non-volatile memory that prevents I / O interference is provided, the apparatus comprising:

[0030] At least one processor;

[0031] At least one memory for storing at least one program;

[0032] When at least one of the programs is executed by at least one of the processors, the non-volatile memory read operation method with IO interference prevention as described in the preceding embodiments is implemented.

[0033] According to one aspect of the embodiments of this application, a storage medium is provided, the storage medium storing a processor-executable program, which, when executed by a processor, implements the non-volatile memory read operation method with anti-IO interference as described in the preceding embodiments.

[0034] The beneficial effects of the non-volatile memory read operation method, apparatus, and storage medium for preventing I / O interference provided in this application are as follows: The method of this application includes enabling a comparator module, projecting the current of the storage cell to the input terminal of the comparator module within a first preset time; after the comparator module outputs a comparison result and a fixed delay is completed, enabling a latch to latch the result; and disabling the comparator module. This application rationally designs the operating timing of the core circuit module for the read operation, effectively avoiding I / O interference, specifically addressing the timing of I / O output data.

[0035] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 The operating timing of the core circuit module for general read operation provided in the embodiments of this application;

[0038] Figure 2 A flowchart illustrating a non-volatile memory read operation method for preventing I / O interference, as provided in an embodiment of this application.

[0039] Figure 3 A block diagram of the core circuit for a general read operation provided in the embodiments of this application;

[0040] Figure 4 The circuit diagram for the control module of the non-volatile memory read operation method for preventing I / O interference provided in the embodiments of this application is shown.

[0041] Figure 5 The operating timing of the core circuit module for read operation provided in the embodiments of this application;

[0042] Figure 6A complete circuit diagram of the non-volatile memory read operation method for preventing I / O interference provided in the embodiments of this application;

[0043] Figure 7 A schematic diagram of a non-volatile memory read operation device for preventing I / O interference provided in an embodiment of this application;

[0044] Figure 8 This is a schematic diagram of another non-volatile memory read operation device for preventing I / O interference, provided in an embodiment of this application. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0046] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] Non-volatile storage (NVS), also known as non-volatile random access memory (NVRAM), is a form of static random access memory that retains its contents when the computer is turned off or loses its external power. Non-volatile memory read operations output data from I / O. During the input process, internal circuitry reads data from subsequent addresses. However, I / O outputs generate power-to-ground interference, and the more I / O operations there are, the greater the interference.

[0049] The above problems arise because the read module is susceptible to external interference at two critical moments during its operation: the pre-charge phase, which is prone to overcharging or undercharging; and the latch-on phase, where interference can cause sudden changes in the comparison result (numerical errors) and latch errors. Figure 1 The operating timing diagram of the core circuit module for general read operation provided in the embodiments of this application is as follows: Figure 3 This is a block diagram of the core circuit for a general read operation provided in an embodiment of this application. (See diagram below.) Figure 1 and 3 As shown, the read module enable in the core circuit module of the general read operation does not specifically avoid the IO toggle time; and since the latch enable is obtained by two-stage RC delay, it is an asynchronous signal with the IO toggle clock, and cannot guarantee that it will avoid the IO toggle time.

[0050] To address the aforementioned issues, this application proposes a method, apparatus, and storage medium for reading non-volatile memory to prevent I / O interference. It also proposes a reasonable timing design for the core circuit module of the read operation, taking into account the timing of I / O output data, to effectively avoid I / O interference.

[0051] Figure 2 A flowchart of a non-volatile memory read operation method for preventing I / O interference provided in an embodiment of this application is shown below. Figure 2 As shown, the non-volatile memory read operation method for preventing I / O interference proposed in this application specifically includes:

[0052] S201. Turn on the comparator module and project the current of the storage cell to the input terminal of the comparator module within a first preset time.

[0053] S202. After the comparator module outputs the comparison result and a fixed delay is completed, the latch is opened to latch the result.

[0054] S203. Turn off the comparator module.

[0055] Optionally, before enabling the comparator module, the method further includes: when the read module is enabled, selecting the corresponding memory cell according to address decoding; charging the memory cell so that the memory cell reaches a preset voltage value within a second preset time. Wherein, when the read module is enabled, the method further includes: sampling the start signal; and enabling pre-charge after sampling is complete.

[0056] In this embodiment, sampling the start signal includes sampling the start signal via the rising edge of the IO clock signal.

[0057] Optionally, after latching the result, the method further includes: sampling the latch signal; and enabling the latch after sampling to ensure that the latch enable is always active around the falling edge of the I / O clock signal. The sampling of the latch signal includes: sampling the latch signal using the rising edge of the I / O clock signal.

[0058] Optionally, after the fixed delay ends, the latch is activated, including: obtaining the duration of the fixed delay; after the duration of the fixed delay, detecting whether the current latch enable signal duration is less than the IO clock signal; if so, the latch is activated and the result is latched.

[0059] The read circuit module of this application includes: a reference current module, a precharge module, a comparator module, and a latch module. The working process of the non-volatile memory read operation method for preventing I / O interference in this application includes: at the start of the read operation, the corresponding memory cell is selected through address decoding; then, the precharge module charges the memory cell BL, ensuring that the BL voltage reaches the designed value within a designed time; then, the precharge module is turned off, and the comparator module is turned on. After the designed time, the current of the memory cell is reflected at the comparator input (generally, memory cells in the erase state have tens of μA of current, while memory cells in the programming state have close to 0 μA of current), therefore, the comparator outputs the corresponding comparison result; then, the latch is turned on to latch the result; finally, the comparator is turned off.

[0060] Figure 4 This is a circuit diagram illustrating the control module implementation of the non-volatile memory read operation method for preventing I / O interference provided in an embodiment of this application. Figure 4 As shown, the control module implementation circuit for the non-volatile memory read operation method with I / O interference prevention provided in this application embodiment includes a read module, a pre-charge RC pulse circuit module, an RC pulse circuit module, and a latching RC pulse circuit module. After the read module enable signal is triggered, the signal enters the pre-charge RC pulse circuit module for pre-charging, and then the RC pulse circuit module latches the RC pulse circuit module to implement the non-volatile memory read operation with I / O interference prevention.

[0061] Figure 5This document describes the operating timing of the core circuit module for the read operation provided in this embodiment. In this embodiment, 1) when the read module is enabled, the start signal is sampled using the IO clock (rising edge). The pre-charge enable is then activated after sampling, ensuring that the effective pre-charge enable always avoids the falling edge of the IO clock (i.e., the data output moment). In conventional designs, latch enable is activated after a fixed delay following the pre-charge enable. Since the fixed delay is asynchronous with the IO clock, the latch enable and data output moments are asynchronous. This invention latches the signal after the fixed delay, then samples the latch signal using the IO clock (rising edge), and activates the latch enable after sampling, ensuring that the effective latch enable always avoids the falling edge of the IO clock (i.e., the data output moment). Typically, the latch enable duration is short (around 3ns), less than half an IO clock cycle, so the data output moment is not encountered during the entire high-level latch period.

[0062] Specifically, Figure 6 A complete circuit diagram of the non-volatile memory read operation method for preventing I / O interference provided in the embodiments of this application is shown below. Figure 6 As shown, the workflow of the non-volatile memory read operation method for preventing I / O interference proposed in this application is as follows: The read module enable signal is issued and input to the rising edge D flip-flop, and the I / O clock signal is input. The precharge RC pulse circuit module performs precharge enable, and the RC pulse circuit module performs latching processing. Latching is completed after the rising edge D flip-flop is triggered.

[0063] Furthermore, this application also proposes a non-volatile memory read operation device to prevent I / O interference, such as... Figure 7 As shown, the device includes:

[0064] The first module 701 is used to enable the comparator module and project the current of the storage cell to the input terminal of the comparator module within a first preset time.

[0065] The second module 702 is used to output the comparison result in the comparator module, and after the fixed delay ends, to open the latch and latch the result.

[0066] The third module 703 is used to disable the comparator module.

[0067] Furthermore, this application also proposes a non-volatile memory read operation device to prevent I / O interference, such as... Figure 8 As shown, the device includes:

[0068] At least one processor;

[0069] At least one memory for storing at least one program;

[0070] When at least one of the programs is executed by at least one of the processors, the non-volatile memory read operation method with IO interference prevention as described in the preceding embodiments is implemented.

[0071] The content of the above method embodiments is applicable to the device embodiments. The specific functions implemented by the device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0072] In addition, this application also proposes a storage medium storing a processor-executable program, which, when executed by a processor, implements the non-volatile memory read operation method with anti-IO interference as described in the preceding embodiments.

[0073] Similarly, the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0074] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0075] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0076] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0077] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0078] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0079] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0080] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0081] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0082] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for reading non-volatile memory to prevent I / O interference, characterized in that, The method includes: When the read module is enabled, the corresponding storage unit is selected according to the address decoding. The storage unit is the basic component of the non-volatile memory, and the storage unit has a one-to-one corresponding BL. The start signal is sampled using the rising edge of the IO clock signal; Enable pre-charge only after sampling is complete; Charge the BL of the corresponding memory cell so that the memory cell reaches a preset voltage value within a second preset time. The comparator module is turned on, and the current of the memory cell is projected to the input terminal of the comparator module within a first preset time. After the comparator module outputs the comparison result and a fixed delay is completed, the latch is activated to latch the result. The latch signal is sampled using the rising edge of the IO clock signal; After sampling is completed, latch enable is enabled to ensure that the latch enable is always active before the falling edge of the I / O operation. The comparator module is turned off.

2. The non-volatile memory read operation method for preventing I / O interference according to claim 1, characterized in that, After the fixed delay ends, the latch is activated, including: Obtain the duration of the fixed delay; After the fixed delay period, it is checked whether the current latch enable signal duration is less than the IO clock signal. If so, the latch is enabled and the result is latched.

3. A non-volatile memory read operation device resistant to I / O interference, characterized in that, The device includes: The first module is used to enable the comparator module and project the current of the storage cell to the input terminal of the comparator module within a first preset time. The storage cell is the basic building block of the non-volatile memory, and the storage cell has a one-to-one corresponding BL. The second module is used to output the comparison result in the comparator module, and after the fixed delay, to open the latch and latch the result. The third module is used to disable the comparator module.

4. A non-volatile memory read operation device resistant to I / O interference, characterized in that, The device includes: At least one processor; At least one memory for storing at least one program; When at least one of the programs is executed by at least one of the processors, the non-volatile memory read operation method with IO interference prevention as described in any one of claims 1-2 is implemented.

5. A storage medium, characterized in that, The storage medium stores a processor-executable program, which, when executed by the processor, implements the non-volatile memory read operation method against I / O interference as described in any one of claims 1-2.

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