Wafer dicing street interconnect structure
By designing a connection structure between the non-laser dicing area and the laser dicing area within the wafer dicing channel, the risk of grain edge delamination caused by laser grooving is resolved, the electrical performance of wafer reliability testing is improved, and the working area of the pad layer is expanded.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-05-26
- Publication Date
- 2026-07-21
AI Technical Summary
In chip packaging processes, laser grooving may cause localized micro-cracks in the wafer dicing channels, leading to the risk of delamination at the die edges and affecting the electrical performance of the wafer in reliability testing.
Design a wafer dicing interconnect structure including a non-laser dicing area and a laser dicing area. The top lead layer is located in the main part of the non-laser dicing area, the top conductive layer is located on both sides of the laser dicing area and the non-laser dicing area, and the pad layer is located above the top lead layer and the conductive layer and is isolated by a first passivation layer. The top lead layer and the pad layer are directly connected.
It significantly improves the electrical performance of wafer reliability testing, while reducing the risk of die edge delamination, expanding the working area of the pad layer, and improving test results.
Smart Images
Figure CN115410985B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wafer testing, and more particularly to an interconnect structure within a wafer dicing channel. Background Technology
[0002] In chip packaging, a laser groove process is performed to remove all circuit structure layers in the area to be cut inside the wafer scribe lane, thereby providing working space for the cutting tool during subsequent mechanical cutting and preventing the tool from damaging the die edge.
[0003] As the laser rapidly burns through the scribe lane area, it inevitably passes through different structural layers, such as test structures and relatively open areas. Especially at the junction of the scribe lanes, it may cause local micro-bursts. These bursts are prone to occur in the passivation layer or low-k layer. If the range is too large or out of control, it will bring the risk of die edge delamination (DED).
[0004] Since the structural design of the dicing channel occurs during the wafer manufacturing stage, while the laser grooving process occurs during the packaging stage, and the parameters and equipment conditions of each packaging plant are different, and since laser cutting will inevitably touch the test key in most cases, the test key generally includes a pad layer and an underlying metal layer. The design of the metal layer has a significant impact on the probability and severity of DED problems, and the area of the metal layer also restricts the electrical performance of wafer reliability testing (WAT). Summary of the Invention
[0005] The technical problem to be solved by this application is to provide an interconnect structure in the wafer dicing channel that can significantly improve the electrical performance of WAT without affecting the probability and severity of DED occurrence.
[0006] To address the aforementioned technical problems, this application provides an interconnect structure within a wafer dicing channel. The wafer dicing channel includes a non-laser dicing area and laser dicing areas located on both sides of the non-laser dicing area. The interconnect structure includes: a top lead layer, located in the main body of the non-laser dicing area; a top conductive layer, located in the non-laser dicing areas on both sides of the laser dicing area and the top lead layer; and a pad layer, located above the top lead layer and the top conductive layer in the non-laser dicing area and the laser dicing area. The top lead layer is directly connected to the pad layer, and a first passivation layer is further included between the top conductive layer and the pad layer.
[0007] In this embodiment of the application, the laser cutting area is a region extending inward from the edge of the wafer cutting channel with a specific width.
[0008] In this embodiment, the width of the top lead layer perpendicular to the wafer dicing direction is less than or equal to the width of the non-laser dicing area.
[0009] In this embodiment, the width of the top lead layer perpendicular to the wafer dicing path extension direction is no more than 27 μm, and the width of the top lead layer parallel to the wafer dicing path extension direction is 50 μm-100 μm.
[0010] In this embodiment, the contact surface between the top lead layer and the pad layer is circular or polygonal.
[0011] In this embodiment, the top conductive layer includes strip-shaped structures extending outward from the edge of the top lead layer and arranged at intervals, as well as annular structures connecting the ends of the strip-shaped structures.
[0012] In this embodiment, the cross-section of the annular structure is quadrilateral, wherein the first and second sides, which are perpendicular to the extension direction of the wafer dicing track, span the non-laser dicing area and the laser dicing area, and the third and fourth sides, which are parallel to the extension direction of the wafer dicing track, are located in the laser dicing area.
[0013] In this embodiment of the application, the lengths of the first side and the second side are 27μm-44μm.
[0014] In this embodiment, the strip structure connecting the first side and the top lead layer, the second side and the top lead layer is located in the non-laser cutting area, and the strip structure connecting the third side and the top lead layer, the fourth side and the top lead layer is located in the laser cutting area.
[0015] In this embodiment, the number of strip structures located in the laser-cut area is less than the number of strip structures located in the non-laser-cut area.
[0016] In this embodiment of the application, a dielectric layer is further included between adjacent strip structures.
[0017] In this embodiment, the wafer dicing interconnect structure further includes a second passivation layer, located on the surface of a pad layer above the first passivation layer.
[0018] In this embodiment, the materials of the first passivation layer and the second passivation layer include silicon compounds.
[0019] In this embodiment, the material of the liner layer includes aluminum.
[0020] Compared with the prior art, the wafer dicing interconnect structure of the present application has the following advantages:
[0021] The wafer dicing interconnect structure of this application includes a top lead layer and a top conductive layer. The top lead layer is located in the main part of the non-laser dicing area and is directly connected to the pad layer, which increases the effective electrical contact area of the WAT and significantly improves the electrical performance of the WAT.
[0022] The top conductive layer includes strip-shaped structures extending outward from the edge of the top lead layer and spaced apart, as well as annular structures connecting the ends of the strip-shaped structures. Most of the strip-shaped structures are located in the non-laser-cut area, and only a small portion of the strip-shaped structures are located in the laser-cut area. This further ensures that the interconnect structure within the wafer dicing channel of the present application does not affect the probability and severity of DED.
[0023] The area of the padding layer covered by the passivation layer of the interconnect structure in the wafer dicing channel is significantly reduced. While keeping the size of the padding layer unchanged, the working area of the padding layer is expanded, which is beneficial to WAT. Attached Figure Description
[0024] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:
[0025] Figure 1 This is a top view schematic diagram of an interconnect structure within a wafer dicing channel.
[0026] Figure 2 for Figure 1 A sectional view at position AA in the middle;
[0027] Figure 3 This is a top view schematic diagram of the interconnect structure within the wafer dicing channel according to an embodiment of this application;
[0028] Figure 4 for Figure 3 A cross-sectional view at position BB in the middle. Detailed Implementation
[0029] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0030] In current 28nm / 14nm dicing, to reduce the area of the top metal layer, it is designed as a mesh, with the pads and top metal layer connected only by a few vias on both sides. While this design can improve the DED (Die-Die) problem during dicing, the limited contact area between the pads and the top metal layer vias is not conducive to WAT (Waste-Adjustable Tape).
[0031] refer to Figure 1 and Figure 2 in Figure 1 This is a top view schematic diagram of the interconnect structure within the wafer dicing channel. Figure 2 for Figure 1 A cross-sectional view at position AA. The interconnect structure within the wafer dicing channel includes a top metal layer 10, the surface of which has a first passivation layer 20. The first passivation layer 20 has several through-holes 21 on both sides. A padding layer 30 is formed on the surface of the first passivation layer 20 and in the through-holes 21. The top metal layer 10 is connected to the padding layer 30 in the through-holes 21. The padding layer 30 has through-holes 41, and a second passivation layer 40 is also included on a portion of the surface of the padding layer 30 and in the through-holes 41. To make... Figure 1 To more clearly show the structure of the top metal layer, remove Figure 1 The structure above the middle and top metal layer 10, the removed structure can be combined Figure 2 This needs to be understood. Because the bottom area of the through-hole 21 is small, the contact area between the top metal layer 10 and the through-hole 21 is small, which is detrimental to WAT (Waste Air Treatment). Simultaneously, the second passivation layer 40 covers a portion of the padding layer 30, reducing the working area of the padding layer 30, which is also detrimental to WAT.
[0032] Therefore, the technical solution of this application improves the top metal layer beneath the backing layer, redistributing its density and reducing the area of the top metal layer in the laser-cut zone to ensure that the probability and severity of DED do not affect the occurrence. Simultaneously, increasing the area of the top metal layer in the non-laser-cut zone can significantly improve the electrical performance of WAT.
[0033] This application provides an in-wafer dicing interconnect structure. Below the in-wafer dicing interconnect structure is the circuit connection structure of the device. The circuit connection structure of the device is an existing structure and will not be described in detail here.
[0034] refer to Figure 3 and Figure 4 ,in Figure 3 This is a top view of the interconnect structure within the wafer dicing channel according to an embodiment of this application. To clearly illustrate the structure of the top lead layer and the top conductive layer of this embodiment, the structure above the top lead layer and the top conductive layer has been removed. The removed structure can be referred to... Figure 4 . Figure 4 for Figure 3 A cross-sectional view at the BB position. The wafer dicing track includes a non-laser dicing area 110 and a laser dicing area 120. The laser dicing area 120 is a region extending inward from the edge of the wafer dicing track with a specific width. This specific width can be determined according to actual conditions, for example, it can be around 8.5 micrometers. The non-laser dicing area 110 is located between the laser dicing areas 120, that is, the laser dicing area 120 is located on both sides of the non-laser dicing area 110. The laser dicing area 120 is adjacent to the die, therefore, the stress generated when cutting the circuit structure within the laser dicing area 120 can easily damage the die, so the design of the circuit structure within the laser dicing area 120 is very important.
[0035] The interconnection structure of this embodiment includes a top lead layer 210 and a top conductive layer 220. The top lead layer 210 is located in the main body of the non-laser-cut area 110 and is used to connect the internal circuitry. The top conductive layer 220 is located in the non-laser-cut areas 110 on both sides of the laser-cut area 120 and the top lead layer 110, and is used to conduct the internal circuitry. The top lead layer 210 and the top conductive layer 220 can be formed in the same process step, therefore, the materials of the top lead layer 210 and the top conductive layer 220 can be the same. For example, the materials of the top lead layer 210 and the top conductive layer 220 can both be metals, such as copper, tungsten, etc.
[0036] The interconnect structure also includes a padding layer 300, which is located above the non-laser-cut area 110 and the laser-cut area 120 above the top lead layer 210 and the top conductive layer 220. The padding layer 300 may be made of aluminum. The top lead layer 210 and the padding layer 300 are directly connected, and a first passivation layer 400 is also included between the top conductive layer 220 and the padding layer 300. The first passivation layer 400 is used to isolate the padding layer 330 and the top conductive layer 220 to prevent leakage during WAT and thus inaccurate test results. The material of the first passivation layer 400 may include a silicon compound, such as silicon dioxide. During testing, the test probe 500 is brought into contact with the surface of the padding layer 300.
[0037] Since the top lead layer 210 occupies the main part of the non-laser-cut area 110, meaning the top lead layer 210 has a large area, connecting it to the pad layer 300 significantly improves electrical performance during testing. This solves the problem of poor testing performance caused by the pad layer and top metal layer being connected through a few through-holes in the past. Furthermore, since the large top lead layer 210 is only located in the non-laser-cut area 110, it does not increase the risk of DED (Device Execution).
[0038] The width of the top lead layer 210 perpendicular to the wafer dicing path extension direction (i.e., in the Y direction) is less than or equal to the width of the non-laser dicing region 110. In some embodiments, the width of the non-laser dicing region 110 is 27 μm, and the width of the top lead layer 210 perpendicular to the wafer dicing path extension direction does not exceed 27 μm. For example, the width of the top lead layer 210 perpendicular to the wafer dicing path extension direction can be 5 μm, 10 μm, 15 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm, etc. Since the area of the top lead layer 210 affects not only the electrical performance during testing, but also the cost of materials and the size of the connection structure, the size of the top lead layer 210 is crucial. When the width of the top lead layer 210 perpendicular to the wafer dicing path is fixed, its width in the direction parallel to the wafer dicing path (i.e., in the X direction) also needs to be limited to better meet the requirements. In this embodiment, the width of the top lead layer 210 in the direction parallel to the wafer dicing path is 50μm-100μm.
[0039] The contact surface between the top lead layer 210 and the padding layer 300 is circular or polygonal. For example, the cross-sectional shape of the top lead layer 210 can be square, rectangular, rhomboid, etc.
[0040] The top conductive layer 220 is not directly connected to the padding layer 300, therefore the area of the top conductive layer 220 does not affect the electrical performance of WAT. Thus, the top conductive layer 220 can be designed as a mesh structure to reduce material costs. In this embodiment, the top conductive layer 220 includes strip structures 221 extending outwards from the edge of the top lead layer 210 and arranged at intervals, and annular structures 222 connecting the ends of the strip structures 221. The width of the strip structures 221 and the distance between adjacent strip structures 221 are determined according to actual conditions.
[0041] In some embodiments, the annular structure 222 is quadrilateral, wherein a first side L1 and a second side L2 perpendicular to the extension direction (i.e., the X direction) of the wafer dicing track span the non-laser dicing region 110 and the laser dicing region 120, and a third side L3 and a fourth side L4 parallel to the extension direction (i.e., the X direction) of the wafer dicing track are located in the laser dicing region 120. In some embodiments, the lengths of the first side L1 and the second side L2 are 27 μm to 44 μm.
[0042] In the strip structure 221, the strip structure 221 connecting the first side L1 and the top lead layer 210, and the second side L2 and the top lead layer 210, is located in the non-laser-cut area 110. The strip structure 221 connecting the third side L3 and the top lead layer 210, and the fourth side L4 and the top lead layer 210, is located in the laser-cut area 120. Furthermore, the number of strip structures located in the laser-cut area 120 is less than the number of strip structures 221 located in the non-laser-cut area 110. That is, the vast majority of the strip structures 221 are located in the non-laser-cut area 110, and only a small portion are located in the laser-cut area 120. This ensures that the probability and severity of DED occurrence are not affected.
[0043] In the actual wafer dicing interconnect structure, a dielectric layer (not shown) is also included between adjacent strip structures 221 to provide structural support. The material of the dielectric layer may include silicon oxide.
[0044] refer to Figure 4In some embodiments, the wafer dicing interconnect structure further includes a second passivation layer 600, which is located on the surface of the pad layer 300 above the first passivation layer 300. The material of the second passivation layer 600 may include a silicon compound, for example, the material of the second passivation layer 600 may include silicon dioxide. (Comparison) Figure 2 and Figure 4 The area of the pad layer 300 covered by the second passivation layer 600 is greatly reduced. Therefore, the interconnect structure in the wafer dicing channel of this application embodiment increases the area of the pad layer 300 opening while keeping the size of the pad layer 300 unchanged, thereby further expanding the working area of the pad layer 300.
[0045] In summary, the wafer dicing interconnect structure of this application increases the contact area between the pad layer and the top metal layer, and places the part of the top metal layer in contact with the pad layer, i.e. the top lead layer, in the main part of the non-laser dicing area, thereby significantly improving the electrical performance of WAT, without affecting the probability and severity of DED.
[0046] After reading this application, those skilled in the art will understand that the foregoing content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0047] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0048] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0049] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0050] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A wafer dicing channel interconnect structure, wherein the wafer dicing channel includes a non-laser dicing region and laser dicing regions located on both sides of the non-laser dicing region, the laser dicing regions being areas extending inwards from the edge of the wafer dicing channel with a specific width, characterized in that, The connection structure includes: The top lead layer is located in the main body of the non-laser-cut area; The top conductive layer is located in the non-laser-cut areas on both sides of the laser-cut area and the top lead layer. The top conductive layer includes strip-shaped structures that extend outward from the edge of the top lead layer and are spaced apart, as well as annular structures that connect the ends of the strip-shaped structures. A pad layer, located above the top lead layer and the top conductive layer, includes a non-laser-cut area and a laser-cut area, wherein the top lead layer is directly connected to the pad layer, and a first passivation layer is further included between the top conductive layer and the pad layer.
2. The wafer dicing interconnect structure according to claim 1, characterized in that, The width of the top lead layer perpendicular to the wafer dicing direction is less than or equal to the width of the non-laser dicing area.
3. The wafer dicing channel interconnect structure according to claim 2, characterized in that, The width of the top lead layer perpendicular to the wafer dicing path extension direction does not exceed 27 μm, and the width of the top lead layer parallel to the wafer dicing path extension direction is 50 μm-100 μm.
4. The wafer dicing interconnect structure according to claim 1, characterized in that, The contact surface between the top lead layer and the padding layer is circular or polygonal.
5. The wafer dicing interconnect structure according to claim 1, characterized in that, The cross-section of the annular structure is quadrilateral, wherein the first and second sides, which are perpendicular to the extension direction of the wafer dicing track, span the non-laser dicing area and the laser dicing area, and the third and fourth sides, which are parallel to the extension direction of the wafer dicing track, are located in the laser dicing area.
6. The wafer dicing channel interconnect structure according to claim 5, characterized in that, The lengths of the first and second sides are 27μm-44μm.
7. The wafer dicing channel interconnect structure according to claim 5, characterized in that, The strip structure connecting the first side and the top lead layer, the second side and the top lead layer is located in the non-laser cutting area, and the strip structure connecting the third side and the top lead layer, the fourth side and the top lead layer is located in the laser cutting area.
8. The wafer dicing channel interconnect structure according to claim 7, characterized in that, The number of strip structures located in the laser-cut area is less than the number of strip structures located in the non-laser-cut area.
9. The wafer dicing channel interconnect structure according to claim 1, characterized in that, A dielectric layer is also included between adjacent strip structures.
10. The wafer dicing interconnect structure according to claim 1, characterized in that, It also includes a second passivation layer, located on the surface of the padding layer above the first passivation layer.
11. The wafer dicing interconnect structure according to claim 10, characterized in that, The materials of the first passivation layer and the second passivation layer include silicon compounds.
12. The wafer dicing interconnect structure according to claim 1, characterized in that, The material of the liner layer includes aluminum.