Semiconductor structure and its formation method

Abstract

A semiconductor structure and its formation method are disclosed. The semiconductor structure includes: a substrate; a dielectric layer located on the substrate; and multiple metal interconnects located in the dielectric layer, including lower sub-interconnects and upper sub-interconnects. The lower sub-interconnects are located in a portion of the dielectric layer, and the upper sub-interconnects are located in the remaining thickness of the dielectric layer above the lower sub-interconnects. Both the lower and upper sub-interconnects extend along a first direction and are arranged parallel to each other along a second direction. Along the first direction, at the break points of adjacent metal interconnects, the lower and upper sub-interconnects are arranged adjacent to each other. In this invention, the lower and upper sub-interconnects are located at different heights in the normal direction of the substrate surface. Therefore, this reduces the limitations imposed by the process on the head-to-head spacing of the metal interconnects, thereby ensuring process reliability while minimizing the head-to-head spacing of the metal interconnects.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the requirements of interconnects after the critical size reduction, the conduction between different metal layers or between a metal layer and a substrate is currently achieved through interconnect structures. As technology nodes advance, the size of interconnect structures is becoming smaller and smaller; correspondingly, the process of forming interconnect structures is becoming more and more difficult. The formation quality of interconnect structures has a significant impact on the back end of line (BEOL) electrical performance and device reliability, and in severe cases, it can affect the normal operation of semiconductor devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the head-to-head spacing of metal interconnects while ensuring process reliability.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a dielectric layer located on the substrate; and a plurality of metal interconnects located within the dielectric layer. The metal interconnects include lower-layer sub-interconnects and upper-layer sub-interconnects. The lower-layer sub-interconnects are located within a portion of the dielectric layer's thickness, and the upper-layer sub-interconnects are located within the remaining thickness of the dielectric layer above the lower-layer sub-interconnects. Both the lower-layer and upper-layer sub-interconnects extend along a first direction and are arranged parallel to each other along a second direction, the first direction being perpendicular to the second direction. Specifically, along the first direction, at the break points of adjacent metal interconnects, the lower-layer and upper-layer sub-interconnects are arranged adjacent to each other.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a first sub-dielectric layer on the substrate; forming a lower sub-interconnect in the first sub-dielectric layer, the lower sub-interconnect extending along a first direction and arranged parallel to a second direction, the first direction being perpendicular to the second direction; forming a second sub-dielectric layer covering the lower sub-interconnect and the first sub-dielectric layer; forming an upper sub-interconnect penetrating the second sub-dielectric layer, the upper sub-interconnect extending along the first direction and arranged parallel to the second direction, the upper sub-interconnect and the lower sub-interconnect constituting a metal interconnect, wherein, along the first direction, at the break position of adjacent metal interconnects, the lower sub-interconnect and the upper sub-interconnect are disposed adjacent to each other.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, the metal interconnect includes a lower sub-interconnect and an upper sub-interconnect. The lower sub-interconnect is located in a dielectric layer of a certain thickness, and the upper sub-interconnect is located in the remaining thickness of the dielectric layer above the lower sub-interconnect. Along the first direction, at the break position of adjacent metal interconnects, the lower sub-interconnect and the upper sub-interconnect are arranged adjacent to each other. Since the lower sub-interconnect and the upper sub-interconnect are located at different thicknesses of the dielectric layer, that is, at different heights in the normal direction of the substrate surface, it is beneficial to reduce the limitations of the process on the head-to-head spacing of the metal interconnects. It can minimize the lateral distance between the ends of adjacent lower and upper sub-interconnects in the first direction, thereby reducing the head-to-head spacing of the metal interconnects while ensuring process reliability.

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, a lower sub-interconnect is formed in a first sub-dielectric layer, and after forming a second sub-dielectric layer covering the lower sub-interconnect and the first sub-dielectric layer, an upper sub-interconnect is formed penetrating the second sub-dielectric layer. The upper sub-interconnect and the lower sub-interconnect constitute a metal interconnect, and along the first direction, at the disconnection position of adjacent metal interconnects, the lower sub-interconnect and the upper sub-interconnect are arranged adjacent to each other. Since the lower sub-interconnect is located in the first sub-dielectric layer and the upper sub-interconnect is located in the second sub-dielectric layer, that is, the lower sub-interconnect and the upper sub-interconnect are located at different heights in the normal direction of the substrate surface, it is beneficial to reduce the limitation of the process on the head-to-head spacing of the metal interconnect, and to minimize the lateral distance between the ends of adjacent lower and upper sub-interconnects in the first direction, thereby reducing the head-to-head spacing of the metal interconnect while ensuring process reliability. Attached Figure Description

[0010] Figure 1 This is a 3D diagram of a semiconductor structure;

[0011] Figure 2 It is a top view of any layer of metal interconnects and dielectric layers;

[0012] Figure 3 This is a perspective view of an embodiment of the semiconductor structure of the present invention;

[0013] Figure 4 yes Figure 3 Top view of the metal interconnects in the middle;

[0014] Figure 5 yes Figure 4 A sectional view along the secant line a1a2;

[0015] Figures 6 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] Due to technological limitations, it is currently difficult to reduce the head-to-head spacing of metal interconnects. This paper analyzes the reasons why it is difficult to reduce the head-to-head spacing of metal interconnects using a semiconductor structure as an example.

[0017] refer to Figure 1 , Figure 1 This is a three-dimensional diagram of a semiconductor structure.

[0018] The semiconductor structure includes: a substrate 10 in which a transistor structure 20 is formed; a dielectric layer (not shown) located on the substrate 10; and a metal interconnect structure (not shown) located within the dielectric layer. In the longitudinal direction (i.e., along the normal direction of the surface of the substrate 10), the metal interconnect structure includes multiple layers of spaced metal interconnects 30. The bottom layer of metal interconnects 30 is electrically connected to the transistor structure 20. Along the normal direction of the surface of the substrate 10, the extension directions of adjacent metal interconnects 30 are perpendicular, and adjacent metal interconnects 30 are connected by via interconnect structures 35.

[0019] Reference Figure 2 , Figure 2 This is a top view of any one layer of metal interconnect 30 and dielectric layer 40. Currently, for each layer of metal interconnect 30, the metal interconnect 30 is a single-layer structure. Within the same layer of metal interconnect 30, along the extending direction of the metal interconnect 30 (e.g., ... Figure 2As shown in the X direction, the head-to-head spacing d of the metal interconnect 30 is limited by the process (e.g., by the photolithography process). Therefore, as the process node evolves, the feature size of the device continues to shrink, which correspondingly increases the process difficulty of the subsequent process, making it difficult to continuously reduce the head-to-head spacing d of the metal interconnect 30 while ensuring process reliability.

[0020] To address the aforementioned technical problem, the semiconductor structure provided in this invention includes a lower sub-interconnect and an upper sub-interconnect. The lower sub-interconnect is located in a dielectric layer of a certain thickness, and the upper sub-interconnect is located in the remaining thickness of the dielectric layer above the lower sub-interconnect. Along the first direction, at the break points of adjacent metal interconnects, the lower and upper sub-interconnects are arranged adjacent to each other. Since the lower and upper sub-interconnects are located at different thicknesses of the dielectric layer—that is, at different heights along the normal direction of the substrate surface—it is advantageous to reduce the limitations imposed by the process on the head-to-head spacing of the metal interconnects. This minimizes the lateral distance between the ends of adjacent lower and upper sub-interconnects in the first direction, thereby reducing the head-to-head spacing of the metal interconnects while ensuring process reliability.

[0021] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Reference Figures 3 to 5 , Figure 3 This is a perspective view of an embodiment of the semiconductor structure of the present invention. Figure 4 yes Figure 3 Top view of the metal interconnects in the middle. Figure 5 yes Figure 4 A sectional view along the secant line a1a2.

[0023] The semiconductor structure includes: a substrate 100 (e.g., ... Figure 5 (as shown); dielectric layer 200 (as shown) Figure 5 As shown), located on substrate 100; multiple metal interconnects 280, located in dielectric layer 200, the metal interconnects 280 including lower sub-interconnects 230 and upper sub-interconnects 260, the lower sub-interconnects 230 located in a portion of the dielectric layer 200, the upper sub-interconnects 260 located in the remaining thickness of the dielectric layer 200 above the lower sub-interconnects 230, both the lower sub-interconnects 230 and the upper sub-interconnects 260 are along a first direction (e.g. Figure 3 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 3The lower sub-interconnect 230 and the upper sub-interconnect 260 are arranged in parallel (as shown in the Y direction). The first direction is perpendicular to the second direction. Along the first direction, at the break position 201 of the adjacent metal interconnect 280, the lower sub-interconnect 230 and the upper sub-interconnect 260 are arranged adjacent to each other.

[0024] The substrate 100 provides a process platform for the formation of the semiconductor structure. Depending on the actual process, the substrate 100 includes a substrate and functional structures formed on the substrate. For example, the functional structures may include semiconductor devices such as MOS field-effect transistors, resistive structures, conductive structures, etc. In this embodiment, multiple front-layer interconnects 110 are formed in the substrate 100, and the normal direction of the surface of the substrate 100 is vertical (e.g., ...). Figure 3 (As shown in the Z-direction). Specifically, the surface of the substrate 100 exposes the front interconnect 110. The front interconnect 110 is used to connect with the metal interconnect 280, thereby realizing the electrical connection between the two. In this embodiment, the front interconnect 280 extends along the second direction and is arranged parallel to the first direction.

[0025] The metal interconnects 280 are used to bring out the electrical components of the functional structures in the substrate 100. It should be noted that in conventional back-end of line (BEOL) processes, each metal interconnect layer is typically a single-layer structure, and the longitudinal extension directions of adjacent metal interconnect layers are perpendicular. However, in this embodiment, the metal interconnects 280 in the same layer are a stacked structure. Specifically, the metal interconnects 280 include a lower-layer sub-interconnect 230 and an upper-layer sub-interconnect 260 located above the lower-layer sub-interconnect 230.

[0026] The upper-layer sub-interconnect 260 and the lower-layer sub-interconnect 230 together constitute the same-layer metal interconnect 280. Therefore, the upper-layer sub-interconnect 260 and the lower-layer sub-interconnect 230 extend in the same direction. Specifically, the lower-layer sub-interconnect 230 extends along a first direction and is arranged parallel to a second direction, while the upper-layer sub-interconnect 260 extends along a first direction and is arranged parallel to a second direction.

[0027] In this embodiment, along the first direction, at the break position 201 of adjacent metal interconnects 280, the lower sub-interconnect 230 and the upper sub-interconnect 260 are arranged adjacently. Adjacent arrangement here means that the projections of the lower sub-interconnect 230 and the upper sub-interconnect 260 on the substrate 100 are adjacent; that is, along the first direction, at the break position 201 of adjacent metal interconnects 280, the lower sub-interconnect 230 and the upper sub-interconnect 260 are arranged head-to-head.

[0028] Since the lower sub-interconnect 230 and the upper sub-interconnect 260 are located at different thicknesses of the dielectric layer 200, that is, at different heights in the longitudinal direction, the head-to-head spacing of the metal interconnect 280 is the lateral distance D1 between the ends of adjacent lower sub-interconnects 230 and upper sub-interconnects 260 (e.g., ...). Figure 5 As shown), this helps to reduce the limitations imposed by the process on the head-to-head spacing of the metal interconnect 280 (e.g., the head-to-head spacing of the metal interconnect 280 is limited by the photolithography process), and can minimize the lateral distance D1 between the ends of adjacent lower sub-interconnects 230 and upper sub-interconnects 260 in the first direction (e.g., as shown). Figure 5 As shown in the figure, this reduces the head-to-head spacing of the 280 metal interconnects while ensuring process reliability.

[0029] Therefore, in this embodiment, in the first direction, adjacent lower layer sub-interconnects 230 are isolated from each other, and adjacent upper layer sub-interconnects 260 are isolated from each other.

[0030] It should be noted that, along the first direction, at the break point 201 of adjacent metal interconnects 280, the lateral distance D1 between the ends of adjacent lower sub-interconnects 230 and upper sub-interconnects 260 should not be too small. If the lateral distance D1 is too small, due to process deviations, the probability of short circuits occurring between adjacent lower sub-interconnects 230 and upper sub-interconnects 260 at the break point 201 of adjacent metal interconnects 280 increases. Therefore, in this embodiment, to ensure process reliability, along the first direction, at the break point 201 of adjacent metal interconnects 280, the lateral distance D1 between the ends of adjacent lower sub-interconnects 230 and upper sub-interconnects 260 is greater than 5 nanometers. Specifically, the lateral distance D1 between the ends of adjacent lower sub-interconnects 230 and upper sub-interconnects 260 is determined according to the circuit design requirements. This embodiment can minimize the lateral distance D1 between the ends of adjacent lower sub-interconnects 230 and upper sub-interconnects 260 in the first direction as the feature size of the device continues to shrink.

[0031] refer to Figure 4 In this embodiment, in the second direction (e.g.) Figure 4 In the Y-direction (as shown), the projections of the lower-layer sub-interconnects 230 and the upper-layer sub-interconnects 260 onto the substrate 100 are alternately arranged. Therefore, in the second direction, the spacing between the lower-layer sub-interconnects 230 facing each other on the sidewall is equal to twice the sum of the spacing between adjacent lower-layer sub-interconnects 230 and upper-layer sub-interconnects 260, and the linewidth of the upper-layer sub-interconnect 260. Therefore, this embodiment increases the spacing between the lower-layer sub-interconnects 230 facing each other on the sidewall. And according to the capacitance formula C = ε rFrom S / 4πkd, we can see that the capacitance is inversely proportional to the spacing of the lower-layer sub-interconnects 230 facing the sidewall; the larger the spacing, the smaller the capacitance, thus reducing the capacitance between the lower-layer sub-interconnects 230. In the capacitance formula, S is the area of ​​the capacitor plates facing each other, d is the spacing between the capacitor plates, and ε... r represents the relative permittivity of the dielectric between the capacitor plates, while k is the electrostatic constant. Similarly, for the upper sub-interconnect 260, in the second direction, the spacing between the upper sub-interconnects 260 facing each other on the sidewalls also increases, thereby reducing the capacitance between the upper sub-interconnects 260.

[0032] Therefore, by alternating the projections of the lower sub-interconnect 230 and the upper sub-interconnect 260 onto the substrate 100 in the second direction, this embodiment effectively reduces the in-layer capacitance of the same-layer metal interconnect 280, thereby reducing the RC delay of the device and correspondingly improving the performance of the semiconductor structure. Specifically, to alternating the projections of the lower sub-interconnect 230 and the upper sub-interconnect 260 onto the substrate 100, for the lower sub-interconnect 230, adjacent lower sub-interconnects 230 are staggered in the first direction along the second direction. Similarly, for the upper sub-interconnect 260, adjacent upper sub-interconnects 260 are staggered in the first direction along the second direction.

[0033] refer to Figure 3 In this embodiment, the upper sub-interconnect 260 further extends along the first direction to the top of a portion of the adjacent lower sub-interconnect 230 and connects to the corresponding lower sub-interconnect 230. The connected upper sub-interconnect 260 and lower sub-interconnect 230 together serve as the same metal interconnect 280. That is, in the same metal interconnect 280, the lower sub-interconnect 230 and the upper sub-interconnect 260 are in the longitudinal direction (e.g., ...). Figure 3 (As shown in the Z-direction) The upper part is stacked. In the back-end process, via interconnect structures located on top of metal interconnect 280 are usually used to achieve electrical connection between metal interconnect 280 and another layer of metal interconnect located above metal interconnect 280. Therefore, by extending the upper sub-interconnect 260 to either side along the first direction to the top of a portion of the adjacent lower sub-interconnect 230, it is beneficial to control the consistency of etching depth during the formation of via interconnect structures, thereby improving process stability. For example, the via interconnect structures located on top of metal interconnect 280 can all be connected to the upper sub-interconnect 260, or all can be connected to the lower sub-interconnect 230.

[0034] It should be noted that when the upper sub-interconnect 260 extends to the top of a portion of the adjacent lower sub-interconnect 230 along the first direction, the length L of the overlapping portion of the lower sub-interconnect 230 and the upper sub-interconnect 260 along the first direction (e.g., Figure 5 The length L of the overlapping portion (as shown) should not be too small or too large. If the length L of the overlapping portion is too small, during the formation of the semiconductor structure, the photolithography alignment error may cause the probability that the upper sub-interconnect 260 cannot be connected to the corresponding lower sub-interconnect 230 to increase, thereby affecting the normal performance of the metal interconnect 280. If the length L of the overlapping portion is too large, it may increase the facing area of ​​the adjacent upper sub-interconnect 260 in the second direction, thereby increasing the intra-layer capacitance of the same layer metal interconnect 280. Therefore, in this embodiment, along the first direction, the length L of the overlapping portion of the lower sub-interconnect 230 and the upper sub-interconnect 260 is 10 nanometers to 2000 nanometers.

[0035] The total thickness of the overlapping lower sub-interconnect 230 and upper sub-interconnect 260 is relatively large. Therefore, according to the circuit design, in a certain region on the substrate 100 (e.g., a region with a high current density in the metal interconnect), the electromigration (EM) effect can be improved by reasonably setting the length L of the overlapping portion of the lower sub-interconnect 230 and upper sub-interconnect 260.

[0036] It should also be noted that when the upper sub-interconnect 260 extends to either side along the first direction to the top of a portion of the adjacent lower sub-interconnect 230, the distance D2 between the ends of the adjacent lower sub-interconnect 230 along the first direction (e.g., ...) Figure 5 The distance D2 between the ends of adjacent lower-layer sub-interconnects 230 should not be too small or too large. If the distance D2 between the ends of adjacent lower-layer sub-interconnects 230 is too small, it will be limited by the process limit of the head-to-head spacing of the lower-layer sub-interconnects 230 along the first direction, making it difficult to form lower-layer sub-interconnects 230 that meet design requirements. If the distance D2 between the ends of adjacent lower-layer sub-interconnects 230 is too large, it will easily lead to the upper-layer sub-interconnect 260 on the side of the lower-layer sub-interconnect 230 being too long. Due to process limitations, the bottom surface of the upper-layer sub-interconnect 260 on the side of the lower-layer sub-interconnect 230 is usually lower than the top surface of the lower-layer sub-interconnect 230. Therefore, when the length of the upper sub-interconnect 260 on the side of the lower sub-interconnect 230 is too large, it is easy to increase the facing area of ​​adjacent upper sub-interconnects 260 in the second direction, or to increase the facing area of ​​adjacent upper sub-interconnects 260 and lower sub-interconnects 230 in the second direction, thereby increasing the intra-layer capacitance of the same-layer metal interconnect 280. Moreover, when the semiconductor structure is operating, the current path becomes longer when it flows through the overlapping lower sub-interconnects 230 and upper sub-interconnects 260, thereby increasing the resistance of the metal interconnect 280. Therefore, in this embodiment, the distance D2 between the ends of adjacent lower sub-interconnects 230 along the first direction is 20 nanometers to 200 nanometers.

[0037] In other embodiments, the layout of the upper and lower sub-interconnects can be of other types depending on the circuit design. For example, some of the lower sub-interconnects are stacked on top of the upper sub-interconnects; or, along the first direction, the upper sub-interconnects are all located on the side of the lower sub-interconnects and isolated from the lower sub-interconnects.

[0038] In this embodiment, during the formation of the semiconductor structure, the dielectric layer 200 in the region corresponding to the upper sub-interconnect 260 needs to be etched to form interconnect trenches for accommodating the upper sub-interconnect 260. The etching process typically includes main etch and over-etch. Compared to the lower sub-interconnect 230, the dielectric layer 200 has lower hardness, and the etching process can easily cause over-etching of the dielectric layer 200 on the side of the lower sub-interconnect 230. Therefore, the bottom surface of the upper sub-interconnect 260 on the side of the lower sub-interconnect 230 is lower than the top surface of the lower sub-interconnect 230. For example, in this embodiment, along the first direction, the region of the upper sub-interconnect 260 that overlaps with the lower sub-interconnect 230 is designated as the overlapping region (not shown), and the remaining region is designated as the non-overlapping region (not shown). The bottom surface of the upper sub-interconnect 260 in the non-overlapping region is lower than the top surface of the lower sub-interconnect.

[0039] In this embodiment, the material of the metal interconnect 280 includes one or more of cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), copper (Cu), platinum (Pt), nickel (Ni), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

[0040] In this embodiment, the lower sub-interconnect 230 includes a first interconnect layer (not shown) and a first diffusion barrier layer (not shown) located between the sidewalls of the first interconnect layer and the dielectric layer 200, and between the bottom of the first interconnect layer and the dielectric layer 200. The first diffusion barrier layer is used to achieve isolation between the first interconnect layer and the dielectric layer 200, blocking conductive material atoms in the first interconnect layer from diffusing into the dielectric layer 200, thereby reducing the impact on the electrical isolation performance of the dielectric layer 200. Furthermore, the first diffusion barrier layer can also improve the electromigration of conductive ions in the first interconnect layer. Therefore, the material of the first diffusion barrier layer includes one or more of Ta, TaN, Ti, and TiN. These materials have high density and can effectively block diffusion. In this embodiment, the material of the first diffusion barrier layer is TaN.

[0041] The material of the first interconnect layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the first interconnect layer is Cu. Cu has low resistivity, which is beneficial for reducing the RC delay of the device, and Cu also has excellent electromigration resistance.

[0042] In this embodiment, the upper sub-interconnect 260 includes a second interconnect layer (not shown), and also includes a second diffusion barrier layer (not shown) located between the sidewall of the second interconnect layer and the dielectric layer 200, between the bottom of the second interconnect layer and the dielectric layer 200, and between the bottom of the second interconnect layer and the top of the lower sub-interconnect 230. For a detailed description of the second interconnect layer and the second diffusion barrier layer, please refer to the corresponding descriptions of the first interconnect layer and the first diffusion barrier layer, respectively, which will not be repeated here.

[0043] In this embodiment, the metal interconnect 280 is spaced apart from the substrate 100 in the longitudinal direction. The semiconductor structure further includes: a first via interconnect structure 241, penetrating the dielectric layer 200 between the bottom of the lower sub-interconnect 230 and the top of the front interconnect 110, wherein the first via interconnect structure 241 electrically connects the lower sub-interconnect 230 and the front interconnect 110; and a second via interconnect structure 242, penetrating the dielectric layer 200 between the bottom of the upper sub-interconnect 260 and the top of the front interconnect 110, wherein the second via interconnect structure 242 electrically connects the upper sub-interconnect 260 and the front interconnect 110. As an example, along the second direction, the linewidth dimension of the bottom of the lower sub-interconnect 230 is larger than the linewidth dimension of the top of the first via interconnect structure 241, and the linewidth dimension of the bottom of the upper sub-interconnect 260 is larger than the linewidth dimension of the top of the second via interconnect structure 242.

[0044] In this embodiment, in the first direction, at the break position of adjacent metal interconnects 280, the portion of the lower sub-interconnect 230 near the end and the portion of the upper sub-interconnect 260 near the end are respectively located above the adjacent front layer interconnect 110. It should be noted that the break position here refers to a physical break, that is, at the head-to-head position of adjacent metal interconnects 280.

[0045] Currently, when metal interconnects are single-layer structures, the head-to-head spacing of the metal interconnects is difficult to further reduce due to process limitations. However, the spacing between adjacent front-layer interconnects in the second direction is small. Therefore, at the break point of adjacent metal interconnects, it is difficult for adjacent metal interconnects in the first direction to be connected to the adjacent front-layer interconnects below through via interconnect structures. In this embodiment, since the lower sub-interconnect 230 and the upper sub-interconnect 260 are arranged adjacently at the break point 201 of the adjacent metal interconnect 280, and the lower sub-interconnect 230 and the upper sub-interconnect 260 are located at different heights in the longitudinal direction, this helps to reduce the process limitations on the head-to-head spacing of the metal interconnects 280. It can minimize the lateral distance D1 between the ends of the adjacent lower sub-interconnects 230 and the upper sub-interconnects 260 in the first direction, thereby allowing the adjacent metal interconnects 280 in the first direction to be connected to the adjacent front-layer interconnects 110 below through via interconnect structures. This correspondingly improves process flexibility.

[0046] Therefore, in this embodiment, in the first direction, at the break position of the adjacent metal interconnect 280, the first through-hole interconnect structure 241 is located near the end of the lower sub-interconnect 230, and the second through-hole interconnect structure 242 is located near the end of the upper sub-interconnect 260.

[0047] In this embodiment, the first via interconnect structure 241 includes a first conductive pillar (not shown) and a third diffusion barrier layer (not shown) located between the sidewall of the first conductive pillar and the dielectric layer 200, and between the bottom of the first conductive pillar and the top of the previous layer interconnect line 110. For a detailed description of the first conductive pillar and the third diffusion barrier layer, please refer to the corresponding descriptions of the first interconnect layer and the first diffusion barrier layer, respectively; they will not be repeated here.

[0048] In this embodiment, the first via interconnect structure 241 and the lower sub-interconnect line 230 are an integral structure. Therefore, during the formation of the semiconductor structure, the first via interconnect structure 241 and the lower sub-interconnect line 230 can be formed using conventional back-end processes. Correspondingly, the first conductive pillar and the first interconnect layer are an integral structure, and the third diffusion barrier layer and the first diffusion barrier layer are an integral structure.

[0049] In this embodiment, the second via interconnect structure 242 includes a second conductive pillar (not shown) and a fourth diffusion barrier layer (not shown) located between the sidewall of the second conductive pillar and the dielectric layer 200, and between the bottom of the second conductive pillar and the top of the previous layer interconnect line 110. For a detailed description of the second conductive pillar and the fourth diffusion barrier layer, please refer to the corresponding descriptions of the first interconnect layer and the first diffusion barrier layer, respectively; these will not be repeated here.

[0050] In this embodiment, the second via interconnect structure 242 and the upper sub-interconnect line 260 are an integral structure. Therefore, during the formation of the semiconductor structure, the second via interconnect structure 242 and the upper sub-interconnect line 260 can be formed using conventional back-end processes. Correspondingly, the second conductive pillar and the second interconnect layer are an integral structure, and the fourth diffusion barrier layer and the second diffusion barrier layer are an integral structure.

[0051] The dielectric layer 200 is used to achieve electrical isolation between the metal interconnects 280. The material of the dielectric layer 200 may include one or more of silicon hydroxide (SiOCH), silicon oxycarbonate (SiOC), silicon oxide (SiO2), fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), and boron-phosphorus-doped silicon dioxide (BPSG). Specifically, the material of the dielectric layer 200 may be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), thereby effectively reducing the capacitance between the metal interconnects 280 and thus reducing the RC delay of the device. In this embodiment, the material of the dielectric layer 200 is silicon hydroxide. Silicon hydroxide is an ultra-low-k dielectric material, which is beneficial for reducing the capacitance between the metal interconnects 280.

[0052] In this embodiment, the dielectric layer 200 includes a first sub-dielectric layer 210 and a second sub-dielectric layer 220 located on top of the first sub-dielectric layer 210. Therefore, the lower sub-interconnect 230 is located in the first sub-dielectric layer 210, the upper sub-interconnect 260 is located in the second sub-dielectric layer 220, the first via interconnect structure 241 penetrates the first sub-dielectric layer 210 between the bottom of the lower sub-interconnect 230 and the top of the previous interconnect 110, and the second via interconnect structure 242 penetrates the first sub-dielectric layer 210 between the bottom of the upper sub-interconnect 260 and the top of the previous interconnect 110.

[0053] The dielectric layer 200 has a stacked structure, so it can be fabricated using conventional back-end processes. The lower sub-interconnect 230 and the first via interconnect structure 241 are formed in the first sub-dielectric layer 210, and a second sub-dielectric layer 220 is formed. The upper sub-interconnect 260 is formed in the second sub-dielectric layer 220, and the second via interconnect structure 242 is formed in the first sub-dielectric layer 210. The formation process of the metal interconnect 280 requires less modification to conventional back-end processes and has high process compatibility.

[0054] In this embodiment, the semiconductor structure further includes: an in-layer etch stop layer 290, located between the top of the lower sub-interconnect 230 exposed by the upper sub-interconnect 260 and the bottom of the second sub-dielectric layer 220, and between the top of the first sub-dielectric layer 210 exposed by the upper sub-interconnect 260 and the bottom of the second sub-dielectric layer 220.

[0055] During the formation of the semiconductor structure, a second sub-dielectric layer 220 needs to be etched within the region corresponding to the upper sub-interconnect 260 to form interconnect trenches for accommodating the upper sub-interconnect 260. During the formation of these interconnect trenches, an in-layer etch stop layer 290 is used to define the etch stop position, thereby mitigating over-etching issues of the exposed lower sub-interconnect line 230 or the first sub-dielectric layer 210 at the bottom of the interconnect trench. The material of the in-layer etch stop layer 290 includes one or more of SiCN (silicon carbonitride), SiCO (silicon oxycarbide), SiN (silicon nitride), Al2O3 (aluminum oxide), and AlN (aluminum nitride). In this embodiment, the material of the in-layer etch stop layer 290 is SiN.

[0056] Figures 6 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0057] Reference Figure 6 and Figure 7 , Figure 6 It is a top view. Figure 7 yes Figure 6 A sectional view along the secant line a1a2, providing a base of 300.

[0058] The substrate 300 provides a process platform for the formation of the semiconductor structure. Depending on the actual process, the substrate 300 includes a substrate and functional structures formed on the substrate, such as semiconductor devices like MOS field-effect transistors, resistive structures, conductive structures, etc.

[0059] In this embodiment, the normal direction of the surface of the substrate 300 is longitudinal. In this embodiment, multiple front-layer interconnects 310 are formed in the substrate 300. Specifically, the front-layer interconnects 310 are exposed on the surface of the substrate 300. The front-layer interconnects 310 are used to connect with subsequently formed metal interconnects, thereby achieving electrical connection between the two. In this embodiment, the front-layer interconnects 310 are along a second direction (e.g., Figure 6 Extending along the Y-direction (as shown in the middle) and along the first direction (e.g. Figure 6 As shown in the X direction, they are arranged in parallel, with the second direction perpendicular to the first direction. For example... Figure 6 As shown, this embodiment illustrates two adjacent front layer interconnects 310 in a first direction.

[0060] refer to Figure 8 A first sub-dielectric layer 410 is formed on the substrate 300.

[0061] The first sub-dielectric layer 410 provides a process platform for the subsequent formation of lower-layer sub-interconnects, and also provides electrical isolation between the lower-layer sub-interconnects. The material of the first sub-dielectric layer 410 may include one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. Specifically, the material of the first sub-dielectric layer 410 may be a low-k dielectric material or an ultra-low-k dielectric material, thereby effectively reducing the capacitance between metal interconnects and thus reducing the RC delay of the device. In this embodiment, the material of the first sub-dielectric layer 410 is silicon hydroxide. Silicon hydroxide is an ultra-low-k dielectric material, which is beneficial for reducing the capacitance between metal interconnects.

[0062] In this embodiment, the first sub-dielectric layer 410 covers the substrate 300 and the front interconnect 310 located in the substrate 300. As an example, the first sub-dielectric layer 410 is formed using a chemical vapor deposition process.

[0063] Reference Figures 9 to 11 Lower layer sub-interconnects 430 (e.g., ...) are formed in the first sub-dielectric layer 410. Figure 11 As shown), the lower layer sub-interconnect 430 extends along the first direction (e.g. Figure 10 (as shown in the X direction) and along the second direction (as shown in the X direction) Figure 10 (As shown in the Y direction) are arranged in parallel, with the first direction perpendicular to the second direction.

[0064] in, Figure 9 This is a cross-sectional view after the first interconnect trench 431 has been formed. Figure 10 This is a top view after the lower-level sub-interconnects 430 are formed. Figure 11 yes Figure 10 A sectional view along the secant line a1a2.

[0065] It should be noted that in traditional back-end processes, each layer of metal interconnects is typically a single-layer structure. However, in this embodiment, the metal interconnects in the same layer are a stacked structure, and the lower sub-interconnect 430 is one of the sub-interconnects in the metal interconnects.

[0066] Specifically, after an upper-layer sub-interconnect is formed above the lower-layer sub-interconnect 430, the upper-layer sub-interconnect and the lower-layer sub-interconnect 230 together constitute a metal interconnect of the same layer. In the later-stage process, the extension directions of adjacent interconnects in the longitudinal direction are perpendicular. Therefore, the extension directions of the lower-layer sub-interconnect 430 and the previous-layer interconnect 310 are perpendicular.

[0067] like Figure 10As shown, in this embodiment, adjacent lower-layer sub-interconnects 430 are isolated in the first direction so that after an upper-layer sub-interconnect is subsequently formed above the lower-layer sub-interconnect 430, the lower-layer sub-interconnect 430 and the upper-layer sub-interconnect are arranged adjacent to each other at the break point of the adjacent metal interconnect. That is, in the first direction, the area between adjacent lower-layer sub-interconnects 430 is used for the subsequent formation of the upper-layer sub-interconnect.

[0068] In this embodiment, along the first direction, the distance D2 between the ends of adjacent lower layer sub-interconnects 430 (e.g., ...) Figure 11 As shown, it meets the requirements of the design rules.

[0069] It should be noted that, since the upper-layer sub-interconnects are subsequently formed above the lower-layer sub-interconnects 430, and these upper-layer sub-interconnects extend to the top of the adjacent lower-layer sub-interconnects 430 along the first direction, the distance D2 between the ends of adjacent lower-layer sub-interconnects 430 along the first direction should not be too small or too large. If the distance D2 between the ends of adjacent lower-layer sub-interconnects 430 is too small, it will be difficult to form a lower-layer sub-interconnect 430 that meets the design requirements due to the limitations of the head-to-head spacing of the lower-layer sub-interconnects 430 along the first direction. If the distance D2 between the ends of adjacent lower-layer sub-interconnects 430 is too large, the length of the upper-layer sub-interconnect on the side of the lower-layer sub-interconnect 430 will be too large after the upper-layer sub-interconnects are formed. Due to process limitations, the bottom surface of the upper-layer sub-interconnect on the side of the lower-layer sub-interconnect 430 will usually be lower than the lower-layer sub-interconnect. The top surface of the sub-interconnect 430 is such that if the length of the upper sub-interconnect on the side of the lower sub-interconnect 430 is too large, it is easy to increase the facing area of ​​adjacent upper sub-interconnects in the second direction, or to increase the facing area of ​​adjacent upper and lower sub-interconnects 430 in the second direction. This results in a higher in-layer capacitance of the same-layer metal interconnect. Moreover, when the semiconductor structure is operating, the path of current flowing through the overlapping lower and upper sub-interconnects 430 becomes longer, resulting in a higher resistance of the metal interconnect. Therefore, in this embodiment, the distance D2 between the ends of adjacent lower sub-interconnects 430 along the first direction is 20 nanometers to 200 nanometers.

[0070] In this embodiment, the material of the lower layer sub-interconnect 430 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0071] In this embodiment, in the first direction, the portion of the lower sub-interconnect 430 near its end is located above the corresponding front interconnect 310, so as to facilitate subsequent electrical connection between the lower sub-interconnect 430 and the front interconnect 310 located below it. Here, the corresponding front interconnect 310 refers to the front interconnect 310 used for electrical connection with the lower sub-interconnect 430.

[0072] like Figure 11 As shown, in this embodiment, during the formation of the lower sub-interconnect 430 in the first sub-dielectric layer 410, the lower sub-interconnect 430 is formed in a portion of the thickness of the first sub-dielectric layer 410, and a first via interconnect structure 441 is also formed in the remaining first sub-dielectric layer 410 between the bottom of the lower sub-interconnect 430 and the top of the previous interconnect 310. The first via interconnect structure 441 electrically connects the lower sub-interconnect 430 and the previous interconnect 310. As an example, along the second direction, the linewidth dimension of the bottom of the lower sub-interconnect 430 is larger than the linewidth dimension of the top of the first via interconnect structure 441.

[0073] Reference Figure 9 Before forming the lower layer sub-interconnect 430 and the first via interconnect structure 441, the method further includes: etching the first sub-dielectric layer 410, forming a first interconnect trench 431 and a first via 432 in the first sub-dielectric layer 410, the top of the exposed portion of the first via 432 of the front layer interconnect 310, and the top of the first via 432 being connected to the bottom of the corresponding first interconnect trench 431, the first interconnect trench 431 extending along a first direction and arranged parallel to each other along a second direction.

[0074] The first interconnect trench 431 is used to provide a spatial location for the formation of the lower layer sub-interconnect 430, and the first through hole 432 is used to provide a spatial location for the formation of the first through hole interconnect structure 441.

[0075] In this embodiment, adjacent first interconnect slots 431 are isolated from each other in the first direction; along the second direction, adjacent first interconnect slots 431 are staggered in the first direction. By staggering the adjacent first interconnect slots 431 in the first direction, after the upper layer sub-interconnects are subsequently formed, the projections of the lower layer sub-interconnects 430 and the upper layer sub-interconnects on the substrate 300 can be alternately arranged in the second direction.

[0076] As an example, along the second direction, the linewidth dimension at the bottom of the first interconnect groove 431 is greater than the linewidth dimension at the top of the first through hole 432.

[0077] In this embodiment, the first interconnect trench 431 and the first via 432 can be formed using an all-in-one etching (AIO etch) method, or the first via 432 can be formed after the first interconnect trench 431 is formed; alternatively, the first interconnect trench 431 can be formed after the first via 432 is formed. Specifically, a dry etching process (e.g., an anisotropic dry etching process) is used to etch the first sub-dielectric layer 410 to form the first interconnect trench 431 and the first via 432. The dry etching process has the characteristic of anisotropic etching, which is beneficial for improving the sidewall morphology quality and dimensional accuracy of the first interconnect trench 431 and the first via 432.

[0078] In this embodiment, along the first direction, the distance D3 between the ends of adjacent first interconnecting trenches 431 (e.g.) Figure 9 (As shown) ranges from 20 nanometers to 200 nanometers.

[0079] Accordingly, refer to Figure 11 The steps of forming the lower sub-interconnect 430 and the first through-hole interconnect structure 441 include: filling the first interconnect material layer in the first interconnect trench 431 and the first through-hole 432 to form the lower sub-interconnect 430 located in the first interconnect trench 431 and the first through-hole interconnect structure 441 located in the first through-hole 441.

[0080] Specifically, after filling the first interconnect material layer, the first interconnect material layer usually also covers the top of the first sub-dielectric layer 410. Therefore, the step of forming the lower sub-interconnect line 430 and the first via interconnect structure 441 further includes: performing a planarization process on the first interconnect material layer (e.g., chemical mechanical polishing) to remove the first interconnect material layer above the top of the first sub-dielectric layer 410.

[0081] The material of the first interconnect material layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the first interconnect material layer is Cu. Cu has a low resistivity, which is beneficial for reducing the RC delay of the device, and Cu also has excellent anti-electromigration ability.

[0082] In this embodiment, before filling the first interconnect material layer in the first interconnect trench 431 and the first through hole 432, a first diffusion barrier layer (not shown) is formed on the sidewall and bottom of the first interconnect trench 431 and the sidewall and bottom of the first through hole 432.

[0083] The first diffusion barrier layer is used to isolate the first interconnect material layer and the first sub-dielectric layer 410. It blocks conductive material atoms in the first interconnect material layer from diffusing into the first sub-dielectric layer 410, thereby reducing the impact on the electrical isolation performance of the first sub-dielectric layer 410. Furthermore, the first diffusion barrier layer can also improve the electromigration of conductive ions in the first interconnect material layer. Therefore, the material of the first diffusion barrier layer includes one or more of Ta, TaN, Ti, and TiN. These materials have high density and can effectively block diffusion. In this embodiment, the material of the first diffusion barrier layer is TaN.

[0084] It should be noted that during the formation of the first diffusion barrier layer, the first diffusion barrier layer 450 also extends to cover the top of the first sub-dielectric layer 410. Correspondingly, during the planarization process of the first interconnect material layer, the first diffusion barrier layer located on top of the first sub-dielectric layer 410 is also removed.

[0085] In this embodiment, a conventional back-end process can be used to form the lower sub-interconnect 430 and the first via interconnect structure 441 in the first sub-dielectric layer 410. The formation process of the metal interconnect has minimal changes to the conventional back-end process and has high process compatibility.

[0086] like Figure 10 As shown, in this embodiment, along the second direction, adjacent lower-layer sub-interconnects 430 are staggered in the first direction. This increases the distance between lower-layer sub-interconnects 430 facing each other on the sidewalls in the second direction. According to the capacitance formula, the greater the distance between capacitor plates, the smaller the capacitance. Therefore, this reduces the capacitance between lower-layer sub-interconnects 430, thereby effectively reducing the intra-layer capacitance of the same-layer metal interconnects, and further reducing the RC delay of the device, thus improving the performance of the semiconductor structure.

[0087] refer to Figure 12 A second sub-dielectric layer 420 is formed, covering the lower sub-interconnect 430 and the first sub-dielectric layer 410. The second sub-dielectric layer 420 and the first sub-dielectric layer 410 constitute dielectric layer 400.

[0088] The second sub-dielectric layer 420 provides a process platform for the subsequent formation of upper-layer sub-interconnects. The second sub-dielectric layer 420 also provides electrical isolation between the upper-layer sub-interconnects. A description of the material of the second sub-dielectric layer 420 can be found in the preceding description of the first sub-dielectric layer 410, and will not be repeated here.

[0089] In this embodiment, the second sub-dielectric layer 420 and the first sub-dielectric layer 410 are made of the same material. As an example, the second sub-dielectric layer 420 is formed using a chemical vapor deposition process.

[0090] Continue to refer to Figure 12 It should be noted that, before forming the second sub-dielectric layer 420 covering the lower sub-interconnect 430 and the first sub-dielectric layer 410, the forming method further includes: forming an in-layer etch stop layer 490 covering the top of the lower sub-interconnect 430 and the top of the first sub-dielectric layer 410.

[0091] The second sub-dielectric layer 420 is subsequently etched to form a second interconnect trench for accommodating the upper sub-interconnects. During the etching process, an in-layer etch stop layer 490 is used to define the etch stop position, thereby improving the over-etching problem of the lower sub-interconnect 430 or the over-etching problem of the first sub-dielectric layer 410 at the bottom of the second interconnect trench. The material of the in-layer etch stop layer 490 includes one or more of SiCN, SiCO, SiN, Al2O3, and AlN. In this embodiment, the material of the in-layer etch stop layer 490 is SiN.

[0092] Accordingly, in the step of forming the second sub-dielectric layer 420, the second sub-dielectric layer 420 covers the in-layer etch stop layer 490.

[0093] Reference Figures 13 to 16 An upper sub-interconnect 460 is formed that penetrates the second sub-dielectric layer 420. The upper sub-interconnect 460 extends along a first direction and is arranged in parallel along a second direction. The upper sub-interconnect 460 and the lower sub-interconnect 430 constitute a metal interconnect 480. Along the first direction, at the break position 401 of the adjacent metal interconnect 480, the lower sub-interconnect 430 and the upper sub-interconnect 460 are arranged adjacent to each other.

[0094] in, Figure 13 It is a sectional view. Figure 14 This is a top view of the lower sub-interconnect 430 and the upper sub-interconnect 460 after the upper sub-interconnect 460 has been formed. Figure 15 This is a 3D view of the lower-layer sub-interconnect 430 and the upper-layer sub-interconnect 460. Figure 16 yes Figure 14 A sectional view along the secant line a1a2.

[0095] In this embodiment, the metal interconnect 480 has a stacked structure, and the upper sub-interconnect 460 is another sub-interconnect within the metal interconnect 480. The upper sub-interconnect 460 and the lower sub-interconnect 430 together constitute the same layer of metal interconnect 480; therefore, the upper sub-interconnect 460 and the lower sub-interconnect 430 extend in the same direction. Specifically, the upper sub-interconnect 460 extends along a first direction and is arranged parallel to it along a second direction.

[0096] In this embodiment, along the first direction, at the break position 401 of adjacent metal interconnects 480, the lower sub-interconnect 430 and the upper sub-interconnect 460 are arranged adjacently. Since the lower sub-interconnect 430 is located in the first sub-sub-dielectric layer 410 and the upper sub-interconnect 460 is located in the second sub-sub-dielectric layer 420, that is, the lower sub-interconnect 430 and the upper sub-interconnect 460 are located at different heights in the normal direction of the substrate 300 surface, therefore, in the first direction, the head-to-head spacing of the metal interconnects 480 is the lateral distance D1 between the ends of adjacent lower sub-interconnects 430 and upper sub-interconnects 460 (e.g., ...). Figure 16 As shown), this helps to reduce the limitations imposed by the process on the head-to-head spacing of the metal interconnect 480 (for example, the head-to-head spacing of the metal interconnect 480 is limited by the photolithography process), and can minimize the lateral distance D1 between the ends of adjacent lower sub-interconnects 430 and upper sub-interconnects 460 in the first direction, thereby reducing the head-to-head spacing of the metal interconnect 480 while ensuring process reliability.

[0097] Therefore, in this embodiment, adjacent upper-layer sub-interconnects 460 are isolated in the first direction.

[0098] It should be noted that, along the first direction, at the break point 401 of adjacent metal interconnects 480, the lateral distance D1 between the ends of adjacent lower sub-interconnects 430 and upper sub-interconnects 460 should not be too small. If the lateral distance D1 is affected by process deviations, it can easily lead to a higher probability of short circuits occurring between adjacent lower sub-interconnects 430 and upper sub-interconnects 460 at the break point 401 of adjacent metal interconnects 480. Therefore, in this embodiment, to ensure process reliability, along the first direction, at the break point 401 of adjacent metal interconnects 480, the lateral distance D1 between the ends of adjacent lower sub-interconnects 430 and upper sub-interconnects 460 is greater than 5 nanometers.

[0099] Specifically, the lateral distance D1 between the ends of adjacent lower sub-interconnects 430 and upper sub-interconnects 460 is determined according to the circuit design requirements. This embodiment can minimize the lateral distance D1 between the ends of adjacent lower sub-interconnects 430 and upper sub-interconnects 460 in the first direction as the feature size of the device continues to shrink.

[0100] like Figure 14 As shown, in this embodiment, in the second direction (e.g. Figure 14 As shown in the Y direction, the projections of the lower layer sub-interconnect 430 and the upper layer sub-interconnect 460 on the substrate 300 are alternately arranged.

[0101] Therefore, in the second direction, the spacing between the lower-layer sub-interconnects 430 facing each other on the sidewall is equal to twice the sum of the spacing between adjacent lower-layer sub-interconnects 430 and upper-layer sub-interconnects 460, and the linewidth of the upper-layer sub-interconnect 460. Thus, this embodiment increases the spacing between the lower-layer sub-interconnects 430 facing each other on the sidewall. According to the capacitance formula, capacitance is inversely proportional to the spacing between the lower-layer sub-interconnects 430 facing each other on the sidewall; the larger the spacing, the smaller the capacitance, thereby reducing the capacitance between the lower-layer sub-interconnects 430.

[0102] Similarly, for the upper sub-interconnect 460, in the second direction, the spacing between the upper sub-interconnects 460 facing each other on the sidewalls is also increased, thereby reducing the capacitance between the upper sub-interconnects 460.

[0103] Therefore, by alternating the projections of the lower sub-interconnect 430 and the upper sub-interconnect 460 onto the substrate 300 in the second direction, this embodiment can effectively reduce the in-layer capacitance of the same-layer metal interconnect 480, thereby reducing the RC delay of the device and correspondingly improving the performance of the semiconductor structure. Accordingly, for the upper sub-interconnect 260, adjacent upper sub-interconnects 260 are staggered in the first direction along the second direction.

[0104] In this embodiment, in the step of forming the upper sub-interconnect 460, adjacent upper sub-interconnects 460 are isolated in the first direction. The upper sub-interconnect 460 also extends along the first direction to either side to the top of a portion of the adjacent lower sub-interconnect 430 and connects to the corresponding lower sub-interconnect 430. The connected upper sub-interconnect 460 and lower sub-interconnect 430 together serve as the same metal interconnect 480. That is, the lower sub-interconnect 430 and the upper interconnect 460 are in the longitudinal direction (e.g., ...). Figure 15 (As shown in the Z-direction) The upper part is stacked. In the back-end process, via interconnect structures located on top of metal interconnect 480 are usually used to achieve electrical connection between metal interconnect 480 and another layer of metal interconnect located above metal interconnect 480. Therefore, by extending the upper sub-interconnect 460 to either side along the first direction to the top of a portion of the adjacent lower sub-interconnect 430, it is beneficial to control the consistency of etching depth during the formation of via interconnect structures, thereby improving process stability. For example, the via interconnect structures located on top of metal interconnect 480 can all be connected to the upper sub-interconnect 460, or all can be connected to the lower sub-interconnect 430.

[0105] It should be noted that when the upper sub-interconnect 460 extends to the top of a portion of the adjacent lower sub-interconnect 430 along the first direction, the length L of the overlapping portion of the lower sub-interconnect 430 and the upper sub-interconnect 460 along the first direction (e.g., Figure 16The length L of the overlapping portion (as shown) should not be too small or too large. If the length L of the overlapping portion is too small, during the formation of the upper sub-interconnect 460, the probability of the upper sub-interconnect 460 failing to connect with the corresponding lower sub-interconnect 430 due to photolithographic alignment errors will increase, thus affecting the normal performance of the metal interconnect 480. If the length L of the overlapping portion is too large, it will easily increase the facing area of ​​adjacent upper sub-interconnects 460 in the second direction, thus increasing the interlayer capacitance of the same layer metal interconnect 480. Therefore, in this embodiment, the length L of the overlapping portion of the lower sub-interconnect 430 and the upper sub-interconnect 460 along the first direction is 10 nanometers to 2000 nanometers.

[0106] The total thickness of the overlapping lower sub-interconnect 430 and upper sub-interconnect 460 is relatively large. Therefore, according to the circuit design, in a certain region on the substrate 300 (e.g., a region with a high current density in the metal interconnect), the electromigration effect can be improved by reasonably setting the length L of the overlapping portion of the lower sub-interconnect 430 and upper sub-interconnect 460.

[0107] In other embodiments, the layout of the upper and lower sub-interconnects can be of other types depending on the circuit design. For example, some of the lower sub-interconnects are stacked on top of the upper sub-interconnects; or, along the first direction, the upper sub-interconnects are all located on the side of the lower sub-interconnects and isolated from the lower sub-interconnects.

[0108] In this embodiment, in the step of forming the upper sub-interconnect 460, the portion of the upper sub-interconnect 460 near the end is located above the corresponding front layer interconnect 310. In the first direction, at the break position 401 of the adjacent metal interconnect 480, the front layer interconnect 310 corresponding to the lower sub-interconnect 430 is arranged adjacent to the front layer interconnect 310 corresponding to the upper sub-interconnect 460.

[0109] Currently, when metal interconnects are single-layer structures, the head-to-head spacing of metal interconnects is difficult to further reduce due to process limitations. However, the spacing between adjacent front-layer interconnects in the second direction is small. Therefore, at the break point of adjacent metal interconnects, it is difficult for adjacent metal interconnects in the first direction to be connected to the adjacent front-layer interconnects below through via interconnect structures. In this embodiment, since the lower-layer sub-interconnect 430 and the upper-layer sub-interconnect 460 are arranged adjacently at the break point 401 of adjacent metal interconnects 480, and the lower-layer sub-interconnect 430 and the upper-layer sub-interconnect 460 are located at different heights in the longitudinal direction, this helps to reduce the process limitations on the head-to-head spacing of metal interconnects 480. It can minimize the lateral distance D1 between the ends of adjacent lower-layer sub-interconnects 430 and upper-layer sub-interconnects 460 in the first direction, thereby solving the problem of adjacent metal interconnects 480 in the first direction being connected to the adjacent front-layer interconnects 310 below through via interconnect structures. This correspondingly improves the flexibility of layout design.

[0110] Moreover, in this embodiment, after forming the lower sub-interconnect 430 and the first via interconnect structure 440, the second sub-dielectric layer 420 and the upper sub-interconnect 460 located in the second sub-dielectric layer 420 are formed. The formation process of the second sub-dielectric layer 420 requires less modification to the traditional back-end process and has high process compatibility.

[0111] In this embodiment, the material of the upper sub-interconnect 460 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0112] In this embodiment, during the formation of the upper sub-interconnect 460 penetrating the second sub-dielectric layer 420, a second via interconnect structure 442 is also formed penetrating the first sub-dielectric layer 410 between the bottom of the upper sub-interconnect 460 and the top of the previous layer interconnect 310. The second via interconnect structure 442 electrically connects the upper sub-interconnect 460 and the previous layer interconnect 310. As an example, along the second direction, the linewidth dimension of the bottom of the upper sub-interconnect 460 is larger than the linewidth dimension of the top of the second via interconnect structure 442.

[0113] In this embodiment, adjacent metal interconnects 480 in the first direction are connected to the adjacent front layer interconnects 310 below through the second through-hole interconnect structure 442 and the first through-hole interconnect structure 441, respectively.

[0114] Reference Figure 13Before forming the upper sub-interconnect 460 and the second via interconnect structure 442, the method further includes: etching the second sub-dielectric layer 420 to form a second interconnect trench 461 penetrating the second sub-dielectric layer 420 and a second via 462 penetrating the bottom of the first sub-dielectric layer 410. The second interconnect trench extends along a first direction and is arranged in parallel along a second direction. Along the first direction, at the disconnection position 402 between the adjacent second interconnect trench 461 and the lower sub-interconnect 430, the second interconnect trench 461 and the lower sub-interconnect 430 are arranged adjacent to each other.

[0115] The second interconnect trench 461 provides space for forming the upper sub-interconnect 460, and the second via 462 provides space for forming the second via interconnect structure 442. Accordingly, in this embodiment, along the first direction, at the disconnection position 402 between adjacent second interconnect trenches 461 and lower sub-interconnects 430, the lateral distance D4 between the ends of adjacent second interconnect trenches 461 and lower sub-interconnects 430 is greater than 5 nanometers.

[0116] like Figure 13 As shown, in this embodiment, in the first direction, the second interconnect trench 461 exposes a portion of the top surface of the lower sub-interconnect 430 and the first sub-dielectric layer 410 corresponding to the side of the lower sub-interconnect 430. In this embodiment, in the first direction, the second interconnect trench 500 exposes a portion of the top surface of the lower sub-interconnect 430, thereby enabling the upper sub-interconnect 460 subsequently formed in the second interconnect trench 500 to partially stack with the lower sub-interconnect 230 and achieve electrical connection, with the connected lower sub-interconnect 230 and upper sub-interconnect 460 forming the same metal interconnect 480.

[0117] Accordingly, in this embodiment, along the first direction, the length of the lower layer sub-interconnect line 430 exposed by the second interconnect trench 461 is 10 nanometers to 2000 nanometers.

[0118] In other embodiments, depending on the circuit design, in certain regions on the substrate (e.g., regions with high current density in the metal interconnects), the total thickness of the metal interconnects in the region is increased by appropriately setting the length of the second interconnect trench exposing the corresponding lower-layer sub-interconnects, thereby improving the EM effect.

[0119] In this embodiment, for the lower sub-interconnect 430, along the second direction, adjacent lower sub-interconnects 430 are staggered in the first direction. Correspondingly, in the first direction, adjacent second interconnect slots 461 are isolated from each other. Along the second direction, adjacent second interconnect slots 461 are staggered in the first direction, and the projections of the lower sub-interconnects 430 and the second interconnect slots 500 on the substrate 300 are alternately arranged.

[0120] In this embodiment, during the etching step of the second sub-dielectric layer 420, the top of the in-layer etch stop layer 490 is used as the etching stop position. There is an etching selectivity ratio between the second sub-dielectric layer 420 and the in-layer etch stop layer 490. Therefore, by using the top of the in-layer etch stop layer 490 as the etching stop position, the probability of the lower sub-interconnect 230 or the first sub-dielectric layer 410 being over-etched is reduced, while ensuring that the etching of the second sub-dielectric layer 420 in each region is completed.

[0121] Accordingly, during the formation of the second interconnect trench 461 and the second via 462, after etching the second sub-dielectric layer 420, the process further includes etching the exposed in-layer etch stop layer 490.

[0122] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to etch the second sub-dielectric layer 420 and the etching stop layer 490 to form the second interconnect trench 500. The dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the second interconnect trench 461 and the second via 462.

[0123] It should be noted that during the formation of the second interconnect trench 500, the etching process typically includes main etching and over-etching. Compared with the lower sub-interconnect 430, the first sub-dielectric layer 410 has a lower hardness. Therefore, the etching process is prone to causing a certain degree of over-etching to the first sub-dielectric layer 410 at the bottom of the second interconnect trench 500. Accordingly, after the formation of the second interconnect trench 500, the top surface of the exposed first sub-dielectric layer 410 of the second interconnect trench 500 is lower than the top surface of the lower sub-interconnect 430.

[0124] In this embodiment, in conjunction with the reference Figures 14 to 16 The step of forming the upper sub-interconnect 460 and the second via interconnect structure 442 includes: filling the second interconnect trench 461 and the second via 462 with a second interconnect material layer to form the upper sub-interconnect 460 located in the second interconnect trench 461 and the second via interconnect structure 442 located in the second via 462.

[0125] Specifically, after filling the second interconnect material layer, the second interconnect material layer usually also covers the top of the second sub-dielectric layer 420. Therefore, the step of forming the upper sub-interconnect line 460 and the second via interconnect structure 442 further includes: planarizing the second interconnect material layer (e.g., chemical mechanical polishing) to remove the second interconnect material layer above the top of the second sub-dielectric layer 420.

[0126] The material of the second interconnect material layer includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, and Ni. In this embodiment, the material of the second interconnect material layer is Cu. Cu has a low resistivity, which is beneficial for reducing the RC delay of the device, and Cu also has excellent anti-electromigration ability.

[0127] In this embodiment, before filling the second interconnect material layer into the second interconnect trench 461 and the second through hole 462, a second diffusion barrier layer is formed on the sidewall and bottom of the second interconnect trench 461 and the sidewall and bottom of the second through hole 462.

[0128] It should be noted that during the formation of the second diffusion barrier layer, the second diffusion barrier layer also extends to cover the top of the second sub-dielectric layer 420. Correspondingly, during the planarization process of the second interconnect material layer, the second diffusion barrier layer located on top of the second sub-dielectric layer 420 is also removed. For a detailed description of the second diffusion barrier layer and its material, please refer to the aforementioned description of the first diffusion barrier layer, which will not be repeated here.

[0129] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a dielectric layer on the substrate; a plurality of back-stage metal interconnection lines in the dielectric layer, the metal interconnection lines comprising lower-layer sub-interconnection lines and upper-layer sub-interconnection lines, the lower-layer sub-interconnection lines being in a partial thickness of the dielectric layer, the upper-layer sub-interconnection lines being in a remaining thickness of the dielectric layer above the lower-layer sub-interconnection lines, the lower-layer sub-interconnection lines and the upper-layer sub-interconnection lines extending along a first direction and being arranged in parallel along a second direction, the first direction being perpendicular to the second direction, wherein along the first direction, the lower-layer sub-interconnection lines and the upper-layer sub-interconnection lines are arranged adjacently at a disconnection position of adjacent metal interconnection lines, and the upper-layer sub-interconnection lines and the lower-layer sub-interconnection lines stacked together form the same layer of the metal interconnection lines.

2. The semiconductor structure of claim 1, wherein, The substrate is provided with a plurality of front-layer interconnection lines, and a normal direction of a surface of the substrate is a longitudinal direction; The metal interconnection lines are spaced apart from the substrate in the longitudinal direction; The semiconductor structure further comprises: a first via interconnection structure penetrating the dielectric layer between a bottom of the lower-layer sub-interconnection line and a top of the front-layer interconnection line, the first via interconnection structure electrically connecting the lower-layer sub-interconnection line and the front-layer interconnection line; a second via interconnection structure penetrating the dielectric layer between a bottom of the upper-layer sub-interconnection line and a top of the front-layer interconnection line, the second via interconnection structure electrically connecting the upper-layer sub-interconnection line and the front-layer interconnection line.

3. The semiconductor structure of claim 2, wherein, The front-layer interconnection lines extend along the second direction and are arranged in parallel along the first direction; In the first direction, at the disconnection position of adjacent metal interconnection lines, a portion of the lower-layer sub-interconnection line close to an end portion and a portion of the upper-layer sub-interconnection line close to an end portion are respectively above adjacent front-layer interconnection lines.

4. The semiconductor structure of claim 1, wherein, In the first direction, the lower-layer sub-interconnection lines are spaced apart from each other, the upper-layer sub-interconnection lines are spaced apart from each other, and the upper-layer sub-interconnection lines extend to a portion of a top of an adjacent lower-layer sub-interconnection line on any side along the first direction and are connected to the corresponding lower-layer sub-interconnection line, the connected upper-layer sub-interconnection line and lower-layer sub-interconnection line together form the same metal interconnection line.

5. The semiconductor structure of claim 1, wherein, In the second direction, projections of the lower-layer sub-interconnection lines and the upper-layer sub-interconnection lines on the substrate are arranged alternately.

6. The semiconductor structure of any one of claims 1 to 5, wherein, A bottom surface of the upper-layer sub-interconnection line on a side of the lower-layer sub-interconnection line is lower than a top surface of the lower-layer sub-interconnection line.

7. The semiconductor structure of any one of claims 1-5, wherein the semiconductor structure is a vertical semiconductor structure. The dielectric layer comprises: a first sub-dielectric layer and a second sub-dielectric layer on a top of the first sub-dielectric layer; The lower-layer sub-interconnection lines are in the first sub-dielectric layer, and the upper-layer sub-interconnection lines are in the second sub-dielectric layer.

8. The semiconductor structure of claim 7, wherein, The semiconductor structure further comprises: an in-layer etching stop layer between a top of the lower-layer sub-interconnection line exposed by the upper-layer sub-interconnection line and a bottom of the second sub-dielectric layer, and between a top of the first sub-dielectric layer exposed by the upper-layer sub-interconnection line and a bottom of the second sub-dielectric layer.

9. The semiconductor structure of claim 8, wherein, The material of the in-layer etching stop layer comprises one or more of SiCN, SiCO, SiN, Al2O3 and AlN.

10. The semiconductor structure of claim 2, wherein, The first via interconnection structure and the lower-layer sub-interconnection line are an integral structure.

11. The semiconductor structure of claim 2, wherein, The second via interconnection structure and the upper sub-interconnection line are an integral structure.

12. The semiconductor structure of claim 1, wherein, In the first direction, a transverse distance between end portions of adjacent lower and upper sub-interconnection lines at a disconnection position of the metal interconnection line is greater than 5 nanometers.

13. The semiconductor structure of claim 4, wherein, In the first direction, a length of an overlapping portion of the lower and upper sub-interconnection lines is 10 nanometers to 2000 nanometers.

14. The semiconductor structure of claim 4, wherein, In the first direction, a distance between end portions of adjacent lower sub-interconnection lines is 20 nanometers to 200 nanometers.

15. The semiconductor structure of claim 1, wherein, The material of the metal interconnection line includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

16. The semiconductor structure of claim 1, wherein, The material of the dielectric layer includes one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG.

17. A method of forming a semiconductor structure, comprising: The method comprises: providing a substrate; forming a first sub-dielectric layer on the substrate; forming lower sub-interconnection lines in the first sub-dielectric layer, the lower sub-interconnection lines extending in a first direction and being arranged in parallel in a second direction, the first direction being perpendicular to the second direction; forming a second sub-dielectric layer covering the lower sub-interconnection lines and the first sub-dielectric layer; forming upper sub-interconnection lines through the second sub-dielectric layer, the upper sub-interconnection lines extending in the first direction and being arranged in parallel in the second direction, the upper sub-interconnection lines and the lower sub-interconnection lines constituting metal interconnection lines in a back-end-of-line, wherein in the first direction, the lower sub-interconnection lines and the upper sub-interconnection lines are arranged adjacently at a disconnection position of the metal interconnection line, and the upper sub-interconnection lines and the lower sub-interconnection lines stacked together constitute the metal interconnection line in the same layer.

18. The method of forming a semiconductor structure of claim 17, wherein In the step of providing the substrate, a plurality of front-layer interconnection lines are formed in the substrate; In the process of forming the lower sub-interconnection lines in the first sub-dielectric layer, the lower sub-interconnection lines are formed in a partial thickness of the first sub-dielectric layer, and a first via interconnection structure is also formed in the first sub-dielectric layer remaining between the bottom of the lower sub-interconnection line and the top of the front-layer interconnection line, the first via interconnection structure electrically connecting the lower sub-interconnection line and the front-layer interconnection line; In the process of forming the upper sub-interconnection lines through the second sub-dielectric layer, a second via interconnection structure is also formed through the first sub-dielectric layer between the bottom of the upper sub-interconnection line and the top of the front-layer interconnection line, the second via interconnection structure electrically connecting the upper sub-interconnection line and the front-layer interconnection line.

19. The method of forming a semiconductor structure of claim 18, wherein In the step of providing the substrate, the front-layer interconnection lines extend in the second direction and are arranged in parallel in the first direction; In the step of forming the lower sub-interconnection lines in the first sub-dielectric layer, a portion of the lower sub-interconnection line close to an end portion is located above a corresponding front-layer interconnection line; In the step of providing the substrate, a plurality of front-layer interconnection lines are formed in the substrate; In the step of forming the upper layer sub-interconnection lines through the second sub-dielectric layer, the portions of the upper layer sub-interconnection lines close to the ends are located above the corresponding front layer interconnection lines, and in the first direction, the corresponding front layer interconnection lines of the lower layer sub-interconnection lines are arranged adjacent to the corresponding front layer interconnection lines of the upper layer sub-interconnection lines at the disconnected positions of the adjacent metal interconnection lines.

20. The method of forming a semiconductor structure of claim 17, wherein In the step of forming the lower layer sub-interconnection lines in the first sub-dielectric layer, in the first direction, the lower layer sub-interconnection lines are isolated from each other. In the step of forming the upper layer sub-interconnection lines through the second sub-dielectric layer, in the first direction, the upper layer sub-interconnection lines are isolated from each other, and the upper layer sub-interconnection lines extend to the top portions of the adjacent lower layer sub-interconnection lines on either side in the first direction and are connected to the corresponding lower layer sub-interconnection lines, and the connected upper layer sub-interconnection lines and lower layer sub-interconnection lines together serve as the same metal interconnection line.

21. The method of forming a semiconductor structure of claim 17, wherein In the step of forming the upper layer sub-interconnection lines through the second sub-dielectric layer, in the second direction, the projections of the lower layer sub-interconnection lines and upper layer sub-interconnection lines on the substrate are arranged alternately.

22. The method of forming a semiconductor structure of claim 18, wherein Before forming the lower layer sub-interconnection lines and the first via interconnection structure, the method further comprises: etching the first sub-dielectric layer to form a first interconnection groove and a first via in the first sub-dielectric layer, the first via exposes the top portion of the front layer interconnection line, and the top portion of the first via is in communication with the bottom portion of the corresponding first interconnection groove, the first interconnection groove extends in the first direction and is arranged in parallel in the second direction; The step of forming the lower layer sub-interconnection lines and the first via interconnection structure comprises: filling a first interconnection material layer in the first interconnection groove and the first via to form the lower layer sub-interconnection lines in the first interconnection groove and the first via interconnection structure in the first via.

23. The method of forming a semiconductor structure of claim 18, wherein, Before forming the upper layer sub-interconnection lines and the second via interconnection structure, the method further comprises: etching the second sub-dielectric layer to form a second interconnection groove through the second sub-dielectric layer and a second via through the bottom portion of the second interconnection groove and the first sub-dielectric layer, the second interconnection groove extends in the first direction and is arranged in parallel in the second direction, and in the first direction, the second interconnection groove and the lower layer sub-interconnection line are arranged adjacent to each other at the disconnected positions of the adjacent second interconnection groove and lower layer sub-interconnection line; The step of forming the upper layer sub-interconnection lines and the second via interconnection structure comprises: filling a second interconnection material layer in the second interconnection groove and the second via to form the upper layer sub-interconnection lines in the second interconnection groove and the second via interconnection structure in the second via.

24. The method of forming a semiconductor structure of claim 23, wherein, After forming the lower layer sub-interconnection lines and before forming the second sub-dielectric layer, the forming method further comprises: forming an in-layer etching stop layer covering the top portion of the lower layer sub-interconnection line and the top portion of the first sub-dielectric layer; In the step of etching the second sub-dielectric layer, the top portion of the in-layer etching stop layer is used as the etching stop position; In the step of etching the second sub-dielectric layer, the top portion of the in-layer etching stop layer is used as the etching stop position; In the process of forming the second interconnection groove and the second via, after etching the second sub-dielectric layer, the process further comprises: etching the exposed layer-in-layer etching stop layer.

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