readout circuit layout, structure and memory layout

Abstract

Embodiments of the present application provide a readout circuit layout, a structure and a memory layout. The readout circuit layout comprises a readout amplification module, a first processing module and a second processing module arranged along a preset direction. The readout amplification module is configured to read out a voltage of a bit line. The first processing module and the second processing module are configured to at least perform noise elimination on an output signal of the readout amplification module. The readout amplification module comprises a first NMOS region and a first PMOS region arranged close to the first processing module, and a second NMOS region and a second PMOS region arranged close to the second processing module. The first NMOS region, the first PMOS region, the second PMOS region and the second NMOS region are arranged along the preset direction. The active patterns of the first NMOS region and the second NMOS region are independently arranged. The active patterns of the first PMOS region and the second PMOS region are independently arranged. The device performance of MOS transistors in the memory readout circuit is improved, thereby reducing the influence of timing mismatch in the readout process of the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory structure design, and in particular to a readout circuit layout, structure, and memory layout. Background Technology

[0002] Dynamic Random Access Memory (DRAM) performs data writing operations by storing charge in the capacitors of the memory cells, and performs data reading operations by reading the charge in the capacitors of the memory cells.

[0003] In DRAM, the memory cell is connected to bit line BL and complementary bit line BLB. During the data readout operation, the sense amplifier in the readout circuit is used to read out the voltage of bit line BL and complementary bit line BLB, and amplify the voltage difference between bit line BL and complementary bit line BLB.

[0004] However, the applicant discovered that, for the sense amplifier structure in the readout circuit, the mismatch between the active regions of the MOS transistors could cause timing misalignment during memory readout. Summary of the Invention

[0005] This application provides a readout circuit layout, structure, and memory layout, and provides a design for an active MOS transistor pattern to improve the device performance of the MOS transistor in the memory readout circuit, thereby reducing the impact of timing mismatch during the memory readout process.

[0006] To address the aforementioned technical problems, this application provides a readout circuit layout, including: a readout amplification module, a first processing module, and a second processing module arranged along a preset direction. The readout amplification module is used to read the voltage of a bit line, and the first and second processing modules are at least used to perform noise cancellation on the output signal of the readout amplification module. The readout amplification module includes: a first NMOS region and a first PMOS region disposed near the first processing module, and a second NMOS region and a second PMOS region disposed near the second processing module. The first NMOS region, the first PMOS region, the second PMOS region, and the second NMOS region are arranged along the preset direction. The active patterns of the first NMOS region and the second NMOS region are independently configured, as are the active patterns of the first PMOS region and the second PMOS region.

[0007] Compared with related technologies, for the MOS structure of the sense amplifier in the readout circuit layout, the active patterns of the two NMOS transistors are set independently, and the active patterns of the two PMOS transistors are set independently. This makes the active regions of the MOS structure in the subsequently formed sense amplifier independent, which can reduce the signal interference problem caused by the sharing of active regions in MOS transistors, thereby improving the device performance of MOS transistors in the readout circuit and reducing the impact of timing mismatch during memory readout.

[0008] Furthermore, the active patterns in the first NMOS region and the second NMOS region are symmetrically arranged, as are the active patterns in the first PMOS region and the second PMOS region. The symmetrical arrangement of MOS transistors within the same sense amplifier ensures a consistent environment for the MOS transistors that need to be matched within the same sense amplifier, thereby balancing the device characteristics of each MOS transistor in the same sense amplifier and improving memory stability.

[0009] Furthermore, the positions of the active patterns in the first processing module and the second processing module are symmetrically arranged. This symmetrical arrangement of the positions of the first and second processing modules within the same sensing amplifier further ensures a consistent environment for the MOS transistors that need to be matched within the same sensing amplifier, thereby improving memory stability.

[0010] Additionally, the first processing module includes a first offset elimination region, a first isolation region, and an equalization region; the first offset elimination region is configured to connect bit lines to complementary readout bit lines, the first isolation region is configured to connect bit lines to readout bit lines, and the equalization region is configured to connect readout bit lines to complementary readout bit lines; the second processing module includes a precharge region, a second isolation region, and a second offset elimination region; the precharge region is configured to precharge bit lines and complementary bit lines based on a precharge command, the second isolation region is configured to connect complementary bit lines to complementary readout bit lines, and the second offset elimination region is configured to connect complementary bit lines to readout bit lines; the active patterns of the first offset elimination region, the first isolation region, and the equalization region are interconnected, and the active patterns of the precharge region, the second isolation region, and the second offset elimination region are interconnected.

[0011] In addition, the active pattern of the first processing module is located between the active pattern of the first NMOS region and the active pattern of the first PMOS region; the active pattern of the second processing module is located between the active pattern of the second NMOS region and the active pattern of the second PMOS region.

[0012] In addition, in a preset direction, the active pattern of the first NMOS region is disposed on the side of the active pattern of the first processing module away from the active pattern of the second processing module, the active pattern of the second NMOS region is disposed on the side of the active pattern of the second processing module away from the active pattern of the first processing module, and the active patterns of the first PMOS region and the second PMOS region are disposed between the active patterns of the first processing module and the second processing module.

[0013] In addition, in a preset direction, the active pattern of the first processing module is located on the side of the active pattern of the first NMOS region and the active pattern of the first PMOS region that are away from the active pattern of the second processing module, and the active pattern of the second processing module is located on the side of the active pattern of the second NMOS region and the active pattern of the second PMOS region that are away from the active pattern of the first processing module.

[0014] In addition, in a preset direction, the active pattern of the first PMOS region is located on the side of the active pattern of the first NMOS region that is close to the active pattern of the second processing module, and the active pattern of the first processing module is located on the side of the active pattern of the first NMOS region that is far away from the active pattern of the second processing module. The active pattern of the second PMOS region is located on the side of the active pattern of the second NMOS region that is close to the active pattern of the first processing module, and the active pattern of the second processing module is located on the side of the active pattern of the second NMOS region that is far away from the active pattern of the first processing module.

[0015] Furthermore, the active patterns of the first processing module and the first NMOS region are located in the same well region, and the active patterns of the second processing module and the second NMOS region are located in the same well region. Active patterns located in the same well region ensure identical ion implantation characteristics, making the ion implantation characteristics of the active patterns of the first processing module and the first NMOS region the same, and the ion implantation characteristics of the active patterns of the second processing module and the second NMOS region the same, further balancing the device characteristics of the various MOS transistors in the same sense amplifier.

[0016] In addition, in a preset direction, the active pattern of the first processing module is disposed on the side of the active pattern of the first NMOS region and the active pattern of the first PMOS region close to the active pattern of the second processing module, and the active pattern of the second processing module is disposed on the side of the active pattern of the second NMOS region and the active pattern of the second PMOS region close to the active pattern of the first processing module.

[0017] In addition, in a preset direction, the active pattern of the first NMOS region is located on the side of the active pattern of the first PMOS region that is far away from the active pattern of the second processing module, the active pattern of the first processing module is located on the side of the active pattern of the first PMOS region that is close to the active pattern of the second processing module, the active pattern of the second NMOS region is located on the side of the active pattern of the second PMOS region that is far away from the active pattern of the first processing module, and the active pattern of the second processing module is located on the side of the active pattern of the second PMOS region that is close to the active pattern of the first processing module.

[0018] In addition, the active pattern of the first PMOS region is located on the side of the active pattern of the first NMOS region that is far away from the active pattern of the second processing module, and the active pattern of the first processing module is located on the side of the active pattern of the first NMOS region that is close to the active pattern of the second processing module. The active pattern of the second PMOS region is located on the side of the active pattern of the second NMOS region that is far away from the active pattern of the first processing module, and the active pattern of the second processing module is located on the side of the active pattern of the second NMOS region that is close to the active pattern of the first processing module.

[0019] Furthermore, the active patterns of the first processing module, the second processing module, the first NMOS region, and the second NMOS region are all located in the same well region. Active patterns located in the same well region ensure identical ion implantation characteristics, making the ion implantation features of the active patterns of the first processing module, the first NMOS region, the second processing module, and the second NMOS region identical, further balancing the device characteristics of the various MOS transistors in the same sense amplifier.

[0020] Furthermore, in a predetermined direction, the active pattern length of the first NMOS region is greater than that of the first PMOS region; the active pattern length of the second NMOS region is greater than that of the second PMOS region. Compared to the active pattern of PMOS, the active pattern of NMOS has a wider dimension, which can provide greater driving capability.

[0021] In addition, the gate patterns of the first NMOS region, the second NMOS region, the gate patterns of the first PMOS region, and the gate patterns of the second PMOS region are arranged along a preset direction, and the gate patterns of the first processing module and the second processing module are arranged in a direction perpendicular to the preset direction.

[0022] This application embodiment also provides a memory layout, including the above-mentioned readout circuit layout. Multiple readout circuit layouts are arranged sequentially in the vertical direction of a preset direction. Two adjacent readout circuit layouts constitute a readout circuit layout group. The readout circuit layout groups share the same active pattern, and the distance between adjacent readout circuit layout groups is equal.

[0023] In addition, the active patterns of the first NMOS region and the second NMOS region are symmetrically arranged, and the active patterns of the first PMOS region and the second PMOS region are symmetrically arranged.

[0024] In addition, the positions of the active patterns in the first processing module and the active patterns in the second processing module are symmetrically arranged.

[0025] Additionally, the first processing module includes a first offset elimination region, a first isolation region, and an equalization region; the first offset elimination region is configured to connect bit lines to complementary readout bit lines, the first isolation region is configured to connect bit lines to readout bit lines, and the equalization region is configured to connect readout bit lines to complementary readout bit lines; the second processing module includes a precharge region, a second isolation region, and a second offset elimination region; the precharge region is configured to precharge bit lines and complementary bit lines based on a precharge command, the second isolation region is configured to connect complementary bit lines to complementary readout bit lines, and the second offset elimination region is configured to connect complementary bit lines to readout bit lines; the active patterns of the first offset elimination region, the first isolation region, and the equalization region are interconnected, and the active patterns of the precharge region, the second isolation region, and the second offset elimination region are interconnected.

[0026] In addition, the memory layout also includes: a connection pattern disposed at the edge of the precharge area and in contact with the active pattern of the precharge area, wherein the connection pattern is used to contact the active patterns of all precharge areas in a direction perpendicular to a preset direction.

[0027] This application embodiment also provides a readout circuit structure, including: a readout amplifier arranged along a preset direction, a first processing circuit, and a second processing circuit, wherein the readout amplifier is used to read out the voltage of the bit line, and the first processing circuit and the second processing circuit are at least used to perform noise cancellation on the output signal of the readout amplifier; the readout amplifier includes: a first NMOS transistor and a first PMOS transistor disposed near the first processing circuit, and a second NMOS transistor and a second PMOS transistor disposed near the second processing circuit, wherein the first processing circuit, the first NMOS transistor, the first PMOS transistor, the second processing circuit, the second NMOS transistor, and the second PMOS transistor are arranged along the preset direction; wherein the active layer of the first NMOS transistor and the active layer of the second NMOS transistor are independently disposed, and the active layer of the first PMOS transistor and the active layer of the second PMOS transistor are independently disposed.

[0028] Compared with related technologies, for the MOS structure of the sense amplifier in the readout circuit layout, the active layers of the two NMOS transistors are set independently, and the active layers of the two PMOS transistors are set independently. This can reduce the signal interference problem caused by the sharing of active layers in the MOS transistors, thereby improving the device performance of the MOS transistors in the readout circuit and reducing the impact of timing mismatch during memory readout. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the memory structure;

[0030] Figure 2 A circuit diagram for the readout circuit;

[0031] Figure 3 The timing diagram for the readout circuit;

[0032] Figure 4 A schematic diagram of the signals in bit line BL / complementary bit line BLB when the MOS transistor of the sense amplifier in the readout circuit is mismatched;

[0033] Figures 5-10 This is a schematic diagram of the readout circuit layout provided in one embodiment of this application;

[0034] Figure 11 This is a schematic diagram of the memory layout provided in another embodiment of this application. Detailed Implementation

[0035] refer to Figure 1 In the structure of the memory, each memory array 100 contains multiple memory cells 1000. Each memory cell 1000 is a 1T1C (1 transistor 1 capacitor) structure consisting of a transistor and a capacitor. The read / write conversion circuit 200, the read circuit 300, the equalization circuit 400, and the input / output circuit 500 are arranged between adjacent memory arrays.

[0036] In this configuration, one of the source or drain terminals of the unit transistor is connected to the unit capacitor, and the other is connected to the bit line BL / complementary bit line BLB. The word line WL is connected to the gate of the unit transistor and is used to selectively turn on the gate of the corresponding unit transistor, so that the unit capacitor is connected to the bit line BL / complementary bit line BLB. This enables the electrical signal in the bit line BL / complementary bit line BLB to be written into the unit capacitor, or the electrical signal in the unit capacitor to be read out into the bit line BL / complementary bit line BLB.

[0037] The equalization circuit 400 connects bit line BL and complementary bit line BLB to equalize the voltage between bit line BL and complementary bit line BLB during the pre-charging phase.

[0038] The input / output circuit 500 includes an input / output transistor, one of which is connected to a bit line BL / complementary bit line BLB, and the other is connected to a local data line Local I / O. The gate is used to receive a selection signal and selects to turn on the bit line BL / complementary bit line BLB corresponding to the selection signal according to the selection signal, so that the bit line BL / complementary bit line BLB is connected to the local data line Local I / O, thereby realizing the data transfer between the bit line BL / complementary bit line BLB and the local data line Local I / O.

[0039] The local data line (Local I / O) is connected to the global data line (Global I / O) through the read / write conversion circuit 200, thereby enabling the transfer of external data or data from the local sensing amplifier (located in the read / write conversion circuit 200) to the local data line (Local I / O), or the output of data from the local data line (Local I / O) to the global data line (Global I / O).

[0040] The readout circuit 300 is connected between bit line BL and complementary bit line BLB. When the electrical signal in the unit capacitor is read out to bit line BL / complementary bit line BLB, since the unit capacitor and bit line BL / complementary bit line BLB share the charge, the voltage of bit line BL / complementary bit line BLB is increased or decreased by a voltage change ΔV by the pre-charge voltage. The readout circuit 300 is used to read out and amplify the voltage change ΔV between bit line BL and complementary bit line BLB in response to the first control signal PCS and the second control signal NCS.

[0041] Specifically, refer to Figure 2 Readout circuit 300 (reference) Figure 1 ), including: a first PMOS transistor <p1>Second PMOS transistor <p2>First NMOS transistor <n1>Second NMOS transistor <n2>Among them, the first PMOS transistor <p1>One of the source or drain terminals is connected to the complementary readout bit line SABLB, and the other is used to receive the first control signal PCS, with its gate connected to the readout bit line SABLB; the second PMOS transistor <p2>One of the source or drain terminals is connected to the read bit line SABL, the other is used to receive the first control signal PCS, and the gate is connected to the complementary read bit line SABLB; the first NMOS transistor <n1>One of the source or drain terminals is connected to the complementary readout bit line SABLB, the other is used to receive the second control signal NCS, and the gate is connected to the bit line BL; the second NMOS transistor <n2>One of the source or drain terminals is connected to the read bit line BLB, the other is used to receive the second control signal NCS, and the gate is connected to the complementary read bit line SABLB.

[0042] Figure 2 The readout circuit 300 is also used for noise cancellation; that is, the readout circuit 300 also includes: a first isolation MOSFET. <n5>Second isolation MOSFET <n6>First offset elimination MOSFET <n7>Second offset elimination MOSFET <n8>Among them, the first isolation MOSFET <n5>One of the source or drain terminals is connected to the bit line BL, and the other is connected to the read bit line SABL. The gate is used to receive the isolation signal (ISO) and is used to connect the bit line BL and the read bit line SABL in response to the isolation signal ISO, or to isolate the bit line BL and the read bit line SABL in response to the isolation signal ISO; a second isolation MOSFET. <n6>One of the source or drain terminals is connected to the complementary bit line BLB, and the other is connected to the complementary read bit line SABLB. The gate is used to receive the isolation signal ISO and is used to connect the complementary bit line BLB and the complementary read bit line SABLB in response to the isolation signal ISO, or to isolate the complementary bit line BLB and the complementary read bit line SABLB in response to the isolation signal ISO; a first offset cancellation MOSFET. <n7>One of the source or drain terminals is connected to the bit line BL, and the other is connected to the complementary read bit line SABLB. The gate is used to receive the offset cancellation signal (OC), and is used to connect the bit line BL and the complementary read bit line SABLB in response to the offset cancellation signal OC, or to disconnect the bit line BL and the complementary read bit line SABLB in response to the offset cancellation signal OC; a second offset cancellation MOSFET. <n8>One of the source or drain terminals is connected to the complementary bit line BLB, and the other is connected to the read bit line SABL. The gate is used to receive the offset cancellation signal OC, and is used to connect the complementary bit line BLB and the read bit line SABL in response to the offset cancellation signal OC, or to disconnect the complementary bit line BLB and the read bit line SABL in response to the offset cancellation signal OC.

[0043] Pre-charging via pre-charge transistor <n3>To achieve this, the equalization circuit 400 uses equalization transistors. <n4>Implementation, precharge transistor <n3>One of the source or drain terminals is used to receive the pre-charge voltage VDD / 2, and the other is used to connect to the equalization transistor. <n4>One of the source or drain terminals, the gate is used to receive the precharge signal PRE, and is used to precharge the read bit line SABL and the complementary read bit line SABLB in response to the precharge signal PRE; equalization transistor <n4>One of the source or drain terminals is connected to the read bit line SABL, and the other is connected to the complementary read bit line SABLB. The gate is used to receive the equalization signal EQ and to equalize the voltage of the read bit line SABL and the complementary read bit line SABLB in response to the equalization signal EQ.

[0044] refer to Figure 3 The data readout process includes five stages: stage 1 (t~t0) performs a pre-charge operation; stage 2 (t0~t1) performs an offset elimination operation; stage 3 (t1~t2) performs a charge sharing operation; stage 4 (t2~t3) performs a pre-readout operation; and stage 5 (t3~t) performs a recovery operation.

[0045] Specifically, during the execution of phase 1, the pre-charge transistor <n3>In response to the logic high (H) precharge signal PRE, the equalization transistor... <n4>In response to the logic high (H) equalization signal EQ, the first isolation MOSFET <n5>Second isolation MOSFET <n6>In response to the logic high (H) isolation signal ISO, the first offset cancel MOSFET... <n7>Second offset elimination MOSFET <n8>In response to the offset cancellation signal OC at logic high (H); bit line BL, complementary bit line BLB, read bit line SABL, and complementary read bit line SABLB are all connected to the precharge voltage VDD / 2, and the first control signal PCS and the second control signal NCS are also charged to the precharge voltage VDD / 2; during the execution of phase 2, the precharge signal PRE and the equalization signal EQ are at low levels, and the first isolation MOSFET... <n5>Second isolation MOSFET <n6>In response to the logic low (L) isolation signal ISO, the first offset cancel MOSFET... <n7>Second offset elimination MOSFET <n8>In response to the offset cancellation signal OC at logic high (H); the first control signal PCS changes from the precharge voltage VDD / 2 to the internal power supply voltage VDD, and the second control signal NCS changes from the precharge voltage VDD / 2 to the ground voltage VSS; during the execution of phase 3, the first isolation MOSFET... <n5>Second isolation MOSFET <n6>In response to the logic high (H) isolation signal ISO, the first offset cancel MOSFET... <n7>Second offset elimination MOSFET <n8>In response to the offset cancellation signal OC at logic low (L), word line WL is activated. At this time, the selected bit line BL / complementary bit line BLB shares charge with the cell capacitor, and the first control signal PCS and the second control signal NCS are converted to the pre-charge voltage VDD / 2. During execution phase 4, when data with a value of "1" is stored in the memory cell, during the pre-read operation phase, the voltage on the read bit line SABL can rise to the internal power supply voltage VDD, and the voltage on the complementary read bit line SABLB can drop to the ground voltage VSS. When the output with a value of "0" is stored in the memory cell, during the pre-read operation phase, the voltage on the read bit line SABL can drop to the ground voltage VSS, and the voltage on the complementary read bit line SABLB can rise to the internal power supply voltage VDD. During execution phase 5, the first isolation MOSFET... <n5>Second isolation MOSFET <n6>In response to the logic high (H) isolation signal ISO, the first offset cancel MOSFET... <n7>Second offset elimination MOSFET <n8>In response to the offset cancellation signal OC at logic high (H), bit line BL, complementary bit line BLB, read bit line SABL and complementary read bit line SABLB are all connected to the precharge voltage VDD / 2, and the first control signal PCS and the second control signal NCS are also charged to the precharge voltage VDD / 2.

[0046] During execution phase 4, inconsistencies in the surrounding device environments of the various MOSFETs in the sense amplifier may lead to different device characteristics among the MOSFETs within the same sense amplifier. Since the device characteristics of the MOSFETs in the same sense amplifier need to be matched, MOSFETs with different device characteristics can affect the amplification capability of the sense amplifier, thereby reducing DRAM performance. (Reference) Figure 4 Due to the inconsistent characteristics of transistors, the voltage of the bit line BL / complementary bit line BLB, which should rise according to the dashed line, will be offset to a certain extent, causing timing misalignment problems during memory readout.

[0047] To address the aforementioned problems, one embodiment of this application provides a readout circuit layout, including: a readout amplification module, a first processing module, and a second processing module arranged along a preset direction. The readout amplification module is used to read the voltage of a bit line, and the first and second processing modules are at least used to perform noise cancellation on the output signal of the readout amplification module. The readout amplification module includes: a first NMOS region and a first PMOS region disposed near the first processing module, and a second NMOS region and a second PMOS region disposed near the second processing module. The first NMOS region, the first PMOS region, the second PMOS region, and the second NMOS region are arranged along the preset direction. The active patterns of the first NMOS region and the second NMOS region are independently configured, as are the active patterns of the first PMOS region and the second PMOS region.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0049] Figures 5-10 The following is a schematic diagram of the readout circuit layout provided in this embodiment. The specific details of the readout circuit layout provided in this embodiment are as follows:

[0050] refer to Figure 5 Read the circuit layout, including:

[0051] The readout amplification module 103, the first processing module 101, and the second processing module 102 are arranged along a preset direction.

[0052] The preset direction is the X direction shown in the figure (corresponding to...). Figure 1 (The arrangement direction of multiple memory arrays 100) The readout amplification module 103 is used to read the voltage of the bit line BL, which is subsequently used to form a sensing amplifier. The first processing module 101 and the second processing module 102 are at least used to perform noise cancellation on the output signal of the readout amplification module 103, which is subsequently used to form a sensing amplifier. Figure 2 The readout circuit 300 is shown.

[0053] Specifically, the readout amplification module 103 includes: a first NMOS region 114 and a first PMOS region 115 located near the first processing module 101, and a second NMOS region 124 and a second PMOS region 125 located near the second processing module 102.

[0054] The first NMOS region 114, the first PMOS region 115, the second NMOS region 124, and the second PMOS region 125 are arranged along a preset direction, that is, the first NMOS region 114, the first PMOS region 115, the second NMOS region 124, and the second PMOS region 125 are arranged in the X direction.

[0055] More specifically, the active patterns of the first NMOS region 114 and the second NMOS region 124 are set independently, as are the active patterns of the first PMOS region 115 and the second PMOS region 125. The active patterns of the two NMOS regions and the two PMOS regions are set independently, so that the active regions of the MOS transistor structure in the subsequently formed sensing amplifier are independent, which can reduce the signal interference problem caused by the sharing of active regions in the MOS transistor.

[0056] Furthermore, in this embodiment, the active patterns of the first NMOS region 114 and the second NMOS region 124 are symmetrically arranged, as are the active patterns of the first PMOS region 115 and the second PMOS region 125. The symmetrical arrangement of MOS transistors within the same sensing amplifier ensures a consistent environment for the matched MOS transistors within the same sensing amplifier, thereby balancing the device characteristics of each MOS transistor in the same sensing amplifier and improving memory stability.

[0057] Specifically, refer to Figures 5-10 The active patterns of the first NMOS region 114 and the second NMOS region 124 are symmetrically arranged according to the axis of symmetry AA1, and the active patterns of the second PMOS region 115 and the second PMOS region 125 are also symmetrically arranged according to the axis of symmetry AA1.

[0058] In addition, for the first NMOS region 114, the second NMOS region 124, the first PMOS region 115, and the second PMOS region 125, the gate patterns of the first PMOS region 114, the second NMOS region 124, the first PMOS region 115, and the second PMOS region 124 are arranged along a preset direction, that is, the gate patterns of the first PMOS region 114, the second NMOS region 124, the first PMOS region 115, and the second PMOS region 124 are arranged along the X direction.

[0059] It should be noted that, in this embodiment, the length of the active pattern in the first NMOS region 114 and the length of the active pattern in the second NMOS region 124 are greater than the lengths of the active patterns in the first PMOS region 115 and the second PMOS region 125. The NMOS active patterns have a wider size compared to the PMOS active patterns, providing greater driving capability. In other embodiments, the size of the PMOS active pattern can also be set to be greater than the size of the NMOS active pattern, or the size of the PMOS active pattern can be the same as the size of the NMOS active pattern.

[0060] Accordingly, in this embodiment, the positions of the active pattern in the first processing module 101 and the active pattern in the second processing module 102 are symmetrically arranged. The symmetrical arrangement of the positions of the first processing module 104 and the second processing module 102 within the same sensing amplifier further ensures that the environment of the MOS transistors requiring matching within the same sensing amplifier is consistent, thereby improving the stability of the memory.

[0061] Specifically, refer to Figures 5-10 The positions of the active patterns in the first processing module 101 and the active patterns in the second processing module 102 are symmetrically set according to the axis of symmetry AA1, that is, the distances from the axis of symmetry AA1 to each position of the active pattern in the first processing module 101 and the corresponding position of the active pattern in the second processing module 102 are equal.

[0062] It should be noted that in this embodiment, the active pattern of the first processing module 101 and the active pattern of the second processing module 102 have different structures. Therefore, the description is "the positions of the active patterns of the first processing module 101 and the active patterns of the second module 102 are symmetrically arranged". In other embodiments, if the active patterns of the first processing module and the active patterns of the second processing module have the same structure, the active patterns of the first processing module and the active patterns of the second processing module can also be symmetrically arranged.

[0063] Continue to refer to Figures 5-10 For the first processing module 101, the first processing module 101 includes a first offset elimination region 111, a first isolation region 121 and an equalization region 131; wherein, the first offset elimination region 111 connects the bit line BL to the complementary read bit line SABLB, the first isolation region 121 is configured to connect the bit line BL to the read bit line SABL, and the equalization region 131 is configured to connect the read bit line SABL to the complementary read bit line SABLB.

[0064] Combination Figure 2 The first offset elimination region 111 is used for the subsequent formation of the first offset elimination MOS transistor. <n7>The first isolation region 121 is used to subsequently form the first isolation MOSFET. <n5>The equalization region 131 is used for the subsequent formation of the equalization MOS transistor. <n4>The first offset elimination region 111 and the first isolation region 121 share a source, which is used to connect the bit line BL; the first isolation region 121 and the equalization region 131 share a drain, which is used to connect the read bit line SABL; the drain of the first offset elimination region 111 and the source of the equalization region 131 are used to connect the complementary read bit line SABLB.

[0065] For the second processing module 102, the second processing module 102 includes a pre-charge region 112, a second isolation region 122, and a second offset elimination region 132; the pre-charge region 112 is configured to pre-charge the bit line BL and the complementary bit line BLB based on the pre-charge instruction, the second isolation region 122 is configured to connect the complementary bit line BLB to the complementary read bit line SABLB, and the second offset elimination region 132 is configured to connect the complementary bit line BLB to the read bit line SABLB.

[0066] Combination Figure 2 The pre-charge region 112 is used to subsequently form a pre-charge MOSFET. <n3>The second isolation region 122 is used to subsequently form the second isolation MOSFET. <n6>The second offset elimination region 132 is used for the subsequent formation of the second offset elimination MOS transistor. <n8>In this configuration, the pre-charge region 112 and the second isolation region 122 share a common source, which is used to connect to the complementary readout bit line SABLB. The second isolation region 122 and the second offset cancellation region 132 share a common drain, which is used to connect to the complementary bit line BLB. The drain of the pre-charge region 112 is used to receive the pre-charge voltage V. DD The source of the second isolation region 132 is used to connect the read bit line SABL.

[0067] It should be noted that in this embodiment, the "source" and "drain" are defined as illustrative examples of this application. They are intended to enable those skilled in the art to understand the configuration of this embodiment and do not constitute a limitation on this embodiment. In other embodiments, the "source" and "drain" defined in this application can be interchanged.

[0068] The active patterns of the first offset elimination region 111, the first isolation region 121, and the equalization region 131 are interconnected, meaning that the active patterns of the first offset elimination region 111, the first isolation region 121, and the equalization region 131 are set with the same active pattern; the active patterns of the pre-charge region 112, the second isolation region 122, and the second offset elimination region 132 are interconnected, meaning that the active patterns of the pre-charge region 112, the second isolation region 122, and the second offset elimination region 132 are set with the same active pattern.

[0069] As mentioned above, in this embodiment, the positions of the active patterns in the first processing module 101 and the second processing module 102 are symmetrically set according to the axis of symmetry AA1. Specifically, the active patterns in the first offset elimination region 111 and the second offset elimination region 132 are symmetrically set according to the axis of symmetry AA1, the active patterns in the first isolation region 121 and the second isolation region 122 are symmetrically set according to the axis of symmetry AA1, and the positions of the active patterns in the equalization region 131 and the pre-charge region 112 are symmetrically set according to the axis of symmetry AA1.

[0070] In addition, for the first processing module 101 and the second processing module 102 in this embodiment, the gate pattern of the first processing module 101 and the gate pattern of the second processing module 102 are arranged in a direction perpendicular to a preset direction, that is, the gate pattern of the first processing module 101 and the gate pattern of the second processing module 102 are arranged perpendicular to the X direction.

[0071] This embodiment provides six layout options for the first processing module 101, the second processing module 102, and the readout amplification module 103, as follows:

[0072] refer to Figure 5 and Figure 6 The active pattern of the first processing module 101 is located on the side away from the active pattern of the first NMOS region 114 and the active pattern of the first PMOS region 115. The active pattern of the second processing module 102 is located on the side away from the active pattern of the second NMOS region 124 and the active pattern of the second PMOS region 125. That is, the first processing module 101 and the second processing module 102 are located on both sides of the readout amplification module 103.

[0073] In a specific example, refer to Figure 5 In a preset direction, the active pattern of the first PMOS region 115 is located on the side of the active pattern of the first NMOS region 114 that is close to the active pattern of the second processing module 102, and the active pattern of the first processing module 101 is located on the side of the active pattern of the first NMOS region 114 that is far away from the active pattern of the second processing module 102. The active pattern of the second PMOS region 125 is located on the side of the active pattern of the second NMOS region 124 that is close to the active pattern of the first processing module 101, and the active pattern of the second processing module 102 is located on the side of the active pattern of the second NMOS region 124 that is far away from the active pattern of the first processing module 101.

[0074] In this configuration, the active pattern of the first processing module 101 and the active pattern of the first NMOS region 114 are disposed in the same well region, and the active pattern of the second processing module 102 and the active pattern of the second NMOS region 124 are disposed in the same well region; for example Figure 5 As shown, the active patterns of the first processing module 101 and the first NMOS region 114 are disposed in the first well region 1001, and the active patterns of the second processing module 102 and the second NMOS region 124 are disposed in the second well region 1002. The active patterns disposed in the same well region can ensure that they have the same ion implantation characteristics, so that the ion implantation characteristics of the active patterns of the first processing module 101 and the first NMOS region 114 are the same, and the ion implantation characteristics of the active patterns of the second processing module 102 and the second NMOS region 124 are the same, further balancing the device characteristics of each MOS transistor in the same sensing amplifier.

[0075] In another specific example, see reference Figure 6 In a preset direction, the active pattern of the first NMOS region 114 is located on the side of the active pattern of the first PMOS region 115 that is close to the active pattern of the second processing module 102, and the active pattern of the first processing module 101 is located on the side of the active pattern of the first PMOS region 115 that is far away from the active pattern of the second processing module 102. The active pattern of the second NMOS region 124 is located on the side of the active pattern of the second PMOS region 125 that is close to the active pattern of the first processing module 101, and the active pattern of the second processing module 102 is located on the side of the active pattern of the second PMOS region 125 that is far away from the active pattern of the first processing module 101.

[0076] The active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 115 are disposed in the same well region, such as... Figure 6 As shown, the active patterns of the first NMOS region 114 and the second NMOS region 115 are disposed in the third well region 1003.

[0077] refer to Figure 7 and Figure 8 The active pattern of the first processing module 101 is located between the active pattern of the first NMOS region 114 and the active pattern of the first PMOS region 115, and the active pattern of the second processing module 102 is located between the active pattern of the second NMOS region 124 and the active pattern of the second PMOS region 125. That is, the first processing module 101 and the second processing module 102 are located within the readout amplification module 103.

[0078] In a specific example, refer to Figure 7 In a preset direction, the active pattern of the first NMOS region 114 is disposed on the side of the active pattern of the first processing module 101 away from the active pattern of the second processing module 102, the active pattern of the second NMOS region 124 is disposed on the side of the active pattern of the second processing module 102 away from the active pattern of the first processing module 101, and the active patterns of the first PMOS region 115 and the second PMOS region 125 are disposed between the active patterns of the first processing module 101 and the active patterns of the second processing module 102.

[0079] In this configuration, the active pattern of the first processing module 101 and the active pattern of the first NMOS region 114 are disposed in the same well region, and the active pattern of the second processing module 102 and the active pattern of the second NMOS region 124 are disposed in the same well region; for example Figure 7 As shown, the active pattern of the first processing module 101 and the active pattern of the first NMOS region 114 are disposed in the fourth well region 1004, and the active pattern of the second processing module 102 and the active pattern of the second NMOS region 124 are disposed in the fifth well region 1005.

[0080] In another specific example, see reference Figure 8 In a preset direction, the active pattern of the first PMOS region 115 is disposed on the side of the active pattern of the first processing module 101 away from the active pattern of the second processing module 102, the active pattern of the second PMOS region 125 is disposed on the side of the active pattern of the second processing module 102 away from the active pattern of the first processing module 101, and the active patterns of the first NMOS region 114 and the second NMOS region 124 are disposed between the active patterns of the first processing module 101 and the active patterns of the second processing module 102.

[0081] The active patterns of the first processing module 101, the first NMOS region 114, the second processing module 102, and the second NMOS region 124 are all located in the same well region; for example... Figure 8 As shown, the active patterns of the first processing module 101, the first NMOS region 114, the second processing module 102, and the second NMOS region 124 are disposed in the sixth well region 1006. The active patterns disposed in the same well region can ensure that they have the same ion implantation characteristics, so that the ion implantation characteristics of the active patterns of the first processing module 101, the first NMOS region 114, the second processing module 102, and the second NMOS region 124 are the same, which further balances the device characteristics of each MOS transistor in the same sensing amplifier.

[0082] refer to Figure 9 and Figure 10 In a preset direction, the active patterns of the first processing module 101 are disposed on the side of the active patterns of the first NMOS region 114 and the first PMOS region 115 close to the second processing module 102, and the active patterns of the second processing module 102 are disposed on the side of the active patterns of the second NMOS region 124 and the second PMOS region 125 close to the first processing module 101. That is, the first processing module 101 and the second processing module 102 are disposed between the readout amplification module 103.

[0083] In a specific example, refer to Figure 9 In a preset direction, the active pattern of the first PMOS region 115 is located on the side of the active pattern of the first NMOS region 114 that is away from the active pattern of the second processing module 102, the active pattern of the first processing module 101 is located on the side of the active pattern of the first NMOS region 114 that is close to the active pattern of the second processing module 102, the active pattern of the second PMOS region 125 is located on the side of the active pattern of the second NMOS region 124 that is away from the active pattern of the first processing module 101, and the active pattern of the second processing module 102 is located on the side of the active pattern of the second NMOS region 124 that is away from the active pattern of the first processing module 101.

[0084] The active patterns of the first processing module 101, the first NMOS region 114, the second processing module 102, and the second NMOS region 124 are all located in the same well region; for example... Figure 9 As shown, the active patterns of the first processing module 101, the first NMOS region 114, the second processing module 102, and the second NMOS region 124 are disposed in the seventh well region 1007.

[0085] In another specific example, see reference Figure 10 In a preset direction, the active pattern of the first NMOS region 114 is located on the side of the active pattern of the first PMOS region 115 that is away from the active pattern of the second processing module 102, the active pattern of the first processing module 101 is located on the side of the active pattern of the first PMOS region 115 that is close to the active pattern of the second processing module 102, the active pattern of the second NMOS region 124 is located on the side of the active pattern of the second PMOS region 125 that is away from the active pattern of the first processing module 101, and the active pattern of the second processing module 102 is located on the side of the active pattern of the second PMOS region 125 that is away from the active pattern of the first processing module 101.

[0086] The active pattern of the first processing module 101 and the active pattern of the second processing module 102 are disposed in the same well region; for example Figure 10 As shown, the active pattern of the first processing module 101 and the active pattern of the second processing module 102 are disposed in the eighth well region 1008.

[0087] Compared with related technologies, for the MOS structure of the sense amplifier in the readout circuit layout, the active patterns of the two NMOS transistors are set independently, and the active patterns of the two PMOS transistors are set independently. This makes the active regions of the MOS structure in the subsequently formed sense amplifier independent, which can reduce the signal interference problem caused by the sharing of active regions in MOS transistors, thereby improving the device performance of MOS transistors in the readout circuit and reducing the impact of timing mismatch during memory readout.

[0088] Another embodiment of this application also provides a memory layout, including the read circuit layout provided in the above embodiments. Multiple read circuit layouts are arranged sequentially in the vertical direction of a preset direction. Two adjacent read circuit layouts constitute a read circuit layout group. The read circuit layout groups share the same active pattern, and the distance between adjacent read circuit layout groups is equal.

[0089] Figure 11 This is a schematic diagram of the memory layout provided in this embodiment. The memory layout provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0090] refer to Figure 11 The memory layout includes multiple readout circuit layouts mentioned in the above embodiments. The multiple readout circuit layouts are arranged sequentially in the vertical direction of a preset direction, that is, the multiple readout circuit layouts are arranged in the direction perpendicular to the X direction.

[0091] Two adjacent readout circuit layouts constitute a readout circuit layout group. The readout circuit layout group shares the same active pattern, and the distance between adjacent readout circuit layout groups is equal.

[0092] For specific references Figure 11 In the vertical direction of the preset direction, this embodiment uses a layout of four readout circuits as an example for detailed explanation. This is only for those skilled in the art to understand this application and does not constitute a limitation on this application. The details are as follows:

[0093] The first and second columns of readout circuit layouts constitute the first readout circuit layout group, and the third and fourth columns of readout circuit layouts constitute the second readout circuit layout group. In the same readout circuit layout group, the first NMOS region 114 shares the same active pattern, the second NMOS region 124 shares the same active pattern, the first PMOS region 115 shares the same active pattern, and the second PMOS region 125 shares the same active pattern.

[0094] In the same memory layout, all first processing modules 101 arranged in the vertical direction of the preset direction share a gate structure, and all second processing modules 102 arranged in the vertical direction of the preset direction share a gate structure.

[0095] The distance between adjacent readout circuit layout groups is equal, including: the distance between any two readout circuit layout groups is equal; for the first readout circuit layout group and the second readout circuit layout group, that is, the distance between adjacent active patterns of the first processing module 101, the distance between adjacent active patterns of the second processing module 102, the distance between adjacent active patterns of the first NMOS region 114, the distance between adjacent active patterns of the second NMOS region 124, the distance between adjacent active patterns of the first PMOS region 115, and the distance between adjacent active patterns of the second PMOS region 125 are equal.

[0096] Continue to refer to Figure 11 Each readout circuit layout includes:

[0097] The readout amplification module 103, the first processing module 101, and the second processing module 102 are arranged along a preset direction.

[0098] Specifically, the readout amplification module 103 includes: a first NMOS region 114 and a first PMOS region 115 located near the first processing module 101, and a second NMOS region 124 and a second PMOS region 125 located near the second processing module 102. The active patterns of the first NMOS region 114 and the second NMOS region 124 are symmetrically arranged, and the active patterns of the first PMOS region 115 and the second PMOS region 125 are symmetrically arranged.

[0099] Accordingly, the positions of the active pattern in the first processing module 101 and the active pattern in the second processing module 102 are symmetrically arranged.

[0100] For the first processing module 101, the first processing module 101 includes a first offset elimination region 111, a first isolation region 121 and an equalization region 131; wherein, the first offset elimination region 111 connects the bit line BL to the complementary read bit line SABLB, the first isolation region 121 is configured to connect the bit line BL to the read bit line SABL, and the equalization region 131 is configured to connect the read bit line SABL to the complementary read bit line SABLB.

[0101] For the second processing module 102, the second processing module 102 includes a pre-charge region 112, a second isolation region 122, and a second offset elimination region 132; the pre-charge region 112 is configured to pre-charge the bit line BL and the complementary bit line BLB based on the pre-charge instruction, the second isolation region 122 is configured to connect the complementary bit line BLB to the complementary read bit line SABLB, and the second offset elimination region 132 is configured to connect the complementary bit line BLB to the read bit line SABLB.

[0102] As mentioned above, in this embodiment, the positions of the active patterns in the first processing module 101 and the second processing module 102 are symmetrically arranged. Specifically, the active patterns in the first offset elimination region 111 and the second offset elimination region 132 are symmetrically arranged, the active patterns in the first isolation region 121 and the second isolation region 122 are symmetrically arranged, and the positions of the active patterns in the equalization region 131 and the pre-charging region 112 are symmetrically arranged.

[0103] In this embodiment, the memory layout further includes a connection pattern 201, disposed at the edge of the pre-charge region 112 and in contact with the active patterns of the pre-charge region 112. In the vertical direction of a preset direction, the connection pattern 201 is used to contact all the active patterns of the pre-charge region 112. Since the size of the active patterns in the pre-charge region 112 is usually smaller than other regions, the connection pattern 201 is used to balance the "environment" of the active regions around the first NMOS region 114 and the second NMOS region 125, thereby further balancing the device characteristics of each MOS transistor in the same sense amplifier. It should be noted that in this embodiment, "environment" consistently refers to the same size, distance, and arrangement of semiconductor structures made of the same material.

[0104] Compared with related technologies, for the MOS structure of the sense amplifier in the readout circuit layout, the active patterns of the two NMOS transistors are set independently, and the active patterns of the two PMOS transistors are set independently. This makes the active regions of the MOS structure in the subsequently formed sense amplifier independent, which can reduce the signal interference problem caused by the sharing of active regions in MOS transistors, thereby improving the device performance of MOS transistors in the readout circuit and reducing the impact of timing mismatch during memory readout.

[0105] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0106] Another embodiment of this application provides a readout circuit structure, including: a readout amplifier arranged along a preset direction, a first processing circuit, and a second processing circuit, wherein the readout amplifier is used to read out the voltage of the bit line, and the first processing circuit and the second processing circuit are at least used to perform noise cancellation on the output signal of the readout amplifier; the readout amplifier includes: a first NMOS transistor and a first PMOS transistor disposed near the first processing circuit, and a second NMOS transistor and a second PMOS transistor disposed near the second processing circuit, wherein the first processing circuit, the first NMOS transistor, the first PMOS transistor, the second processing circuit, the second NMOS transistor, and the second PMOS transistor are arranged along the preset direction; wherein the active layer of the first NMOS transistor and the active layer of the second NMOS transistor are independently disposed, and the active layer of the first PMOS transistor and the active layer of the second PMOS transistor are independently disposed.

[0107] The readout circuit structure provided in this embodiment will be further described in detail below. The readout circuit structure includes:

[0108] A sense amplifier, a first processing circuit, and a second processing circuit are arranged along a preset direction. The sense amplifier is used to read the voltage of the bit line, and the first and second processing circuits are used at least to perform noise cancellation on the output signal of the sense amplifier.

[0109] In conjunction with the above embodiments, the readout amplification module 103 is used to form the readout amplifier, the first processing module 101 is used to form the first processing circuit, and the second processing module 102 is used to form the second processing circuit.

[0110] The readout amplifier includes a first NMOS transistor and a first PMOS transistor disposed near the first processing circuit, and a second NMOS transistor and a second PMOS transistor disposed near the second processing circuit. The first processing circuit, the first NMOS transistor, the first PMOS transistor, the second processing circuit, the second NMOS transistor, and the second PMOS transistor are arranged along a preset direction.

[0111] In conjunction with the above embodiments, the first NMOS region 114 is used to form the first NMOS transistor, the second NMOS region 124 is used to form the second NMOS transistor, the first PMOS region 115 is used to form the first PMOS transistor, and the second PMOS region 125 is used to form the second PMOS transistor.

[0112] The active layers of the first NMOS transistor and the second NMOS transistor are set independently of each other, as are the active layers of the first PMOS transistor and the second PMOS transistor.

[0113] Compared with related technologies, for the MOS structure of the sense amplifier in the readout circuit layout, the active layers of the two NMOS transistors are set independently, and the active layers of the two PMOS transistors are set independently. This can reduce the signal interference problem caused by the sharing of active layers in the MOS transistors, thereby improving the device performance of the MOS transistors in the readout circuit and reducing the impact of timing mismatch during memory readout.

[0114] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0115] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A readout circuit layout, characterized in that, include: A readout amplification module, a first processing module, and a second processing module are arranged along a preset direction. The readout amplification module is used to read out the voltage of the bit line, and the first processing module and the second processing module are at least used to perform noise cancellation on the output signal of the readout amplification module. The readout amplification module includes: a first NMOS region and a first PMOS region disposed near the first processing module, and a second NMOS region and a second PMOS region disposed near the second processing module. The first NMOS region, the first PMOS region, the second PMOS region, and the second NMOS region are arranged along the preset direction. The active patterns of the first NMOS region and the second NMOS region are set independently, and the active patterns of the first PMOS region and the second PMOS region are set independently. The positions of the active patterns in the first processing module and the active patterns in the second processing module are symmetrically arranged. The first processing module includes: a first offset elimination region, a first isolation region, and an equalization region; The first offset elimination region is configured to connect the bit line to the complementary read bit line, the first isolation region is configured to connect the bit line to the read bit line, and the equalization region is configured to connect the read bit line to the complementary read bit line. The second processing module includes: a pre-charge region, a second isolation region, and a second offset elimination region; The precharge region is configured to precharge the bit line and the complementary bit line based on a precharge command, the second isolation region is configured to connect the complementary bit line to the complementary readout bit line, and the second offset elimination region is configured to connect the complementary bit line to the readout bit line. The active patterns of the first offset elimination region, the first isolation region, and the equalization region are interconnected, and the active patterns of the pre-charge region, the second isolation region, and the second offset elimination region are interconnected.

2. The readout circuit layout according to claim 1, characterized in that, The active patterns of the first NMOS region and the second NMOS region are symmetrically arranged, and the active patterns of the first PMOS region and the second PMOS region are symmetrically arranged.

3. The readout circuit layout according to claim 1, characterized in that, include: The active pattern of the first processing module is disposed between the active pattern of the first NMOS region and the active pattern of the first PMOS region; The active pattern of the second processing module is disposed between the active pattern of the second NMOS region and the active pattern of the second PMOS region.

4. The readout circuit layout according to claim 3, characterized in that, In the preset direction, the active pattern of the first NMOS region is disposed on the side of the active pattern of the first processing module away from the active pattern of the second processing module, the active pattern of the second NMOS region is disposed on the side of the active pattern of the second processing module away from the active pattern of the first processing module, and the active patterns of the first PMOS region and the second PMOS region are disposed between the active patterns of the first processing module and the second processing module.

5. The readout circuit layout according to claim 1, characterized in that, In the preset direction, the active pattern of the first processing module is disposed on the side away from the active pattern of the first NMOS region and the active pattern of the first PMOS region, and the active pattern of the second processing module is disposed on the side away from the active pattern of the second NMOS region and the active pattern of the second PMOS region.

6. The readout circuit layout according to claim 5, characterized in that, In the preset direction, the active pattern of the first PMOS region is disposed on the side of the active pattern of the first NMOS region close to the active pattern of the second processing module, and the active pattern of the first processing module is disposed on the side of the active pattern of the first NMOS region away from the active pattern of the second processing module. The active pattern of the second PMOS region is disposed on the side of the active pattern of the second NMOS region close to the active pattern of the first processing module, and the active pattern of the second processing module is disposed on the side of the active pattern of the second NMOS region away from the active pattern of the first processing module.

7. The readout circuit layout according to claim 6, characterized in that, The active pattern of the first processing module and the active pattern of the first NMOS region are disposed in the same well region, and the active pattern of the second processing module and the active pattern of the second NMOS region are disposed in the same well region.

8. The readout circuit layout according to claim 1, characterized in that, In the preset direction, the active pattern of the first processing module is disposed on the side of the active pattern of the first NMOS region and the active pattern of the first PMOS region close to the active pattern of the second processing module, and the active pattern of the second processing module is disposed on the side of the active pattern of the second NMOS region and the active pattern of the second PMOS region close to the active pattern of the first processing module.

9. The readout circuit layout according to claim 8, characterized in that, In the preset direction, the active pattern of the first NMOS region is disposed on the side of the active pattern of the first PMOS region away from the active pattern of the second processing module, the active pattern of the first processing module is disposed on the side of the active pattern of the first PMOS region close to the active pattern of the second processing module, the active pattern of the second NMOS region is disposed on the side of the active pattern of the second PMOS region away from the active pattern of the first processing module, and the active pattern of the second processing module is disposed on the side of the active pattern of the second PMOS region close to the active pattern of the first processing module.

10. The readout circuit layout according to claim 8, characterized in that, In the preset direction, the active pattern of the first PMOS region is disposed on the side of the active pattern of the first NMOS region away from the active pattern of the second processing module, and the active pattern of the first processing module is disposed on the side of the active pattern of the first NMOS region close to the active pattern of the second processing module. The active pattern of the second PMOS region is disposed on the side of the active pattern of the second NMOS region away from the active pattern of the first processing module, and the active pattern of the second processing module is disposed on the side of the active pattern of the second NMOS region close to the active pattern of the first processing module.

11. The readout circuit layout according to claim 10, characterized in that, The active patterns of the first processing module, the second processing module, the first NMOS region, and the second NMOS region are disposed in the same well region.

12. The readout circuit layout according to claim 1, characterized in that, In the preset direction, the active pattern length of the first NMOS region is greater than the active pattern length of the first PMOS region; the active pattern length of the second NMOS region is greater than the active pattern length of the second PMOS region.

13. The readout circuit layout according to claim 1, characterized in that, The gate pattern of the first NMOS region, the gate pattern of the second NMOS region, the gate pattern of the first PMOS region, and the gate pattern of the second PMOS region are arranged along the preset direction, and the gate pattern of the first processing module and the gate pattern of the second processing module are arranged in a direction perpendicular to the preset direction.

14. A memory layout, characterized in that, The system includes multiple readout circuit layouts as described in any one of claims 1 to 13, wherein the multiple readout circuit layouts are arranged sequentially in a direction perpendicular to a preset direction, and two adjacent readout circuit layouts constitute a readout circuit layout group, wherein the readout circuit layout group shares the same active pattern, and the distance between adjacent readout circuit layout groups is equal.

15. The memory layout according to claim 14, characterized in that, The active patterns of the first NMOS region and the second NMOS region are symmetrically arranged, and the active patterns of the first PMOS region and the second PMOS region are symmetrically arranged.

16. The memory layout according to claim 15, characterized in that, The positions of the active patterns in the first processing module and the active patterns in the second processing module are symmetrically arranged.

17. The memory layout according to claim 14, wherein the first processing module comprises: A first offset elimination region, a first isolation region, and an equalization region; the first offset elimination region is configured to connect the bit line to the complementary readout bit line, the first isolation region is configured to connect the bit line to the readout bit line, and the equalization region is configured to connect the readout bit line to the complementary readout bit line; The second processing module includes: a pre-charge region, a second isolation region, and a second offset elimination region; The precharge region is configured to precharge the bit line and the complementary bit line based on a precharge command, the second isolation region is configured to connect the complementary bit line to the complementary readout bit line, and the second offset elimination region is configured to connect the complementary bit line to the readout bit line. The active patterns of the first offset elimination region, the first isolation region, and the equalization region are interconnected, and the active patterns of the pre-charge region, the second isolation region, and the second offset elimination region are interconnected.

18. The memory layout according to claim 17, characterized in that, Also includes: A connecting pattern is disposed at the edge of the pre-charge area and contacts the active pattern of the pre-charge area. In the vertical direction of the preset direction, the connecting pattern is used to contact all the active patterns of the pre-charge area.

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