Semiconductor structure and method of manufacturing a semiconductor structure

CN115411034BActive Publication Date: 2026-08-28CHANGXIN MEMORY TECH INC
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
CN202110579403.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-05-26
Publication Date
2026-08-28
Estimated Expiration
2041-05-26

AI Technical Summary

Technical Problem

[0005]有鉴于此,本发明实施例提供一种半导体结构及半导体结构制作方法,以解决在蚀刻布线层的过程中,构成布线层的导电物会溅射在绝缘层上,导电物在绝缘层上容易发生扩散,以形成对电路/器件的泄露路径,降低连接柱的隔离性能的技术问题

Benefits of technology

[0036]本实施例提供的半导体结构及半导体结构制作方法,膜层结构设置在基底上,膜层结构背离基底的一侧设置有布线层,基底背离膜层结构的一侧设置延伸至布线层的连接孔,连接孔的孔壁上设置有绝缘层;绝缘层上设置有阻挡环,阻挡环的一端与布线层接合,阻挡环的中心线线连接孔的中心线共线设置,阻挡环的扩散性小于布线层的扩散性;连接孔内设置有与布线层接合的连接柱。通过设置阻挡环,在沿连接孔蚀刻部分布线层之后,阻挡环可以阻止因蚀刻而溅射形成的导电物向外扩散,进而避免形成电路/器件的泄露路径,提高了连接柱的隔离性能。

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN115411034B_ABST
    Figure CN115411034B_ABST
Patent Text Reader

Abstract

The embodiment of the application belongs to the technical field of semiconductor manufacturing, and relates to a semiconductor structure and a semiconductor structure manufacturing method, and is used for solving the problem that a conductive object is prone to diffusion on an insulating layer to form a leakage path of a circuit / device and reduce the isolation performance of a connecting column. The semiconductor structure is provided with a wiring layer on the side of a film layer structure away from a substrate, the side of the substrate away from the film layer structure is provided with a connecting hole extending to the wiring layer, and an insulating layer is arranged on the hole wall of the connecting hole; a blocking ring is arranged on the insulating layer, the center line of the blocking ring is arranged in line with the center line of the connecting hole, the diffusion property of the blocking ring is smaller than that of the wiring layer; and a connecting column is arranged in the connecting hole and is bonded with the wiring layer. By arranging the blocking ring, after etching part of the wiring layer along the connecting hole, the blocking ring can prevent the conductive object formed by sputtering due to etching from diffusing outward, thereby avoiding the formation of a leakage path of a circuit / device and improving the isolation performance of the connecting column.
Need to check novelty before this filing date? Find Prior Art

Claims

1. A semiconductor structure, characterized in that, It includes: a substrate and a membrane structure disposed on the substrate, wherein a wiring layer is disposed on the side of the membrane structure away from the substrate; a connection hole extending to the wiring layer is disposed on the side of the substrate opposite to the membrane structure, and an insulating layer is disposed on the wall of the connection hole; A blocking ring is provided on the insulating layer, one end of which is joined to the wiring layer, and the center line of the blocking ring is collinear with the center line of the connecting hole. The diffusion of the blocking ring is less than that of the wiring layer. A connecting post is provided in the connecting hole, and the connecting post is joined to the wiring layer. The film structure includes a shallow trench isolation layer and an interlayer isolation layer stacked together. Both the shallow trench isolation layer and the interlayer isolation layer are disposed between the wiring layer and the substrate, and the interlayer isolation layer is disposed close to the wiring layer. The length of the blocking ring along the center line direction is less than the thickness of the interlayer isolation layer.

2. The semiconductor structure according to claim 1, characterized in that, The blocking ring is disposed on the inner wall of the insulating layer.

3. The semiconductor structure according to claim 2, characterized in that, An annular blocking groove is provided on the inner wall of the insulating layer, and the blocking ring is accommodated in the annular blocking groove.

4. The semiconductor structure according to claim 1, characterized in that, The blocking ring is disposed on the outer wall of the insulating layer.

5. The semiconductor structure according to claim 4, characterized in that, An annular blocking groove is provided on the outer wall of the insulating layer, and the blocking ring is accommodated in the annular blocking groove.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The wiring layer is a copper layer, and the blocking ring is a tungsten ring.

7. The semiconductor structure according to any one of claims 1-5, characterized in that, The wall thickness of the blocking ring is 0.07μm-0.2μm.

8. The semiconductor structure according to any one of claims 1-5, characterized in that, A conductive buffer layer is provided between the connecting post and the insulating layer.

9. The semiconductor structure according to claim 8, characterized in that, The thickness of both the conductive buffer layer and the insulating layer is 2500 Å-5000 Å.

10. The semiconductor structure according to claim 8, characterized in that, The conductive buffer layer is a tantalum layer.

11. A method for fabricating a semiconductor structure, characterized in that, A substrate is provided, and a film structure is formed on the substrate; An annular blocking groove is formed on the side of the membrane structure opposite to the substrate; The blocking groove is filled with blocking material to form a blocking ring; An annular transition groove is formed on the outer or inner side of the blocking ring; The transition groove is filled with insulating material to form an insulating ring; A wiring layer is formed on the film structure; A blind hole extending to the blocking ring is formed on the side of the substrate opposite to the film structure, and an insulating sidewall that contacts the insulating ring is formed on the hole wall of the blind hole, so that the insulating ring and the insulating sidewall constitute an insulating layer; Remove the membrane structure within the barrier ring to form a connection hole extending to the wiring layer; A connecting post is formed within the connecting hole to engage with the wiring layer; The membrane structure includes a shallow trench isolation layer and an interlayer isolation layer stacked together. Both the shallow trench isolation layer and the interlayer isolation layer are disposed between the wiring layer and the substrate, and the interlayer isolation layer is disposed close to the wiring layer. The length of the blocking ring along the centerline direction is less than the thickness of the interlayer isolation layer.

12. The semiconductor structure fabrication method according to claim 11, characterized in that, The process includes the following steps prior to forming the connecting post: A conductive buffer layer is formed on the insulating layer.

13. The semiconductor structure fabrication method according to claim 11, characterized in that, The process of removing the membrane structure within the barrier ring to form a connection hole extending to the wiring layer includes: The membrane structure within the barrier ring is etched through the blind via to form a hole that extends into a portion of the wiring layer; the hole and the blind via together constitute the connection hole.

14. The semiconductor structure fabrication method according to claim 11, characterized in that, After forming the wiring layer, the process further includes: The substrate is then thinned.

15. The semiconductor structure fabrication method according to claim 11, characterized in that, After forming the connecting post, the following is also included: A contact pad is formed on the substrate to engage with one end of the connecting post opposite to the wiring layer.

Citation Information

Patent Citations

  • Integrated Circuit Devices Including a Through-Silicon Via Structure and Methods of Fabricating the Same

    US20150102497A1

  • Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer

    US6509267B1