Composite semiconductor substrate, semiconductor device, and method for manufacturing the same

Abstract

Embodiments of the present invention disclose a composite semiconductor substrate, a semiconductor device and a method of manufacturing the same. A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer, and an insulating layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulating layer is over the oxygen-doped crystalline semiconductor layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to composite semiconductor substrates, semiconductor devices, and methods for manufacturing the same. Background Technology

[0002] Semiconductor dies are fabricated on semiconductor substrates through various manufacturing operations (such as deposition, photolithography, etching, implantation, or similar operations). In recent years, composite semiconductor substrates (such as silicon-on-insulator (SOI) substrates) have been developed as alternative substrates. SOI substrates are substrates with a device silicon layer separated from the underlying silicon wafer by an insulating layer. SOI substrates offer advantages such as reduced parasitic capacitance, reduced power consumption, reduced current leakage, and increased ability to operate at higher temperatures.

[0003] The high resistivity of the treated silicon wafer allows for the fulfillment of certain application requirements (such as device isolation, passive device quality factor, etc.). Due to the low doping of the treated silicon wafer, carriers tend to accumulate at the interface between the treated silicon wafer and the insulating layer. The voltage applied to the overlay device can interact with the accumulated carriers, thereby degrading the performance of the overlay device. In some applications (such as radio frequency (RF) applications), RF signals can suffer from crosstalk and nonlinear distortion. Summary of the Invention

[0004] An embodiment of the present invention discloses a composite semiconductor substrate comprising: a semiconductor substrate; an oxygen-doped crystalline semiconductor layer above the semiconductor substrate, wherein the oxygen-doped crystalline semiconductor layer comprises a crystalline semiconductor material and a variety of oxygen dopants; and an insulating layer above the oxygen-doped crystalline semiconductor layer.

[0005] An embodiment of the present invention discloses a semiconductor device comprising: a composite semiconductor substrate, which includes: a semiconductor substrate; a well-rich layer above the semiconductor substrate, the well-rich layer including: a crystalline material; and a plurality of oxygen dopants in the crystalline material; an insulating layer above the well-rich layer; and a semiconductor component above the composite semiconductor substrate.

[0006] An embodiment of the present invention discloses a method for manufacturing a composite semiconductor substrate, comprising: receiving a semiconductor substrate; forming a well-rich layer comprising a crystalline material over the semiconductor substrate; forming a plurality of oxygen dopants in the crystalline material; and forming an insulating layer over the well-rich layer. Attached Figure Description

[0007] The aspects of the embodiments disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating various aspects of a method for manufacturing a composite substrate according to one or more embodiments of the present disclosure is provided.

[0009] Figure 2A , 2B 2C and 2D are schematic diagrams of one of the various operations for manufacturing a composite semiconductor substrate according to one or more embodiments of the present disclosure.

[0010] Figure 3 The present invention provides schematic diagrams of semiconductor devices according to some embodiments of the present disclosure. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances of various components for implementing the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the following description of a first component formed above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms (e.g., "below," "under," "below," "above," "above," "over") may be used herein to describe the relationship of one element or component to another element or component(s), as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and therefore the spatially relative descriptive terms used herein shall be interpreted in the same manner.

[0013] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or segments, but these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another. When terms such as “first,” “second,” and “third” are used herein, these terms do not imply a sequence or order unless the context clearly indicates otherwise.

[0014] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances in which the event or situation actually occurs and instances in which the event or situation approximately occurs. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%). For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the values ​​can be considered "substantially" the same or equal. For example, "substantially" parallel can be a range of angular variation of a straight line relative to 0° less than or equal to ±10° (e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°). For example, "generally" vertical can refer to the range of angular variation relative to 90° less than or equal to ±10° (e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°).

[0015] The characteristic of composite semiconductor substrates is that the semiconductor regions in which the circuits are formed are isolated from the bulk substrate by an electrically insulating layer. One advantage of isolating the circuit from the bulk substrate is the reduction of parasitic capacitance. Therefore, composite semiconductor substrates are attractive for high-frequency applications, such as radio frequency (RF) communication circuits. As the demands for quality and performance in RF devices increase, the requirements for high linearity and accuracy in RF circuits also continue to rise. Among other requirements, attempts have been made to prevent signals in one part of the circuit from affecting signals in another part of the circuit and degrading them. This effect is called crosstalk. Mitigating crosstalk is crucial for RF communication circuits because the impedance of specific parasitic paths within the circuit tends to be minimized at the frequencies used to carry signals in the RF circuitry. Since these same parasitic paths connect nodes within the circuit carrying different signals, crosstalk is particularly problematic for RF applications. Furthermore, it is crucial that the parasitic capacitances exposed to signals within the circuit are not signal-dependent. This requirement is critical because errors caused by signal dependence are difficult to calibrate and are inherently nonlinear.

[0016] In one or more embodiments disclosed herein, a composite semiconductor substrate (e.g., a silicon-on-insulator (SOI) substrate) is provided. The composite semiconductor substrate includes a bulk substrate (e.g., a semiconductor substrate), an oxygen-doped crystalline semiconductor layer, and an insulating layer. The oxygen-doped crystalline semiconductor layer is configured as a well-rich layer. The oxygen-doped crystalline semiconductor layer includes one or more crystalline materials configured to trap carriers. The crystalline material may include a polycrystalline semiconductor material (e.g., polycrystalline silicon). The oxygen-doped crystalline semiconductor layer further includes an oxygen dopant configured to help suppress die regrowth in the well-rich layer during thermal operation and simultaneously help increase the resistivity of the well-rich layer. Therefore, parasitic capacitance can be reduced, and leakage current can be mitigated. For some high-frequency applications (e.g., RF applications), reducing parasitic capacitance and reducing leakage current can help mitigate nonlinear distortion of RF signals and reduce crosstalk, and help improve RF device performance. The oxygen-doped crystalline semiconductor layer can be formed by deposition and therefore has a flatter surface. Therefore, planarization operations (e.g., CMP operations) can be omitted.

[0017] Figure 1 This is a flowchart illustrating various aspects of a method for fabricating a composite semiconductor substrate according to one or more embodiments of the present disclosure. Method 100 begins at operation 110, wherein a semiconductor substrate is received. Method 100 continues at operation 120, wherein a well-rich layer comprising a crystalline material is formed over the semiconductor substrate. Method 100 continues at operation 130, wherein a plurality of oxygen dopants are formed in the crystalline material. Method 100 continues at operation 140, wherein an insulating layer is formed over the well-rich layer.

[0018] Method 100 is merely an example and is not intended to limit this disclosure beyond what is expressly described in the invention claims. Additional operations may be provided before, during, and after method 100, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of the method.

[0019] Figure 2A , 2B Figures 2C and 2D are schematic diagrams of one of the various operations in the fabrication of a composite semiconductor substrate according to one or more embodiments of the present disclosure. Figure 2A China and Figure 1In operation 110, a semiconductor substrate 10 is received. The semiconductor substrate 10 may comprise a bulk substrate. The semiconductor substrate 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. In some embodiments, the semiconductor substrate 10 is a treatment substrate configured to treat and establish a base of an overlay layer to be formed. In some embodiments, the semiconductor substrate 10 is a high resistivity treatment substrate. By way of example, the semiconductor substrate 10 may have a resistivity greater than 1 kΩ-cm, but is not limited thereto. In some embodiments, the semiconductor substrate 10 comprises a silicon wafer (e.g., a single-crystal silicon substrate), but is not limited thereto. In some embodiments, the material of the semiconductor substrate 10 may comprise other semiconductor materials (e.g., III-V semiconductor materials, silicon carbide, silicon germanium, germanium, gallium arsenide, etc.).

[0020] like Figure 2B China and Figure 1 As shown in operation 120, a rich-well layer 12 is formed over a semiconductor substrate 10. The rich-well layer 12 may be in contact with the semiconductor substrate 10. The rich-well layer 12 comprises a crystalline material. The crystalline material may contain crystal defects that may be configured to trap carriers. In some embodiments, the crystalline material may comprise a crystalline semiconductor material (e.g., a polycrystalline semiconductor material). By way of example, the polycrystalline semiconductor material may comprise polycrystalline silicon, etc. In some embodiments, the polycrystalline semiconductor material may be recrystallized from an amorphous semiconductor material.

[0021] In some embodiments, the well-rich layer 12 refers to a semiconductor layer having crystal defects capable of trapping carriers. The crystal defects in the well-rich layer 12 may include dislocations (i.e., regions where atoms are not in their proper positions or are misaligned within the lattice) and / or oxidation-induced overlap (OISF). The crystal defects may serve as recombination centers configured to trap carriers from the insulating layer. Once trapped within a recombination center, the carrier lifetime is reduced. Therefore, carrier accumulation along the top surface of the semiconductor substrate 10 is reduced, thereby mitigating parasitic surface conduction that introduces nonlinear distortion into radio frequency (RF) signals.

[0022] In some embodiments, the well-rich layer 12 may be formed by a deposition operation, but is not limited thereto. Figure 2BAs shown, a semiconductor substrate 10 can be loaded into the reaction chamber 50 of a furnace tool and placed on a support 52 (e.g., a chuck in the reaction chamber 50). A crystalline material (e.g., polycrystalline silicon) can be formed over the semiconductor substrate 10 by introducing a source gas 54A into the reaction chamber 50. The furnace tool includes a heater to heat the source gas 54A in the reaction chamber 50. The source gas 54A is decomposed, thereby forming a well-rich layer 12 over the semiconductor substrate 10. In some embodiments, the source gas 54A may contain a silicon-containing gas (e.g., silane, dichlorosilane (DCS), combinations thereof, etc.). In some embodiments, the temperature in the reaction chamber 50 during the formation of the well-rich layer 12 is controlled at a relatively low temperature compared to the temperature during epitaxial operation to mitigate overgrowth of the polycrystalline silicon wafer size. In some embodiments, the temperature in the reaction chamber 50 during the formation of the well-rich layer 12 is below 900°C. By way of example, the temperature in the reaction chamber 50 is in the range of about 550°C to about 650°C, but is not limited thereto. In some embodiments, the pressure in the reaction chamber 50 is relatively low when the well-rich layer 12 is formed, for example, in the range of about 0.25 Torr to about 20 Torr, but not limited thereto.

[0023] like Figure 2B China and Figure 1 As shown in operation 130, various oxygen dopants are formed in the crystalline material. In some embodiments, the oxygen dopants may be formed together with the formation of the crystalline material. For example, various oxygen dopants may be formed by introducing an oxygen-containing gas 54B into the reaction chamber 50 during the formation of polycrystalline silicon. By way of example, the oxygen-containing gas 54B may comprise hydrogen peroxide gas, nitrous oxide gas, oxygen, combinations thereof, etc. In some embodiments, a carrier gas 54C (e.g., nitrogen, argon, or the like) may be introduced into the reaction chamber 50 to carry the source gas 54A and / or the oxygen-containing gas 54B. The amount of oxygen-containing gas 54B relative to the amount of source gas 54A may be adjusted to modify the oxygen-to-polycrystalline silicon ratio.

[0024] In some embodiments, the amount of oxygen-containing gas 54B relative to the amount of source gas 54A can be adjusted to further modify the resistivity of the well-rich layer 12. For example, when a relatively high resistivity of the well-rich layer 12 is required, the amount of oxygen-containing gas 54B relative to the amount of source gas 54A can be increased. When a relatively low resistivity of the well-rich layer 12 is required, the amount of oxygen-containing gas 54B relative to the amount of source gas 54A can be decreased. In some embodiments, the resistivity of the well-rich layer 12 may be in the range of about 1 kΩ-cm to about 9 kΩ-cm, but is not limited thereto.

[0025] A well-rich layer 12 comprising a crystalline material (e.g., polycrystalline silicon) and an oxygen dopant forms an oxygen-doped crystalline semiconductor layer. The polycrystalline silicon in the oxygen-doped crystalline semiconductor layer is configured to trap carriers, thereby helping to mitigate parasitic capacitance and leakage current. When the polycrystalline silicon material is formed, the oxygen dopant in the oxygen-doped crystalline semiconductor layer helps suppress the growth of the polycrystalline silicon die size. The oxygen dopant in the oxygen-doped crystalline semiconductor layer can further suppress the regrowth of the polycrystalline silicon die size during continuous thermal operation. In some embodiments, the die size of the crystalline semiconductor material in the oxygen-doped crystalline semiconductor layer is less than or equal to 0.1 micrometers. By example, the die size of the crystalline semiconductor material in the oxygen-doped crystalline semiconductor layer is generally in the range of 0.03 micrometers to 0.1 micrometers. The die size of the crystalline semiconductor material in the oxygen-doped crystalline semiconductor layer is generally in the range of 0.03 micrometers to 0.08 micrometers. The die size of the crystalline semiconductor material in the oxygen-doped crystalline semiconductor layer is generally in the range of 0.03 micrometers to 0.05 micrometers. Because the die size of polysilicon is controlled to be small, more grain boundaries are generated in polysilicon. Therefore, the carrier trapping capability of the well-rich layer 12 can be increased.

[0026] In some embodiments, the ratio of the amount of oxygen dopant to the amount of crystalline semiconductor material is in the range of about 0.05 to about 0.2, about 0.05 to about 0.15, or about 0.05 to about 0.1, but is not limited thereto. For example, the concentration of oxygen dopant in the well-rich layer 12 can be about 5E19 atoms / cm³. 3 Up to approximately 1E21 atoms / cm 3 Within this range, the concentration of polycrystalline silicon can be approximately 1E22 atoms / cm³. 3 In some embodiments, the concentration of oxygen dopant in the well-rich layer 12 may be substantially constant. In some other embodiments, the concentration of oxygen dopant in the well-rich layer 12 may vary along the depth direction. By way of example, the concentration of oxygen dopant in the well-rich layer 12 may increase along the depth direction from the upper surface away from the semiconductor substrate 10 to near the bottom surface of the semiconductor substrate 10. The concentration of oxygen dopant in the well-rich layer 12 may decrease along the depth direction from the upper surface to the bottom surface. The concentration of oxygen dopant in the well-rich layer 12 may vary along the depth direction continuously or in multiple stages.

[0027] Compared to epitaxially grown crystalline semiconductor layers, the well-rich layer 12 formed by deposition can have a relatively flat surface. Because the well-rich layer 12 has a flatter surface, its initial thickness can be the same as its target thickness, and successive planarization operations (e.g., CMP operations) can be omitted. Therefore, manufacturing costs can be reduced. In some embodiments, the thickness of the well-rich layer 12 can be less than or equal to 2.5 micrometers (e.g., between about 1.8 micrometers and 2.0 micrometers), but is not limited thereto.

[0028] In some embodiments, the rich well layer 12 may be in electrical contact with the semiconductor substrate 10. In some alternative embodiments, an intermediate layer that does not interfere with carrier transport between the rich well layer 12 and the semiconductor substrate 10 may exist between the rich well layer 12 and the semiconductor substrate 10.

[0029] like Figure 2C China and Figure 1 As shown in operation 140, an insulating layer 14 is formed over the well-rich layer 12. In some embodiments, the insulating layer 14 comprises a buried oxide layer. By way of example, the insulating layer 14 is a buried silicon oxide layer (e.g., a thermally heated silicon oxide layer). In some embodiments, the buried oxide layer may be a thermally heated oxide layer formed by oxidation in a furnace. The insulating layer 14 may be formed by other suitable oxidation operations. The insulating layer 14 is configured to electrically isolate the active semiconductor layer to be formed from the semiconductor substrate 10. In some embodiments, a planarization operation (e.g., a CMP operation) may be performed on the insulating layer 14 to planarize the surface of the insulating layer 14. In some other embodiments, since the insulating layer 14 is grown on the flat surface of the well-rich layer 12, the CMP operation for planarizing the insulating layer 14 may also be omitted.

[0030] like Figure 2D As shown, an active layer 16 may be formed over an insulating layer 14 to form a composite semiconductor substrate 1. The active layer 16 may contact a well-rich layer 12. In some embodiments, the active layer 16 may include an active semiconductor layer (e.g., a surface silicon layer or other semiconductor layer). In some embodiments, the active layer 16 may be formed by bonding a semiconductor wafer (e.g., a silicon wafer) to the insulating layer 14. In some embodiments, the semiconductor wafer may be thinned to a suitable thickness by, for example, grinding or polishing. In some embodiments, the active layer 16 may be configured as an active region for fabricating a semiconductor component (e.g., a passive device and / or an active device). In some embodiments, the semiconductor component may include a radio frequency (RF) device.

[0031] like Figure 2DAs shown, the composite semiconductor substrate 1 includes a well-rich layer 12 interposed between a semiconductor substrate 10 and an insulating layer 14. The well-rich layer 12 may be an oxygen-doped crystalline semiconductor layer comprising a crystalline semiconductor material (e.g., polysilicon) and oxygen dopants distributed within the crystalline semiconductor material. The oxygen-doped crystalline semiconductor layer is configured to trap carriers. When the crystalline semiconductor material is formed, the oxygen dopants in the oxygen-doped crystalline semiconductor layer help suppress the growth of the die size of the crystalline semiconductor material. The oxygen dopants in the oxygen-doped crystalline semiconductor layer further help suppress the regrowth of the die size of the polysilicon during continuous thermal operation. With the aid of oxygen dopants, the die size of the crystalline semiconductor material in the oxygen-doped crystalline semiconductor layer can be controlled to be less than or equal to 0.1 micrometers. The oxygen dopants in the oxygen-doped crystalline semiconductor layer also help generate more grain boundaries with crystal defects in the crystalline semiconductor material, and thus increase the carrier trapping capability of the oxygen-doped crystalline semiconductor layer. Therefore, the parasitic capacitance of the composite semiconductor substrate can be reduced, and leakage current can be mitigated. For some high-frequency applications (such as radio frequency (RF) communication circuits), reducing parasitic capacitance and leakage current can help mitigate nonlinear distortion of RF signals and improve RF device performance. During the fabrication of devices (such as RF switches), composite semiconductor substrates may undergo annealing operations or be subjected to high temperatures. Oxygen dopants in oxygen-doped crystalline semiconductor layers are configured to prevent crystalline semiconductor dies from adjoining each other, thus helping to suppress die regrowth during annealing operations or at high temperatures.

[0032] The composite semiconductor substrate and semiconductor device disclosed herein are not limited to the embodiments mentioned above, and may have other different embodiments. For the sake of simplicity and ease of comparison between the embodiments disclosed herein, the same components in the following embodiments are labeled with the same numbers. To facilitate comparison between embodiments, the differences between different embodiments will be described in detail below, and the same features will not be repeated.

[0033] Figure 3 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 3 As shown, the semiconductor device 30 may include a composite semiconductor substrate 2 and a semiconductor component 40. The composite semiconductor substrate 2 includes a semiconductor substrate 10, a well-rich layer 12, an insulating layer 14, and an active layer 16. The well-rich layer 12 may be an oxygen-doped crystalline semiconductor layer, comprising a crystalline semiconductor material (e.g., polysilicon) and oxygen dopants distributed in the crystalline semiconductor material. The well-rich layer 12 may be configured to trap carriers. The configuration of the semiconductor substrate 10, the well-rich layer 12, the insulating layer 14, and the active layer 16 may be similar to that shown below. Figure 2D The composite semiconductor substrate 1 is shown in the figure.

[0034] Semiconductor component 40 is disposed above composite semiconductor substrate 2. In some embodiments, semiconductor component 40 may include RF (radio frequency) transistors, etc. In some embodiments, semiconductor component 40 may include gate electrode 42, gate insulating layer 44, source / drain region 46, and spacer structure 48. Gate electrode 42 may be disposed above active layer 16. Gate insulating layer 44 may be disposed between gate electrode 42 and active layer 16. Source / drain region 46 may be formed on the opposite side of gate electrode 42 in active layer 16. Spacer structure 48 may be disposed on the opposite side of gate electrode 42. In some alternative embodiments, semiconductor component 40 may include RF device (e.g., RF switching device, etc.).

[0035] When the period of the RF signal is shorter than the majority carrier relaxation time, the majority carriers in the semiconductor substrate 10 may not respond to the RF signal. The majority carriers may appear frozen, and the semiconductor substrate 10 may be expressed as a dielectric. However, silicon has specific properties that can produce undesirable behavior in some RF applications. For example, the doping level in the high-resistivity semiconductor substrate 10 is very low or absent. Therefore, oxide charges at the surface of the semiconductor substrate 10 or a weak electric field in the semiconductor substrate 10 can induce an inversion or accumulation layer, which can be used as a surface conductive layer at the surface of the semiconductor substrate 10. An RF signal crossing over the surface of the semiconductor substrate 10 can modulate the surface conductive layer, which can lead to nonlinear capacitance, nonlinear conductivity, or both affecting the RF interaction between the semiconductor substrate 10 and other overlying layers. Nonlinear characteristics can introduce harmonic distortion in the RF signal that exceeds permissible limits. The well-rich layer 12 comprises a crystalline material (e.g., polycrystalline silicon) and an oxygen dopant. The crystalline material of the well-rich layer 12 contains crystal defects with dislocations. The crystal defects are configured to trap carriers in the semiconductor substrate 10 and / or the insulating layer 14. By trapping carriers within crystal defects in the crystalline material of the well-rich layer 12, parasitic surface conduction that can cause nonlinear distortion of RF signals can be mitigated. In some embodiments, the SOI substrate 2 may undergo some annealing operation or be subjected to high temperatures. The oxygen dopant of the well-rich layer 12 is configured to prevent the crystalline material dies from adjoining each other, and thus helps to suppress die regrowth during annealing operations or at high temperatures. With the oxygen dopant, the crystalline material dies can be controlled to have a smaller die size and finer grain structure, and thus the trap density of the well-rich layer 12 can be increased.

[0036] In some embodiments disclosed herein, the composite semiconductor substrate includes a well-rich layer interposed between a bulk semiconductor substrate and an insulating layer. The well-rich layer may be an oxygen-doped crystalline semiconductor layer comprising a crystalline semiconductor material (e.g., polysilicon) and oxygen dopants distributed within the crystalline semiconductor material. The oxygen-doped crystalline semiconductor layer is configured to trap carriers. During the formation of the crystalline semiconductor material, the oxygen dopants in the oxygen-doped crystalline semiconductor layer help suppress the growth of the die size of the crystalline semiconductor material. The oxygen dopants in the oxygen-doped crystalline semiconductor layer further help suppress the regrowth of the die size of the polysilicon during continuous thermal operation. With the aid of the oxygen dopants, the die size of the crystalline semiconductor material in the oxygen-doped crystalline semiconductor layer can be controlled to be less than or equal to 0.1 micrometers. The oxygen dopants in the oxygen-doped crystalline semiconductor layer also help generate more grain boundaries with more crystal defects in the crystalline semiconductor material, and thus increase the carrier trapping capability of the oxygen-doped crystalline semiconductor layer. Therefore, the parasitic capacitance of the composite semiconductor substrate can be reduced, and leakage current can be mitigated. For some high-frequency applications (such as radio frequency (RF) communication circuit applications), reducing parasitic capacitance and leakage current can help alleviate nonlinear distortion of RF signals and help improve the performance of RF devices.

[0037] In some embodiments, the composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer, and an insulating layer. The oxygen-doped crystalline semiconductor layer is located above the semiconductor substrate and comprises a crystalline semiconductor material and various oxygen dopants. The insulating layer is located above the oxygen-doped crystalline semiconductor layer.

[0038] In some embodiments, the semiconductor device may include a composite semiconductor substrate and a semiconductor component. The composite semiconductor substrate includes a semiconductor substrate, a well-rich layer, and an insulating layer. The well-rich layer is located above the semiconductor substrate. The well-rich layer includes a crystalline material and a variety of oxygen dopants in the crystalline material. The insulating layer is located above the well-rich layer. The semiconductor component is located above the composite semiconductor substrate.

[0039] In some embodiments, a method for manufacturing a composite semiconductor substrate includes the following operations: receiving a semiconductor substrate; forming a well-rich layer comprising a crystalline material over the semiconductor substrate; forming a plurality of oxygen dopants in the crystalline material; and forming an insulating layer over the well-rich layer.

[0040] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other programs and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0041] Symbol Explanation

[0042] 1. Composite semiconductor substrate

[0043] 2. Composite semiconductor substrate / silicon-on-insulator (SOI) substrate

[0044] 10 Semiconductor substrate

[0045] 12. Well-rich layer

[0046] 14 Insulation layer

[0047] 16 Active Layer

[0048] 30 Semiconductor Devices

[0049] 40 Semiconductor Components

[0050] 42 Gate electrode

[0051] 44 Gate insulating layer

[0052] 46 Source / Drain Region

[0053] 48 Spacer Structure

[0054] 50 reaction chambers

[0055] 52 Support

[0056] 54A Source Gas

[0057] 54B Oxygen-containing gas

[0058] 54C carrier gas

[0059] 100 methods

[0060] 101 First Surface

[0061] 102 Second Surface

[0062] 110 Operation

[0063] 120 Operation

[0064] 130 Operation

[0065] 140 Operations

Claims

1. A composite semiconductor substrate, comprising: Semiconductor substrate; An oxygen-doped crystalline semiconductor layer is disposed above the semiconductor substrate, wherein the oxygen-doped crystalline semiconductor layer comprises a crystalline semiconductor material and a plurality of oxygen dopants, the crystalline semiconductor material comprising crystal defects having dislocations, and the oxygen dopants are configured to prevent the crystalline semiconductor material dies from being adjacent to each other. An insulating layer is located above the oxygen-doped crystalline semiconductor layer; and An active layer is located above the insulating layer, wherein the oxygen-doped crystalline semiconductor layer is separated from the active layer by the insulating layer, the active layer is in contact with the insulating layer, and the insulating layer is in contact with the oxygen-doped crystalline semiconductor layer, the resistivity of the oxygen-doped crystalline semiconductor layer being in the range of 1 KΩ-cm to 9 KΩ-cm, and the crystalline semiconductor material containing the crystal defects is configured to capture carriers from the insulating layer.

2. The composite semiconductor substrate according to claim 1, wherein the crystalline semiconductor material comprises polycrystalline silicon.

3. The composite semiconductor substrate according to claim 1, wherein the insulating layer comprises a buried oxide layer.

4. The composite semiconductor substrate according to claim 1, wherein the die size of the crystalline semiconductor material is less than or equal to 0.1 micrometers.

5. The composite semiconductor substrate of claim 4, wherein the die size of the crystalline semiconductor material is substantially in the range of 0.03 micrometers to 0.1 micrometers.

6. The composite semiconductor substrate according to claim 1, wherein the thickness of the crystalline semiconductor material is less than or equal to 2.5 micrometers.

7. The composite semiconductor substrate according to claim 1, wherein the ratio of the amount of oxygen dopant to the amount of the crystalline semiconductor material is in the range of 0.05 to 0.

1.

8. A semiconductor device comprising: Composite semiconductor substrate, comprising: Semiconductor substrate; A rich-well layer is disposed above the semiconductor substrate, the rich-well layer comprising: Crystallized materials; and Multiple oxygen dopants in the crystalline material, wherein the concentration of the oxygen dopants in the well-rich layer varies along the depth direction in a multi-level manner, and the oxygen dopants are configured to prevent the bare wafers of the crystalline material from being adjacent to each other; An insulating layer, which is located above the well-rich layer; and An active layer is situated above the insulating layer, wherein the well-rich layer is separated from the active layer, and the insulating layer has a first surface facing and contacting the well-rich layer and a second surface facing and contacting the active layer; and A semiconductor component above the composite semiconductor substrate, wherein the semiconductor component is separated from the rich well layer, the semiconductor component includes a gate electrode and a spacer structure, the gate electrode is separated from the spacer structure, and the rich well layer is configured to capture carriers from the insulating layer.

9. The semiconductor device of claim 8, wherein the crystalline material comprises a polycrystalline semiconductor material.

10. The semiconductor device of claim 8, wherein the insulating layer comprises a thermal oxide layer.

11. The semiconductor device of claim 8, wherein the die size of the crystalline material is less than or equal to 0.1 micrometers.

12. The semiconductor device of claim 11, wherein the die size of the crystalline material is substantially in the range of 0.03 micrometers to 0.1 micrometers.

13. The semiconductor device of claim 8, wherein the ratio of the amount of oxygen dopant to the amount of crystalline material is in the range of 0.05 to 0.

1.

14. A method for manufacturing a composite semiconductor substrate, comprising: Accepts semiconductor substrates; A well-rich layer comprising a crystalline material is formed over the semiconductor substrate; Multiple oxygen dopants are formed in the crystalline material, wherein the oxygen dopants are configured to prevent the bare wafers of the crystalline material from adjoining each other; An insulating layer is formed above the well-rich layer; and An active layer is formed above the insulating layer, wherein the active layer is formed by bonding a semiconductor wafer to the insulating layer, the active layer is adjacent to the insulating layer, the insulating layer is directly adjacent to the rich well layer, and the rich well layer is configured to capture carriers from the insulating layer.

15. The method of claim 14, wherein the bare sheet size of the crystalline material is less than or equal to 0.1 micrometers.

16. The method of claim 14, wherein the ratio of the amount of oxygen dopant to the amount of the crystalline material is in the range of 0.05 to 0.

2.

17. The method of claim 14, wherein forming the crystalline material over the semiconductor substrate and forming the plurality of oxygen dopants in the crystalline material comprises: The crystalline material is deposited over the semiconductor substrate by introducing a source gas into the reaction chamber; and During the formation of the crystalline material over the semiconductor substrate, oxygen-containing gas is introduced into the reaction chamber to form the various oxygen dopants in the crystalline material.

18. The method of claim 17, wherein the oxygen-containing gas comprises hydrogen peroxide, nitrous oxide, oxygen, or a combination thereof.

19. The method of claim 17, further comprising adjusting the amount of the oxygen-containing gas relative to the amount of the source gas to modify the resistivity of the well-rich layer.

20. The method of claim 19, wherein the resistivity of the well-rich layer is in the range of 1 kΩ-cm to 9 kΩ-cm.

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