Finfet

Abstract

The application provides a fin field effect transistor, comprising a substrate, an insulating layer, a fin, a source, a drain and a gate structure; the insulating layer is on the substrate; the fin protrudes from the insulating layer and comprises a source region, a drain region and a channel region between the source region and the drain region; the fin comprises a first heterojunction structure, a second heterojunction structure,..., and an n-th heterojunction structure stacked in sequence in a direction away from the substrate, n>=2; the first heterojunction structure comprises a first channel layer and a first barrier layer, the second heterojunction structure comprises a second channel layer and a second barrier layer,..., and the n-th heterojunction structure comprises an n-th channel layer and an n-th barrier layer; at least one of the first barrier layer, the second barrier layer,..., and the n-th barrier layer is doped with an N-type element; the source covers the source region, the drain covers the drain region, and the gate structure covers the channel region. According to the embodiment of the application, the linear working characteristics of the fin field effect transistor can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a fin field-effect transistor. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] To further promote the application of heterojunction devices in fields with higher current and higher frequency, research on multi-channel heterojunction materials and devices is essential. Compared with single-channel heterojunctions, dual-channel heterojunctions can achieve a higher total 2DEG concentration, which significantly increases the device's saturation current. However, the increased total barrier layer thickness of dual-channel heterojunction materials leads to a larger distance between the device gate and the underlying channel, thus reducing gate control capability, lowering the device's transconductance peak value, and requiring further improvement in linear operating characteristics.

[0004] In fields such as communications, the linearity of semiconductor devices is a crucial parameter. However, in conventional HEMT devices, due to factors such as decreased electron saturation velocity and increased series resistance, the transconductance initially rises with increasing gate-source bias, reaches a certain peak, and then declines. This decline in transconductance affects the device's linearity. Summary of the Invention

[0005] The purpose of this invention is to provide a fin field-effect transistor to improve the linear operating characteristics of HEMT devices.

[0006] To achieve the above objectives, the present invention provides a fin field-effect transistor, comprising: Substrate; An insulating layer located on the substrate; A fin protruding from the insulating layer, the fin including a source region, a drain region, and a channel region located between the source region and the drain region; the fin including: a first heterojunction structure, a second heterojunction structure, ..., and an nth heterojunction structure, n≥2, sequentially stacked in a direction away from the substrate; the first heterojunction structure including a first channel layer and a first barrier layer, the second heterojunction structure including a second channel layer and a second barrier layer, ..., the nth heterojunction structure including an nth channel layer and an nth barrier layer, wherein at least one of the first barrier layer, the second barrier layer, ..., and the nth barrier layer is doped with an N-type element; A source covering the source region, a drain covering the drain region, and a gate structure covering the channel region.

[0007] Optionally, the doped N-type element includes at least one of Si, Ge, Sn, Se, or Te.

[0008] Optionally, the concentration of N-type dopant in the first barrier layer is greater than that in the second barrier layer, ..., and the concentration of N-type dopant in any one of the nth barrier layers.

[0009] Optionally, the concentration of N-type dopant in the nth barrier layer is less than the concentration of N-type dopant in the first barrier layer, the second barrier layer, ..., and any one of the (n-1)th barrier layers.

[0010] Optionally, the concentration of N-type dopant elements in the first barrier layer, the second barrier layer, ..., the nth barrier layer gradually decreases layer by layer.

[0011] Optionally, the N-type dopant element may be doped in the form of uniform doping, gradient doping, delta doping, or modulation doping.

[0012] Optionally, at least one of the first barrier layer, the second barrier layer, ..., and the nth barrier layer includes a first N-type ion doped region, a second N-type ion doped region, ..., the mth N-type ion doped region arranged sequentially, where m is a positive integer and m≥2.

[0013] Optionally, at least two of the first N-type ion doped region, the second N-type ion doped region, ..., the m-th N-type ion doped region are connected together, and the concentrations of the N-type dopants in the two connected N-type ion doped regions are different.

[0014] Optionally, the first N-type ion doped region, the second N-type ion doped region, ..., the m-th N-type ion doped region are distributed at intervals.

[0015] Optionally, the first N-type ion doped region, the second N-type ion doped region, ..., the m-th N-type ion doped region are arranged along the gate width direction.

[0016] Optionally, the N-type ion doping concentration of the first N-type ion doped region, the second N-type ion doped region, ..., the m-th N-type ion doped region gradually increases or gradually decreases from the first N-type ion doped region to the m-th N-type ion doped region.

[0017] Optionally, the N-type ion doping concentration of the first N-type ion doped region, the second N-type ion doped region, ..., the m-th N-type ion doped region gradually increases or gradually decreases from both ends of the first N-type ion doped region and the m-th N-type ion doped region toward the middle.

[0018] Optionally, the fin has multiple portions, the source covers multiple source regions, the drain covers multiple drain regions, and the gate structure covers multiple channel regions.

[0019] Optionally, the doping concentration of N-type elements in the same barrier layer of the multiple fins may be the same or different.

[0020] Optionally, the doping concentration of N-type elements in the same barrier layer of the multiple fins gradually increases or decreases from the fins on both sides to the fin in the center.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. Compared to planar HEMT devices, finned field-effect transistors (FFETs) utilize the gate's control over the channel across three surfaces, thus enhancing the gate's control over the channel. This invention provides N-type ion doping, such as Si-doped barrier layers, which alters the 2DEG concentration in the corresponding region, thereby regulating the threshold voltage of that region. Furthermore, the effect of N-type ion doping on regulating the threshold voltage in this region is influenced by the doping concentration. N-type ion doping provides additional current, broadens the transconductance peak range, and improves the linearity of the transconductance.

[0022] 2. N-type ion doping reduces contact resistance and increases source / drain current, but the mobility and isoelectric properties remain relatively stable. N-type ions can be used to achieve high current and reduce source / drain resistance.

[0023] 3. Furthermore, by mutually compensating the transconductance of a series of N-type ion-doped regions in the barrier layer, and by mutually compensating and co-acting with the transconductances of a series of devices with similar transconductance peaks but shifted peak points, transconductance stability is achieved over a large gate voltage range, thereby improving device linearity. Compared to existing methods, this approach does not require addressing the physical mechanism of the device's own transconductance characteristics; it directly utilizes devices with different transconductance characteristics to compensate for each other, avoiding extensive adjustments to the device and material structure, reducing design complexity, while maintaining the same linearization effect.

[0024] 4. Multiple fins connected between the source and drain increase the breakdown voltage and improve dynamic characteristics. The multiple fins increase the gate control area, enhance gate control capability, increase carrier density while maintaining stable semiconductor mobility, reduce sheet resistance, and significantly improve the device's frequency characteristics. Attached Figure Description

[0025] Figure 1 This is a schematic cross-sectional view of the fin field-effect transistor according to the first embodiment of the present invention; Figure 2 yes Figure 1 A top view of a fin field-effect transistor; Figure 3 yes Figure 2 A top view of a fin field-effect transistor after removing the source, drain, and gate. Figure 4 This is a schematic cross-sectional view of the fin field-effect transistor according to the second embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the fin field-effect transistor according to the third embodiment of the present invention; Figure 6 This is a schematic cross-sectional view of the fin field-effect transistor according to the fourth embodiment of the present invention; Figure 7 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the fifth embodiment of the present invention.

[0026] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below: Detailed Implementation

[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic cross-sectional view of the fin field-effect transistor according to the first embodiment of the present invention; Figure 2 yes Figure 1 A top view of a fin field-effect transistor; Figure 3 yes Figure 2 A top view of a fin field-effect transistor after removing the source, drain, and gate.

[0029] Reference Figures 1 to 3 As shown, the fin field-effect transistor 1 includes: Substrate 10; Insulating layer 11 located on substrate 10; A fin 12 protrudes from the insulating layer 11. The fin 12 includes a source region 12a, a drain region 12b, and a channel region 12c located between the source region 12a and the drain region 12b. The fin 12 includes a first heterojunction structure 121, a second heterojunction structure 122, and a third heterojunction structure 123 stacked sequentially in a direction away from the substrate 10. The first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b. The second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b. The third heterojunction structure 123 includes a third channel layer 123a and a third barrier layer 123b. The first barrier layer 121b is doped with an N-type element. The source 13 covers the source region 12a, the drain 14 covers the drain region 12b, and the gate structure 15 covers the channel region 12c.

[0030] The substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, or diamond.

[0031] The insulating layer 11 can be made of silicon dioxide.

[0032] The fin 12 is connected to the substrate 10. In this embodiment, the fin field-effect transistor 1 includes a fin 12.

[0033] Reference Figure 1 As shown, taking the first heterojunction structure 121 as an example, the first heterojunction structure 121 includes a first channel layer 121a close to the substrate 10 and a first barrier layer 121b away from the substrate 10. A two-dimensional electron gas can be formed at the interface between the first channel layer 121a and the first barrier layer 121b.

[0034] Both the first channel layer 121a and the first barrier layer 121b can be made of GaN-based materials, and the bandgap of the first barrier layer 121b is greater than that of the first channel layer 121a. The first barrier layer 121b can be made of AlGaN, and the first channel layer 121a can be made of GaN.

[0035] In this embodiment, the gate structure 15 includes only the gate 15a. The materials of the gate 15a, source 13, and drain 14 can be metals, such as Ti / Al / Ni / Au, Ni / Au, etc. A Schottky contact can be formed between the gate 15a and the fin 12, and an ohmic contact can be formed between the source 13 and the source region 12a, and between the drain 14 and the drain region 12b.

[0036] In this embodiment, the compositions of the first channel layer 121a, the second channel layer 122a, and the third channel layer 123a are fixed in the direction facing away from the substrate 10, and the compositions of the first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b are also fixed. The first barrier layer 121b is doped with an N-type element 16, which may include at least one of Si, Ge, Sn, Se, or Te. The doping method of the N-type dopant element 16 can be uniform doping, gradient doping, delta doping, or modulation doping.

[0037] N-type ion doping, such as Si-doped barrier layers, changes the 2DEG concentration in the corresponding region, thereby regulating the threshold voltage in the corresponding region; furthermore, the effect of N-type ion doping on regulating the threshold voltage in this region is affected by the doping concentration.

[0038] The fin field-effect transistor 1 in this embodiment can be considered as a parallel connection of several devices with different transconductance distributions. Each heterojunction structure corresponds to one device. Through this parallel structure, the different transconductances of the devices are mutually compensated, thereby achieving relative stability of the transconductance value over a large gate-source bias range, resulting in good linearity for the fin field-effect transistor 1.

[0039] N-type ion doping provides additional current, broadens the transconductance peak range, and improves transconductance linearity. N-type ion doping reduces contact resistance and increases source / drain current, but the mobility and isoelectric properties remain relatively stable. High current can be achieved using N-type ions, while reducing source / drain resistance.

[0040] Furthermore, the fin field-effect transistor 1 in this embodiment can effectively reduce the sheet resistance and contact resistance of the epitaxial structure, thereby improving the frequency characteristics of the device. Third, the fabrication and process tuning of the fin field-effect transistor 1 introduces minimal additional effects, resulting in higher feasibility and repeatability. It can achieve high breakdown voltage and high output current while maintaining high linearity.

[0041] In other embodiments, the fin 12 may include: a first heterojunction structure 121, a second heterojunction structure 122, ..., and an nth heterojunction structure, n≥2, which are sequentially stacked in a direction away from the substrate 10; the first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b, the second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b, ..., and the nth heterojunction structure includes an nth channel layer and an nth barrier layer; at least one of the second barrier layers 122b, ..., and the nth barrier layer is doped with an N-type element.

[0042] Figure 4 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the second embodiment of the present invention.

[0043] Reference Figure 4 As shown, the fin field-effect transistor in this embodiment 2 is largely the same as the fin field-effect transistor in embodiment 1, except that: in the fin field-effect transistor 2, the first barrier layer 121b, the second barrier layer 122b and the third barrier layer 123b are all doped with N-type dopant element 16, and from bottom to top, the concentration of N-type dopant element 16 in the first barrier layer 121b, the second barrier layer 122b and the third barrier layer 123b gradually decreases.

[0044] Because the lower the heterojunction layer, the weaker the gate's control over it, the lower the transconductance peak and the reduced linear operating characteristics. In this embodiment, the concentration of N-type dopant 16 is gradually decreased layer by layer in the multi-layer barrier structure from bottom to top. The higher doping concentration of N-type dopant 16 in the lower barrier layers can achieve a higher 2DEG density, significantly increasing the device's saturation current. For power applications, improving the saturation current is crucial. By adjusting the N-type dopant 16 concentration in different barrier layers, the saturation current of each heterojunction layer can be adjusted, thereby making the transconductance peak of each heterojunction layer more uniform.

[0045] Since the FinFET 2 can be considered as a parallel connection of several devices with different transconductance distributions, this parallel structure allows for mutual compensation of the different transconductances of the devices, thereby achieving relative stability of the transconductance value over a large gate-source bias range and giving the FinFET 2 excellent linearity.

[0046] In other embodiments, the concentration of N-type dopant 16 in the first barrier layer 121b can be greater than the concentration of N-type dopant 16 in either the second barrier layer 122b or the third barrier layer 123b, or the concentration of N-type dopant 16 in the third barrier layer 123b can be less than the concentration of N-type dopant 16 in either the first barrier layer 121b or the second barrier layer 122b.

[0047] In other embodiments, the fin 12 may include: a first heterojunction structure 121, a second heterojunction structure 122, ..., and an nth heterojunction structure, n≥2, which are sequentially stacked in a direction away from the substrate 10; the first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b, the second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b, ..., and the nth heterojunction structure includes an nth channel layer and an nth barrier layer; the concentration of N-type dopant in the first barrier layer 121b is greater than the concentration of N-type dopant in any one of the second barrier layers 122b, ..., and the nth barrier layer, or the concentration of N-type dopant in the nth barrier layer is less than the concentration of N-type dopant in any one of the first barrier layer 121b, the second barrier layer 122b, ..., and the (n-1)th barrier layer. Specifically, the concentration of N-type doped elements in the first barrier layer 121b, the second barrier layer 122b, ..., and the nth barrier layer can be gradually reduced.

[0048] Figure 5 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the third embodiment of the present invention.

[0049] Reference Figure 5As shown, the fin field-effect transistor of this embodiment 3 is largely the same as the fin field-effect transistors of embodiments 1 and 2, with the only difference being that: in the fin field-effect transistor 3, the first barrier layer 121b includes a first N-type ion doped region S1, a second N-type ion doped region S2, ... and a m-th N-type ion doped region Sm arranged sequentially, where m is a positive integer and m≥2; the first N-type ion doped region S1, the second N-type ion doped region S2, ... and the m-th N-type ion doped region Sm are arranged along the gate width direction, and the N-type ion doping concentration of the first N-type ion doped region S1, the second N-type ion doped region S2, ... and the m-th N-type ion doped region Sm increases from both ends toward the middle.

[0050] Along the gate width direction, the dimensions of the first N-type ion doped region S1, the second N-type ion doped region S2, ... and the m-th N-type ion doped region Sm can be equal or unequal.

[0051] In this embodiment, refer to Figure 5 As shown, the first N-type ion doped region S1, the second N-type ion doped region S2, ..., the m-th N-type ion doped region Sm are all connected together in all numbers. In other embodiments, a portion of the adjacent regions may be connected together, a portion may be separated, or all of the adjacent regions may be separated. When all of the adjacent regions are separated, the concentration of the N-type dopant element in the first N-type ion doped region S1, the second N-type ion doped region S2, ..., the m-th N-type ion doped region Sm can be the same or different.

[0052] By mutually compensating the transconductance of a series of N-type ion-doped regions in the barrier layer, and by mutually compensating and co-acting with the transconductance of a series of devices with similar transconductance peaks but shifted peak points, transconductance stability is achieved over a large gate voltage range, thereby improving the linearity of the fin field-effect transistor 3. Compared with existing methods, this approach does not require addressing the physical mechanism of the transconductance characteristics of the devices themselves, but directly utilizes the mutual compensation of devices with different transconductance characteristics. This avoids extensive adjustments to the device and material structure, reduces design complexity, and does not diminish the linearization effect.

[0053] In other embodiments, at least one barrier layer among the second barrier layer 122b, ..., and the nth barrier layer may include a first N-type ion doped region S1, a second N-type ion doped region S2, ..., and a m-th N-type ion doped region Sm arranged sequentially, where m is a positive integer and m≥2. The first N-type ion doped region S1, the second N-type ion doped region S2, ..., and the m-th N-type ion doped region Sm may be connected in all numbers of adjacent pairs; or connected in some numbers of adjacent pairs and spaced apart in some numbers; or spaced apart in all numbers of adjacent pairs. When all numbers of adjacent pairs are spaced apart, the concentration of the N-type dopant element in the N-type ion doped regions of the first N-type ion doped region S1, the second N-type ion doped region S2, ..., and the m-th N-type ion doped region Sm may be the same or different.

[0054] The distribution, number, and doping concentration of a series of N-type ion-doped regions in different barrier layers can be different.

[0055] In other embodiments, the arrangement of the first N-type ion doped region S1, the second N-type ion doped region S2, ..., the m-th N-type ion doped region Sm of each barrier layer can form an angle with the gate width direction, and the angle can be acute or right angle.

[0056] Furthermore, the N-type ion doping concentration of the first N-type ion doped region S1, the second N-type ion doped region S2, ..., the m-th N-type ion doped region Sm can increase or decrease from the first N-type ion doped region S1 to the m-th N-type ion doped region Sm. Or, the N-type ion doping concentration of the first N-type ion doped region S1, the second N-type ion doped region S2, ..., the m-th N-type ion doped region Sm decreases from both ends of the first N-type ion doped region S1 and the m-th N-type ion doped region Sm toward the middle.

[0057] Figure 6 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the fourth embodiment of the present invention.

[0058] Reference Figure 6 As shown, the fin field-effect transistor in this embodiment four is largely the same as the fin field-effect transistors in embodiments one to three, except that: in the fin field-effect transistor 4, the gate structure 15 includes a gate insulating layer 15b and a gate 15a.

[0059] In other words, the fin field-effect transistor 4 is a MIS HEMT transistor.

[0060] The material of the gate insulating layer 15b can be silicon dioxide, hafnium dioxide, etc.

[0061] Figure 7This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the fifth embodiment of the present invention.

[0062] Reference Figure 7 As shown, the fin field-effect transistor of this embodiment 5 is largely the same as the fin field-effect transistors of embodiments 1 to 4, except that: in the fin field-effect transistor 5, the fin portion 12 has multiple fins, the source 13 covers multiple source regions 12a, the drain 14 covers multiple drain regions 12b, and the gate structure 15 covers multiple channel regions 12c.

[0063] In contrast to a single channel region 12c, multiple channel regions 12c can form multiple parallel channels between the source 13 and the drain 14, reducing the on-resistance of the fin field-effect transistor 5.

[0064] Multiple fins 12 are connected between the source 13 and the drain 14 to increase the breakdown voltage and improve dynamic characteristics. The multiple fins 12 can also increase the gate control area, improve the gate control capability, increase the carrier density while maintaining the stability of the semiconductor mobility, reduce the surface resistance, and greatly improve the frequency characteristics of the fin field-effect transistor 5.

[0065] Furthermore, the doping concentration of N-type elements in the same barrier layer of the plurality of fins 12 can be the same or different. That is, the doping concentration of N-type elements in the first barrier layer 121b of the plurality of fins 12 can be the same or different, the doping concentration of N-type elements in the second barrier layer 122b of the plurality of fins 12 can be the same or different, ..., the doping concentration of N-type elements in the nth barrier layer of the plurality of fins 12 can be the same or different.

[0066] The doping concentration of N-type elements in the same barrier layer of multiple fins 12 can gradually increase or decrease from the fins on both sides to the fin in the center. That is, the doping concentration of N-type elements in the first barrier layer 121b of multiple fins 12 gradually increases or decreases from the fins on both sides to the fin in the center, the doping concentration of N-type elements in the second barrier layer 122b of multiple fins 12 gradually increases or decreases from the fins on both sides to the fin in the center, ..., and the doping concentration of N-type elements in the nth barrier layer of multiple fins 12 gradually increases or decreases from the fins on both sides to the fin in the center.

[0067] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A fin field-effect transistor, characterized in that, include: Substrate (10); An insulating layer (11) located on the substrate (10) includes a groove penetrating the insulating layer; A fin (12) is located on the substrate exposed by the groove and protrudes from the insulating layer (11). The fin (12) includes a source region (12a), a drain region (12b), and a channel region (12c) located between the source region (12a) and the drain region (12b). The fin (12) includes a first heterojunction structure (121), a second heterojunction structure (122), ..., an nth heterojunction structure, n≥2, which are stacked sequentially in a direction away from the substrate (10). 1) The heterojunction structure (122) includes a first channel layer (121a) and a first barrier layer (121b), the second heterojunction structure (122) includes a second channel layer (122a) and a second barrier layer (122b), ..., the nth heterojunction structure includes an nth channel layer and an nth barrier layer, the first barrier layer (121b), the second barrier layer (122b), ..., and at least one of the nth barrier layers is doped with an N-type element; wherein the fin (12) located in the channel region (12c) includes an upper surface and at least two opposing sidewalls; A source electrode (13) covering the source region (12a), and a drain electrode (14) covering the drain region (12b); and A gate structure (15) covers the upper surface of the fin (12) and the at least two opposing sidewalls located in a portion of the channel region (12c) to improve gate control capability; The first barrier layer (121b), the second barrier layer (122b), ..., and at least one barrier layer in the nth barrier layer includes a first N-type ion doped region (S1), a second N-type ion doped region (S2), ..., an m-th N-type ion doped region (Sm) arranged sequentially, where m is a positive integer and m≥2, and the first N-type ion doped region (S1), the second N-type ion doped region (S2), ..., and the m-th N-type ion doped region (Sm) do not overlap in their orthogonal projections onto the substrate; The first N-type ion doped region (S1), the second N-type ion doped region (S2), ..., the m-th N-type ion doped region (Sm) are distributed separately; The first N-type ion doped region (S1), the second N-type ion doped region (S2), ..., the m-th N-type ion doped region (Sm) are arranged at an angle to the gate width direction, and the angle is an acute angle or a right angle. The fin (12) has multiple portions, the source (13) covers multiple source regions (12a), the drain (14) covers multiple drain regions (12b), and the gate structure (15) covers multiple channel regions (12c). The doping concentration of N-type elements in the same barrier layer of the multiple fins (12) gradually increases or decreases from the fins on both sides to the fins in the center.

2. The fin field-effect transistor according to claim 1, characterized in that, The doped N-type element includes at least one of Si, Ge, Sn, Se, or Te.

3. The fin field-effect transistor according to claim 1, characterized in that, The concentration of N-type doped elements in the first barrier layer (121b) is greater than the concentration of N-type doped elements in the second barrier layer (122b), ..., and any one of the nth barrier layers, or the concentration of N-type doped elements in the nth barrier layer is less than the concentration of N-type doped elements in the first barrier layer (121b), the second barrier layer (122b), ..., and any one of the (n-1)th barrier layers.

4. The fin field-effect transistor according to claim 3, characterized in that, The concentration of N-type doped elements in the first barrier layer (121b), the second barrier layer (122b), ..., the nth barrier layer gradually decreases layer by layer.

5. The fin field-effect transistor according to claim 1, characterized in that, N-type doped elements can be doped in the form of uniform doping, gradient doping, delta doping, or modulation doping.

6. The fin field-effect transistor according to claim 1, characterized in that, The N-type ion doping concentration of the first N-type ion doped region (S1), the second N-type ion doped region (S2), ..., the m-th N-type ion doped region (Sm) gradually increases or gradually decreases from the first N-type ion doped region (S1) to the m-th N-type ion doped region (Sm).

7. The fin field-effect transistor according to claim 1, characterized in that, The N-type ion doping concentration of the first N-type ion doped region (S1), the second N-type ion doped region (S2), ..., the m-th N-type ion doped region (Sm) gradually increases or decreases from both ends of the first N-type ion doped region (S1) and the m-th N-type ion doped region (Sm) toward the middle.

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