Finfet

Abstract

The application provides a fin field effect transistor, comprising a substrate, an insulating layer, a fin, a source, a drain and a gate structure; the insulating layer is on the substrate; the fin protrudes from the insulating layer and comprises a source region, a drain region and a channel region between the source region and the drain region; the fin comprises a first heterojunction structure, a second heterojunction structure,..., and an n-th heterojunction structure stacked in sequence in a direction away from the substrate, n>=2; the first heterojunction structure comprises a first channel layer and a first barrier layer, the second heterojunction structure comprises a second channel layer and a second barrier layer,..., and the n-th heterojunction structure comprises an n-th channel layer and an n-th barrier layer; the components of at least two of the first barrier layer, the second barrier layer,..., and the n-th barrier layer are different; the source covers the source region, the drain covers the drain region, and the gate structure covers the channel region. According to the embodiment of the application, the linear working characteristics of the fin field effect transistor can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a fin field-effect transistor. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] To further promote the application of heterojunction devices in fields with higher current and higher frequency, research on multi-channel heterojunction materials and devices is essential. Compared with single-channel heterojunctions, dual-channel heterojunctions can achieve a higher total 2DEG concentration, which significantly increases the device's saturation current. However, the increased total barrier layer thickness of dual-channel heterojunction materials leads to a larger distance between the device gate and the underlying channel, thus reducing gate control capability, lowering the device's transconductance peak value, and requiring further improvement in linear operating characteristics.

[0004] In fields such as communications, the linearity of semiconductor devices is a crucial parameter. However, in conventional HEMT devices, due to factors such as decreased electron saturation velocity and increased series resistance, the transconductance initially rises with increasing gate-source bias, reaches a certain peak, and then declines. This decline in transconductance affects the device's linearity. Summary of the Invention

[0005] The purpose of this invention is to provide a fin field-effect transistor to improve the linear operating characteristics of HEMT devices.

[0006] To achieve the above objectives, the present invention provides a fin field-effect transistor, comprising:

[0007] Substrate;

[0008] An insulating layer located on the substrate;

[0009] A fin protruding from the insulating layer, the fin including a source region, a drain region, and a channel region located between the source region and the drain region; the fin including: a first heterojunction structure, a second heterojunction structure, ..., and an nth heterojunction structure, n≥2, sequentially stacked in a direction away from the substrate; the first heterojunction structure including a first channel layer and a first barrier layer, the second heterojunction structure including a second channel layer and a second barrier layer, ..., the nth heterojunction structure including an nth channel layer and an nth barrier layer, wherein the composition of the first barrier layer, the second barrier layer, ..., is different from at least two of the nth barrier layer;

[0010] A source covering the source region, a drain covering the drain region, and a gate structure covering the channel region.

[0011] Optionally, the materials of the first barrier layer, the second barrier layer, ..., and the nth barrier layer are all AlGaN.

[0012] Optionally, from bottom to top, the composition of Al in the first barrier layer, the second barrier layer, ..., and the nth barrier layer gradually decreases.

[0013] Optionally, from bottom to top, the composition of Al in the first barrier layer, the second barrier layer, ..., and the nth barrier layer increases and then decreases layer by layer.

[0014] Optionally, the number of barrier layers above the highest barrier layer of the Al component is greater than or equal to the number of barrier layers below the highest barrier layer of the Al component.

[0015] Optionally, at least one of the first barrier layer, the second barrier layer, ..., and the nth barrier layer has an Al composition that remains constant, gradually decreases, or gradually increases.

[0016] Optionally, the fin has multiple portions, the source covers multiple source regions, the drain covers multiple drain regions, and the gate structure covers multiple channel regions.

[0017] Optionally, at least two of the plurality of fins may have different heights or widths.

[0018] Optionally, from bottom to top, the thickness of the first barrier layer, the second barrier layer, ..., and the nth barrier layer gradually decreases.

[0019] Optionally, the width of the first heterojunction structure is greater than the width of the second heterojunction structure, ..., and any one of the nth heterojunction structures, or the width of the nth heterojunction structure is less than the width of the first heterojunction structure, the second heterojunction structure, ..., and any one of the (n-1)th heterojunction structures.

[0020] Optionally, the width of the first heterojunction structure, the second heterojunction structure, ..., the nth heterojunction structure gradually decreases.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] 1. Compared to planar HEMT devices, fin-type field-effect transistors (FETs) improve gate-channel control by utilizing the gate's control over three surfaces. Furthermore, the fin configuration comprises n heterojunction structures stacked along the thickness direction. By varying the composition, thickness, and / or width of the barrier layer of each heterojunction structure, the transconductance peak value and threshold voltage of each heterojunction structure are altered. The superposition of multiple heterojunction structures enhances the device's linear operating characteristics.

[0023] 2. The fin field-effect transistor provided by this invention effectively reduces the sheet resistance and contact resistance of the epitaxial structure through a multi-layered stacked heterojunction structure, thereby improving the frequency characteristics of the device. At least two barrier layers with different compositions achieve mutual compensation of transconductance, resulting in relative stability of transconductance over a wide gate-source bias range. Increased electron saturation velocity leads to excellent linearity. The device fabrication and process tuning of this invention introduce minimal additional effects, exhibiting higher feasibility and repeatability. It maintains high linearity while achieving high breakdown voltage and high output current.

[0024] 3. Due to the decreasing control over the gate in the lower layers of the heterojunction structure, the peak transconductance of the device decreases, resulting in reduced linearity. This invention addresses this by progressively decreasing the Al composition in multiple barrier layers from bottom to top. The higher Al composition in the lower barrier layers allows for a higher 2DEG density, significantly increasing the device's saturation current. For power applications, improving the saturation current is crucial. By adjusting the Al composition of different barrier layers, the saturation current of each heterojunction layer is adjusted, thereby making the peak transconductance of each heterojunction layer more uniform. The semiconductor structure of this invention can be viewed as a parallel connection of several devices with different transconductance distributions. This parallel structure achieves mutual compensation between the different transconductances of the devices, thereby achieving relative stability of the transconductance value over a large gate-source bias range, resulting in excellent linearity.

[0025] 4. The Al composition in the barrier layer can adjust the peak value and distribution of transconductance. This invention ensures the control of the top gate over the bottom channel by gradually increasing and then decreasing the Al composition in multiple barrier layers from bottom to top, while adjusting the linearity of the device.

[0026] 5. Multiple fins connected between the source and drain increase the breakdown voltage and improve dynamic characteristics. The multiple fins increase the gate control area, enhance gate control capability, increase carrier density while maintaining stable semiconductor mobility, reduce sheet resistance, and significantly improve the device's frequency characteristics.

[0027] 6. At least two of the multiple fins have different heights or widths. The fin field-effect transistor of this invention can be regarded as a parallel connection of several devices with different transconductance distributions. By having at least two of the multiple fins in this parallel structure have different heights or widths, mutual compensation of the different transconductances of the devices can be achieved. The wider the fin, the flatter and smaller the transconductance; the narrower the fin, the narrower and higher the transconductance, thereby achieving relative stability of the transconductance value over a large gate-source bias range. Attached Figure Description

[0028] Figure 1 This is a schematic cross-sectional view of the fin field-effect transistor according to the first embodiment of the present invention;

[0029] Figure 2 yes Figure 1 A top view of a fin field-effect transistor;

[0030] Figure 3 yes Figure 2 A top view of a fin field-effect transistor after removing the source, drain, and gate.

[0031] Figure 4 This is a schematic cross-sectional view of the fin field-effect transistor according to the second embodiment of the present invention;

[0032] Figure 5 This is a schematic cross-sectional view of the fin field-effect transistor according to the third embodiment of the present invention;

[0033] Figure 6 This is a schematic cross-sectional view of the fin field-effect transistor according to the fourth embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the fifth embodiment of the present invention.

[0035] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0036] Substrate 10 Insulating layer 11

[0037] Fin 12 Source Region 12a

[0038] Leakage area 12b, Channel area 12c

[0039] First heterojunction structure 121 First channel layer 121a

[0040] First barrier layer 121b Second heterojunction structure 122

[0041] Second channel layer 122a Second barrier layer 122b

[0042] Third heterojunction structure 123 Third channel layer 123a

[0043] Third barrier layer 123b Source 13

[0044] Drain 14 Gate structure 15

[0045] Gate 15a Gate insulating layer 15b

[0046] Fin field-effect transistors 1, 2, 3, 4, 5 Detailed Implementation

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figure 1 This is a schematic cross-sectional view of the fin field-effect transistor according to the first embodiment of the present invention; Figure 2 yes Figure 1 A top view of a fin field-effect transistor; Figure 3 yes Figure 2 A top view of a fin field-effect transistor after removing the source, drain, and gate.

[0049] Reference Figures 1 to 3 As shown, the fin field-effect transistor 1 includes:

[0050] Substrate 10;

[0051] Insulating layer 11 located on substrate 10;

[0052] A fin 12 protrudes from the insulating layer 11. The fin 12 includes a source region 12a, a drain region 12b, and a channel region 12c located between the source region 12a and the drain region 12b. The fin 12 includes a first heterojunction structure 121, a second heterojunction structure 122, and a third heterojunction structure 123 stacked sequentially in a direction away from the substrate 10. The first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b. The second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b. The third heterojunction structure 123 includes a third channel layer 123a and a third barrier layer 123b. The first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b have different component sizes.

[0053] The source 13 covers the source region 12a, the drain 14 covers the drain region 12b, and the gate structure 15 covers the channel region 12c.

[0054] The substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, or diamond.

[0055] The insulating layer 11 can be made of silicon dioxide.

[0056] The fin 12 is connected to the substrate 10. In this embodiment, the fin field-effect transistor 1 includes a fin 12.

[0057] Reference Figure 1 As shown, taking the first heterojunction structure 121 as an example, the first heterojunction structure 121 includes a first channel layer 121a close to the substrate 10 and a first barrier layer 121b away from the substrate 10. A two-dimensional electron gas can be formed at the interface between the first channel layer 121a and the first barrier layer 121b.

[0058] Both the first channel layer 121a and the first barrier layer 121b can be made of GaN-based materials, and the bandgap of the first barrier layer 121b is greater than that of the first channel layer 121a. The first barrier layer 121b can be made of AlGaN, and the first channel layer 121a can be made of GaN.

[0059] In this embodiment, the gate structure 15 includes only the gate 15a. The materials of the gate 15a, source 13, and drain 14 can be metals, such as Ti / Al / Ni / Au, Ni / Au, etc. A Schottky contact can be formed between the gate 15a and the fin 12, and an ohmic contact can be formed between the source 13 and the source region 12a, and between the drain 14 and the drain region 12b.

[0060] a) In this embodiment, in the direction away from the substrate 10, the compositions of the first channel layer 121a, the second channel layer 122a, and the third channel layer 123a are fixed, while the Al composition in the first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b gradually decreases. The Al composition in the third barrier layer 123b is less than that in the second barrier layer 122b, and the two-dimensional electron gas concentration in the third heterojunction structure 123 is less than that in the second heterojunction structure 122. The Al composition in the second barrier layer 122b is less than that in the first barrier layer 121b, and the two-dimensional electron gas concentration in the second heterojunction structure 122 is less than that in the first heterojunction structure 121. The higher the two-dimensional electron gas concentration of the heterojunction structure, the worse the control capability of the gate 15a pair on the heterojunction structure, and the more negatively the transconductance peak shifts; conversely, the more positively the transconductance peak shifts.

[0061] (b) Furthermore, the high concentration of two-dimensional electron gas in the heterojunction structure can significantly increase the saturation current of the device, which is crucial for power applications. The saturation current of the device corresponding to the first heterojunction structure 121 is greater than that of the device corresponding to the second heterojunction structure 122, and the saturation current of the device corresponding to the second heterojunction structure 122 is greater than that of the device corresponding to the third heterojunction structure 123. The larger the saturation current of the device corresponding to the heterojunction structure, the larger the peak transconductance, and vice versa.

[0062] c) Third, the third heterojunction structure 123 is close to the gate 15a, while the first heterojunction structure 121 is far from the gate 15a. The closer the heterojunction structure is to the gate 15a, the stronger the control capability of the gate 15a over the heterojunction structure, the more the transconductance peak value shifts to the positive direction, and the larger the transconductance peak value; conversely, the more the transconductance peak value shifts to the negative direction, and the smaller the transconductance peak value.

[0063] The fin field-effect transistor 1 in this embodiment can be considered as a parallel connection of several devices with different transconductance distributions. Combining the three factors mentioned above (a), (b), and (c), the different Al compositions of each barrier layer achieve mutual compensation of transconductance. Through this parallel structure, mutual compensation of the different transconductances of the devices is achieved, thereby realizing relative stability of the transconductance value over a large gate-source bias range, resulting in excellent linearity for the fin field-effect transistor 1.

[0064] Furthermore, the fin field-effect transistor 1 in this embodiment can effectively reduce the sheet resistance and contact resistance of the epitaxial structure, thereby improving the frequency characteristics of the device. Third, the fabrication and process tuning of the fin field-effect transistor 1 introduces minimal additional effects, resulting in higher feasibility and repeatability. It can achieve high breakdown voltage and high output current while maintaining high linearity.

[0065] In this embodiment, the first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b are identical in all parameters except for the Al composition. The first channel layer 121a, the second channel layer 122a, and the third channel layer 123a are also identical in all parameters.

[0066] In other embodiments, in the fin field-effect transistor 1, the Al content in the first barrier layer 121b may be greater than the Al content of either the second barrier layer 122b or the third barrier layer 123b; or the Al content in the third barrier layer 123b may be less than the Al content of either the first barrier layer 121b or the second barrier layer 122b.

[0067] In other embodiments, the fin 12 may include: a first heterojunction structure 121, a second heterojunction structure 122, ..., and an nth heterojunction structure, n≥2, which are sequentially stacked in a direction facing away from the substrate 10; the first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b, the second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b, ..., and the nth heterojunction structure includes an nth channel layer and an nth barrier layer. The barrier layers, including the first channel layer 121a, the second channel layer 122a, ..., and the nth channel layer, have fixed compositions. The Al composition in the first barrier layer 121b is greater than the Al composition in the second barrier layer 122b, ..., and any one of the nth barrier layers, or the Al composition in the nth barrier layer is less than the Al composition in the first barrier layer 121b, the second barrier layer 122b, ..., and any one of the (n-1)th barrier layers, where n is 2, 4, or more. Specifically, the Al composition in the first barrier layer 121b, the second barrier layer 122b, ..., and the nth barrier layer can gradually decrease, or increase and then decrease, or at least one barrier layer may have a constant Al composition, gradually decrease, or gradually increase.

[0068] For the first barrier layer 121b, the second barrier layer 122b, ..., the nth barrier layer, the Al composition first increases and then decreases. The number of barrier layers above the barrier layer with the highest Al composition can be greater than or equal to the number of barrier layers below the barrier layer with the highest Al composition.

[0069] Figure 4 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the second embodiment of the present invention.

[0070] Reference Figure 4 As shown, the fin field-effect transistor in this embodiment 2 is largely the same as the fin field-effect transistor in embodiment 1, except that the thickness of the first barrier layer 121b, the second barrier layer 122b and the third barrier layer 123b in the fin field-effect transistor 2 gradually decreases.

[0071] d) In this embodiment, the thicknesses of the first channel layer 121a, the second channel layer 122a, and the third channel layer 123a are fixed, while the thicknesses of the first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b gradually decrease. A larger barrier layer thickness results in a larger saturation current and a larger peak transconductance in the heterojunction. For power applications, increasing the saturation current is crucial. By adjusting the thickness of different barrier layers, the saturation current of each heterojunction layer is adjusted, thereby making the peak transconductance of each heterojunction layer more uniform.

[0072] Combining factors c) and d) above, this embodiment achieves mutual compensation of different transconductances of the device by controlling the different thicknesses of the barrier layers, thereby achieving relative stability of the transconductance value within a large gate-source bias range, and making the fin field-effect transistor 2 have good linearity.

[0073] In this embodiment, the first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b are identical in all parameters except for their thickness. The first channel layer 121a, the second channel layer 122a, and the third channel layer 123a are also identical in all parameters.

[0074] In other embodiments, in the fin field-effect transistor 1, the thickness of the first barrier layer 121b may be greater than the thickness of either the second barrier layer 122b or the third barrier layer 123b; or the thickness of the third barrier layer 123b may be less than the thickness of either the first barrier layer 121b or the second barrier layer 122b.

[0075] In other embodiments, the fin 12 may include: a first heterojunction structure 121, a second heterojunction structure 122, ..., and an nth heterojunction structure, n≥2, which are sequentially stacked in a direction away from the substrate 10; the first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b, the second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b, ..., and the nth heterojunction structure includes an nth channel layer and an nth barrier layer; the thicknesses of the first channel layer 121a, the second channel layer 122a, ..., and the nth channel layer are fixed; the thickness of the first barrier layer 121b is greater than the thickness of any one of the second barrier layers 122b, ..., and the nth barrier layer, or the thickness of the nth barrier layer is less than the thickness of any one of the first barrier layer 121b, the second barrier layer 122b, ..., and the (n-1)th barrier layer; n is 2, or 4 or more. Specifically, the thickness of the first barrier layer 121b, the second barrier layer 122b, ..., the nth barrier layer can be gradually reduced.

[0076] Figure 5 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the third embodiment of the present invention.

[0077] Reference Figure 5 As shown, the fin field-effect transistor of this embodiment 3 is largely the same as the fin field-effect transistor of embodiment 1, except that in the fin field-effect transistor 3, the width of the first heterojunction structure 121, the second heterojunction structure 122, ..., the nth heterojunction structure gradually decreases.

[0078] e) In this embodiment, the widths of the first channel layer 121a, the second channel layer 122a, and the third channel layer 123a gradually decrease, as do the widths of the first barrier layer 121b, the second barrier layer 122b, and the third barrier layer 123b. The larger the width of the barrier layer in the heterojunction structure, the worse the control capability of the gate 15a pair over the heterojunction structure, and the more negatively the transconductance peak value shifts; conversely, the smaller the width, the more positively the transconductance peak value shifts. On the other hand, the larger the width of the barrier layer in the heterojunction structure, the larger the saturation current in the heterojunction structure, and the correspondingly larger the transconductance peak value. For power applications, increasing the saturation current is crucial. By adjusting the width of different barrier layers, the saturation current of each heterojunction layer is adjusted, thereby making the transconductance peak value of each heterojunction layer more uniform.

[0079] Combining the two factors mentioned above (c) and (e), this embodiment achieves mutual compensation of different transconductances of the device by controlling the different width dimensions of the barrier layer of different heterojunction structure layers, thereby achieving relative stability of the transconductance value within a large gate-source bias range, and making the fin field-effect transistor 3 have good linearity.

[0080] In this embodiment, the first heterojunction structure 121, the second heterojunction structure 122, and the third heterojunction structure 123 are identical in all parameters except for their width dimensions.

[0081] In other embodiments, the width of the first heterojunction structure 121 may be greater than the width of any one of the second heterojunction structures 122, ..., and the nth heterojunction structure, or the width of the nth heterojunction structure may be less than the width of any one of the first heterojunction structure 121, the second heterojunction structure 122, ..., and the (n-1)th heterojunction structure layer.

[0082] In other embodiments, the fin 12 may include: a first heterojunction structure 121, a second heterojunction structure 122, ..., and an nth heterojunction structure, n≥2, which are stacked sequentially in a direction away from the substrate 10; the first heterojunction structure 121 includes a first channel layer 121a and a first barrier layer 121b, the second heterojunction structure 122 includes a second channel layer 122a and a second barrier layer 122b, ..., and the nth heterojunction structure includes an nth channel layer and an nth barrier layer; the width of the first heterojunction structure 121 is greater than the width of any one of the second heterojunction structures 122, ..., and the nth heterojunction structure, or the width of the nth heterojunction structure is less than the width of any one of the first heterojunction structure 121, the second heterojunction structure 122, ..., and the (n-1)th heterojunction structure, where n is 2, or 4 or more. Specifically, the width dimensions of the first heterojunction structure 121, the second heterojunction structure 122, ..., and the nth heterojunction structure can be gradually reduced.

[0083] In other embodiments, the width dimensions of the first heterojunction structure 121, the second heterojunction structure 122, and the third heterojunction structure 123 may also gradually decrease in a stepped manner.

[0084] In other embodiments, all or any two of the solutions described in embodiments one to three can be used in combination.

[0085] Figure 6 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the fourth embodiment of the present invention.

[0086] Reference Figure 6 As shown, the fin field-effect transistor in this embodiment four is largely the same as the fin field-effect transistors in embodiments one to three, except that: in the fin field-effect transistor 4, the gate structure 15 includes a gate insulating layer 15b and a gate 15a.

[0087] In other words, the fin field-effect transistor 4 is a MIS HEMT transistor.

[0088] The material of the gate insulating layer 15b can be silicon dioxide, hafnium dioxide, etc.

[0089] Figure 7 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor according to the fifth embodiment of the present invention.

[0090] Reference Figure 7 As shown, the fin field-effect transistor of this embodiment 5 is largely the same as the fin field-effect transistors of embodiments 1 to 4, except that: in the fin field-effect transistor 5, the fin portion 12 has multiple fins, the source 13 covers multiple source regions 12a, the drain 14 covers multiple drain regions 12b, and the gate structure 15 covers multiple channel regions 12c.

[0091] In contrast to a single channel region 12c, multiple channel regions 12c can form multiple parallel channels between the source 13 and the drain 14, reducing the on-resistance of the fin field-effect transistor 5.

[0092] Multiple fins 12 are connected between the source 13 and the drain 14 to increase the breakdown voltage and improve dynamic characteristics. The multiple fins 12 can also increase the gate control area, improve the gate control capability, increase the carrier density while maintaining the stability of the semiconductor mobility, reduce the surface resistance, and greatly improve the frequency characteristics of the fin field-effect transistor 5.

[0093] Among the multiple fins 12, at least two fins 12 may have different heights or widths.

[0094] The fin field-effect transistor 5 in this embodiment can be regarded as a parallel connection of several devices with different transconductance distributions. By having at least two of the multiple fins 12 in this parallel structure have different heights or widths, mutual compensation of the different transconductances of the devices can be achieved. Among the multiple fins 12, the wider the fin 12, the flatter and smaller the transconductance; the narrower the fin 12, the narrower and higher the transconductance, thereby achieving relative stability of the transconductance value over a large gate-source bias range.

[0095] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A fin field-effect transistor, characterized in that, include: Substrate (10); An insulating layer (11) is located on the substrate (10). A fin (12) protruding from the insulating layer (11) includes a source region (12a), a drain region (12b), and a channel region (12c) located between the source region (12a) and the drain region (12b); wherein the source region (12a), the channel region (12c), and the drain region (12b) are arranged sequentially along the length direction (Y) of the fin (12), and the dimensions of the source region (12a), the channel region (12c), and the drain region (12b) along the width direction (X) of the fin (12) are the same as the dimensions along the width direction (X) of the fin (12); the fin (12) includes: facing towards A first heterojunction structure (121), a second heterojunction structure (122), ..., and an nth heterojunction structure, n≥2, are stacked sequentially in a direction away from the substrate (10); the first heterojunction structure (121) includes a first channel layer (121a) and a first barrier layer (121b); the second heterojunction structure (122) includes a second channel layer (122a) and a second barrier layer (122b), ...; the nth heterojunction structure includes an nth channel layer and an nth barrier layer; the composition of the first barrier layer (121b), the second barrier layer (122b), ..., is different from that of at least two of the nth barrier layer. The source electrode (13) covering the source region (12a) of the fin (12), the drain electrode (14) covering the drain region (12b) of the fin (12), and the gate structure (15) covering the channel region (12c) of the fin (12). The first barrier layer (121b), the second barrier layer (122b), ..., and the nth barrier layer are all made of AlGaN. From bottom to top, the Al composition of the first barrier layer (121b), the second barrier layer (122b), ..., and the nth barrier layer increases and then decreases layer by layer to adjust the linearity of the fin field-effect transistor. The fin (12) is multiple, and at least two of the multiple fins (12) have different heights or widths.

2. The fin field-effect transistor according to claim 1, characterized in that, The number of barrier layers above the highest barrier layer of the Al component is greater than or equal to the number of barrier layers below the highest barrier layer of the Al component.

3. The fin field-effect transistor according to claim 1, characterized in that, The Al composition of at least one of the first barrier layer (121b), the second barrier layer (122b), ..., and the nth barrier layer remains constant, gradually decreases, or gradually increases.

4. The fin field-effect transistor according to claim 1, characterized in that, The source (13) also covers multiple source regions (12a), the drain (14) also covers multiple drain regions (12b), and the gate structure (15) also covers multiple channel regions (12c).

5. The fin field-effect transistor according to claim 1, characterized in that, From bottom to top, the thickness of the first barrier layer (121b), the second barrier layer (122b), ..., and the nth barrier layer gradually decreases.

6. The fin field-effect transistor according to claim 1, characterized in that, The width of the first heterojunction structure (121) is greater than the width of the second heterojunction structure (122), ..., and any one of the nth heterojunction structures, or the width of the nth heterojunction structure is less than the width of the first heterojunction structure (121), the second heterojunction structure (122), ..., and any one of the (n-1)th heterojunction structures.

7. The fin field-effect transistor according to claim 6, characterized in that, The width of the first heterojunction structure (121), the second heterojunction structure (122), ..., the nth heterojunction structure gradually decreases.

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