Light-emitting diode with improved electrode conductivity and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode and a preparation method thereof for improving the conductivity of electrodes, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode comprises: a substrate, an epitaxial layer, a first electrode, and a second electrode; the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, the epitaxial layer has a groove exposing the first semiconductor layer, the first electrode is located in the groove and connected to the first semiconductor layer, and the second electrode is located on the surface of the second semiconductor layer; at least one of the first electrode and the second electrode comprises a gold layer and a nano copper wire located in the gold layer. The embodiments of the present disclosure can reduce the amount of gold used when making electrodes and reduce the production cost of light-emitting diodes.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved electrode conductivity and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is an extremely influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In the related art, a light-emitting diode generally includes a substrate, an epitaxial layer and two electrodes, wherein the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence on the substrate. Among them, one electrode is located on the second semiconductor layer and electrically connected to the second semiconductor layer, and a groove is also provided on the second semiconductor layer to expose the first semiconductor layer, and the other electrode is located in the groove and electrically connected to the first semiconductor layer.

[0004] In order to improve the current expansion performance of the light-emitting diode, the thickness of the electrode is usually set to be thicker; however, the material used to make the electrode is mostly gold, which increases the production cost of the light-emitting diode. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode with improved electrode conductivity and a method for manufacturing the same, which can reduce the amount of gold used in manufacturing the electrode and reduce the manufacturing cost of the light-emitting diode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: a substrate, an epitaxial layer, a first electrode, and a second electrode; the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, the epitaxial layer has a groove exposing the first semiconductor layer, the first electrode is located in the groove and connected to the first semiconductor layer, and the second electrode is located on the surface of the second semiconductor layer; at least one of the first electrode and the second electrode includes a gold layer and a plurality of nano copper wires located in the gold layer.

[0007] Optionally, the nano copper wire includes two AuSn segments, two CuAu segments and a gold-coated Cu segment, the two CuAu segments are respectively located at both ends of the gold-coated Cu segment and connected to the gold-coated Cu segment, the two AuSn segments are respectively located at both ends of the gold-coated Cu segment, and the two AuSn segments are respectively connected to the two CuAu segments.

[0008] Optionally, in a cross section perpendicular to the substrate, the first electrode or the second electrode comprises a Cr layer, a Ti layer, a first Au layer, the gold layer and a second Au layer stacked in sequence, and the gold layer has the nano copper wires therein.

[0009] Optionally, the thickness of the Cr layer is 10 angstroms to 50 angstroms, the thickness of the Ti layer is 1000 angstroms to 3000 angstroms, the thickness of the first Au layer is 3000 angstroms to 7000 angstroms, the thickness of the gold layer is 3000 angstroms to 7000 angstroms, and the thickness of the second Au layer is 2000 angstroms to 5000 angstroms.

[0010] Optionally, the length of the AuSn segment is 2 μm to 5 μm, the length of the CuAu segment is 2 μm to 5 μm, and the length of the gold-coated Cu segment is 5 μm to 15 μm.

[0011] Optionally, in the length direction of the CuAu segment, the Cu content in the CuAu segment changes gradually from one end to the other, and the content at one end close to the gold-coated Cu segment is greater than that at the other end.

[0012] Optionally, the second electrode includes an electrode block and an electrode strip, one end of the electrode strip is connected to the electrode block, and the nano copper wire is located in the electrode strip.

[0013] Optionally, a plurality of the nano-copper wires are distributed in parallel and at intervals, and the nano-copper wires extend along the length direction of the electrode strips.

[0014] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode, the method comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, the epitaxial layer having a groove exposing the first semiconductor layer; making a first electrode and a second electrode on the epitaxial layer, the first electrode being located in the groove and connected to the first semiconductor layer, and the second electrode being located on the surface of the second semiconductor layer; at least one of the first electrode and the second electrode comprising a gold layer and a plurality of nano-copper wires located in the gold layer.

[0015] Optionally, before forming the first electrode and the second electrode on the epitaxial layer, the method includes: forming a transparent conductive layer on the second semiconductor layer; and irradiating the transparent conductive layer with laser light in a region corresponding to the nano copper wire.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode provided by the embodiment of the present disclosure includes an epitaxial layer stacked on a substrate, and the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence. The second electrode is located on the second semiconductor layer, and the epitaxial layer has a groove exposing the first semiconductor layer. The first electrode is located in the groove and connected to the first semiconductor layer, so that the light-emitting diode can emit light by energizing the two electrodes. At least one of the first electrode and the second electrode includes a gold layer and a plurality of nano copper wires embedded in the gold layer.

[0018] Compared with using a gold layer as an electrode, setting part of the electrode area as nano-copper wire can reduce the amount of gold used in making the electrode by setting nano-copper wire to replace part of the gold. Nano-copper wire also has good conductivity, which ensures the current expansion performance of the light-emitting diode and saves the amount of gold used in making the electrode, thereby reducing the production cost of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 AA section diagram provided;

[0022] Figure 3 is a partial structural schematic diagram of an electrode provided by an embodiment of the present disclosure;

[0023] Figure 4 is a schematic structural diagram of a nano copper wire provided by an embodiment of the present disclosure;

[0024] Figure 5 is a cross-sectional view of an electrode provided by an embodiment of the present disclosure;

[0025] Figure 6 is a graph showing the relationship between the Cu content and the distance between each position in the CuAu segment and the AuSn segment provided by an embodiment of the present disclosure;

[0026] Figure 7 It is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0027] The descriptions of the marks in the figure are as follows:

[0028] 10. Substrate;

[0029] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove;

[0030] 31. first electrode; 32. second electrode; 321. electrode block; 322. electrode strip;

[0031] 320, gold layer; 330, nano copper wire; 331, AuSn segment; 332, CuAu segment; 333, Cu segment; 334, Cr layer; 335, Ti layer; 336, first Au layer; 338, second Au layer;

[0032] 41. Transparent conductive layer; 42. Current blocking layer; 43. Passivation layer; 44. Reflective layer. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] Figure 1 FIG. 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode includes: a substrate 10 , an epitaxial layer 20 , a second electrode 32 and a first electrode 31 .

[0036] Figure 2 yes Figure 1 Provided AA cross-section diagram. Figure 2As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence on the substrate 10, the epitaxial layer 20 has a groove 24 exposing the first semiconductor layer 21, the first electrode 31 is located in the groove 24 and connected to the first semiconductor layer 21, and the second electrode 32 is located on the surface of the second semiconductor layer 23.

[0037] Figure 3 Schematic diagram of a partial structure of an electrode provided by an embodiment of the present disclosure. Figure 1 , 2 As shown in 3 , at least one of the first electrode 31 and the second electrode 32 includes a gold layer 320 and a plurality of nano copper wires 330 located in the gold layer 320 .

[0038] The light-emitting diode provided by the embodiment of the present disclosure includes an epitaxial layer 20 stacked on a substrate 10, and the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence. The second electrode 32 is located on the second semiconductor layer 23, and the epitaxial layer 20 has a groove 24 that exposes the first semiconductor layer 21. The first electrode 31 is located in the groove 24 and is connected to the first semiconductor layer 21, so that the light-emitting diode can emit light by applying power to the two electrodes. Among them, at least one of the first electrode 31 and the second electrode 32 includes a gold layer 320 and a plurality of nano copper wires 330 embedded in the gold layer 320.

[0039] Compared with using the gold layer 320 as the electrode, part of the electrode area is set as the nano copper wire 330. By setting the nano copper wire 330 to replace part of the gold, the amount of gold used in making the electrode can be reduced, and the nano copper wire 330 also has good conductivity. This ensures the current expansion performance of the light-emitting diode, saves the amount of gold used in making the electrode, and reduces the production cost of the light-emitting diode.

[0040] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0041] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0042] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0043] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0044] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0045] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0046] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0047] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0048] Alternatively, if Figure 2 As shown, the light emitting diode further includes a transparent conductive layer 41 . The transparent conductive layer 41 is located on the surface of the second semiconductor layer 23 , and the transparent conductive layer 41 is located between the second electrode 32 and the second semiconductor layer 23 .

[0049] Exemplarily, the transparent conductive layer 41 can be an indium tin oxide (ITO) film layer. The indium tin oxide film layer has good transmittance and low resistivity. Using the indium tin oxide film layer as the transparent conductive layer 41 can allow more light to be transmitted from the transparent conductive layer 41, thereby ensuring the effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves the injection efficiency.

[0050] Exemplarily, the thickness of the transparent conductive layer 41 may be 800 angstroms to 1200 angstroms.

[0051] Alternatively, if Figure 2 As shown, the light-emitting diode also includes a current blocking layer 42, which is located on the surface of the second semiconductor layer 23, and between the transparent conductive layer 41 and the second semiconductor layer 23, and the orthographic projection of the current blocking layer 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode 32 on the substrate.

[0052] By disposing the current blocking layer 42 between the transparent conductive layer 41 and the second semiconductor layer 23 , current transfer can be blocked, allowing more current to be transferred to various regions of the second semiconductor layer 23 through the transparent conductive layer 41 .

[0053] Alternatively, if Figure 2 As shown, the light emitting diode further includes a passivation layer 43 , which is located on the surface of the second semiconductor layer 23 , the surface of the transparent conductive layer 41 , the surface of the second electrode 32 , the surface of the first semiconductor layer 21 and the surface of the first electrode 31 .

[0054] The passivation layer 43 has via holes respectively exposing the second electrode 32 and the first electrode 31 , so that electricity can be supplied to the second electrode 32 and the first electrode 31 through the via holes.

[0055] Exemplarily, the passivation layer 43 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 1000 angstroms to 3000 angstroms. For example, the thickness of the silicon oxide layer is 2000 angstroms.

[0056] Alternatively, if Figure 2 As shown, the light emitting diode further includes a reflective layer 44 , and the reflective layer 44 is located on a surface of the substrate 10 away from the epitaxial layer 20 .

[0057] For example, the reflective layer 44 may be a distributed Bragg reflector (DBR) layer, which includes a plurality of periodically alternately stacked SiO 2 Layer and TiO 2 The number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0058] Among them, SiO in the DBR layer 2 The thickness of the layer can be 800 angstroms to 1200 angstroms, TiO 2 The layer thickness may be 500 angstroms to 900 angstroms.

[0059] The DBR layer is used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the light emitting surface of the light emitting diode, thereby improving the light emitting effect.

[0060] Alternatively, if Figure 1 As shown, the second electrode 32 includes an electrode block 321 and an electrode strip 322 , one end of the electrode strip 322 is connected to the electrode block 321 , and the nano copper wire 330 is located in the electrode strip 322 .

[0061] In the disclosed embodiment, multiple copper nanowires 330 are embedded in the electrode strips 322 at intervals, which can significantly reduce the amount of gold used in making electrodes. The copper nanowires 330 have better conductivity, which also ensures the current expansion performance of the light-emitting diode.

[0062] Furthermore, since the electrode block 321 is the portion of the electrode used for conducting electricity to the outside, not providing the nano copper wire 330 in this area can ensure good conductivity.

[0063] Optionally, the diameter of the nano copper wire 330 is 30 nm to 70 nm. Exemplarily, the diameter of the nano copper wire 330 is 50 nm.

[0064] By setting the diameter of the nano copper wire within the above range, it is possible to avoid setting the nano copper wire too thin, which would not reduce the amount of gold used to save costs; it is also possible to avoid setting the nano copper wire too thick, which would significantly reduce the gold content in the electrode and affect the current conduction of the electrode.

[0065] Alternatively, if Figure 3 As shown, a plurality of nano copper wires 330 are distributed in parallel and spaced apart from each other, and the nano copper wires 330 extend along the length direction of the electrode strips 322 .

[0066] By arranging the nano copper wires 330 in an orderly manner along the length direction of the electrode strips 322, it is possible to ensure that the current is smoothly conducted along the length direction of the electrode strips 322, thereby ensuring the conductive performance of the electrode.

[0067] Figure 4 3 is a schematic diagram of the structure of a nano copper wire 330 provided in an embodiment of the present disclosure. Figure 4 As shown, the nano copper wire 330 includes two AuSn segments 331, two CuAu segments 332 and a gold-coated Cu segment 333. The two CuAu segments 332 are respectively located at the two ends of the gold-coated Cu segment 333 and are connected to the gold-coated Cu segment 333. The two AuSn segments 331 are respectively located at the two ends of the gold-coated Cu segment 333, and the two AuSn segments 331 are respectively connected to the two CuAu segments 332.

[0068] Combination Figure 4 , Figure 4 From left to right in the figure, the first AuSn segment 331, the first CuAu segment 332, the gold-clad Cu segment 333, the second AuSn segment 331 and the second CuAu segment 332 are connected in sequence.

[0069] In the disclosed embodiment, since the gold-clad Cu segment 333 is coated in the gold layer 320, in order to improve the connection reliability between the gold-clad Cu segment 333 and the gold layer 320, an AuSn segment 331 is provided at the end of the gold-clad Cu segment 333, and the AuSn segment 331 is used as solder to firmly connect the gold-clad Cu segment 333 and the gold layer 320 together.

[0070] Furthermore, since the connection stability between the gold in the AuSn segment 331 and the copper in the gold-clad Cu segment 333 is poor, a CuAu segment 332 including both copper and gold is provided between the AuSn segment 331 and the gold-clad Cu segment 333 as a transition segment, which can effectively improve the connection stability of the AuSn segment 331 at both ends of the gold-clad Cu segment 333.

[0071] In the embodiment of the present disclosure, the second electrode 32 includes a gold layer 320 , and the gold layer 320 includes a plurality of nano copper wires 330 .

[0072] Figure 5is a cross-sectional view of an electrode provided in an embodiment of the present disclosure. Figure 5 is a cross-sectional view of the region where the nano copper wire is located in the second electrode, such as Figure 5 As shown, in a cross section perpendicular to the substrate direction, the second electrode includes a Cr layer 334 , a Ti layer 335 , a first Au layer 336 , a gold layer 320 , and a second Au layer 338 stacked in sequence, and the gold layer 320 has nano copper wires 330 therein.

[0073] In the disclosed embodiment, the Cr layer 334 is used to act as an ohmic contact, allowing the nano copper wire 330 to be electrically connected to the gold layer 320. The Ti layer 335 acts as an adhesion, allowing the Cr layer 334 to be reliably connected to the gold layer 320. The first Au layer 336 serves as a substrate for the gold layer 320, and the second Au layer 338 is used to protect the gold layer 320.

[0074] Exemplarily, the thickness of the Cr layer 334 is 10 angstroms to 50 angstroms. For example, the thickness of the Cr layer 334 is 30 angstroms.

[0075] Illustratively, the thickness of the Ti layer 335 is 1000 angstroms to 3000 angstroms. For example, the thickness of the Ti layer 335 is 2000 angstroms.

[0076] Exemplarily, the thickness of the first Au layer 336 is 3000 angstroms to 7000 angstroms. For example, the thickness of the first Au layer 336 is 5000 angstroms.

[0077] Exemplarily, the thickness of the gold layer 320 is 3000 angstroms to 7000 angstroms. For example, the thickness of the gold layer 320 is 5000 angstroms.

[0078] Exemplarily, the thickness of the second Au layer 338 is 2000 angstroms to 5000 angstroms. For example, the thickness of the second Au layer 338 is 3000 angstroms.

[0079] Optionally, the length of the AuSn segment 331 is 2 μm to 5 μm, the length of the CuAu segment 332 is 2 μm to 5 μm, and the length of the gold-clad Cu segment 333 is 5 μm to 15 μm.

[0080] By setting the length of the AuSn segment 331 within the above range, it is possible to avoid the AuSn segment 331 being too short, which would fail to achieve the purpose of welding and fixing the gold-clad Cu segment 333 and the gold layer 320; it is also possible to avoid the AuSn segment 331 being too long, which would increase the manufacturing cost.

[0081] By setting the length of the CuAu segment 332 within the above range, it can be avoided that the CuAu segment 332 is set too short, which will fail to achieve the purpose of enhancing the connection reliability between the gold-clad Cu segment 333 and the AuSn segment 331; it can also be avoided that the CuAu segment 332 is set too long, which will increase the production cost.

[0082] By setting the length of the gold-clad Cu segment 333 within the above range, it is possible to avoid the gold-clad Cu segment 333 being set too short, which would not reduce the amount of replacement gold used to save costs; it is also possible to avoid the gold-clad Cu segment 333 being set too long, which would significantly reduce the gold content in the electrode and affect the current conduction of the electrode.

[0083] By way of example, the length of the AuSn segment 331 is 2 μm, the length of the CuAu segment 332 is 3 μm, and the length of the gold-clad Cu segment 333 is 10 μm.

[0084] Optionally, in the length direction of the CuAu segment 332 , the Cu content in the CuAu segment 332 changes gradually from one end to the other, and the content at one end close to the gold-clad Cu segment 333 is greater than the content at the other end.

[0085] In the disclosed embodiment, the Cu content in the CuAu segment 332 near the AuSn segment 331 is relatively low, which can make the connection between the CuAu segment 332 and the AuSn segment 331 more stable; the Cu content in the CuAu segment 332 near the gold-clad Cu segment 333 is relatively high, which can make the connection between the CuAu segment 332 and the gold-clad Cu segment 333 more stable.

[0086] The copper content may refer to: the mass percentage of Cu in the CuAu segment 332 .

[0087] Figure 6 3 is a graph showing the relationship between the Cu content and the distance between each position in the CuAu segment 332 and the AuSn segment 331 provided by an embodiment of the present disclosure. Figure 6 As shown, the CuAu segment 332 includes three Cu content intervals. In the first interval of the CuAu segment 332, the distance between each position in the CuAu segment 332 and the AuSn segment 331 is relatively close. At this time, the Cu content of each position in the CuAu segment 332 can be 20%; in the second interval of the CuAu segment 332, the distance between each position in the CuAu segment 332 and the AuSn segment 331 is moderate. At this time, the Cu content of each position in the CuAu segment 332 can be 50%; in the third interval of the CuAu segment 332, the distance between each position in the CuAu segment 332 and the AuSn segment 331 is relatively far. At this time, the Cu content of each position in the CuAu segment 332 can be 100%. In this way, the CuAu segment 332 can play a good role in transition connection, effectively improving the connection stability of the AuSn segments 331 at both ends of the gold-clad Cu segment 333.

[0088] Figure 7 is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure. Figure 2 The light emitting diode shown. Figure 7 As shown, the preparation method comprises:

[0089] S11: providing a substrate 10.

[0090] S12 : forming an epitaxial layer 20 on the substrate 10 .

[0091] The epitaxial layer 20 has a groove 24 exposing the first semiconductor layer 21 .

[0092] S13 : forming a first electrode 31 and a second electrode 32 on the epitaxial layer 20 .

[0093] The first electrode 31 is located in the groove 24 and connected to the first semiconductor layer 21 , and the second electrode 32 is located on the surface of the second semiconductor layer 23 ; at least one of the first electrode 31 and the second electrode 32 includes a gold layer 320 and a plurality of nano copper wires 330 located in the gold layer 320 .

[0094] The light-emitting diode prepared by this preparation method includes an epitaxial layer 20 stacked on a substrate 10, and the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence. The second electrode 32 is located on the second semiconductor layer 23, and the epitaxial layer 20 has a groove 24 exposing the first semiconductor layer 21. The first electrode 31 is located in the groove 24 and is connected to the first semiconductor layer 21, so that the light-emitting diode can emit light by energizing the two electrodes. Among them, at least one of the first electrode 31 and the second electrode 32 includes a gold layer 320 and a plurality of nano copper wires 330 embedded in the gold layer 320. Compared with using the gold layer 320 as an electrode, a part of the electrode is set as the nano copper wire 330, so that by setting the nano copper wire 330 to replace part of the gold, the amount of gold used in making the electrode can be reduced, and the nano copper wire 330 also has good conductivity, so that the current expansion performance of the light-emitting diode is guaranteed, and the amount of gold used in making the electrode is saved, thereby reducing the production cost of the light-emitting diode.

[0095] In step S11, the substrate 10 is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0096] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0097] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0098] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0099] Growing the epitaxial layer 20 on the substrate 10 in step S12 may include: sequentially forming a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 on a sapphire substrate by MOCVD technology.

[0100] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0101] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0102] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0103] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0104] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

[0105] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0106] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0107] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0108] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0109] After the epitaxial layer 20 is formed in step S12 , the preparation method further includes: etching the second semiconductor layer 23 to form a groove 24 exposing the second semiconductor layer 23 .

[0110] Before step S13 , the preparation method further includes: forming a current blocking layer 42 on the second semiconductor layer 23 .

[0111] The current blocking layer 42 is located on the surface of the second semiconductor layer 23 .

[0112] By providing the current blocking layer 42 between the transparent conductive layer 41 and the second semiconductor layer 23 , current transmission can be blocked, thereby preventing the current from directly extending to the second semiconductor layer 23 after flowing out of the electrode.

[0113] After forming the current blocking layer 42, the preparation method further includes the following two steps:

[0114] In the first step, a transparent conductive layer 41 is formed on the second semiconductor layer 23 .

[0115] Exemplarily, the transparent conductive layer 41 may be an indium tin oxide (ITO) film layer.

[0116] The thickness of the transparent conductive layer 41 may be 800 angstroms to 1200 angstroms.

[0117] In the second step, laser irradiation is performed on the area of ​​the transparent conductive layer 41 corresponding to the location of the nano copper wire 330 .

[0118] During laser irradiation, the laser power is 0.1w and the laser irradiation time is 1ms.

[0119] Since the gold layer 320 is filled with nano-copper wires 330, the conduction of current is weakened to a certain extent. By performing laser irradiation on the area of ​​the transparent conductive layer 41 corresponding to the location of the nano-copper wires 330, the current conduction effect of the area can be improved, thereby compensating for the current conduction performance of the gold layer 320 that is weakened due to the replacement of the gold layer 320 by the nano-copper wires 330.

[0120] Step S13 may include: manufacturing the second electrode 32 on the surface of the transparent conductive layer 41 , and manufacturing the first electrode 31 on the surface of the first semiconductor layer 21 in the groove 24 .

[0121] The second electrode 32 has gold as a main component, and the first electrode 31 is deposited with gold as a base material.

[0122] The second electrode 32 includes an electrode block 321 and an electrode strip 322 . One end of the electrode strip 322 is connected to the electrode block 321 . The nano copper wire 330 is located in the electrode strip 322 .

[0123] In the disclosed embodiment, multiple nano copper wires 330 are embedded in the electrode strips 322 at intervals, which can significantly reduce the amount of gold used in making electrodes. The nano copper wires 330 also have good conductivity, which also ensures the current expansion performance of the light-emitting diode.

[0124] Optionally, the diameter of the nano copper wire 330 is 30 nm to 70 nm. Exemplarily, the diameter of the nano copper wire 330 is 50 nm.

[0125] Among them, the nano copper wire 330 includes two AuSn segments 331, two CuAu segments 332 and a gold-coated Cu segment 333. The two CuAu segments 332 are respectively located at the two ends of the gold-coated Cu segment 333 and are connected to the gold-coated Cu segment 333. The two AuSn segments 331 are respectively located at the two ends of the gold-coated Cu segment 333, and the two AuSn segments 331 are respectively connected to the two CuAu segments 332.

[0126] In a cross section perpendicular to the substrate direction, the first electrode 31 or the second electrode 32 includes a Cr layer 334, a Ti layer 335, a first Au layer 336, a gold layer 320, and a second Au layer 338 stacked in sequence. The gold layer 320 has nano copper wires 330 therein.

[0127] In the embodiment of the present disclosure, the process of preparing the second electrode may include:

[0128] First, a gold electrode is formed on the surface of the transparent conductive layer.

[0129] Then, in the area on the gold electrode corresponding to the electrode strip, a sorting device is used to arrange multiple sections of nano copper wires on the surface of the gold electrode in the required arrangement.

[0130] Next, the nano copper wire is heated so that the AuSn segments at both ends of the nano copper wire are heated and welded to the gold electrodes.

[0131] Finally, a layer of gold film is plated on the surface of the gold electrode and the nano copper wire to form a plurality of nano copper wires embedded in the gold layer, thereby obtaining a second electrode.

[0132] In the cross section perpendicular to the substrate, the second electrode includes a Cr layer, a Ti layer, a first Au layer, a gold layer and a second Au layer stacked in sequence, and the gold layer 320 has nano copper wires 330 in it.

[0133] In the above preparation process, the nano copper wire is prepared separately and then combined with the gold electrode to prepare the second electrode. The process of the nano copper wire may include:

[0134] First, a first Au film, a Cu layer, and a second Au film are deposited in sequence to form a gold-coated Cu film.

[0135] Then, a mask plate is formed on the surface of the gold-coated Cu film to cover the gold-coated Cu film, and CuAu films are deposited on both sides of the gold-coated Cu film.

[0136] Next, a mask plate is formed on the surface of the CuAu film and the gold-coated Cu film to cover the gold-coated Cu film and the CuAu film, and an AuSn film is formed on one side of the two CuAu films to obtain a nano copper film.

[0137] Finally, the mask is removed, a photoresist layer is formed on the surface of the nano copper film, and the nano copper film is etched to form multiple line segments to obtain multiple copper nanowires.

[0138] After step S13 , the preparation method further includes: forming a passivation layer 43 on the surface of the transparent conductive layer 41 , the surface of the second electrode 32 , the surface of the second semiconductor layer 23 , the surface of the first semiconductor layer 21 and the surface of the first electrode 31 .

[0139] The passivation layer 43 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0140] After the passivation layer 43 is formed, two through holes need to be formed by etching on the surface of the passivation layer 43 .

[0141] like Figure 2 As shown, one of the through holes exposes the second electrode 32 , and the other through hole exposes the first electrode 31 .

[0142] After two through holes are formed by etching on the passivation layer 43 , a first soldering point block and a second soldering point block may be formed on the surface of the passivation layer 43 .

[0143] The first soldering point block is connected to the second electrode 32 through a through hole, and the second soldering point block is connected to the first electrode 31 through another through hole.

[0144] After step S13 , the process may further include: thinning the sapphire substrate to a thickness of 80 μm, and forming a reflective layer 44 on a surface of the sapphire substrate away from the epitaxial layer 20 .

[0145] For example, the reflective layer 44 may be a distributed Bragg reflector, abbreviated as a DBR layer, which includes a plurality of periodically alternately stacked SiO 2 Layer and TiO 2 The number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0146] Among them, SiO in the DBR layer 2 The thickness of the layer can be 800 angstroms to 1200 angstroms, TiO 2 The layer thickness may be 500 angstroms to 900 angstroms.

[0147] Finally, the sapphire substrate can be cut and scratched by invisible cutting, which can effectively reduce the loss of brightness. Then, the light-emitting diode is obtained by testing.

[0148] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: a substrate (10), an epitaxial layer (20), a first electrode (31) and a second electrode (32); The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) which are sequentially stacked on the substrate (10); the epitaxial layer (20) has a groove (24) exposing the first semiconductor layer (21); the first electrode (31) is located in the groove (24) and connected to the first semiconductor layer (21); and the second electrode (32) is located on the surface of the second semiconductor layer (23); At least one of the first electrode (31) and the second electrode (32) includes a gold layer (320) and a plurality of nano copper wires (330) located in the gold layer (320).

2. The light emitting diode according to claim 1, characterized in that: The nano copper wire (330) comprises two AuSn segments (331), two CuAu segments (332) and a gold-coated Cu segment (333); the two CuAu segments (332) are respectively located at two ends of the gold-coated Cu segment (333) and are connected to the gold-coated Cu segment (333); the two AuSn segments (331) are respectively located at two ends of the gold-coated Cu segment (333), and the two AuSn segments (331) are respectively connected to the two CuAu segments (332).

3. The light emitting diode according to claim 2, characterized in that: In a cross section perpendicular to the substrate (10), the first electrode (31) or the second electrode (32) comprises a Cr layer (334), a Ti layer (335), a first Au layer (336), the gold layer (320) and a second Au layer (338) stacked in sequence, and the nano copper wire (330) is contained in the gold layer (320).

4. The light emitting diode according to claim 3, characterized in that: The thickness of the Cr layer (334) is 10 angstroms to 50 angstroms, the thickness of the Ti layer (335) is 1000 angstroms to 3000 angstroms, the thickness of the first Au layer (336) is 3000 angstroms to 7000 angstroms, the thickness of the gold layer (320) is 3000 angstroms to 7000 angstroms, and the thickness of the second Au layer (338) is 2000 angstroms to 5000 angstroms.

5. The light emitting diode according to claim 2, characterized in that: The length of the AuSn segment (331) is 2 μm to 5 μm, the length of the CuAu segment (332) is 2 μm to 5 μm, and the length of the gold-coated Cu segment (333) is 5 μm to 15 μm.

6. The light emitting diode according to claim 2, characterized in that: In the length direction of the CuAu segment (332), the Cu content in the CuAu segment (332) changes gradually from one end to the other, and the content at one end close to the gold-coated Cu segment (333) is greater than that at the other end.

7. The light emitting diode according to any one of claims 1 to 6, characterized in that: The second electrode (32) comprises an electrode block (321) and an electrode strip (322), one end of the electrode strip (322) is connected to the electrode block (321), and the nano copper wire (330) is located in the electrode strip (322).

8. The light emitting diode according to claim 7, characterized in that: A plurality of the nano copper wires (330) are distributed in parallel and at intervals, and the nano copper wires (330) extend along the length direction of the electrode strips (322).

9. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, and the epitaxial layer has a groove exposing the first semiconductor layer; A first electrode and a second electrode are fabricated on the epitaxial layer, wherein the first electrode is located in the groove and connected to the first semiconductor layer, and the second electrode is located on the surface of the second semiconductor layer; at least one of the first electrode and the second electrode comprises a gold layer and a plurality of nano copper wires located in the gold layer.

10. The preparation method according to claim 9, characterized in that: Before forming the first electrode and the second electrode on the epitaxial layer, the method comprises: forming a transparent conductive layer on the second semiconductor layer; The region of the transparent conductive layer corresponding to the nano copper wire is irradiated with laser.

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