Comparator, chip and electronic device

Abstract

The present application relates to the technical field of integrated circuits, and discloses a comparator, a chip and an electronic device, wherein the comparator comprises a latch circuit and a calibration circuit, the latch circuit comprises a first pull-down unit and a second pull-down unit, and the calibration circuit comprises: a first calibration unit, the first calibration unit comprises a first switch tube and a first calibration tube connected in series, and the first switch tube and the first calibration tube are connected in parallel with the first pull-down unit; a second calibration unit, the second calibration unit comprises a second switch tube and a second calibration tube connected in series, and the second switch tube and the second calibration tube are connected in parallel with the second pull-down unit; and an adjusting unit, the adjusting unit is used for adjusting the control voltage of the first calibration tube and the second calibration tube to adjust the pull-down capability of the first pull-down unit and the second pull-down unit, and then adjusting the input offset voltage of the comparator. The comparator can improve the offset voltage adjusting range and the comparison accuracy, and the circuit is simple and conducive to integration.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a comparator, chip, and electronic device. Background Technology

[0002] In recent years, with the development of integrated circuit technology, analog-to-digital converters (ADCs) have been widely used in the biomedical field, especially in neuroscience, MRI, and X-ray imaging, greatly promoting the advancement of biomedical technology and facilitating the intelligentization and miniaturization of biomedical systems. The comparator is the core component of the ADC, and its speed, accuracy, input offset voltage, and power consumption directly affect the overall performance of the ADC. The input offset voltage of the comparator is mainly caused by factors such as process errors, resulting in dimensional deviations in the symmetrically positioned MOS transistors inside, such as input pairs and latch input pairs. The input offset voltage of the comparator severely affects the accuracy of the ADC; the larger the input offset voltage, the lower the accuracy of the comparator. Therefore, how to reduce the input offset voltage of the comparator is an urgent problem to be solved.

[0003] In related technologies, charge pump technology is mostly used to calibrate the input offset voltage. Its basic structure is as follows: Figure 1 As shown. During calibration, the gate voltage V_CALIP of calibration transistor M1 is fixed, and the voltage of the upper plate of capacitor C0 is used as the gate voltage V_CALIN of calibration transistor M2, with an initial value of 0. A short pulse signal is generated based on the comparison result of the comparator. This pulse signal is used to open switch S1 or S2, thereby charging and discharging the upper plate of capacitor C0 until it reaches a stable state. This changes the gate voltage V_CALIN of calibration transistor M2, thus achieving the calibration of the comparator.

[0004] The drawback of the aforementioned technologies is that they require a large capacitor for charge storage and release, which increases the area of ​​the comparator and is not conducive to on-chip integration. Summary of the Invention

[0005] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, the first objective of this invention is to provide a comparator that achieves comparator calibration by connecting a calibration unit in parallel at each of the two pull-down units of the latch circuit, and adjusting the control voltage of the calibration transistor in the calibration unit through an adjustment unit to regulate the pull-down capability of the pull-down units, thereby adjusting the input offset voltage of the comparator. This results in a simple circuit structure, eliminates the need for additional external capacitors, facilitates on-chip integration, and provides a wide calibration range.

[0006] The second objective of this invention is to provide a chip.

[0007] The third objective of this invention is to provide an electronic device.

[0008] To achieve the above objectives, a first aspect of the present invention provides a comparator, comprising: a latch circuit and a calibration circuit. The latch circuit includes a first pull-down unit and a second pull-down unit. The first pull-down unit is used to pull down a first differential output signal of the comparator according to a second differential output signal of the comparator. The second pull-down unit is used to pull down a second differential output signal according to the first differential output signal. The calibration circuit includes: a first calibration unit, comprising a first switching transistor and a first calibration transistor connected in series, the first switching transistor and the first calibration transistor being connected in series and then in parallel with the first pull-down unit; a second calibration unit, comprising a second switching transistor and a second calibration transistor connected in series, the second switching transistor and the second calibration transistor being connected in series and then in parallel with the second pull-down unit; and an adjustment unit, the adjustment unit being connected to the control terminals of the first calibration transistor and the second calibration transistor respectively. The adjustment unit is used to adjust the control voltages of the first calibration transistor and the second calibration transistor to adjust the pull-down capability of the first pull-down unit and the second pull-down unit, thereby adjusting the input offset voltage of the comparator.

[0009] According to the comparator of the present invention, a calibration unit is connected in parallel at each of the two pull-down units of the latch circuit, and the pull-down capability of the pull-down unit is adjusted by adjusting the control voltage of the calibration tube in the calibration unit through the adjustment unit, thereby adjusting the input offset voltage of the comparator, thus realizing the calibration of the comparator. The circuit structure is simple, no additional off-chip capacitors are required, which is conducive to on-chip integration, and the calibration range is wide.

[0010] According to one embodiment of the present invention, the first pull-down unit includes a third switch transistor, the first end of which is connected to the first pull-down node of the latch circuit, the second end of which is grounded, and the control terminal of which is connected to the second differential output terminal of the comparator; the second pull-down unit includes a fourth switch transistor, the first end of which is connected to the second pull-down node of the latch circuit, the second end of which is grounded, and the control terminal of which is connected to the first differential output terminal of the comparator.

[0011] According to one embodiment of the present invention, the comparator further includes a pre-amplifier circuit, and the latch circuit further includes: a first input unit connected to a second output terminal, a first differential output terminal, and a first pull-down node of the pre-amplifier circuit, the first input unit being used to turn on the first differential output terminal and the first pull-down node according to a second output signal of the pre-amplifier circuit; and a second input unit connected to a first output terminal, a second differential output terminal, and a second pull-down node of the pre-amplifier circuit, the second input unit being used to turn on the second differential output terminal and the second pull-down node according to a first output signal of the pre-amplifier circuit.

[0012] According to one embodiment of the present invention, the first input unit includes a fifth switch transistor, the first end of which is connected to a first differential output terminal, the second end of which is connected to a first pull-down node, and the control terminal of which is connected to the second output terminal of the pre-amplifier circuit; the second input unit includes a sixth switch transistor, the first end of which is connected to a second differential output terminal, the second end of which is connected to a second pull-down node, and the control terminal of which is connected to the first output terminal of the pre-amplifier circuit.

[0013] According to one embodiment of the present invention, the latching circuit further includes a first pull-up unit and a second pull-up unit, wherein the first pull-up unit is used to pull up the first differential output signal according to the second differential output signal, and the second pull-up unit is used to pull up the second differential output signal according to the first differential output signal.

[0014] According to one embodiment of the present invention, the first pull-up unit includes a seventh switch transistor, the first end of which is connected to a preset power supply, the second end of which is connected to a first differential output terminal of a comparator, and the control terminal of which is connected to a second differential output terminal of the comparator; the second pull-up unit includes an eighth switch transistor, the first end of which is connected to a preset power supply, the second end of which is connected to a second differential output terminal, and the control terminal of which is connected to a first differential output terminal.

[0015] According to one embodiment of the present invention, the latch circuit further includes: a first reset unit, which is connected to a first clock signal terminal and a first pull-down node, and is used to reset the first pull-down node according to the first clock signal; and a second reset unit, which is connected to the first clock signal terminal and the second pull-down node, and is used to reset the second pull-down node according to the first clock signal.

[0016] According to one embodiment of the present invention, the first reset unit includes a ninth switch transistor, the first end of which is connected to a first pull-down node, the second end of which is grounded, and the control terminal of which is connected to a first clock signal terminal; the second reset unit includes a tenth switch transistor, the first end of which is connected to a second pull-down node, the second end of which is grounded, and the control terminal of which is connected to the first clock signal terminal.

[0017] According to one embodiment of the present invention, the latch circuit further includes: a third reset unit, which is connected to the second clock signal terminal and the first differential output terminal of the comparator, and is used to reset the first differential output terminal according to the second clock signal; and a fourth reset unit, which is connected to the second clock signal terminal and the second differential output terminal of the comparator, and is used to reset the second differential output terminal according to the second clock signal.

[0018] According to one embodiment of the present invention, the third reset unit includes an eleventh switch, the first terminal of which is connected to a preset power supply, the second terminal of which is connected to a first differential output terminal, and the control terminal of which is connected to a second clock signal terminal; the fourth reset unit includes a twelfth switch, the first terminal of which is connected to a preset power supply, the second terminal of which is connected to a second differential output terminal, and the control terminal of which is connected to a second clock signal terminal.

[0019] According to one embodiment of the present invention, the pre-amplification circuit includes a pre-amplification unit, which is connected to the first differential input terminal and the second differential input terminal of the comparator, the latch circuit and the first clock signal terminal. The pre-amplification unit is used to pre-amplify the first differential input signal and the second differential input signal according to the first clock signal.

[0020] According to one embodiment of the present invention, the pre-amplification unit includes: a thirteenth switch, the first terminal of which is connected to a preset power supply, and the control terminal of which is connected to a first clock signal terminal; a fourteenth switch, the first terminal of which is connected to the second terminal of which is connected to the thirteenth switch, and the control terminal of which is connected to a first differential input terminal; a fifteenth switch, the first terminal of which is connected to the second terminal of which is connected to the thirteenth switch, and the control terminal of which is connected to a second differential input terminal; a sixteenth switch, the first terminal of which is connected to the second terminal of which is connected to the fourteenth switch, and the connection point serves as the second output terminal of the pre-amplification circuit, the second terminal of which is grounded, and the control terminal of which is connected to the first clock signal terminal; and a seventeenth switch, the first terminal of which is connected to the second terminal of which is connected to the fifteenth switch, and the connection point serves as the first output terminal of the pre-amplification circuit, the second terminal of which is grounded, and the control terminal of which is connected to the first clock signal terminal.

[0021] According to one embodiment of the present invention, the pre-amplification circuit includes an inverter connected to a first clock signal terminal, which is used to invert the first clock signal to obtain a second clock signal.

[0022] According to one embodiment of the present invention, the inverter includes an eighteenth switch and a nineteenth switch. The first terminal of the eighteenth switch is connected to a preset power supply, the second terminal of the eighteenth switch is connected to the first terminal of the nineteenth switch, the second terminal of the nineteenth switch is grounded, and the control terminals of the eighteenth and nineteenth switches are both connected to a first clock signal terminal.

[0023] According to one embodiment of the present invention, the first end of the first switching transistor is connected to the first pull-down node, the second end of the first switching transistor is connected to the first end of the first calibration transistor, the second end of the first calibration transistor is grounded, and the control terminal of the first switching transistor is connected to the second differential output terminal; the first end of the second switching transistor is connected to the second pull-down node, the second end of the second switching transistor is connected to the first end of the second calibration transistor, the second end of the second calibration transistor is grounded, and the control terminal of the second switching transistor is connected to the first differential output terminal.

[0024] According to one embodiment of the present invention, the adjustment unit includes: a first voltage divider circuit and a first switching circuit, wherein the first voltage divider circuit is used to divide a first preset voltage to obtain P first voltage divider voltages, and the first switching circuit is connected to the control terminal of the first voltage divider circuit and the first calibration tube, and the first switching circuit is used to input one of the P first voltage divider voltages to the control terminal of the first calibration tube according to a first gating signal, wherein P is an integer greater than 1; a second voltage divider circuit and a second switching circuit, wherein the second voltage divider circuit is used to divide a second preset voltage to obtain N second voltage divider voltages, and the second switching circuit is connected to the control terminal of the second voltage divider circuit and the second calibration tube, and the second switching circuit is used to input one of the N second voltage divider voltages to the control terminal of the second calibration tube according to a second gating signal, wherein N is an integer greater than 1.

[0025] According to one embodiment of the present invention, the values ​​of the P first voltage dividers range from 400mV to 500mV, and the values ​​of the N second voltage dividers range from 0mV to 700mV.

[0026] According to one embodiment of the present invention, the adjustment unit further includes: a first gating generation circuit, which is used to generate a first gating signal based on a first calibration stage control signal, a calibration clock signal, and a first latch signal; and a second gating generation circuit, which is used to generate a second gating signal based on a second calibration stage control signal, a calibration clock signal, and a second latch signal.

[0027] According to one embodiment of the present invention, both the first gating circuit and the second gating circuit are composed of flip-flops and logic gates.

[0028] According to one embodiment of the present invention, the first gating generation circuit and the second gating generation circuit have the same structure. The first gating generation circuit includes: an AND gate, P+1 flip-flops, a first NOT gate, P-1 second NOT gates, and P-1 NOR gates. The three inputs of the AND gate are respectively connected to a first calibration stage control terminal, a calibration clock signal terminal, and a first latch signal terminal. The output of the AND gate is connected to the clock signal terminal of each flip-flop. The inputs and outputs of the P+1 flip-flops are connected in series, with the input of the first flip-flop connected in series connected to a preset power supply, and the input of the P+1 flip-flops connected in series connected to a preset power supply. The output of the inverter is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to the clear terminal of each flip-flop; the inputs of P-1 second NOT gates are connected to the outputs of the first to P-1 flip-flops respectively, and the outputs of P-1 second NOT gates are connected to the first inputs of P-1 NOR gates respectively; the second inputs and outputs of P-1 NOR gates are connected in series, and the second input of the first NOR gate connected in series is connected to the output of the Pth flip-flop. The first strobe signal is output through the output of the Pth flip-flop and the output of each NOR gate.

[0029] According to one embodiment of the present invention, the adjustment unit further includes: a controller, the controller being configured to output a first calibration stage control signal, a second calibration stage control signal, a calibration clock signal, a first latch signal, and a second latch signal, wherein, in the first calibration stage, the controller outputs the second calibration stage control signal and the calibration clock signal to gradually adjust the control voltage of the second calibration transistor until the control voltage of the second calibration transistor is greater than the input offset voltage of the comparator, and outputs the second latch signal to keep the control voltage of the second calibration transistor constant; in the second calibration stage, the controller outputs the first calibration stage control signal and the calibration clock signal to gradually adjust the control voltage of the first calibration transistor until the control voltage of the first calibration transistor is greater than the input offset voltage of the comparator after the first calibration stage, and outputs the first latch signal to keep the control voltage of the first calibration transistor constant.

[0030] According to one embodiment of the present invention, the controller is configured to determine that the control voltage of the second calibration tube is greater than the input offset voltage of the comparator when the second differential output signal of the comparator is detected to be a square wave signal, and to determine that the control voltage of the first calibration tube is greater than the input offset voltage of the comparator after the first calibration stage when the first differential output signal of the comparator is detected to be a square wave signal.

[0031] According to one embodiment of the present invention, the first calibration stage includes N calibration cycles, the second calibration stage includes P calibration cycles, and each calibration cycle includes K first clock signals, where K is an integer greater than 1. The controller is configured to: determine that the control voltage of the second calibration transistor is greater than the input offset voltage of the comparator when the second differential output signal of the comparator is detected to be a square wave signal and the number of square waves in the square wave signal is greater than a preset number; and determine that the control voltage of the first calibration transistor is greater than the input offset voltage of the comparator after the first calibration stage when the first differential output signal of the comparator is detected to be a square wave signal and the number of square waves in the square wave signal is greater than a preset number, where the preset number is half of K rounded down.

[0032] According to one embodiment of the invention, the controller is also configured to calibrate the comparator each time it is powered on.

[0033] According to one embodiment of the present invention, during calibration, the first differential input terminal and the second differential input terminal are shorted together and connected to the common-mode voltage after being shorted together.

[0034] To achieve the above objectives, a second aspect of the present invention provides a chip including the aforementioned comparator.

[0035] According to the chip of the present invention, the comparator is calibrated by connecting a calibration unit in parallel at each of the two pull-down units of the latch circuit, and adjusting the control voltage of the calibration tube in the calibration unit by the adjustment unit to adjust the pull-down capability of the pull-down unit, thereby adjusting the input offset voltage of the comparator. The circuit structure is simple, no additional external capacitors are required, which is beneficial for on-chip integration, and the calibration range is wide.

[0036] To achieve the above objectives, a third aspect of the present invention provides an electronic device including the aforementioned chip.

[0037] According to the electronic device of the present invention, by means of the aforementioned chip, a calibration unit is connected in parallel at each of the two pull-down units of the latch circuit, and the pull-down capability of the pull-down unit is adjusted by adjusting the control voltage of the calibration tube in the calibration unit through the adjustment unit, thereby adjusting the input offset voltage of the comparator, and the calibration of the comparator is realized. The circuit structure is simple, no additional external capacitors are required, which is conducive to on-chip integration, and the calibration range is wide.

[0038] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0039] Figure 1 This is a circuit diagram for the calibration of a comparator in related technologies;

[0040] Figure 2 This is a schematic diagram of a comparator according to an embodiment of the present invention;

[0041] Figure 3 A circuit diagram of a comparator according to an embodiment of the present invention;

[0042] Figure 4 This is a partial circuit diagram of an adjustment unit according to an embodiment of the present invention;

[0043] Figure 5 This is a graph showing the transfer characteristics of the input offset voltage versus the control voltage of the calibration tube according to an embodiment of the present invention.

[0044] Figure 6 This is a schematic diagram of a gating generation circuit according to an embodiment of the present invention;

[0045] Figure 7 A waveform diagram of a gating signal according to an embodiment of the present invention;

[0046] Figure 8 A waveform diagram of each signal during the calibration stage according to an embodiment of the present invention;

[0047] Figure 9 The waveforms of various signals during a calibration cycle according to an embodiment of the present invention are shown.

[0048] Figure 10 This is a waveform diagram of the input mismatch voltage of a comparator before calibration according to an embodiment of the present invention;

[0049] Figure 11 The waveform of the calibrated input mismatch voltage of a comparator according to an embodiment of the present invention is shown.

[0050] Figure 12 This is a schematic diagram of the structure of a chip according to an embodiment of the present invention;

[0051] Figure 13 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0052] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0053] The comparator, chip, and electronic device proposed in the embodiments of the present invention are described below with reference to the accompanying drawings.

[0054] Figure 2This is a schematic diagram of a comparator according to an embodiment of the present invention, with reference to... Figure 2 As shown, the comparator 100 includes a latch circuit 110 and a calibration circuit.

[0055] The latch circuit 110 includes a first pull-down unit 111 and a second pull-down unit 112. The first pull-down unit 111 is used to pull down the first differential output signal VCOMP_P of the comparator 100 according to the second differential output signal VCOMP_N of the comparator 100. The second pull-down unit 112 is used to pull down the second differential output signal VCOMP_N according to the first differential output signal VCOMP_P. The calibration circuit includes a first calibration unit 121, a second calibration unit 122, and an adjustment unit 123. The first calibration unit 121 includes a first switch transistor M1 and a first calibration transistor Q1 connected in series. The first switch transistor M1 and the first calibration transistor Q1 are connected in series and then in parallel with the first pull-down unit 111. The second calibration unit 122 includes a second switch transistor M2 and a second calibration transistor Q2 connected in series. The second switch transistor M2 and the second calibration transistor Q2 are connected in series and then in parallel with the second pull-down unit 112. The adjustment unit 123 is connected to the control terminals of the first calibration transistor Q1 and the second calibration transistor Q2 respectively. The adjustment unit 123 is used to adjust the control voltage of the first calibration transistor Q1 and the second calibration transistor Q2 to adjust the pull-down capability of the first pull-down unit 111 and the second pull-down unit 112, thereby adjusting the input offset voltage of the comparator 100.

[0056] Specifically, when comparator 100 is operating, latch circuit 110 compares the first differential input signal and the second differential input signal of comparator 100, and outputs a first differential output signal VCOMP_P and a second differential output signal VCOMP_N. The comparison result of the first differential input signal and the second differential input signal can be obtained based on the first differential output signal VCOMP_P and the second differential output signal VCOMP_N. When the amplitude difference between the first differential signal VCOMP_P and the second differential signal VCOMP_N of comparator 100 is small, due to factors such as manufacturing process errors, comparator 100 has an input offset voltage, causing errors in the first differential output signal VCOMP_P and the second differential output signal VCOMP_N, severely affecting the comparison accuracy of comparator 100. Therefore, it is necessary to reduce this input offset voltage.

[0057] Based on this, in an embodiment of the invention, a first calibration unit 121 is connected in parallel at the first pull-down unit 111 of the latch circuit 110. The first calibration unit 121 is composed of a first switching transistor M1 and a first calibration transistor Q1 connected in series. A second calibration unit 122 is connected in parallel at the second pull-down unit 112. The second calibration unit 122 is composed of a second switching transistor M2 and a second calibration transistor Q2 connected in series. At the same time, the gate voltages of the first calibration transistor Q1 and the second calibration transistor Q2 are controlled by the adjustment unit 123 so that a portion of the offset voltage is offset by the first calibration transistor Q1 and the second calibration transistor Q2, so that the comparator 100 outputs the correct first differential output signal VCOMP_P and the correct second differential output signal VCOMP_N. Since the first pull-down unit 111 pulls down the first differential output signal VCOMP_P according to the second differential output signal VCOMP_N, its pull-down capability is proportional to the second differential output signal VCOMP_N. That is, the larger the second differential output signal VCOMP_N is, the stronger the pull-down capability of the first pull-down unit 111 is. Therefore, when the level of the second differential output signal VCOMP_N changes, the pull-down capability of the first pull-down unit 111 can be adjusted. Similarly, since the second pull-down unit 112 pulls down the second differential output signal VCOMP_N according to the first differential output signal VCOMP_P, its pull-down capability is proportional to the first differential output signal VCOMP_P. That is, the larger the first differential output signal VCOMP_P is, the stronger the pull-down capability of the second pull-down unit 112 is. Therefore, when the level of the first differential output signal VCOMP_P changes, the pull-down capability of the second pull-down unit 112 can be adjusted. The adjustment unit 123 controls the gate voltage of the first calibration tube Q1 and the second calibration tube Q2, so that the pull-down capability of the first pull-down unit 111 and the second pull-down unit 112 is different. This cancels the offset voltage caused by process errors and other factors in the circuit, thereby reducing the input offset voltage of the comparator 100. This reduces the influence of the component material and size of the comparator 100 on the comparison result, improves the comparison accuracy, and this method is not limited by the conversion voltage ratio, and has a wide range of adjustment for the input offset voltage.

[0058] In the above embodiments, by connecting a calibration unit in parallel at each of the two pull-down units of the latch circuit, and adjusting the control voltage of the calibration tube in the calibration unit by the adjustment unit to adjust the pull-down capability of the pull-down unit, the input offset voltage of the comparator is adjusted, thereby achieving the calibration of the comparator. The circuit structure is simple, no additional off-chip capacitors are required, which is beneficial for on-chip integration, and the calibration range is wide.

[0059] In some embodiments, reference Figure 3As shown, the first pull-down unit 111 includes a third switch M3. The first terminal of the third switch M3 is connected to the first pull-down node J1 of the latch circuit 110, the second terminal of the third switch M3 is grounded to GND, and the control terminal of the third switch M3 is connected to the second differential output terminal COMP_N of the comparator 100. The second pull-down unit 112 includes a fourth switch M4. The first terminal of the fourth switch M4 is connected to the second pull-down node J2 of the latch circuit 110, the second terminal of the fourth switch M4 is grounded to GND, and the control terminal of the fourth switch M4 is connected to the first differential output terminal COMP_P of the comparator 100. Optionally, both the third switch M3 and the fourth switch M4 can be PMOS transistors, etc.

[0060] Furthermore, the first terminal of the first switching transistor M1 is connected to the first pull-down node J1, the second terminal of the first switching transistor M1 is connected to the first terminal of the first calibration transistor Q1, the second terminal of the first calibration transistor Q1 is grounded to GND, and the control terminal of the first switching transistor M1 is connected to the second differential output terminal COMP_N; the first terminal of the second switching transistor M2 is connected to the second pull-down node J2, the second terminal of the second switching transistor M2 is connected to the first terminal of the second calibration transistor Q2, the second terminal of the second calibration transistor Q2 is grounded to GND, and the control terminal of the second switching transistor M2 is connected to the first differential output terminal COMP_P. Optionally, the first switching transistor M1, the second switching transistor M2, the first calibration transistor Q1, and the second calibration transistor Q2 can all be PMOS transistors, etc.

[0061] Furthermore, the comparator 100 also includes a pre-amplifier circuit 130, and the latch circuit 110 further includes a first input unit 113 and a second input unit 114. The first input unit 113 is connected to the second output terminal DIN, the first differential output terminal COMP_P, and the first pull-down node J1 of the pre-amplifier circuit 130. The first input unit 113 is used to turn on the first differential output terminal COMP_P and the first pull-down node J1 according to the second output signal VDIN (i.e., the signal of the second output terminal DIN of the pre-amplifier circuit 130). The second input unit 114 is connected to the first output terminal DIP, the second differential output terminal COMP_N, and the second pull-down node J2 of the pre-amplifier circuit 130. The second input unit 114 is used to turn on the second differential output terminal COMP_N and the second pull-down node J2 according to the first output signal VDIP (i.e., the signal of the first output terminal DIP of the pre-amplifier circuit 130).

[0062] Optionally, the first input unit 113 includes a fifth switch M5, the first terminal of which is connected to the first differential output terminal COMP_P, the second terminal of which is connected to the first pull-down node J1, and the control terminal of which is connected to the second output terminal DIN of the pre-amplifier circuit 130; the second input unit 114 includes a sixth switch M6, the first terminal of which is connected to the second differential output terminal COMP_N, the second terminal of which is connected to the second pull-down node J2, and the control terminal of which is connected to the first output terminal DIP of the pre-amplifier circuit 130. Optionally, both the fifth switch M5 and the sixth switch M6 can be PMOS transistors, etc.

[0063] Furthermore, the latch circuit 110 also includes a first pull-up unit 115 and a second pull-up unit 116. The first pull-up unit 115 is used to pull up the first differential output signal VCOMP_P (i.e., the signal of the first differential output terminal COMP_P) according to the second differential output signal VCOMP_N (i.e., the signal of the second differential output terminal COMP_N). The second pull-up unit 116 is used to pull up the second differential output signal VCOMP_N according to the first differential output signal VCOMP_P.

[0064] Optionally, the first pull-up unit 115 includes a seventh switch M7, the first terminal of which is connected to a preset power supply VDD, the second terminal of which is connected to the first differential output terminal COMP_P of the comparator 100, and the control terminal of which is connected to the second differential output terminal COMP_N of the comparator 100; the second pull-up unit 116 includes an eighth switch M8, the first terminal of which is connected to the preset power supply VDD, the second terminal of which is connected to the second differential output terminal COMP_N, and the control terminal of which is connected to the first differential output terminal COMP_P. Optionally, both the seventh switch M7 and the eighth switch M8 can be NMOS transistors, etc.

[0065] refer to Figure 3 As shown, when comparator 100 is working, in the initial state, the first differential output signal VCOMP_P (i.e., the signal of the first differential output terminal COMP_P) and the second differential output signal VCOMP_N (i.e., the signal of the second differential output terminal COMP_N) are both at a high level. Under the action of the first differential output signal VCOMP_P, the fourth switch M4 and the eighth switch M8 are turned on. Under the action of the second differential output signal VCOMP_N, the third switch M3 and the seventh switch M7 are turned on.

[0066] When the first output signal VDIP of the pre-amplifier circuit 130 is greater than the second output signal VDIN, the conduction capability of the sixth switch M6 is greater than that of the fifth switch M5. The falling rate of the second differential output signal VCOMP_N is greater than that of the first differential output signal VCOMP_P, causing the level of the first differential output signal VCOMP_P to be greater than that of the second differential output signal VCOMP_N. This, in turn, causes the conduction capability of the seventh switch M7 to be greater than that of the eighth switch M8, further increasing the level of the first differential output signal VCOMP_P. This increase in the level of the first differential output signal VCOMP_P increases the conduction capability of the fourth switch M4, thus decreasing the level of the second differential output signal VCOMP_N. This constitutes positive feedback, ultimately resulting in the level of the first differential output signal VCOMP_P being VDD and the level of the second differential output signal VCOMP_N being 0. Due to the presence of positive feedback, the entire comparison process is completed quickly.

[0067] Similarly, when the first output signal VDIP of the preamplifier circuit 130 is less than the second output signal VDIN, the level of the first differential output signal VCOMP_P will eventually be 0, and the level of the second differential output signal VCOMP_N will be VDD.

[0068] Ideally, the switching transistors in comparator 100 that are symmetrically positioned, such as the input pair of transistors (the fifth switching transistor M5 and the sixth switching transistor M6) in latch circuit 110, should be identical in size. When there is no signal input, the level of the first differential output signal VCOMP_P should be the same as the level of the second differential output signal VCOMP_N. However, due to factors such as process errors, the dimensions of the switching transistors in symmetrical positions may deviate, causing the levels of the first differential output signal VCOMP_P and the second differential output signal VCOMP_N to be different. Therefore, comparator 100 needs to be calibrated. For example, a first switch M1 and a first calibration transistor Q1 are connected in parallel between the first and second terminals of the third switch M3, and a second switch M2 and a second calibration transistor Q2 are connected in parallel between the first and second terminals of the fourth switch M4. The pull-down capability of the third switch M3 and the fourth switch M4 is adjusted by adjusting the control voltage of the first calibration transistor Q1 and the second calibration transistor Q2, thereby making the level of the first differential output signal VCOMP_P basically the same as the level of the second differential output signal VCOMP_N.

[0069] Specifically, in the initial state, both the first differential output signal VCOMP_P and the second differential output signal VCOMP_N are at a high level. Under the action of the first differential output signal VCOMP_P, the fourth switch M4, the second switch M2 and the eighth switch M8 are turned on. Under the action of the second differential output signal VCOMP_N, the third switch M3, the first switch M1 and the seventh switch M7 are turned on. Assuming there is no size deviation between the symmetrically positioned switching transistors in the pre-amplifier circuit 130, then the first output signal VDIP and the second output signal VDIN of the pre-amplifier circuit 130 are the same. Assuming there is a size deviation between the input pair transistors of the latch circuit 110, namely the fifth switching transistor M5 and the sixth switching transistor M6, then the conduction capabilities of the fifth switching transistor M5 and the sixth switching transistor M6 are different. Assuming the conduction capability of the fifth switching transistor M5 is greater than that of the sixth switching transistor M6, even if the first output signal VDIP and the second output signal VDIN are the same or slightly smaller than the second output signal VDIN, the falling rate of the first differential output signal VCOMP_P will be greater than the falling rate of the second differential output signal VCOMP_N. This will cause the level of the second differential output signal VCOMP_N to be greater than the level of the first differential output signal VCOMP_P, thus causing an error in the comparison result.

[0070] Under the above assumptions, without calibrating comparator 100, the conduction capability of the fifth switch M5 is greater than that of the sixth switch M6, and the conduction capability of the eighth switch M8 is greater than that of the seventh switch M7. This causes the level of the second differential output signal VCOMP_N to become larger. The increase in the level of the second differential output signal VCOMP_N increases the conduction capability of the third switch M3, thereby causing the level of the first differential output signal VCOMP_P to become smaller. Ultimately, the first differential output signal VCOMP_P stabilizes at a low level, and the second differential output signal VCOMP_N stabilizes at a high level, making the final comparison result inconsistent with the actual result. During comparator 100 calibration, the control voltages of the first calibration transistor Q1 and the second calibration transistor Q2 are adjusted by the adjustment unit 123, thereby adjusting the conduction capability of the first calibration transistor Q1 and the second calibration transistor Q2. This changes the falling rate of the first differential output signal VCOMP_P and the second differential output signal VCOMP_N, thus changing the levels of the first differential output signal VCOMP_P and the second differential output signal VCOMP_N. This alters the conduction capability of the third switch transistor M3 and the fourth switch transistor M4, i.e., changes their pull-down capability. Ultimately, this makes the levels of the first differential output signal VCOMP_P and the second differential output signal VCOMP_N essentially the same, thereby reducing the input offset voltage and avoiding the phenomenon of incorrect comparison results caused by offset voltage due to differences in the size of the switching transistors.

[0071] Therefore, by connecting two series-connected switching transistors and a calibration transistor in parallel at the pull-down pair (i.e., the third and fourth switching transistors) of the latching circuit, and adjusting the control voltage of the calibration transistor to adjust the conduction capability of the pull-down pair (i.e., the third and fourth switching transistors), the input offset voltage of the comparator can be greatly reduced.

[0072] In some embodiments, continue to refer to Figure 3 As shown, the latch circuit 110 further includes a first reset unit 117 and a second reset unit 118. The first reset unit 117 is connected to the first clock signal terminal CLK and the first pull-down node J1, and is used to reset the first pull-down node J1 according to the first clock signal CLK (i.e., the signal of the first clock signal terminal CLK, which can be represented by CLK). The second reset unit 118 is connected to the first clock signal terminal CLK and the second pull-down node J2, and is used to reset the second pull-down node J2 according to the first clock signal CLK.

[0073] Optionally, the first reset unit 117 includes a ninth switch M9, the first terminal of which is connected to the first pull-down node J1, the second terminal of which is grounded to GND, and the control terminal of which is connected to the first clock signal terminal CLK; the second reset unit 118 includes a tenth switch M10, the first terminal of which is connected to the second pull-down node J2, the second terminal of which is grounded to GND, and the control terminal of which is connected to the first clock signal terminal CLK. Optionally, both the ninth switch M9 and the tenth switch M10 can be PMOS transistors, etc.

[0074] In some embodiments, the latch circuit 110 further includes a third reset unit 119 and a fourth reset unit 1110. The third reset unit 119 is connected to the second clock signal terminal CLKB and the first differential output terminal COMP_P of the comparator 100. The third reset unit 119 is used to reset the first differential output terminal COMP_P according to the second clock signal CLKB (i.e., the signal of the second clock signal terminal CLKB, which can be represented by CLKB, and this signal is opposite to the first clock signal CLK). The fourth reset unit 1110 is connected to the second clock signal terminal CLKB and the second differential output terminal COMP_N of the comparator 100. The fourth reset unit 1110 is used to reset the second differential output terminal COMP_N according to the second clock signal CLKB.

[0075] Optionally, the third reset unit 119 includes an eleventh switch M11, the first terminal of which is connected to a preset power supply VDD, the second terminal of which is connected to a first differential output terminal COMP_P, and the control terminal of which is connected to a second clock signal terminal CLKB; the fourth reset unit 1110 includes a twelfth switch M12, the first terminal of which is connected to a preset power supply VDD, the second terminal of which is connected to a second differential output terminal COMP_N, and the control terminal of which is connected to a second clock signal terminal COMP_N. Optionally, both the eleventh switch M11 and the twelfth switch M12 can be NMOS transistors, etc.

[0076] Specifically, a reset operation is required before comparator 100 compares the first differential input signal and the second differential input signal. (Reference) Figure 3 As shown, during reset, the first clock signal CLK is set to high, turning on both the ninth and tenth switches M9 and M10, and resetting the first and second pull-down nodes J1 and J2 to low. Since the second clock signal CLKB is opposite to the first clock signal CLK, it is set to low, turning on both the eleventh and twelfth switches M11 and M12, and resetting the first differential output COMP_P and the second differential output COMP_N to high. This is to facilitate subsequent comparison of the first and second differential input signals.

[0077] Therefore, multiple reset units can be used to reset the first pull-down node, the second pull-down node, the first differential output terminal, and the second differential output terminal, so as to facilitate the comparison operation of the comparator in the future.

[0078] In some embodiments, continue to refer to Figure 3 As shown, the pre-amplification circuit 130 includes a pre-amplification unit 131, which is connected to the first differential input terminal INP and the second differential input terminal INN of the comparator 100, the latch circuit 110 and the first clock signal terminal CLK. The pre-amplification unit 131 is used to pre-amplify the first differential input signal VINP and the second differential input signal VINN according to the first clock signal CLK.

[0079] Optionally, the pre-amplification unit 131 includes: a thirteenth switch M13, a fourteenth switch M14, a fifteenth switch M15, a sixteenth switch M16, and a seventeenth switch M17. Among them, the first terminal of the thirteenth switch M13 is connected to the preset power supply VDD, and the control terminal of the thirteenth switch M13 is connected to the first clock signal terminal CLK; the first terminal of the fourteenth switch M14 is connected to the second terminal of the thirteenth switch M13, and the control terminal of the fourteenth switch M14 is connected to the first differential input terminal INP; the first terminal of the fifteenth switch M15 is connected to the second terminal of the thirteenth switch M13, and the control terminal of the fifteenth switch M15 is connected to the second differential input terminal INN; the first terminal of the sixteenth switch M16 is connected to the second terminal of the fourteenth switch M14, and the connection point serves as the second output terminal DIN of the pre-amplifier circuit 130; the second terminal of the sixteenth switch M16 is grounded to GND; and the control terminal of the sixteenth switch M16 is connected to the first clock signal terminal CLK; the first terminal of the seventeenth switch M17 is connected to the second terminal of the fifteenth switch M15, and the connection point serves as the first output terminal DIP of the pre-amplifier circuit; the second terminal of the seventeenth switch M17 is grounded to GND; and the control terminal of the seventeenth switch M17 is connected to the first clock signal terminal CLK. Optionally, the thirteenth switch M13, the fourteenth switch M14 and the fifteenth switch M15 can all be NMOS transistors, and the sixteenth switch M16 and the seventeenth switch M17 can all be PMOS transistors.

[0080] In some embodiments, the pre-amplification circuit 130 includes an inverter 132, which is connected to the first clock signal terminal CLK. The inverter 132 is used to invert the first clock signal CLK to obtain the second clock signal CLKB.

[0081] Optionally, the inverter 132 includes an eighteenth switch M18 and a nineteenth switch M19. The first terminal of the eighteenth switch M18 is connected to a preset power supply VDD, and the second terminal of the eighteenth switch M18 is connected to the first terminal of the nineteenth switch M19. The second terminal of the nineteenth switch M19 is grounded to GND. The control terminals of both the eighteenth switch M18 and the nineteenth switch M19 are connected to the first clock signal terminal CLK. Optionally, the eighteenth switch M18 can be an NMOS transistor, etc., and the nineteenth switch M19 can be a PMOS transistor, etc.

[0082] refer to Figure 3As shown, when comparator 100 is operating, during the reset phase, the first clock signal CLK is high, the nineteenth switch M19 is turned on, and the second clock signal CLKB is low. Under the action of the first clock signal CLK, the sixteenth switch M16 and the seventeenth switch M17 are turned on, the first output signal VDIP and the second output signal VDIN of the preamplifier circuit 130 are both low, and the fifth switch M5 and the sixth switch M6 are both turned off, so no signal comparison is performed. At the same time, the ninth switch M9 and the tenth switch M10 are both turned on, and the first pull-down node J1 and the second pull-down node J2 are both low to reset the first pull-down node J1 and the second pull-down node J2. Under the action of the second clock signal CLKB, the eleventh switch M11 and the twelfth switch M12 are both turned on, and the first differential output terminal COMP_P and the second differential output terminal COMP_N are both high to reset the first differential output terminal COMP_P and the second differential output terminal COMP_N.

[0083] During the comparison phase, the first clock signal CLK is low, the eighteenth switch M18 is turned on, and the second clock signal CLKB is high. Under the action of the first clock signal CLK, the thirteenth switch M13 is turned on. The first differential input signal VINP and the second differential input signal VINN are input through the fourteenth switch M14 and the fifteenth switch M15, and pre-amplified to output the first output signal VDIP and the second output signal VDIN, which are then input to the latch circuit 110 for comparison. For example, when the first differential input signal VINP is greater than the second differential input signal VINN, the conduction capability of the fifteenth switch M15 is greater than that of the fourteenth switch M14, making the first output signal VDIP greater than the second output signal VDIN. When the first output signal VDIP is greater than the second output signal VDIN, the conduction capability of the sixth switch M6 is greater than that of the fifth switch M5. The falling rate of the second differential output signal VCOMP_N is greater than that of the first differential output signal VCOMP_P, causing the level of the first differential output signal VCOMP_P to be greater than that of the second differential output signal VCOMP_N. This, in turn, causes the conduction capability of the seventh switch M7 to be greater than that of the eighth switch M8, further increasing the level of the first differential output signal VCOMP_P. This increase in the level of the first differential output signal VCOMP_P increases the conduction capability of the fourth switch M4, thus decreasing the level of the second differential output signal VCOMP_N. This constitutes positive feedback, ultimately resulting in the level of the first differential output signal VCOMP_P being VDD and the level of the second differential output signal VCOMP_N being 0. Due to the presence of positive feedback, the entire comparison process is completed quickly.

[0084] Similarly, when the first differential input signal VINP is less than the second differential input signal VINN, the level of the first differential output signal VCOMP_P will eventually be 0, and the level of the second differential output signal VCOMP_N will be VDD.

[0085] Therefore, the comparator can compare differential input signals, and the comparator can be calibrated by controlling the calibration tube in the calibration unit through the adjustment unit, thus ensuring the comparator's comparison accuracy.

[0086] In some embodiments, reference Figure 4 As shown, the adjustment unit 123 includes a first voltage divider circuit 1231 and a first switching circuit 1232. The first voltage divider circuit 1231 is used to divide the first preset voltage to obtain P first voltage dividers, denoted as V_P. <0> ~V_P <p-1>The first switching circuit 1232 is connected to the control terminal of the first voltage divider circuit 1231 and the first calibration tube Q1. The first switching circuit 1232 is used to input one of the P first voltage divider voltages to the control terminal of the first calibration tube Q1 according to the first strobe signal SHFT_P, where P is an integer greater than 1.

[0087] Furthermore, the adjustment unit 123 also includes: a second voltage divider circuit 1233 and a second switching circuit 1234. The second voltage divider circuit 1233 is used to divide the second preset voltage to obtain N second voltage dividers, denoted as V_N. <0> ~V_N <n-1>The second switching circuit 1234 is connected to the control terminal of the second voltage divider circuit 1233 and the second calibration tube Q2. The second switching circuit 1234 is used to input one of the N second voltage divider voltages into the control terminal of the second calibration tube Q2 according to the second strobe signal SHFT_N, where N is an integer greater than 1.

[0088] Specifically, refer to Figure 4 As shown, the first voltage divider circuit 1231 and the second voltage divider circuit 1233 can be composed of a resistor array, the first switch circuit 1232 and the second switch circuit 1234 can be composed of a switch array, and the voltages of the first voltage divider circuit 1231 and the second voltage divider circuit 1233 can be selected by the corresponding switch circuits and used as the control voltage of the corresponding calibration tube.

[0089] More specifically, the first voltage divider circuit 1231 can be constructed by connecting P+1 voltage divider resistors in series between the first preset power supply VDD1 and the reference ground VSS. The first preset voltage is the voltage difference between the voltage provided by the first preset power supply VDD1 and the reference ground VSS. Based on the voltage divider principle, a voltage, namely the first voltage divider voltage, can be obtained between every two adjacent voltage divider resistors, denoted as V_P. <0> ~V_P <p-1>The first switching circuit 1232 can be composed of P TG gates (transmission gates). Whether it is turned on or off is controlled by the first strobe signal SHFT_P and its opposite signal SHFT_P_M. At any given time, only one of the P TG gates is turned on, thereby providing the first voltage divider voltage V_P corresponding to the turned-on TG gate to the first calibration tube Q1 to adjust the control voltage V_CALIP of the first calibration tube Q1, and thus adjust the pull-down capability of the first pull-down unit 111.

[0090] It should be noted that the second voltage divider circuit 1233 is similar to the first voltage divider circuit 1231, and the second switching circuit 1234 is similar to the first switching circuit 1232. See the attached reference for details. Figure 4 As shown, I will not go into details here.

[0091] In some embodiments, P first voltage divider voltages V_P <0> ~V_P <p-1>The value range is 400mV to 500mV, and there are N second voltage divider voltages V_N. <0> ~V_N <n-1>The range is 0mV to 700mV.

[0092] Specifically, refer to Figure 5 As shown, according to the curve of the input offset voltage of comparator 100 changing with the control voltage of the calibration tube, when the first voltage divider voltage V_P is 450mV and the second voltage divider voltage V_N varies between 300mV and 600mV, the input offset voltage is quite sensitive to changes. By setting a certain margin, the first voltage divider voltage V_P can be controlled. <0> ~V_P <p-1>The value range is set to 400mV~500mV, and the second voltage divider voltage V_N is... <0> ~V_N <n-1>The value range is set to 0mV to 700mV to achieve rapid and accurate adjustment of the input offset voltage. Further, as a specific example, P can be set to 11, with P first voltage divider voltages V_P. <0> ~V_P <p-1>The voltage values ​​are: 400mV, 410mV, 420mV, 430mV, 440mV, 450mV, 460mV, 470mV, 480mV, 490mV, and 500mV, respectively; N is set to 15, representing N second voltage divider voltages V_N. <0> ~V_N <n-1>The values ​​are: 0mV, 50mV, 100mV, 150mV, 200mV, 250mV, 300mV, 350mV, 400mV, 450mV, 500mV, 550mV, 600mV, 650mV, and 700mV.

[0093] In some embodiments, reference Figure 6 As shown, the adjustment unit 123 further includes a first gating generation circuit 1235 and a second gating generation circuit 1236. The first gating generation circuit 1235 generates a first gating signal SHFT_P based on the first calibration stage control signal CALI_PERI_B, the calibration clock signal CLK_CALI, and the first latch signal LATCH_P. The second gating generation circuit 1236 generates a second gating signal SHFT_N based on the second calibration stage control signal CALI_PERI, the calibration clock signal CLK_CALI, and the second latch signal LATCH_N. The second calibration stage control signal CALI_PERI is the opposite of the first calibration stage control signal CALI_PERI_B.

[0094] Specifically, as described above, the P TG gates in the first switching circuit 1232 and the N TG gates in the second switching circuit 1234 all need to be selected for operation. Therefore, a first selection generation circuit 1235 and a second selection generation circuit 1236 need to be set accordingly. The first selection generation circuit 1235 and the second selection generation circuit 1236 generate selection signals based on the first calibration stage control signal CALI_PERI_B, the second calibration stage control signal CALI_PERI, the calibration clock signal CLK_CALI, the first latch signal LATCH_P, and the second latch signal LATCH_N to select from the P first voltage divider voltages V_P. <0> ~V_P <p-1>and N second voltage divider voltages V_N <0> ~V_N <n-1>One of them is selected as the control voltage V_CALIP of the first calibration tube Q1 and the control voltage V_CALIN of the second calibration tube Q2.

[0095] It should be noted that the first calibration stage control signal CALI_PERI_B and the second calibration control signal CALI_PERI are used to switch the calibration of the first calibration transistor Q1 or the second calibration transistor Q2. For example, when the first calibration stage control signal CALI_PERI_B is high and the second calibration control signal CALI_PERI is low, the first calibration transistor Q1 is calibrated, that is, the control voltage of the first calibration transistor Q1 is adjusted to reduce the input offset voltage; when the first calibration stage control signal CALI_PERI_B is low and the second calibration control signal CALI_PERI is high, the second calibration transistor Q2 is calibrated, that is, the control voltage of the second calibration transistor Q2 is adjusted to reduce the input offset voltage.

[0096] The calibration clock signal CLK_CALI is used to control calibration. For example, calibration can start on the rising edge of the calibration clock signal CLK_CALI and stop on the falling edge of the calibration clock signal CLK_CALI.

[0097] The first latch signal LATCH_P is used to latch the calibration result of the first calibration transistor Q1. For example, when calibrating the first calibration transistor Q1, the first latch signal LATCH_P can be set to a high level. When the control voltage V_CALIP of the first calibration transistor Q1 is adjusted to a suitable level, the first latch signal LATCH_P is set to a low level to stop the calibration of the first calibration transistor Q1 and keep the current control voltage V_CALIP of the first calibration transistor Q1 unchanged. The second latch signal LATCH_N works on a similar principle to the first latch signal LATCH_P, and will not be described in detail here.

[0098] Therefore, by setting up a gating generation circuit, a gating signal is generated based on the calibration stage control signal, calibration clock signal, and latch signal to adjust the control voltage of the first calibration transistor and the second calibration transistor, thereby achieving calibration of the first calibration transistor and the second calibration transistor and reducing the input offset voltage.

[0099] In some embodiments, both the first gating circuit 1235 and the second gating circuit 1236 are composed of flip-flops and logic gates. Optionally, the first gating circuit 1235 and the second gating circuit 1236 have the same structure.

[0100] refer to Figure 6 As shown, the first gating generation circuit 1235 includes: an AND gate, P+1 flip-flops TR1 to TRP+1, a first NOT gate NOT1, P-1 second NOT gates (for simplicity, only one second NOT gate NOT2 is used in the figure), and P-1 NOR gates NOR. <1> ~NOR <p-1>The three inputs of the AND gate are connected to the first calibration stage control terminal CALI_PERI_B, the calibration clock signal terminal CLK_CALI, and the first latch signal terminal LATCH_P, respectively (it should be noted that for ease of understanding, the port numbers and corresponding signals are the same). The output terminal CLKP of the AND gate is connected to the clock signal terminal CLK of each flip-flop TR1 to TRP+1. The input terminals D and output terminals Q of P+1 flip-flops TR1 to TRP+1 are connected in series, and the input terminal D of the first flip-flop TR1 is connected to the preset power supply VDD. The output terminal Q of the P+1th flip-flop TRP+1 is connected to the input terminal of the first NOT gate NOT1, and the output terminal of the first NOT gate NOT1 is connected to the clear terminal CLR of each flip-flop TR1 to TRP+1. The input terminals of P-1 second NOT gates NOT2 are connected to the output terminals Q of the first flip-flop TR1 to the P-1th flip-flop TRP-1, respectively. The output terminals of P-1 second NOT gates NOT2 are connected to P-1 NOR gates NOR gates. <1> ~NOR <p-1>The first input terminals are connected accordingly; P-1 NOR gates <1> ~NOR <p-1>The second input and output terminals are connected in series, for example, the first NOR gate. <1> The second input terminal is connected to the second NOR gate. <2> Connect the output of the second NOR gate to the output of the second NOR gate. <2> The second input terminal is connected to the third NOR gate. <3> The outputs of the gates are connected together, and so on, with the (P-1)th NOR gate connected in series. <p-1>The second input terminal is connected to the output terminal Q of the Pth flip-flop TRP, where each NOR gate... <1> ~NOR <p-1>The output of the first strobe signal SHFT_P is output from the output terminal of the Pth flip-flop TRP. This first strobe signal comprises P signals, namely SHFT_P... <0> ~SHFT_P <p-1>NOR gate <1> ~NOR <p-1>The output terminal outputs the first to the (P-1)th first strobe signals SHFT_P <0> ~SHFT_P <p-2>The output of the Pth flip-flop TRP outputs the Pth first strobe signal SHFT_P. <p-1>.

[0101] Specifically, refer to Figure 6 As shown, P+1 flip-flops TR1 to TRP+1 can be D flip-flops, meaning that the level of the input D before the rising edge of the clock signal CLK is latched to the output Q, and this latch continues until the next rising edge of the clock signal. According to the AND gate, when the first calibration stage control signal CALI_PERI_B, the calibration clock signal CLK_CALI, and the first latch signal LATCH_P are all high, the clock signal CLK of P+1 flip-flops TR1 to TRP+1 is also high, and all P+1 flip-flops TR1 to TRP+1 are triggered. Since P+1 flip-flops TR1 to TRP+1 are connected in series, and the input D of the first flip-flop TR1 is connected to the preset power supply VDD, the output Q of the first flip-flop TR1 is high, while the output Q of the second flip-flop TR2 to the P+1th flip-flop TRP+1 is low. Based on the second NOT gate NOT2 and P-1 NOR gates NOR... <1> ~NOR <p-1>It can be seen that the first strobe signal SHFT_P <0> The first strobe signal is at a high level, while all other first strobe signals are at a low level.

[0102] When the calibration clock signal CLK_CALI goes high again, the clock signal terminals CLK of the P+1 flip-flops TR1 to TRP+1 are all high, and all P+1 flip-flops TR1 to TRP+1 are triggered. At this time, the output terminals Q of the first flip-flop TR1 and the second flip-flop TR2 are both high, while the output terminals Q of the third flip-flop TR3 to the P+1th flip-flop TRP+1 are all low. This is based on the second NOT gate NOT2 and P-1 NOR gates NOR. <1> ~NOR <p-1>It can be seen that the first strobe signal SHFT_P <1> The first strobe signal is at a high level, while all other first strobe signals are at a low level.

[0103] Following the above process sequentially, we can eventually obtain the following: Figure 7 The first strobe signal shown is SHFT_P <0> ~SHFT_P <p-1>When the output Q of the (P+1)th flip-flop is high, the output of the first NOT gate (NOT1) is low, triggering the clear input of the (P+1)th flip-flop, thus setting the first strobe signal SHFT_P... <0> ~SHFT_P <p-1>All are at a low level, resetting P+1 flip-flops for subsequent use.

[0104] It should be noted that the structure and working principle of the second gating circuit 1236 are the same as those of the first gating circuit 1235, the difference being the quantity setting, which will not be elaborated here.

[0105] Additionally, it should be noted that, Figure 7 CALI_CTL is a calibration control signal used to control the calibration of comparator 100. For example, when the calibration control signal CALI_CTL is high, the calibration of comparator 100 begins, and when the calibration control signal CALI_CTL is low, the calibration ends.

[0106] In some embodiments, the adjustment unit 123 further includes a controller, which is configured to output a first calibration stage control signal CALI_PERI_B, a second calibration stage control signal CALI_PERI, a calibration clock signal CLK_CALI, a first latch signal LATCH_P, and a second latch signal LATCH_N. During the first calibration stage (also known as the coarse adjustment stage), the controller outputs the second calibration stage control signal CALI_PERI and the calibration clock signal CLK_CALI to gradually adjust the control voltage V_CALIN of the second calibration transistor Q2 until the control voltage V_CALIN of the second calibration transistor Q2 is greater than... The input offset voltage of comparator 100 is used to output a second latch signal LATCH_N to keep the control voltage V_CALIN of the second calibration transistor Q2 constant. In the second calibration stage (also known as the fine-tuning stage), the first calibration stage control signal CALI_PERI_B and the calibration clock signal CLK_CALI are output to gradually adjust the control voltage V_CALIP of the first calibration transistor Q1 until the control voltage V_CALIP of the first calibration transistor Q1 is greater than the input offset voltage of comparator 100 after the first calibration stage. Then, the first latch signal LATCH_P is output to keep the control voltage V_CALIP of the first calibration transistor Q1 constant.

[0107] Furthermore, the controller is used to determine that the control voltage V_CALIN of the second calibration tube Q2 is greater than the input offset voltage of the comparator 100 when the second differential output signal VCOMP_N of the comparator 100 is detected as a square wave signal, and to determine that the control voltage V_CALIP of the first calibration tube Q1 is greater than the input offset voltage of the comparator 100 after the first calibration stage when the first differential output signal VCOMP_P of the comparator 100 is detected as a square wave signal.

[0108] Specifically, calibration can be performed each time comparator 100 is powered on. During calibration, the first differential input terminal INP and the second differential input terminal INN are shorted and connected to the common-mode voltage. At this time, the voltage difference between the first differential output signal VCOMP_P and the second differential output signal VCOMP_N is the input offset voltage inside comparator 100. This offset voltage includes the mismatch voltage caused by the size and manufacturing process of each switch in the comparator.

[0109] refer to Figure 8 As shown, the controller can first output a high-level second calibration stage control signal CALI_PERI, and the corresponding first calibration stage control signal CALI_PERI_B is low-level. At this time, the first calibration stage, i.e., the coarse adjustment stage, is entered.

[0110] In the first calibration phase, the controller outputs a calibration clock signal CLK_CALI, which is a periodic square wave signal, and also outputs a high-level second latch signal LATCH_N. At this time, the second strobe generation circuit 1236 generates a second strobe signal SHFT_N based on the calibration clock signal CLK_CALI. <0> ~SHFT_N <14> To obtain from N second voltage divider voltages V_N <0> ~V_N <n-1>In the first calibration stage, a second voltage divider is selected sequentially as the control voltage V_CALIN of the second calibration tube Q2 to adjust its control voltage V_CALIN. For example, when the first voltage divider ranges from 400mV to 500mV, the second voltage divider ranges from 0mV to 700mV, and P is 11 and N is 15, the control voltage V_CALIP of the first calibration tube Q1 can be stabilized at 400mV, and the control voltage V_CALIN of the second calibration tube Q2 can be sequentially adjusted to 0mV, 50mV, 100mV, ..., 700mV to adjust its control voltage V_CALIN.

[0111] When the control voltage V_CALIN of the second calibration transistor Q2 is 0mV, the control voltage V_CALIP of the first calibration transistor Q1 is much greater than that of the second calibration transistor Q2. Therefore, the conduction capability of the branch containing the first calibration transistor Q1 is much greater than that of the branch containing the second calibration transistor Q2. This causes the first differential output signal VCOMP_P to be pulled down to a low level under positive feedback, while the second differential output signal VCOMP_N is pulled up to a high level. At this time, the flag signal FLAG_N is low. Subsequently, as the control voltage V_CALIN of the second calibration transistor Q2 gradually increases, when it exceeds the input offset voltage inside the comparator 100, the second differential output signal VCOMP_N will become a square wave signal. At this time, the flag signal FLAG_N becomes high, and the corresponding second latch signal LATCH_N becomes low. Under the action of the second latch signal LATCH_N... Figure 6 The clock signal terminal CLK of each flip-flop is fixed at a low level, thereby making the second strobe signal SHFT_N <0> ~SHFT_N <14> Maintain the current state, such as Figure 8 As shown, assuming that when the control voltage V_CALIN of the second calibration tube Q2 is 200mV, which is greater than the input offset voltage inside comparator 100, then the second strobe signal SHFT_N <4> The second strobe signal will be kept at a high level, while the other second strobe signals will be kept at a low level. The control voltage V_CALIN of the second calibration tube Q2 will be fixed at 200mV. This completes the calibration of the second calibration tube Q2 and ends the first calibration stage.

[0112] After the first calibration phase ends, the controller outputs a low-level second calibration phase control signal CALI_PERI, while the corresponding first calibration phase control signal CALI_PERI_B goes high. At this point, the second calibration phase, or fine-tuning phase, begins.

[0113] In the second calibration phase, the controller continues to output the calibration clock signal CLK_CALI, which is a periodic square wave signal, and outputs a high-level first latch signal LATCH_P. At this time, the first strobe generation circuit 1235 generates a first strobe signal SHFT_P based on the calibration clock signal CLK_CALI. <0> ~SHFT_P <10> From P first voltage divider voltages V_P <0> ~V_P <p-1>A first voltage divider is selected sequentially as the control voltage V_CALIP of the first calibration transistor Q1 to adjust the control voltage V_CALIP of the first calibration transistor Q1. For example, the control voltage V_CALIP of the first calibration transistor Q1 is adjusted sequentially to 400mV, 410mV, 420mV, ..., 500mV to adjust the control voltage V_CALIP of the first calibration transistor Q1.

[0114] When the control voltage V_CALIP of the first calibration transistor Q1 is 400mV, the control voltage V_CALIN of the second calibration transistor Q2 is 200mV, which is less than the control voltage V_CALIP of the first calibration transistor Q1. Therefore, the conduction capability of the branch containing the first calibration transistor Q1 is greater than that of the branch containing the second calibration transistor Q2. This causes the first differential output signal VCOMP_P to be pulled down to a low level under the action of positive feedback, while the second differential output signal VCOMP_N is pulled up to a high level. At this time, the flag signal FLAG_P is low. Subsequently, as the control voltage V_CALIP of the first calibration transistor Q1 gradually increases, when the control voltage V_CALIP of the first calibration transistor Q1 increases to a level greater than the input offset voltage inside the comparator 100 after the first calibration stage, the first differential output signal VCOMP_P will become a square wave signal. At this time, the flag signal FLAG_P becomes high, and the corresponding first latch signal LATCH_P becomes low. Under the action of the first latch signal LATCH_P... Figure 6 The clock signal terminal CLK of each flip-flop is fixed at a low level, thereby making the first strobe signal SHFT_P <0> ~SHFT_P <10> Maintain the current state, such as Figure 8 As shown, assuming that when the control voltage V_CALIP of the first calibration tube Q1 is 430mV, which is greater than the input offset voltage inside the comparator 100 after the first calibration stage, then the first strobe signal SHFT_P <3> The first strobe signal will be kept at a high level, while the other first strobe signals will be kept at a low level. The control voltage V_CALIP of the first calibration tube Q1 will be fixed at 430mV. This completes the calibration of the first calibration tube Q1 and ends the second calibration stage.

[0115] Therefore, the comparator is calibrated by adjusting the control voltage of the first and second calibration transistors. The circuit structure is simple, no additional external capacitors are required, which is beneficial for on-chip integration, and the calibration range is wide.

[0116] Furthermore, the first calibration phase includes N calibration cycles, and the second calibration phase includes P calibration cycles, such as... Figure 8 As shown, the first calibration phase includes 15 calibration cycles, and the second calibration phase includes 11 calibration cycles. Each calibration cycle includes K first clock signals CLK, meaning that K calibrations are performed within each calibration cycle, where K is an integer greater than 1. The controller is further configured to: determine that the control voltage V_CALIN of the second calibration transistor Q2 is greater than the input offset voltage of the comparator 100 when the second differential output signal VCOMP_N of the comparator 100 is detected as a square wave signal and the number of square waves in the square wave signal is greater than a preset number; and determine that the control voltage V_CALIP of the first calibration transistor Q1 is greater than the input offset voltage of the comparator 100 after the first calibration phase when the first differential output signal VCOMP_P of the comparator 100 is detected as a square wave signal and the number of square waves in the square wave signal is greater than a preset number, where the preset number is half of K rounded down.

[0117] It should be noted that, since noise interference may occur at the differential input of comparator 100 during the calibration process, multiple calibrations can be performed in each calibration cycle, and the comparison results can be counted. Only when a certain result appears more than half the time can the result be confirmed as the comparison result of the current calibration cycle, so as to improve the accuracy of calibration.

[0118] Specifically, since the control voltages of the first calibration tube Q1 and the second calibration tube Q2 are different, and there is mismatch in various parts of the comparator 100, when the first differential input signal and the second differential input signal of the comparator 100 are the same, one of the first differential output signal VCOMP_P and the second differential output signal VCOMP_N must always be at a high level.

[0119] refer to Figure 9 As shown, assuming the second differential output signal VCOMP_N is always high, then for the first differential output signal VCOMP_P, it is high when the first clock signal CLK is high and low when the first clock signal CLK is low. That is, the first differential output signal VCOMP_P is a square wave signal with the same characteristics as the first clock signal CLK. If counters CNT4_P and CNT4_N are used to record the comparison results—specifically, counter CNT4_P records the number of square waves in the first differential output signal VCOMP_P within a calibration cycle, and counter CNT4_N records the number of square waves in the second differential output signal VCOMP_N within a calibration cycle—then, since the first differential output signal VCOMP_P is a square wave, counter CNT4_P counts. When the count reaches a preset number (assuming 16 comparisons are performed within a calibration cycle, i.e., K is 16, this preset number can be 8), it indicates that the first differential output signal VCOMP_P is low. At this time, a high-level flag signal FLAG_P is output, and counters CNT4_P and CNT4_N are reset. Therefore, even if input noise causes the comparator 100 to err, as long as the number of occurrences is less than a certain number, the output flag signal FLAG_P will not be erroneous, thus greatly reducing the impact of input noise on the calibration results.

[0120] The principle is the same when the first differential output signal VCOMP_P is always high, so it will not be repeated here.

[0121] Furthermore, in combination Figure 8 and Figure 9 At the beginning of the first calibration phase, it is assumed that the first differential output signal VCOMP_P is a square wave signal and the second differential output signal VCOMP_N is at a high level. As the control voltage V_CALIN of the second calibration transistor Q2 gradually increases, when the second differential output signal VCOMP_N becomes a square wave signal, it indicates that the second differential output signal VCOMP_N is less than the first differential output signal VCOMP_P. The control voltage V_CALIN of the second calibration transistor Q2 is greater than the input offset voltage inside the comparator 100, thereby achieving the calibration of the second calibration transistor Q2. Similarly, at the start of the second calibration phase, the second differential output signal VCOMP_N is a square wave signal, and the first differential output signal VCOMP_P is high. As the control voltage V_CALIP of the first calibration transistor Q1 gradually increases, when the first differential output signal VCOMP_P becomes a square wave signal, it indicates that the first differential output signal VCOMP_P is less than the second differential output signal VCOMP_N, and the control voltage V_CALIP of the first calibration transistor Q1 is greater than the input offset voltage inside the comparator 100 after the first calibration phase. This achieves the calibration of the first calibration transistor Q1, and consequently, the calibration of the comparator 100. Therefore, during the calibration process, by confirming whether the differential output signal is a square wave signal, it can be determined whether the control voltage of the current calibration transistor is appropriate, making the calibration process simpler. Furthermore, using multiple comparisons to determine the result avoids the influence of input noise on the calibration result.

[0122] To verify the calibration effect, Figure 10 The waveform of the input offset voltage of comparator 100 before calibration is shown. Figure 11 The waveform of the input offset voltage of comparator 100 after calibration is given. Figure 10 and Figure 11 As can be seen, the input mismatch voltage of the comparator 100 using the calibration method of this application is reduced from 3.27mV to 189.88uV, which significantly reduces the input mismatch voltage and effectively improves the comparison accuracy of the comparator 100.

[0123] In summary, the comparator according to the embodiments of the present invention achieves comparator calibration by connecting a calibration unit in parallel at each of the two pull-down units of the latch circuit and adjusting the control voltage of the calibration tube in the calibration unit through the adjustment unit. This greatly reduces the input offset voltage of the comparator, has high calibration accuracy, and can effectively reduce the input offset voltage of the comparator with one calibration each time the comparator is powered on, reducing the number of calibrations and improving the working efficiency of the comparator. Moreover, the circuit structure is simple and low-cost, requiring no additional external capacitors, which is conducive to on-chip integration. It also has a wide calibration range, and by comparing multiple times, the influence of input noise on the calibration results is avoided.

[0124] In some embodiments, a chip is also provided.

[0125] Figure 12 This is a block diagram of a chip according to an embodiment of the present invention, with reference to... Figure 12 As shown, the chip 1000 includes the aforementioned comparator 100.

[0126] According to the chip of the present invention, the comparator is calibrated by connecting a calibration unit in parallel at each of the two pull-down units of the latch circuit and adjusting the control voltage of the calibration tube in the calibration unit through the adjustment unit. This greatly reduces the input offset voltage of the comparator, has high calibration accuracy, and can effectively reduce the input offset voltage of the comparator by calibration once each time the comparator is powered on, reducing the number of calibrations and improving the working efficiency of the comparator. The circuit structure is simple and low-cost, does not require additional external capacitors, is conducive to on-chip integration, and has a wide calibration range. At the same time, by comparing multiple times, the influence of input noise on the calibration results is avoided.

[0127] In some embodiments, an electronic device is also provided.

[0128] Figure 13 This is a block diagram of an electronic device according to an embodiment of the present invention, with reference to... Figure 13 As shown, the electronic device 10000 includes the aforementioned chip 1000.

[0129] According to the electronic device of the present invention, by means of the aforementioned chip, a calibration unit is connected in parallel at each of the two pull-down units of the latch circuit, and the control voltage of the calibration tube in the calibration unit is adjusted by the adjustment unit, thereby realizing the calibration of the comparator. This greatly reduces the input offset voltage of the comparator, has high calibration accuracy, and can effectively reduce the input offset voltage of the comparator by one calibration each time the comparator is powered on, reducing the number of calibrations and improving the working efficiency of the comparator. Moreover, the circuit structure is simple and low-cost, does not require additional external capacitors, is conducive to on-chip integration, and has a wide calibration range. At the same time, by comparing multiple times, the influence of input noise on the calibration results is avoided.

[0130] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0131] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0132] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0133] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0134] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A comparator, characterized in that, include: The system includes a latching circuit and a calibration circuit. The latching circuit includes a first pull-down unit and a second pull-down unit. The first pull-down unit is used to pull down the first differential output signal of the comparator based on the second differential output signal of the comparator. The second pull-down unit is used to pull down the second differential output signal based on the first differential output signal. The calibration circuit includes: The first calibration unit includes a first switching transistor and a first calibration transistor connected in series. The first switching transistor and the first calibration transistor are connected in parallel with the first pull-down unit. The second calibration unit includes a second switch transistor and a second calibration transistor connected in series. The second switch transistor and the second calibration transistor are connected in parallel with the second pull-down unit. An adjustment unit is connected to the control terminals of the first calibration tube and the second calibration tube respectively. The adjustment unit is used to adjust the control voltage of the first calibration tube and the second calibration tube to adjust the pull-down capability of the first pull-down unit and the second pull-down unit, thereby adjusting the input offset voltage of the comparator. The first pull-down unit includes a third switching transistor. The first end of the third switching transistor is connected to the first pull-down node of the latch circuit, the second end of the third switching transistor is grounded, and the control end of the third switching transistor is connected to the second differential output end of the comparator. The second pull-down unit includes a fourth switching transistor. The first end of the fourth switching transistor is connected to the second pull-down node of the latch circuit, the second end of the fourth switching transistor is grounded, and the control end of the fourth switching transistor is connected to the first differential output end of the comparator. The comparator further includes a pre-amplifier circuit, and the latch circuit further includes: The first input unit is connected to the second output terminal, the first differential output terminal, and the first pull-down node of the pre-amplifier circuit. The first input unit is used to turn on the first differential output terminal and the first pull-down node according to the second output signal of the pre-amplifier circuit. The second input unit is connected to the first output terminal, the second differential output terminal, and the second pull-down node of the pre-amplifier circuit. The second input unit is used to turn on the second differential output terminal and the second pull-down node according to the first output signal of the pre-amplifier circuit. The first input unit includes a fifth switch transistor, the first end of which is connected to the first differential output terminal, the second end of which is connected to the first pull-down node, and the control terminal of which is connected to the second output terminal of the pre-amplifier circuit. The second input unit includes a sixth switch transistor. The first end of the sixth switch transistor is connected to the second differential output terminal, the second end of the sixth switch transistor is connected to the second pull-down node, and the control terminal of the sixth switch transistor is connected to the first output terminal of the pre-amplifier circuit.

2. The comparator according to claim 1, characterized in that, The latching circuit further includes a first pull-up unit and a second pull-up unit. The first pull-up unit is used to pull up the first differential output signal according to the second differential output signal, and the second pull-up unit is used to pull up the second differential output signal according to the first differential output signal.

3. The comparator according to claim 2, characterized in that, The first pull-up unit includes a seventh switch transistor. The first end of the seventh switch transistor is connected to a preset power supply, the second end of the seventh switch transistor is connected to the first differential output terminal of the comparator, and the control terminal of the seventh switch transistor is connected to the second differential output terminal of the comparator. The second pull-up unit includes an eighth switch transistor. The first end of the eighth switch transistor is connected to the preset power supply, the second end of the eighth switch transistor is connected to the second differential output terminal, and the control terminal of the eighth switch transistor is connected to the first differential output terminal.

4. The comparator according to claim 1, characterized in that, The latch circuit also includes: A first reset unit is connected to a first clock signal terminal and a first pull-down node. The first reset unit is used to reset the first pull-down node according to the first clock signal. The second reset unit is connected to the first clock signal terminal and the second pull-down node, and is used to reset the second pull-down node according to the first clock signal.

5. The comparator according to claim 4, characterized in that, The first reset unit includes a ninth switch transistor, the first end of which is connected to the first pull-down node, the second end of which is grounded, and the control terminal of which is connected to the first clock signal terminal. The second reset unit includes a tenth switch transistor. The first end of the tenth switch transistor is connected to the second pull-down node, the second end of the tenth switch transistor is grounded, and the control end of the tenth switch transistor is connected to the first clock signal end.

6. The comparator according to claim 2, characterized in that, The latch circuit also includes: The third reset unit is connected to the second clock signal terminal and the first differential output terminal of the comparator. The third reset unit is used to reset the first differential output terminal according to the second clock signal. The fourth reset unit is connected to the second clock signal terminal and the second differential output terminal of the comparator. The fourth reset unit is used to reset the second differential output terminal according to the second clock signal.

7. The comparator according to claim 6, characterized in that, The third reset unit includes an eleventh switch transistor. The first terminal of the eleventh switch transistor is connected to a preset power supply, the second terminal of the eleventh switch transistor is connected to the first differential output terminal, and the control terminal of the eleventh switch transistor is connected to the second clock signal terminal. The fourth reset unit includes a twelfth switch transistor. The first end of the twelfth switch transistor is connected to the preset power supply, the second end of the twelfth switch transistor is connected to the second differential output terminal, and the control terminal of the twelfth switch transistor is connected to the second clock signal terminal.

8. The comparator according to claim 1, characterized in that, The pre-amplification circuit includes a pre-amplification unit, which is connected to the first differential input terminal and the second differential input terminal of the comparator, the latch circuit, and the first clock signal terminal. The pre-amplification unit is used to pre-amplify the first differential input signal and the second differential input signal according to the first clock signal.

9. The comparator according to claim 8, characterized in that, The pre-amplification unit includes: The thirteenth switch has its first terminal connected to a preset power supply and its control terminal connected to the first clock signal terminal. The fourteenth switch is connected to the first terminal of the thirteenth switch, and the control terminal of the fourteenth switch is connected to the first differential input terminal. The fifteenth switch, the first terminal of which is connected to the second terminal of the thirteenth switch, and the control terminal of which is connected to the second differential input terminal; The sixteenth switch has its first terminal connected to the second terminal of the fourteenth switch, and the connection point serves as the second output terminal of the pre-amplifier circuit. The second terminal of the sixteenth switch is grounded, and the control terminal of the sixteenth switch is connected to the first clock signal terminal. The seventeenth switch has its first terminal connected to the second terminal of the fifteenth switch, and the connection point serves as the first output terminal of the pre-amplification circuit. The second terminal of the seventeenth switch is grounded, and the control terminal of the seventeenth switch is connected to the first clock signal terminal.

10. The comparator according to claim 6, characterized in that, The pre-amplification circuit includes an inverter connected to a first clock signal terminal. The inverter is used to invert the first clock signal to obtain the second clock signal.

11. The comparator according to claim 10, characterized in that, The inverter includes an eighteenth switch and a nineteenth switch. The first terminal of the eighteenth switch is connected to a preset power supply, the second terminal of the eighteenth switch is connected to the first terminal of the nineteenth switch, the second terminal of the nineteenth switch is grounded, and the control terminals of the eighteenth and nineteenth switches are both connected to the first clock signal terminal.

12. The comparator according to claim 1, characterized in that, The first terminal of the first switching transistor is connected to the first pull-down node, the second terminal of the first switching transistor is connected to the first terminal of the first calibration transistor, the second terminal of the first calibration transistor is grounded, and the control terminal of the first switching transistor is connected to the second differential output terminal. The first end of the second switch is connected to the second pull-down node, the second end of the second switch is connected to the first end of the second calibration tube, the second end of the second calibration tube is grounded, and the control terminal of the second switch is connected to the first differential output terminal.

13. The comparator according to claim 12, characterized in that, The adjustment unit includes: A first voltage divider circuit and a first switching circuit, wherein the first voltage divider circuit is used to divide a first preset voltage to obtain P first voltage divider voltages, and the first switching circuit is connected to the control terminal of the first voltage divider circuit and the first calibration tube, wherein the first switching circuit is used to input one of the P first voltage divider voltages to the control terminal of the first calibration tube according to a first gating signal, wherein P is an integer greater than 1; The second voltage divider circuit and the second switching circuit are used to divide the second preset voltage to obtain N second voltage dividers. The second switching circuit is connected to the control terminal of the second voltage divider circuit and the second calibration tube. The second switching circuit is used to input one of the N second voltage dividers into the control terminal of the second calibration tube according to the second selection signal, where N is an integer greater than 1.

14. The comparator according to claim 13, characterized in that, The P first voltage dividers range from 400mV to 500mV, and the N second voltage dividers range from 0mV to 700mV.

15. The comparator according to claim 13, characterized in that, The adjustment unit further includes: A first gating generation circuit is used to generate the first gating signal based on a first calibration stage control signal, a calibration clock signal, and a first latch signal. The second gating generation circuit is used to generate the second gating signal based on the second calibration stage control signal, the calibration clock signal, and the second latch signal.

16. The comparator according to claim 15, characterized in that, Both the first gating circuit and the second gating circuit are composed of flip-flops and logic gates.

17. The comparator according to claim 15, characterized in that, The first gating generation circuit and the second gating generation circuit have the same structure. The first gating generation circuit includes: an AND gate, P+1 flip-flops, a first NOT gate, P-1 second NOT gates, and P-1 NOR gates. The three input terminals of the AND gate are respectively connected to the first calibration stage control terminal, the calibration clock signal terminal, and the first latch signal terminal, and the output terminal of the AND gate is connected to the clock signal terminal of each of the flip-flops; The inputs and outputs of P+1 flip-flops are connected in series, with the input of the first flip-flop connected to a preset power supply, the output of the P+1 flip-flop connected to the input of the first NOT gate, and the output of the first NOT gate connected to the reset terminal of each flip-flop. The inputs of P-1 of the second NOT gates are connected to the outputs of the first to P-1 flip-flops, and the outputs of P-1 of the second NOT gates are connected to the first inputs of P-1 of the NOR gates. The second inputs and outputs of P-1 NOR gates are connected in series, and the second input of the first NOR gate in series is connected to the output of the Pth flip-flop. The first strobe signal is output through the output of the Pth flip-flop and the output of each NOR gate.

18. The comparator according to claim 17, characterized in that, The adjustment unit further includes a controller, which is configured to output the first calibration stage control signal, the second calibration stage control signal, the calibration clock signal, the first latch signal, and the second latch signal, wherein... In the first calibration phase, the second calibration phase control signal and the calibration clock signal are output to gradually adjust the control voltage of the second calibration transistor until the control voltage of the second calibration transistor is greater than the input offset voltage of the comparator, and the second latch signal is output to keep the control voltage of the second calibration transistor constant. In the second calibration phase, the first calibration phase control signal and the calibration clock signal are output to gradually adjust the control voltage of the first calibration transistor until the control voltage of the first calibration transistor is greater than the input offset voltage of the comparator after the first calibration phase. The first latch signal is then output to keep the control voltage of the first calibration transistor constant.

19. The comparator according to claim 18, characterized in that, The controller is configured to determine that the control voltage of the second calibration tube is greater than the input offset voltage of the comparator when the second differential output signal of the comparator is detected to be a square wave signal, and to determine that the control voltage of the first calibration tube is greater than the input offset voltage of the comparator after the first calibration stage when the first differential output signal of the comparator is detected to be a square wave signal.

20. The comparator according to claim 18, characterized in that, The first calibration phase includes N calibration cycles, the second calibration phase includes P calibration cycles, and each calibration cycle includes K first clock signals, where K is an integer greater than 1. The controller is used to: When the second differential output signal of the comparator is detected to be a square wave signal and the number of square waves in the square wave signal is greater than a preset number, it is determined that the control voltage of the second calibration tube is greater than the input offset voltage of the comparator. When the first differential output signal of the comparator is detected to be a square wave signal and the number of square waves in the square wave signal is greater than the preset number, it is determined that the control voltage of the first calibration tube is greater than the input offset voltage of the comparator after the first calibration stage, wherein the preset number is half of K rounded down.

21. The comparator according to any one of claims 18-20, characterized in that, The controller is also used to calibrate the comparator each time it is powered on.

22. The comparator according to claim 8, characterized in that, During calibration, the first differential input terminal and the second differential input terminal are shorted together, and then connected to the common-mode voltage.

23. A chip, characterized in that, Includes a comparator according to any one of claims 1-22.

24. An electronic device, characterized in that, Includes the chip according to claim 23.

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