Ramp signal generating circuit

Abstract

The embodiment of the present application provides a kind of ramp signal generation circuit.The ramp signal generation circuit includes: cascade level trigger, it is suitable for receiving first signal, and at least two second signals are sequentially generated under the driving of first signal and its inverse signal;First current steering unit includes at least two first current steering that are sequentially connected in parallel, each first current steering is suitable for sequentially receiving one of at least two second signals and sequentially turning on or off based on the received one second signal, so that the first current steering unit outputs increasing or decreasing current to generate ramp signal.The ramp signal generation circuit provided by the embodiment of the present application can reduce inter-symbol interference, reduce the difficulty of circuit design, reduce the difficulty of circuit timing constraints and reduce the glitch of output signal, so as to improve the quality of image sensor.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a ramp signal generation circuit that can be used in image sensors. Background Technology

[0002] In the process of converting analog signals to digital signals in an image sensor, a ramp signal is required as the comparison level of the comparator.

[0003] In existing technologies, segmented current-controlled digital-to-analog converters are typically used to generate ramp signals to achieve a balance between circuit area, power consumption, and performance. However, an N-bit precision ramp signal requires an N-bit binary input and further decoding of the higher bits from binary to temperature code. This makes the circuit prone to inter-symbol interference, complex decoding circuitry, difficulty in controlling circuit timing, and severe glitches in the ramp output, resulting in unsatisfactory practical performance. Summary of the Invention

[0004] One object of the present invention is to provide an improved ramp signal generation circuit to reduce inter-symbol interference, reduce the difficulty of circuit design, reduce the difficulty of circuit timing constraints, and reduce glitches in the output signal.

[0005] The ramp signal generation circuit provided in this embodiment of the invention includes: a cascaded level trigger, adapted to receive a first signal and sequentially generate at least two second signals under the drive of the first signal and its inverted signal; a first current rudder unit, including at least two first current rudders connected in parallel in sequence, each first current rudder being adapted to sequentially receive one of the at least two second signals and sequentially turn on or off based on the received second signal, so that the first current rudder unit outputs an increasing or decreasing current to generate a ramp signal.

[0006] Optionally, the cascaded level trigger includes at least two cascaded triggers to output at least two second signals respectively, each trigger being adapted to output one of the at least two second signals.

[0007] Optionally, one of two adjacent flip-flops uses the first signal as its clock signal, and the other uses the inverted signal as its clock signal.

[0008] Optionally, the cascaded level trigger includes an inverter adapted to receive a first signal and invert it to output an inverted signal to another.

[0009] Optionally, the trigger in the first stage takes either the power supply level or the ground level as input.

[0010] Optionally, each subsequent flip-flop takes the output of the preceding flip-flop as its input.

[0011] Optionally, the trigger includes a D trigger.

[0012] Optionally, the current weights of each first current rudder are the same.

[0013] Optionally, a second current rudder unit is included in parallel with the first current rudder unit. The second current rudder unit includes at least one second current rudder. Each of the at least one second current rudder is adapted to receive a third signal and to be turned on or off based on the received third signal, so that the second current rudder unit outputs an increasing or decreasing current to generate a ramp signal.

[0014] Optionally, the second current rudder unit includes at least two second current rudders connected in parallel in sequence, wherein each second current rudder has a different current weight.

[0015] Optionally, the current weights of each second current rudder are sequentially weighted in binary order from the least significant bit to the most significant bit.

[0016] Optionally, the first current rudder unit is located in the high position, and the second current rudder unit is located in the low position.

[0017] Compared with the prior art, the technical solutions of the embodiments of the present invention have beneficial effects.

[0018] For example, the ramp signal generation circuit provided in this embodiment of the invention utilizes cascaded level triggers. Only one bit of data input is needed to generate multiple control signals, causing corresponding current sources to sequentially turn on or off from low to high bits, thereby generating a rising or falling ramp signal. This not only reduces inter-symbol interference and helps improve image quality when applied to image sensors, but also avoids complex circuit design, saves space, reduces power consumption, and contributes to cost savings.

[0019] For example, the ramp signal generation circuit provided in the embodiments of the present invention can also be used as a segmented current-rudder type digital-to-analog converter, wherein the first current rudder unit serves as the temperature code unit of the segmented current-rudder type digital-to-analog converter, and the second current rudder unit serves as the binary code unit of the segmented current-rudder type digital-to-analog converter.

[0020] For example, compared to traditional segmented current-rudder type digital-to-analog converters, the ramp signal generation circuit provided in this embodiment of the invention only requires (M+1) bits of data input for ramp signals with N-bit precision (traditional segmented current-rudder type digital-to-analog converters require N bits of data input). This effectively reduces the use of data input lines, reduces inter-symbol interference, thereby saving costs and improving the image quality of the image sensor.

[0021] For example, compared to the traditional segmented current-controlled digital-to-analog converter where the temperature code unit generates the temperature code through a decoding circuit, this embodiment of the invention uses cascaded level triggers to generate the control signal QT. And each control signal QT They all have the same path and delay, which not only simplifies the timing of the control signals of the binary current steering unit (second current steering unit) and the temperature code current steering unit (first current steering unit), but also allows the circuit to operate at a higher clock frequency. At the same time, since decoding is not required, the glitches of the ramp signal can be reduced, thereby improving the image quality of the image sensor. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the ramp signal generation circuit in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a cascaded level trigger in an embodiment of the present invention;

[0024] Figure 3 This is a timing diagram of the ramp signal generation circuit in this embodiment of the invention, where the RST (i.e., RESET) signal is the reset signal of the flip-flops in the cascaded level flip-flops, the clk signal is the clock signal of the ramp signal generation circuit, and Bit... <m-1:0>The signal is the third signal, Bit <m>The signal is the first signal, QT <1> Signals, QT <2> Signals...and QT<2 N-M -1> The signals are respectively the first second signal, the second second signal, ... and the 2nd second signal. N-M -1 is the second signal, Vramp is the ramp voltage signal generated by the ramp signal generation circuit. Detailed Implementation

[0025] To make the objectives, features, and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described below are merely illustrative of the present invention and not intended to limit the scope of the invention.

[0026] Reference Figure 1 This invention provides a ramp signal generation circuit 10.

[0027] Specifically, the ramp signal generation circuit 10 includes a cascaded level trigger 100 and a first current steering unit 200.

[0028] In a specific implementation, the cascaded level trigger 100 is adapted to receive the first signal and, driven by the first signal and its inverted signal, sequentially generate at least two second signals.

[0029] The first current rudder unit 200 includes at least two first current rudders 210 connected in parallel in sequence. Each first current rudder 210 is adapted to receive one of at least two second signals in sequence, and to turn on or off in sequence based on the received second signal, so that the first current rudder unit 200 outputs an increasing or decreasing current to generate a ramp signal.

[0030] In a specific implementation, each first current rudder 210 includes a first current source 211 and a first switch 212. The first switch 212 in each first current rudder 210 is connected to the cascaded level trigger 100 and the first current source 211 in the first current rudder 210, respectively. It is adapted to receive a second signal from the cascaded level trigger 100 and to turn on or off the first current source 211 in the first current rudder 210 based on the received second signal.

[0031] In some embodiments, the ramp signal generating circuit 10 may further include a second current rudder unit 300 connected in parallel with the first current rudder unit 200.

[0032] Specifically, the second current rudder unit 300 includes at least one second current rudder 310. Each of the at least one second current rudder 310 is adapted to receive a third signal and to turn on or off based on the received third signal, so that the second current rudder unit 300 outputs an increasing or decreasing current to generate a ramp signal.

[0033] In a specific implementation, each second current rudder 310 includes a second current source 311 and a second switch 312. The second switch 312 in each second current rudder 310 is adapted to receive a third signal and, based on the received third signal, to turn on or off the second current source 311 in the second current rudder 310.

[0034] In a specific implementation, the ramp signal generating circuit 10 is adapted to receive digital signals and generate ramp signals based on the received digital signals.

[0035] In a specific implementation, the digital signal received by the ramp signal generation circuit 10 can be represented in binary.

[0036] Specifically, the first (i.e., the least significant bit) to the Mth bit of the digital signal received by the ramp signal generation circuit 10 can be represented as Bit. <m:0>Furthermore, the bits in this digital signal <m>As the first signal input, a cascaded level trigger 100 is used, and the Bit in the digital signal is... <m-1:0>The third signal input is used to the second current steering unit 300. Here, M is a positive integer greater than or equal to 1.

[0037] Furthermore, the precision of the ramp signal generation circuit 10 can be expressed as N bits, where N is a positive integer greater than M. Also, the second current rudder unit 300 in the ramp signal generation circuit 10 is positioned below the first current rudder unit 200, and the second current rudder unit 300 includes M second current rudders 310, while the first current rudder unit 200 includes 2... N-M -1 first current rudder 210.

[0038] In some embodiments, M can be a positive integer greater than or equal to 2. In this case, the M second current rudders 310 in the second current rudder unit 300 are connected in parallel sequentially.

[0039] In some embodiments, the current weights of the M second current rudders 310 connected in parallel in sequence can be different, that is, the current weights of the M second current sources 311 among the M second current rudders 310 connected in parallel in sequence can be different.

[0040] In specific implementation, the current weights of the M parallel second current rudders 310 can be sequentially weighted from low to high bits using binary weighting. That is, the current weights of the M second current sources 311 (one second current rudder 310 includes one second current source 311) in the M parallel second current rudders 310 can be sequentially weighted from low to high bits using binary weighting.

[0041] In practical implementation, the current source value of the second current source 311 in the lowest-order second current rudder 310 can be represented as I0. Then, the current source values ​​of the M second current sources 311 in the second current rudder unit 300, in order from the lowest to the highest order, can be represented as 2. 0 I0, 2 1 I0, 2 2 I0……2 M-1 I0.

[0042] In specific implementation, the third signal received sequentially by the M second switches 312 in the second current steering unit 300, according to the order of the second switches 312 from low to high bits, are the bits in the digital signal. <0> Bit <1> Bit <2> ...and Bit <m-1>.

[0043] In practice, the digital signal received by the ramp signal generation circuit 10 is continuous.

[0044] Assume that the second current steering unit 300 includes three second current steering units 310, and that the three second current sources 311 (one second current source 311 per second current steering unit 310) in the order from least significant to most significant are, respectively, the first second current source 311, the second second current source 311, and the third second current source 311. Correspondingly, the three second switches 312 (one second switch 312 per second current steering unit 310) are, respectively, the first second switch 312, the second second switch 312, and the third second second switch 312.

[0045] Based on this, we continue to assume that continuous digital signals are continuously increasing digital signals, and that continuously increasing digital signals can be represented in binary as 1101, 1110, and 1111 in sequence.

[0046] In specific implementation, the last three digits of these digital signals are used as the third signal, that is, the second current steering unit 300 uses the consecutive 101, 110, and 111 as the third signal.

[0047] First, input 101 is used as the third signal. Then, the first, second, and third switches 312 in the second current rudder 310 sequentially receive 1, 0, and 1 as corresponding third signals. Specifically, the first switch 312 turns on the first second current source 311 based on the received third signal 1; the second switch 312 turns off the second second current source 311 based on the received third signal 0; and the third switch 312 turns on the third second current source 311 based on the received third signal 1.

[0048] The current source values ​​of the first second current source 311, the second second current source 311, and the third second current source 311 are 2. 0 I0, 2 1 I0, 2 2 If I0, then the current value output by the second current steering unit 300 based on the third signal 101 is 2. 0 I0+2 2 I0 = 5I0.

[0049] Next, input 110 is used as the third signal, and the first, second, and third switches 312 in the second current rudder 310 sequentially receive 0, 1, and 1 as corresponding third signals. Specifically, the first switch 312 disconnects the first second current source 311 based on the received third signal 0, the second switch 312 turns on the second second current source 311 based on the received third signal 1, and the third switch 312 turns on the third second current source 311 based on the received third signal 1.

[0050] The current source values ​​of the first second current source 311, the second second current source 311, and the third second current source 311 are 2. 0 I0, 2 1 I0, 2 2 If I0, then the current value output by the second current steering unit 300 based on the third signal 110 is 2. 1 I0+2 2 I0 = 6I0.

[0051] Finally, input 111 is used as the third signal, and the first, second, and third second switches 312 in the second current rudder 310 receive 1, 1, and 1 respectively as corresponding third signals. Specifically, the first second switch 312 turns on the first second current source 311 based on the received third signal 1, the second second switch 312 turns on the second second current source 311 based on the received third signal 1, and the third second switch 312 turns on the third second current source 311 based on the received third signal 1.

[0052] The current source values ​​of the first second current source 311, the second second current source 311, and the third second current source 311 are 2. 0 I0, 2 1 I0, 2 2 Therefore, the second current steering unit 300 outputs a current value of 2 based on the third signal 111. 0 I0+2 1 I0+2 2 I0 = 7I0.

[0053] Therefore, when the ramp signal generating circuit 10 receives the continuously increasing digital signal, the second current steering unit 300 can output an increasing current signal based on the continuously increasing digital signal. This increasing current signal is the rising ramp signal output by the second current steering unit 300.

[0054] In other embodiments, the ramp signal generating circuit 10 can also receive continuously decreasing digital signals, and the second current steering unit 300 can output a decreasing current signal based on the continuously decreasing digital signals. The decreasing current signal is the descending ramp signal output by the second current steering unit 300.

[0055] In this embodiment of the invention, the first current steering unit 200 is adapted to output an increasing or decreasing current based on a second signal output by the cascaded level trigger 100 to generate a ramp signal.

[0056] Specifically, the cascaded level flip-flop 100 may include at least two flip-flops cascaded in sequence. The at least two cascaded flip-flops are used to output at least two second signals respectively, and each flip-flop is adapted to output one of the at least two second signals.

[0057] As mentioned earlier, for the ramp signal generation circuit 10 with an accuracy of N bits, its first current steering unit 200 may include 2 N-M -1 first current rudder 210. In each first current rudder 210, a first switch 212 is connected to a cascaded level trigger 100 and a first current source 211 in that first current rudder 210, respectively. It is adapted to receive a second signal from the cascaded level trigger 100 and, based on the received second signal, to turn the first current source 211 in the first current rudder 210 on or off. Thus, the cascaded level trigger 100 needs to sequentially generate 2... under the drive of the first signal and its inverted signal. N-M -1 second signal, to be output to 2 respectively N-M -1 first switch 212. Among them, one first switch 212 is adapted to receive a second signal.

[0058] Reference Figure 2 In this case, the cascaded level trigger 100 may include 2 N-M -1 cascaded flip-flops 110.

[0059] In some embodiments, trigger 110 may include a D trigger.

[0060] In specific implementation, 2 N-M -1 cascaded flip-flops 110 are used to output 2 respectively. N-M -1 second signal, each flip-flop 110 is adapted to output 2 N-M -1 is one of the second signals.

[0061] Specifically, they are cascaded sequentially from front to back (where the first one is the first stage trigger 110, and the last one is the second stage trigger 110). N-M The -1 level flip-flop 110), each flip-flop 110 in the cascaded level flip-flop 100 is adapted to sequentially output the first second signal QT. <1> The second signal QT <2> ...the i-th second signal QT ...and the 2nd N-M -1 second signal QT<2 N-M -1>.

[0062] In a specific implementation, one of the two adjacent flip-flops 110 uses the first signal as its clock signal, and the other uses the inverted signal of the first signal as its clock signal.

[0063] In specific implementation, if the first signal is a high-level signal, then the inverted signal of the first signal is a low-level signal; if the first signal is a low-level signal, then the inverted signal of the first signal is a high-level signal.

[0064] For example, if the first signal is 1, then its inverted signal is 0; or, if the first signal is 0, then its inverted signal is 1.

[0065] As mentioned above, in this embodiment of the invention, the Bit in the digital signal <m>As the first signal input to the cascaded level flip-flop 100. Thus, one of two adjacent flip-flops 110 in the cascaded level flip-flop 100 is activated by the first signal Bit. <m>As a clock signal, the other one is the first signal Bit. <m>The inverted signal is used as the clock signal.

[0066] In a specific implementation, the cascaded level trigger 100 also includes an inverter 120.

[0067] Specifically, the inverter 120 is connected to the odd-numbered or even-numbered flip-flop 110 in the cascaded level flip-flop 100 (i.e., the other of two adjacent flip-flops 110 in the cascaded level flip-flop 100), and is adapted to receive the first signal and output the first signal as an inverted signal of the first signal to the odd-numbered or even-numbered flip-flop 110 (i.e., the other of two adjacent flip-flops 110 in the cascaded level flip-flop 100).

[0068] Reference Figure 2 In some embodiments, the inverter 120 is connected to the even-numbered flip-flop 110 in the cascaded level flip-flop 100, and is adapted to receive a first signal and output the first signal as an inverted signal of the first signal to the even-numbered flip-flop 110.

[0069] In this embodiment of the invention, each flip-flop 110 in the subsequent stage uses the output of the flip-flop 110 in the preceding stage as its input. Furthermore, the flip-flop 110 in the first stage uses either the power supply level VDD or ground level as its input.

[0070] The following is combined Figure 1 and Figure 2 The example shown and its corresponding timing diagram for generating the ramp signal are shown. Figure 3 The second signal output by the cascaded level trigger 100 will be explained.

[0071] Reference Figure 3 In some embodiments, when the reset signal RST of all the flip-flops 110 in the cascaded level flip-flop 100 is a low level signal, each flip-flop 110 in the cascaded level flip-flop 100 sequentially outputs the first second signal QT. <1> The second signal QT <2> ...the i-th second signal QT ...and the 2nd N-M -1 second signal QT<2 N -M -1>all are 0.

[0072] Accordingly, when the reset signal RST of all flip-flops 110 in the cascaded level flip-flop 100 is high, the cascaded level flip-flop 100 starts to work. In this case, all flip-flops 110 in the cascaded level flip-flop 100 are active high-level flip-flops, and the first second signal QT of each flip-flop 110 in the cascaded level flip-flop 100 is output sequentially according to the time sequence. <1> The second signal QT <2> ...the i-th second signal QT ...and the 2nd N-M -1 second signal QT<2 N-M -1> All are 1.

[0073] In practical implementation, the duration of the high-level reset signal RST can be determined according to the specific application scenario. For example, the duration of the high-level reset signal RST can be twice the duration of the clock signal clk of the ramp signal generation circuit 10. N -1 times.

[0074] As mentioned above, in this embodiment of the invention, the Bit in the digital signal received by the ramp signal generation circuit 10 is... <m>As the first signal input, cascade level trigger 100.

[0075] Reference Figure 2 The odd-numbered flip-flop 110 in the cascaded level flip-flop 100 uses the first signal Bit <m>As a clock signal, the even-numbered flip-flop 110 in the cascaded level flip-flop 100 uses the first signal Bit. <m>The inverted signal is used as the clock signal.

[0076] In this embodiment of the invention, by inverting the clocks of two adjacent flip-flops 110 in the cascaded level flip-flop 100, the clock signal of the first signal bit can be adjusted. <m>The second signal can be output on both the rising and falling edges.

[0077] Reference Figure 3 In the first signal Bit <m>When the first toggling edge (rising edge) arrives, the first stage trigger 110 (refer to...) Figure 2 Its input is the power supply level VDD, and its output is the first second signal QT. <1> =1, and the first second signal QT <1> As the input to the second-stage trigger 110, in Bit <m>When the second toggling edge (falling edge) arrives, the second stage flip-flop 110 outputs the second second signal QT. <2> =1; and so on, the (i-1)th second signal QT output by the flip-flop 110 of the (i-1)th stage. <i-1>As the input to the i-th stage flip-flop 110, when Bit <m>When the i-th toggle edge arrives, the i-th stage flip-flop 110 outputs the i-th second signal QT. =1, until the 2nd N-M -1 level trigger 110 output 2nd N-M -1 second signal QT<2 N-M -1>=1.

[0078] In other embodiments, the first signal Bit <m>The first flip edge can also be a falling edge. Accordingly, the first signal bit... <m>The second flip edge can be the rising edge. And so on.

[0079] As mentioned earlier, for the ramp signal generation circuit 10 with an accuracy of N bits, its first current steering unit 200 may include 2 N-M -1 first current rudder 210.

[0080] Reference Figure 1 In some embodiments, 2 N-M The current weights of the first current rudder 210 can be the same, i.e., 2 N-M -1 of the first current rudder 210 N-M -1 The current weights of the first current sources 211 can be the same (a first current rudder 210 includes a first current source 211).

[0081] In practical implementation, 2 N-M The current source values ​​of the first current source 211 are all set to 2. M I0.

[0082] In practice, following the order from lowest to highest digit, 2 can be sequentially... N-M The -1 first current source 211 are respectively represented as the first first current source 211, the second first current source 211, ... the i-th first current source 211, ... and the 2nd first current source 211. N-M -1 position first current source 211.

[0083] Accordingly, following the order from least significant bit to most significant bit, we can sequentially assign the bits that are respectively related to 2. N-M -1 first current source 211 corresponds to 2 N-M -1 The first switches 212 are respectively represented as the first first switch 212, the second first switch 212, ... the i-th first switch 212, ... and the 2nd first switch 212. N-M -1 position first switch 212.

[0084] First signal Bit <m>When the first toggling edge arrives, the first stage trigger 110 (refer to...) Figure 2 Its input is the power supply level VDD, and its output is the first second signal QT. <1> =1, the first switch 212 receives the first second signal QT. <1> =1, and based on the first received second signal QT <1> =1, which turns on the first current source 211 until the high level signal of the reset signal RST ends.

[0085] First signal Bit <m>When the second toggle edge arrives, the second stage flip-flop 110 outputs the second second signal QT. <2> =1, the second bit of the first switch 212 receives the second second signal QT. <2> =1, and based on the received second signal QT <2> =1, which turns on the second current source 211 until the high level signal of the reset signal RST ends.

[0086] And so on, in the first signal Bit <m>When the i-th toggle edge arrives, the i-th stage flip-flop 110 outputs the i-th second signal QT. =1, the i-th first switch 212 receives the i-th second signal QT =1, and based on the received i-th second signal QT =1, which turns on the first current source 211 of the i-th bit until the high level signal of the reset signal RST ends.

[0087] Finally, in the first signal bit <m>The 2nd N-M When the -1st flip edge arrives, the 2nd N-M -1 level trigger 110 output 2nd N-M -1 second signal QT<2 N-M -1>=1, 2nd N-M -1 bit first switch 212 receives the second N-M -1 second signal QT<2 N -M -1>=1, and based on the received second... N-M -1 second signal QT<2 N-M -1>=1 and thus the 2nd N-M -1 The first current source 211 is turned on until the high level signal of the reset signal RST ends.

[0088] In specific implementation, the first signal Bit <m>The flip period can be 2 times the clock signal clk of the ramp signal generation circuit 10. M times.

[0089] Because of the 2 in the first current steering unit 200 N-M -1 The current weights of the first current sources 211 are the same, and the 2 in the first current rudder unit 200 N-M -1 The first current source 211 is turned on sequentially from low bit to high bit, so the first current rudder unit 200 can output an increasing current as a rising ramp signal.

[0090] In other embodiments, 2 in the first current steering unit 200 N-M -1 The first current source 211 can also be disconnected sequentially from low to high bits. For example, in the initial state, 2 of the first current rudder units 200 can be disconnected sequentially. N-M -1 First current source 211 is turned on, and ground level is used as the input of cascaded level flip-flops 100, and all flip-flops 110 in cascaded level flip-flops 100 are active high-level flip-flops. Then, the first second signal QT is output sequentially by each flip-flop 110 in cascaded level flip-flops 100 in chronological order. <1> The second signal QT <2> ...the i-th second signal QT =1...and the 2nd N-M -1 second signal QT<2 N-M -1> are all 0. Therefore, the 2 in the first current steering unit 200 can be made... N -M -1 The first current source 211 is disconnected sequentially from low to high bits. Correspondingly, the first current steering unit 200 can output a decreasing current as a descending ramp signal.

[0091] In this embodiment of the invention, when the ramp signal generation circuit 10 includes a cascaded level trigger 100 and a first current steering unit 200, the cascaded level trigger 100 can be based on a bit in the digital signal. <m>At least two second signals are generated and output to the first current steering unit 200. The first current steering unit 200 can output an increasing or decreasing current based on the at least two second signals to generate an upward or downward ramp signal.

[0092] In this embodiment of the invention, when the ramp signal generation circuit 10 further includes a second current steering unit 300, the second current steering unit 300 can be based on a bit in the digital signal. <m-1:0>The output current increases or decreases to generate a rising or falling ramp signal.

[0093] Therefore, when the ramp signal generation circuit 10 includes a cascaded level trigger 100, a first current steering unit 200, and a second current steering unit 300, it can be based on the bit in the digital signal. <m:0>The output current increases or decreases to generate a rising or falling ramp signal.

[0094] In this case, the ramp signal generation circuit 10 can be used as a segmented current-rudder type digital-to-analog converter, wherein the first current rudder unit 200 serves as the temperature code unit of the segmented current-rudder type digital-to-analog converter, and the second current rudder unit 300 serves as the binary code unit of the segmented current-rudder type digital-to-analog converter.

[0095] Reference Figure 1 In some embodiments, the ramp signal generation circuit 10 further includes a load resistor R.

[0096] When the increasing or decreasing current generated by the ramp signal generation circuit 10 flows through the load resistor R, the ramp signal generation circuit 10 can generate an increasing or decreasing voltage as a rising or falling ramp signal.

[0097] Reference Figure 3 In some embodiments, the ramp signal generation circuit 10 may generate a rising ramp voltage signal Vramp based on an increasing current.

[0098] Understandably, in Figure 3 In the example shown, the sequentially increasing 2's in the ramp voltage signal are omitted. N-M -1 step.

[0099] Specifically, due to the first second signal QT <1> The second signal QT <2> ...the i-th second signal QT =1...and the 2nd N-M -1 second signal QT<2 N-M -1> All are based on the first signal Bit <m>This is generated by continuous flipping, and the first signal Bit <m>A toggle cycle of a certain length (e.g., the first signal bit) <m>The flip period can be 2 times the clock signal clk of the ramp signal generation circuit 10. M Therefore, the ramp signal generated by the ramp signal generation circuit 10 (including the ramp current signal and the ramp voltage signal) is in the first signal Bit. <m>Each flip cycle presents a step. The ramp signal generated by ramp signal generation circuit 10 consists of 2... N-M It is formed by a series of continuously rising steps.

[0100] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the invention, even when only a single embodiment is described with respect to a particular feature. The feature examples provided in this disclosure are intended to be illustrative and not limiting, unless otherwise stated. In practice, one or more technical features of the dependent claims may be combined with the technical features of the independent claims as needed and where technically feasible, and the technical features from the respective independent claims may be combined in any suitable manner rather than solely by the specific combinations listed in the claims.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m>

Claims

1. A ramp signal generation circuit, characterized in that, include: A cascaded level trigger is adapted to receive a first signal and, driven by the first signal and its inverted signal, sequentially generate at least two second signals; The first current rudder unit includes at least two first current rudders connected in parallel in sequence. Each first current rudder is adapted to receive one of the at least two second signals in sequence and to turn on or off in sequence based on the received second signal, so that the first current rudder unit outputs an increasing or decreasing current to generate a ramp signal; wherein the current weight of each first current rudder is the same. A second current rudder unit connected in parallel with the first current rudder unit, the second current rudder unit including at least one second current rudder, each of the at least one second current rudder being adapted to receive a third signal and to be turned on or off based on the received third signal, so that the second current rudder unit outputs an increasing or decreasing current to generate a ramp signal; the second current rudder unit includes at least two second current rudders connected in parallel in sequence, wherein the current weight of each second current rudder is different; The first signal is the highest bit of the digital signal received by the ramp signal generation circuit, and the third signal is the other bits of the digital signal.

2. The ramp signal generation circuit according to claim 1, characterized in that, The cascaded level trigger includes at least two cascaded triggers to output the at least two second signals respectively, and each of the triggers is adapted to output one of the at least two second signals.

3. The ramp signal generation circuit according to claim 2, characterized in that, One of the two adjacent flip-flops uses the first signal as its clock signal, and the other uses the inverted signal as its clock signal.

4. The ramp signal generation circuit according to claim 3, characterized in that, The cascaded level trigger includes an inverter adapted to receive the first signal and invert it into the inverted signal for output to the other.

5. The ramp signal generation circuit according to any one of claims 2 to 4, characterized in that, The trigger located in the first stage takes either a power supply level or a ground level as input.

6. The ramp signal generation circuit according to claim 5, characterized in that, Each of the subsequent triggers takes the output of the trigger in the preceding stage as its input.

7. The ramp signal generation circuit according to claim 6, characterized in that, The trigger includes a D trigger.

8. The ramp signal generation circuit according to claim 1, characterized in that, The current weights of each of the second current rudders are sequentially weighted in binary order from the least significant bit to the most significant bit.

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