Analog-to-digital converter and method of operation thereof

Abstract

Analog-to-digital converter includes a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, and a control logic circuit. A method of operation of the analog-to-digital converter includes during a first sampling period, switching a toggle signal to a first level to cause the first selection circuit to reset the first capacitor array with a first voltage setting and to cause the second selection circuit to reset the second capacitor array with the first voltage setting, and during a second sampling period, switching the toggle signal to a second level to cause the first selection circuit to reset the first capacitor array with a second voltage setting and to cause the second selection circuit to reset the second capacitor array with the second voltage setting. The control logic circuit switches the toggle signal between the first level and the second level in a uniform sequence during a plurality of sampling periods.

Description

Technical Field

[0001] This invention relates to electronic circuits, and in particular to an analog-to-digital converter and its operating method. Background Technology

[0002] An analog-to-digital converter (ADC) is a device used to convert continuous analog signals into discrete digital signals. It is widely used in audio systems, video systems, communication systems, and various digital signal processing systems. A successive approximation register (SAR) ADC is an analog-to-digital converter that uses a capacitor array for analog-to-digital conversion. It features low power consumption and is suitable for mobile or portable devices. However, due to capacitor mismatch in the capacitor array used in SAR ADCs, nonlinear errors can occur, reducing the accuracy of the SAR ADC. Summary of the Invention

[0003] Embodiments of the present invention provide an operation method for an analog-to-digital converter. The analog-to-digital converter includes a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, and control logic circuitry. Each group of capacitors in the first capacitor array includes a first capacitor and a second capacitor, having substantially equal capacitance values. Each group of capacitors in the second capacitor array includes a first capacitor and a second capacitor, having substantially equal capacitance values. The first selection circuit is coupled to the first capacitor array, the second selection circuit is coupled to the second capacitor array, and the control logic circuitry is coupled to the first selection circuit and the second selection circuit. The operation method includes, during a first sampling period, switching the switching signal to a first level, causing a first selection circuit to output a first reference voltage to a first capacitor in each group of capacitors in the first capacitor array and a second reference voltage to a second capacitor in each group of capacitors in the first capacitor array; and causing a second selection circuit to output the first reference voltage to a first capacitor in each group of capacitors in the second capacitor array and a second reference voltage to a second capacitor in each group of capacitors in the second capacitor array; and during a second sampling period, switching the switching signal to a second level, causing the first selection circuit to output the second reference voltage to a first capacitor in each group of capacitors in the first capacitor array and a second reference voltage to a second capacitor in each group of capacitors in the first capacitor array; and causing the second selection circuit to output the second reference voltage to a first capacitor in each group of capacitors in the second capacitor array and a second reference voltage to a second capacitor in each group of capacitors in the second capacitor array. The control logic circuit switches the switching signal between the first level and the second level in a uniform sequence during multiple sampling periods, and the first level and the second level are different.

[0004] Embodiments of the present invention provide an analog-to-digital converter, comprising a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, a comparator, and control logic circuitry. The first capacitor array is coupled to the first selection circuit and includes multiple groups of capacitors, each group including a first capacitor and a second capacitor. The second capacitor array is coupled to the second selection circuit and includes multiple groups of capacitors, each group including a first capacitor and a second capacitor. The comparator includes a first input terminal coupled to the first capacitor array, a second input terminal coupled to the second capacitor array, and an output terminal. The control logic circuitry is coupled to the output terminal of the comparator and to the first and second selection circuits. During a first sampling period, the control logic circuitry switches a switching signal to a first level, causing the first selection circuit to output a first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and to output a second reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and causing the second selection circuit to output the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and to output the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. During the second sampling period, the control logic circuit switches the switching signal to a second level, causing the first selection circuit to output a second reference voltage to the first capacitor of each group of capacitors in the first capacitor array and to output a first reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and causing the second selection circuit to output a second reference voltage to the first capacitor of each group of capacitors in the second capacitor array and to output a first reference voltage to the second capacitor of each group of capacitors in the second capacitor array. The control logic circuit switches the switching signal between the first level and the second level in a uniform sequence during multiple sampling periods, and the first level and the second level are different. Attached Figure Description

[0005] Figure 1A This is a circuit diagram of an analog-to-digital converter according to an embodiment of the present invention.

[0006] Figure 1B yes Figure 1A A circuit diagram of the first selection circuit and / or the second selection circuit.

[0007] Figure 2 yes Figure 1A The flowchart shows the operation method of the analog-to-digital converter.

[0008] Figure 3A This is a circuit diagram of another analog-to-digital converter according to an embodiment of the present invention.

[0009] Figure 3B yes Figure 3A A circuit diagram of the first selection circuit and / or the second selection circuit.

[0010] Figure 4A and Figure 4B yes Figure 3A A flowchart of another operating method for the analog-to-digital converter in the process. Detailed Implementation

[0011] Figure 1A This is a circuit diagram of an analog-to-digital converter 1 according to an embodiment of the present invention. The analog-to-digital converter 1 is a 3-bit split capacitor successive approximation register (SAR) analog-to-digital converter, which can convert differential input voltages Vip and Vin into digital output data Dout according to a successive approximation method (such as a binary search method). The differential input voltages Vip and Vin can be provided by a first signal source and a second signal source, respectively. The digital output data Dout can contain 3 bits. The analog-to-digital converter 1 can generate a set of digital output data Dout in each operating cycle. Each operating cycle can include a sampling stage (or acquisition stage) and a quantization stage (or conversion stage). The analog-to-digital converter 1 can sample the differential input voltages Vip and Vin in the sampling stage to generate a pair of sampled signals, and quantize the pair of sampled signals in the quantization stage to generate digital output data Dout. The quantization stage can include multiple (3) conversions to sequentially generate multiple (3) bits of digital output data Dout. During multiple sampling stages, the analog-to-digital converter 1 can be reset according to two voltage settings, thereby reducing voltage errors caused by capacitive component mismatch, reducing its integral nonlinearity (INL) error and differential nonlinearity (DNL) error, while providing high-speed analog-to-digital conversion.

[0012] The analog-to-digital converter 1 may include switches SW1 and SW2, a first capacitor array 141, a first selection circuit 121, a second capacitor array 142, a second selection circuit 122, a comparator 16, and a control logic circuit 18. The first selection circuit 121 and switch SW1 are coupled to the first capacitor array 141, and the second selection circuit 122 and switch SW2 are coupled to the second capacitor array 142. The comparator 16 may include a first receiving terminal coupled to the first capacitor array 141, a second receiving terminal coupled to the second capacitor array 142, and an output terminal coupled to the control logic circuit 18. The control logic circuit 18 is coupled to the first selection circuit 121 and the second selection circuit 122.

[0013] The first capacitor array 141 may include three groups of capacitors, each with a different capacitance value. Each group of capacitors includes a first capacitor and a second capacitor, which have substantially equal capacitance values. The first group of capacitors in the first capacitor array 141 may include a first capacitor C1pa and a second capacitor C1pb, the second group may include a first capacitor C2pa and a second capacitor C2pb, and the third group may include a first capacitor C3pa and a second capacitor C3pb. The first, second, and third groups of capacitors in the first capacitor array 141 may correspond to the most significant bit (MSB) to the least significant bit (LSB) of the digital output data Dout, respectively. The first capacitor C1pa and the second capacitor C1pb may each have a substantially equal capacitance value of 3C, and the first group of capacitors in the first capacitor array 141 may have a capacitance value of 6C; the first capacitor C2pa and the second capacitor C2pb may each have a substantially equal capacitance value of 2C, and the second group of capacitors in the first capacitor array 141 may have a capacitance value of 4C; the first capacitor C3pa and the second capacitor C3pb may each have a substantially equal capacitance value of 1C, and the third group of capacitors in the first capacitor array 141 may have a capacitance value of 2C. Each of the capacitors C1pa, C1pb, C2pa, C2pb, C3pa, and C3pb may include an upper plate and a lower plate. The upper plate of each of the capacitors C1pa, C1pb, C2pa, C2pb, C3pa, and C3pb may be coupled to the switch SW1.

[0014] Similarly, the second capacitor array 142 also includes three groups of capacitors, each with a different capacitance value. Each group includes a first capacitor and a second capacitor, which have substantially equal capacitance values. The first group of capacitors in the second capacitor array 142 may include a first capacitor C1na and a second capacitor C1nb, the second group may include a first capacitor C2na and a second capacitor C2nb, and the third group may include a first capacitor C3na and a second capacitor C3nb. The first, second, and third groups of capacitors in the second capacitor array 142 may correspond to the most significant bit to the least significant bit of the digital output data Dout, respectively. The first capacitor C1na and the second capacitor C1nb may each have a substantially equal capacitance value of 3C, and the first group of capacitors in the second capacitor array 142 may have a capacitance value of 6C; the first capacitor C2na and the second capacitor C2nb may each have a substantially equal capacitance value of 2C, and the second group of capacitors in the second capacitor array 142 may have a capacitance value of 4C; the first capacitor C3na and the second capacitor C3nb may each have a substantially equal capacitance value of 1C, and the third group of capacitors in the second capacitor array 142 may have a capacitance value of 2C. Each of capacitors C1na, C1nb, C2na, C2nb, C3na, and C3nb may include an upper plate and a lower plate. The upper plates of capacitors C1na, C1nb, C2na, C2nb, C3na, and C3nb may be coupled to switch SW2.

[0015] The first selection circuit 121 can receive a first reference voltage V1 and a second reference voltage V2 to configure the three sets of capacitors in the first capacitor array 141. The second selection circuit 122 can receive the first reference voltage V1 and the second reference voltage V2 to configure the three sets of capacitors in the second capacitor array 142. In some embodiments, the first reference voltage V1 can be a supply voltage, such as 1.8V, and the second reference voltage V2 can be a ground voltage, such as 0V. In other embodiments, the first reference voltage V1 can be a ground voltage, and the second reference voltage V2 can be a supply voltage. The first selection circuit 121 can be coupled to the lower plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, and C3pb. The second selection circuit 122 can be coupled to the lower plate of capacitors C1na, C1nb, C2na, C2nb, C3na, and C3nb.

[0016] The first selection circuit 121 and the second selection circuit 122 may be implemented by one or more switches connected to the reference voltage and one or more multiplexers, but are not limited thereto. Figure 1BThis is a circuit diagram of one embodiment of the first selection circuit 121 / second selection circuit 122. The first selection circuit 121 will be explained below; the second selection circuit 122 can be configured and operated according to similar principles as the first selection circuit 121. The first selection circuit 121 may include inverters 1a, 1b, 2a, 2b, 3a, 3b, multiplexers M1a, M1b, M2a, M2b, M3a, M3b, and switching circuits S1a, S1b, S2a, S2b, S3a, S3b. Inverters 1a, 1b, 2a, 2b, 3a, 3b can be coupled to control logic circuit 18 and can be coupled to multiplexers M1a, M1b, M2a, M2b, M3a, M3b respectively. Multiplexers M1a, M1b, M2a, M2b, M3a, M3b can be coupled to control logic circuit 18 and can be coupled to switching circuits S1a, S1b, S2a, S2b, S3a, S3b respectively. Switching circuits S1a, S1b, S2a, S2b, S3a, S3b can be coupled to the lower plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb of the first capacitor array 141 respectively.

[0017] Inverters 1a, 1b, 2a, 2b, 3a, 3b can each receive a corresponding selection signal from control logic circuit 18. Multiplexers M1a, M1b, M2a, M2b, M3a, M3b can each receive a corresponding selection signal from control logic circuit 18 and an inverted corresponding selection signal from inverters 1a, 1b, 2a, 2b, 3a, 3b. Based on the switching signal Sswp, they select one of the corresponding selection signal and the inverted corresponding selection signal as the output signal of the corresponding multiplexer, and output the corresponding multiplexer output signal to the switching circuits S1a, S1b, S2a, S2b, S3a, S3b. Each switching circuit S1a, S1b, S2a, S2b, S3a, S3b includes switches SV1 and SV2. Switch SV1 can receive a first reference voltage V1, and switch SV2 can receive a second reference voltage V2. Each switching circuit S1a, S1b, S2a, S2b, S3a, S3b can be controlled by the corresponding multiplexer output signals of multiplexers M1a, M1b, M2a, M2b, M3a, M3b to output a first reference voltage V1 or a second reference voltage V2.

[0018] refer to Figure 1ADuring the sampling phase, switches SW1 and SW2 can be turned on, and the first capacitor array 141 and the second capacitor array 142 can sample the differential input voltages Vip and Vin, respectively. The control logic circuit 18 can generate a switching signal Sswp and can switch the switching signal Sswp between a first level and a second level in a uniform sequence during multiple sampling periods, with the first level and the second level being different. The first level can be logic "0", and the second level can be logic "1". The uniform sequence can be an alternating sequence, a random sequence, or other specific sequences. When the uniform sequence is an alternating sequence, the control logic circuit 18 can switch the switching signal Sswp alternately between the first level and the second level. When the uniform sequence is a random sequence, the control logic circuit 18 can randomly switch the switching signal Sswp between the first level and the second level, and the probability of the switching signal Sswp switching to the first level and the second level is substantially the same. Other specific sequences can be sequences that are not purely alternating or not purely random. For example, other specific sequences could be that the exchange signal Sswp is at a first level for N sampling periods, and then at a second level for the next N sampling periods. In other embodiments, the exchange signal Sswp for the current data operation can be determined by information from previously sampled data, specifying whether it is at a first or second level. During the sampling period, the first selection circuit 121 and the second selection circuit 122 can output the voltage from either the first or second voltage setting to capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb and capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, respectively, based on the exchange signal Sswp. Tables 1 and 2 show the first and second voltage settings, respectively.

[0019] Table 1

[0020] capacitance C1pa C1pb C2pa C2pb C3pa C3pb Lower plate voltage V1 V2 V1 V2 V1 V2 capacitance C1na C1nb C2na C2nb C3na C3nb Lower plate voltage V1 V2 V1 V2 V1 V2

[0021] Table 2

[0022] capacitance C1pa C1pb C2pa C2pb C3pa C3pb Lower plate voltage V2 V1 V2 V1 V2 V1 capacitance C1na C1nb C2na C2nb C3na C3nb Lower plate voltage V2 V1 V2 V1 V2 V1

[0023] When sampling is performed and the exchange signal Sswp is at the first level, the first selection circuit 121 can output the corresponding voltage in the first voltage setting to the lower plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, and switch SW1 can be turned on to transmit the differential input voltage Vip to the upper plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, thereby establishing voltage Vp at the first receiving terminal of comparator 16; the second selection circuit 122 can output the corresponding voltage in the first voltage setting to the lower plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, and switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, thereby establishing voltage Vn at the second receiving terminal of comparator 16. When sampling is performed and the exchange signal Sswp is at the second level, the first selection circuit 121 can output the corresponding voltage in the second voltage setting to the lower plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, and switch SW1 can be turned on to transmit the differential input voltage Vip to the upper plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, thereby establishing voltage Vp; the second selection circuit 122 can output the corresponding voltage in the second voltage setting to the lower plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, and switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, thereby establishing voltage Vn.

[0024] In other embodiments, when the switching signal Sswp is at the first level, the first selection circuit 121 can output the corresponding voltage in the second voltage setting to the lower plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, and switch SW1 can be turned on to transmit the differential input voltage Vip to the upper plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, thereby establishing voltage Vp; the second selection circuit 122 can output the corresponding voltage in the second voltage setting to the lower plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, and switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, thereby establishing voltage Vn. When sampling is performed and the exchange signal Sswp is at the second level, the first selection circuit 121 can output the corresponding voltage in the first voltage setting to the lower plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, and switch SW1 can be turned on to transmit the differential input voltage Vip to the upper plate of capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, thereby establishing voltage Vp; the second selection circuit 122 can output the corresponding voltage in the first voltage setting to the lower plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, and switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb, thereby establishing voltage Vn.

[0025] During the quantization stage, the analog-to-digital converter 1 performs three conversions on the three bits of the digital output data Dout. Comparator 16 compares voltages Vp and Vn to generate three comparison results. Control logic circuit 18 stores each comparison result as the value of one bit of the digital output data Dout and generates selection signals based on each comparison result to set multiplexers M1pa, M1pb and M1na, M1nb to update voltages Vp and Vn. The comparison result can be a binary "0" or a binary "1". For example, when performing a most significant bit conversion, if voltage Vp is greater than voltage Vn, comparator 16 can generate a binary "1" as the comparison result. Control logic circuit 18 can store the binary "1" as the most significant bit, generate a selection signal to set multiplexers M1pa and M1pb to output ground voltage to the lower plate of capacitors C1pa and C1pb to pull down voltage Vp, and generate a selection signal to set multiplexers M1na and M1nb to output supply voltage to the lower plate of capacitors C1na and C1nb to boost voltage Vn. The updated voltage Vp will be lower than the previous voltage Vp, and the updated voltage Vn will be higher than the previous voltage Vn. If voltage Vp is less than voltage Vn, comparator 16 generates a binary "0" as the comparison result. Control logic circuit 18 stores the binary "0" as the most significant bit, generates a selection signal to set multiplexers M1pa and M1pb to output the supply voltage to the lower plates of capacitors C1pa and C1pb to boost voltage Vp, and generates a selection signal to set multiplexers M1na and M1nb to output the ground voltage to the lower plates of capacitors C1na and C1nb to pull down voltage Vn. The updated voltage Vp will be higher than the previous voltage Vp, and the updated voltage Vn will be lower than the previous voltage Vn. Analog-to-digital converter 1 can sequentially compare and update voltages Vp and Vn to generate a 3-bit value of digital output data Dout, and output digital output data Dout for subsequent use.

[0026] Figure 2 This is a flowchart of an operation method 200 for an analog-to-digital converter 1. Operation method 200 includes steps S202 and S204, used to reset the first capacitor array 141 and the second capacitor array 142 using two voltage settings during multiple sampling periods. Any reasonable technical modifications or adjustments to the steps are within the scope of this invention. Steps S202 and S204 are as follows:

[0027] Step S202: During the first sampling period, the switching signal Sswp is switched to the first level, so that the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor of each group of capacitors in the first capacitor array 141 and outputs the second reference voltage V2 to the second capacitor of each group of capacitors in the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor of each group of capacitors in the second capacitor array 142 and outputs the second reference voltage V2 to the second capacitor of each group of capacitors in the second capacitor array 142.

[0028] Step S204: During the second sampling period, the switching signal Sswp is switched to the second level so that the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor of each group of capacitors in the first capacitor array 141 and outputs the first reference voltage V1 to the second capacitor of each group of capacitors in the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor of each group of capacitors in the second capacitor array 142 and outputs the first reference voltage V1 to the second capacitor of each group of capacitors in the second capacitor array 142.

[0029] The second sampling period can be the next sampling period after the first sampling period, or it can be several sampling periods apart from the first sampling period. Method 200 is explained below in conjunction with analog-to-digital converter 1.

[0030] During the first sampling period, the control logic circuit 18 switches the switching signal Sswp to the first level. The first selection circuit 121 outputs the first reference voltage V1 to the first capacitor C1pa of the first group of capacitors, the first capacitor C2pa of the second group of capacitors, and the first capacitor C3pa of the third group of capacitors in the first capacitor array 141, and outputs the second reference voltage V2 to the second capacitor C1pb of the first group of capacitors, the second capacitor C2pb of the second group of capacitors, and the second capacitor C3pb of the third group of capacitors in the first capacitor array 141. The second selection circuit 122 outputs the first reference voltage V1 to the first capacitor C1na of the first group of capacitors, the first capacitor C2na of the second group of capacitors, and the first capacitor C3na of the third group of capacitors in the second capacitor array 142, and outputs the second reference voltage V2 to the second capacitor C1nb of the first group of capacitors, the second capacitor C2nb of the second group of capacitors, and the second capacitor C3nb of the third group of capacitors in the second capacitor array 142, as shown in the first voltage setting in Table 1 (step S202).

[0031] During the second sampling period, the control logic circuit 18 switches the switching signal Sswp to the second level. The first selection circuit 121 outputs the second reference voltage V2 to the first capacitor C1pa, the first capacitor C2pa, and the first capacitor C3pa of the first group of capacitors in the first capacitor array 141, and outputs the first reference voltage V1 to the second capacitor C1pb, the second capacitor C2pb, and the second capacitor C3pb of the first group of capacitors in the first capacitor array 141. The second selection circuit 122 outputs the second reference voltage V2 to the first capacitor C1na, the first capacitor C2na, and the first capacitor C3na of the first group of capacitors in the second capacitor array 142, and outputs the first reference voltage V1 to the second capacitor C1nb, the second capacitor C2nb, and the second capacitor C3nb of the first group of capacitors in the second capacitor array 142, as shown in the second voltage setting in Table 2 (step S204).

[0032] Figure 3A This is a circuit diagram of another analog-to-digital converter 3 in an embodiment of the present invention. The difference between analog-to-digital converter 3 and analog-to-digital converter 1 is that the first capacitor C1pa of the first group of capacitors in the first capacitor array 341 of analog-to-digital converter 3 is further divided into a first capacitor portion C1pa1 and a second capacitor portion C1pa2, and the first capacitor C1na of the first group of capacitors in the second capacitor array 342 is further divided into a first capacitor portion C1na1 and a second capacitor portion C1na2.

[0033] The first selection circuit 321 and the second selection circuit 322 may be implemented by one or more switches connected to the reference voltage and one or more multiplexers, but are not limited thereto. Figure 3BThis is a circuit diagram of one embodiment of the first selection circuit 321 / second selection circuit 322. The following explanation focuses on the first selection circuit 321; the second selection circuit 322 can be configured and operated according to similar principles as the first selection circuit 321. The first selection circuit 321 may include inverters 1a1, 1a2, 1b1, 1b2, 2a, 2b, 3a, 3b, multiplexers M1a1, M1a2, M1b1, M1b2, M2a, M2b, M3a, M3b, and switching circuits S1a1, S1a2, S1b1, S1b2, S2a, S2b, S3a, S3b. Inverters 1a1, 1a2, 1b1, 1b2, 2a, 2b, 3a, 3b can be coupled to control logic circuit 18 and can be coupled to multiplexers M1a1, M1a2, M1b1, M1b2, M2a, M2b, M3a, M3b respectively. Multiplexers M1a1, M1a2, M1b1, M1b2, M2a, M2b, M3a, M3b can be coupled to control logic circuit 18 and can be coupled to multiplexers M1a1, M1a2, M1b1, M1b2, M2a, M2b, M3a, M3b respectively. Coupled to the switching circuits S1a1, S1a2, S1b1, S1b2, S2a, S2b, S3a, S3b, the switching circuits S1a1, S1a2, S1b1, S1b2, S2a, S2b, S3a, S3b can be respectively coupled to the lower plate of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb of the first capacitor array 341.

[0034] Inverters 1a1, 1a2, 1b1, 1b2, 2a, 2b, 3a, 3b can each receive corresponding selection signals from control logic circuit 18. Multiplexers M1a1, M1a2, M1b1, M1b2, M2a, M2b, M3a, M3b can each receive corresponding selection signals from control logic circuit 18 and inverted corresponding selection signals from inverters 1a1, 1a2, 1b1, 1b2, 2a, 2b, 3a, 3b respectively. Based on the switching signal Sswp, they select one of the corresponding selection signals and the inverted corresponding selection signals as the corresponding multiplexer output signals, and output the corresponding multiplexer output signals to switching circuits S1a1, S1a2, S1b1, S1b2, S2a, S2b, S3a, S3b respectively. Each switching circuit S1a1, S1a2, S1b1, S1b2, S2a, S2b, S3a, S3b includes switches SV1 and SV2. Switch SV1 can receive a first reference voltage V1, and switch SV2 can receive a second reference voltage V2. Each switching circuit S1a1, S1a2, S1b1, S1b2, S2a, S2b, S3a, S3b can be controlled by the corresponding multiplexer output signals of multiplexers M1a1, M1a2, M1b1, M1b2, M2a, M2b, M3a, M3b to output either the first reference voltage V1 or the second reference voltage V2.

[0035] The capacitance value of the first capacitor portion of the first capacitor of the larger group of capacitors in the first capacitor array 341 can be substantially equal to the capacitance value of the first capacitor of the smaller group of capacitors in the first capacitor array 341, and the capacitance value of the first capacitor portion of the second capacitor of the larger group of capacitors in the first capacitor array 341 can be substantially equal to the capacitance value of the first capacitor of the smaller group of capacitors in the first capacitor array 341. For example, the capacitance value of the first capacitor portion C1pa1 of the first capacitor of the first group of capacitors in the first capacitor array 341 can be substantially equal to the capacitance value 2C of the first capacitor C2pa of the second group of capacitors in the first capacitor array 341, and the capacitance value of the first capacitor portion C1pb1 of the second group of capacitors in the first capacitor array 341 can be substantially equal to the capacitance value 2C of the first capacitor C2pa of the second group of capacitors in the first capacitor array 341. The capacitance value of the second capacitor portion of the first capacitor of the larger group of capacitors in the first capacitor array 341 can be equal to the remaining capacitance of the first capacitor of the larger group of capacitors excluding the first capacitor portion. For example, the capacitance value of the second capacitor portion C1pa2 of the first capacitor of the first group of capacitors in the first capacitor array 341 can be equal to 1C.

[0036] The capacitance value of the first capacitor portion of the first capacitor in a group of larger capacitors in the second capacitor array 342 can be substantially equal to the capacitance value of the first capacitor in a group of smaller capacitors in the second capacitor array 342, and the capacitance value of the first capacitor portion of the second capacitor in the group of larger capacitors in the second capacitor array 342 can be substantially equal to the capacitance value of the first capacitor in the group of smaller capacitors in the second capacitor array 342. For example, the capacitance value of the first capacitor portion C1na1 of the first capacitor C1na in the first group of capacitors in the second capacitor array 342 can be substantially equal to the capacitance value 2C of the first capacitor C2na in the second group of capacitors in the second capacitor array 342, and the capacitance value of the first capacitor portion C1nb1 of the second capacitor C1nb in the first group of capacitors in the second capacitor array 342 can be substantially equal to the capacitance value 2C of the first capacitor C2na in the second group of capacitors in the second capacitor array 342. The capacitance value of the second capacitor portion of the first capacitor in the group of larger capacitors in the second capacitor array 342 can be equal to the remaining capacitance of the first capacitor in the group of larger capacitors excluding the first capacitor portion. For example, the capacitance value of the second capacitor portion C1na2 of the first capacitor of the first group of capacitors in the second capacitor array 342 can be equal to 1C.

[0037] The following explains the differences between analog-to-digital converter 3 and analog-to-digital converter 1.

[0038] During sampling, the first selection circuit 321 and the second selection circuit 322 can output the voltage from either the first or second voltage setting to capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb and capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, according to the exchange signal Sswp. Tables 3 and 4 show the first and second voltage settings, respectively:

[0039] Table 3

[0040] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage V1 V1 V2 V2 V1 V2 V1 V2 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage V1 V1 V2 V2 V1 V2 V1 V2

[0041] Table 4

[0042]

[0043]

[0044] The analog-to-digital converter 3 is also applicable to operation method 200. During the first sampling period, the control logic circuit 18 switches the switching signal Sswp to a first level, and the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 and the second capacitor portion C1pa2 of the first group of capacitors in the first capacitor array 341, the first capacitor C2pa of the second group of capacitors, and the first capacitor C3pa of the third group of capacitors, and outputs the second reference voltage V2 to the first capacitor portion C1pb1 and the second capacitor portion C1pb2 of the second group of capacitors in the first capacitor array 341, the second capacitor C2pb of the second group of capacitors, and the third capacitor portion C3pa of the third group of capacitors. The second capacitor C3pb of the first group of capacitors, the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1na1 and the second capacitor portion C1na2 of the first group of capacitors, the first capacitor C2na of the second group of capacitors and the first capacitor C3na of the third group of capacitors, and outputs the second reference voltage V2 to the first capacitor portion C1nb1 and the second capacitor portion C1nb2 of the second capacitor of the first group of capacitors, the second capacitor C2nb of the second group of capacitors and the second capacitor C3nb of the third group of capacitors (step S202).

[0045] During the second sampling period, the control logic circuit 18 switches the switching signal Sswp to the second level. The first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pa1 and the second capacitor portion C1pa2 of the first group of capacitors in the first capacitor array 341, the first capacitor C2pa of the second group of capacitors and the first capacitor C3pa of the third group of capacitors, and outputs the first reference voltage V1 to the first capacitor portion C1pb1 and the second capacitor portion C1pb2 of the second group of capacitors in the first capacitor array 341, the second capacitor C2pb of the second group of capacitors and the third capacitor C3pa of the third group of capacitors. The second capacitor C3pb of the first group of capacitors, the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 and the second capacitor portion C1na2 of the first capacitor C1na of the first group of capacitors, the first capacitor C2na of the second group of capacitors and the first capacitor C3na of the third group of capacitors, and outputs the first reference voltage V1 to the first capacitor portion C1nb1 and the second capacitor portion C1nb2 of the second capacitor C1nb of the first group of capacitors, the second capacitor C2nb of the second group of capacitors and the second capacitor C3nb of the third group of capacitors (step S204).

[0046] Since the analog-to-digital converters 1 and 3 and the operation method 200 uniformly use the first voltage setting and the second voltage setting to reset the first capacitor array 141, 341 and the second capacitor array 142, 342 during multiple sampling periods, the output-input curve of the entire analog-to-digital converter will effectively switch between the two configurations. This results in the average nonlinear error being offset by positive and negative values ​​at most digital code positions, reducing the differential linear error and integral linear error caused by capacitor mismatch.

[0047] Figure 4A and Figure 4B This is a flowchart of another operation method 400 of the analog-to-digital converter 3. Method 400 includes steps S402 to S428, which can be used after step S204 in method 200, namely, the first capacitor array 341 and the second capacitor array 342 are reset during the second sampling period according to the second voltage setting shown in Table 4. Steps S402, S412, and S422 are used to set the first capacitor array 341 and the second capacitor array 342 during the first conversion period. Steps S414 to S418 and S424 to S428 are used to set the first capacitor array 341 and the second capacitor array 342 during the second conversion period. Any reasonable technical changes or adjustments to the steps are within the scope of this invention. Steps S402 to S428 are as follows:

[0048] Step S402: Determine whether voltage Vp is greater than voltage Vn; if yes, proceed to step S412; if no, proceed to step S422.

[0049] Step S412: During the first conversion, the first selection circuit 321 outputs the second reference voltage V2 to the second capacitor C1pb of a group of larger capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the first reference voltage V1 to the first capacitor C1na of a group of larger capacitors in the second capacitor array 342.

[0050] Step S414: Determine whether voltage Vp is less than voltage Vn; if yes, proceed to step S416; if no, proceed to step S418.

[0051] Step S416: During the second conversion, the first selection circuit 321 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the larger capacitor group in the first capacitor array 341 or the first capacitor portion C1pb1 of the second capacitor C1pb of the larger capacitor group in the first capacitor array 341. The second selection circuit 322 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na of the larger capacitor group in the second capacitor array 342 or the first capacitor portion C1nb1 of the second capacitor C1nb of the larger capacitor group in the second capacitor array 342.

[0052] Step S418: During the second conversion, the first selection circuit 321 outputs the second reference voltage V2 to a group of smaller capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the first reference voltage V1 to a group of smaller capacitors in the second capacitor array 342.

[0053] Step S422: During the first conversion, the first selection circuit 321 outputs the first reference voltage V1 to the first capacitor C1pa of a group of larger capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the second reference voltage V2 to the second capacitor C1nb of a group of larger capacitors in the second capacitor array 342.

[0054] Step S424: Determine whether voltage Vp is greater than voltage Vn; if yes, proceed to step S426; if no, proceed to step S428.

[0055] Step S426: During the second conversion, the first selection circuit 321 outputs the second reference voltage V2 to the first capacitor portion C1pa1 of the first capacitor C1pa of the larger capacitor group in the first capacitor array 341 or the first capacitor portion C1pb1 of the second capacitor C1pb of the larger capacitor group in the first capacitor array 341. The second selection circuit 322 outputs the first reference voltage V1 to the first capacitor portion C1na1 of the first capacitor C1na of the larger capacitor group in the second capacitor array 342 or the first capacitor portion C1nb1 of the second capacitor C1nb of the larger capacitor group in the second capacitor array 342.

[0056] Step S428: During the second conversion, the first selection circuit 321 outputs the first reference voltage V1 to the first capacitor C2pa of a group of smaller capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the second reference voltage V2 to the second capacitor C2nb of a group of smaller capacitors in the second capacitor array 342.

[0057] The steps of method 400 are explained below in conjunction with analog-to-digital converter 3. During the sampling period of the first selection circuit 321 and the second selection circuit 322, a second voltage is used to set the reset capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb and capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, as shown in Table 4. The first reference voltage V1 can be the supply voltage and the second reference voltage V2 can be the ground voltage. After the quantization stage begins, during the first conversion period, comparator 16 determines whether voltage Vp is greater than voltage Vn (step S402).

[0058] If voltage Vp is greater than voltage Vn, then the first selection circuit 321 outputs the second reference voltage V2 to the first capacitor portion C1pb1 and the second capacitor portion C1pb2 of the second capacitor C1pb in the first group of capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the first reference voltage V1 to the first capacitor portion C1na1 and the second capacitor portion C1na2 of the first capacitor C1na in the second capacitor array 342, as shown in Table 5 (step S412):

[0059] Table 5

[0060] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage V2 V2 "V2” "V2” V2 V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage "V1” "V1” V1 V1 V2 V1 V2 V1

[0061] During the second conversion, comparator 16 determines whether voltage Vp is less than voltage Vn (step S414). If voltage Vp is less than voltage Vn, the first selection circuit 321 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa in the first group of capacitors in the first capacitor array 341 or the first capacitor portion C1pb1 of the second capacitor C1pb in the first group of capacitors in the first capacitor array 341. The second selection circuit 322 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na in the first group of capacitors in the second capacitor array 342 or the first capacitor portion C1nb1 of the second capacitor C1nb in the first group of capacitors in the second capacitor array 342 (step S416).

[0062] In some embodiments, the first selection circuit 321 can output the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa in the first group of capacitors in the first capacitor array 341, and the second selection circuit 322 can output the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb in the first group of capacitors in the second capacitor array 342, as shown in Table 6:

[0063] Table 6

[0064] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage "V1” V2 V2 V2 V2 V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage V1 V1 "V2” V1 V2 V1 V2 V1

[0065] In other embodiments, the first selection circuit 321 can output the first reference voltage V1 to the first capacitor portion C1pb1 of the second capacitor C1pb in the first capacitor array 341 to switch the first capacitor portion C1pb1 back to its reset value (V1), and the second selection circuit 322 can output the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na in the second capacitor array 342 to switch the first capacitor portion C1na1 back to its reset value (V2), as shown in Table 7:

[0066] Table 7

[0067] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage V2 V2 "V1” V2 V2 V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage "V2” V1 V1 V1 V2 V1 V2 V1

[0068] In other embodiments, the first selection circuit 321 and the second selection circuit 322 can output the voltage settings shown in Tables 7 and 6 to the first capacitor array 341 and the second capacitor array 342 respectively according to a uniform sequence. The uniform sequence can be an alternating sequence or a random sequence. When the uniform sequence is an alternating sequence, the first selection circuit 321 and the second selection circuit 322 can output the voltage settings of Tables 7 and 6 to the first capacitor array 341 and the second capacitor array 342 in turn during multiple conversion periods. When the uniform sequence is a random sequence, the first selection circuit 321 and the second selection circuit 322 can randomly output the voltage settings shown in Tables 7 and 6 to the first capacitor array 341 and the second capacitor array 342 during multiple conversion periods, and the probability of the voltage settings shown in Tables 7 and 6 occurring is substantially the same.

[0069] If in step S414 comparator 16 determines that voltage Vp is not less than voltage Vn, then the first selection circuit 321 outputs the second reference voltage V2 to the second capacitor C2pb of the second group of capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the first reference voltage V1 to the first capacitor C2na of the second group of capacitors in the second capacitor array 342, as shown in Table 8 (step S418).

[0070] Table 8

[0071] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage V2 V2 V2 V2 V2 "V2” V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage V1 V1 V1 V1 "V1” V1 V2 V1

[0072] If, in step S402, comparator 16 determines that voltage Vp is not greater than voltage Vn, then the first selection circuit 321 outputs the first reference voltage V1 to the first capacitor portion C1pa1 and the second capacitor portion C1pa2 of the first group of capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the second reference voltage V2 to the first capacitor portion C1nb1 and the second capacitor portion C1nb2 of the second capacitor in the first group of capacitors in the second capacitor array 342, as shown in Table 9 (step S422).

[0073] Table 9

[0074] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage "V1” "V1” V1 V1 V2 V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage V2 V2 "V2” "V2” V2 V1 V2 V1

[0075] During the second conversion, comparator 16 determines whether voltage Vp is greater than voltage Vn (step S424). If voltage Vp is greater than voltage Vn, the first selection circuit 321 outputs the second reference voltage V2 to the first capacitor portion C1pa1 of the first group of capacitors in the first capacitor array 341 or the first capacitor portion C1pb1 of the second group of capacitors in the first capacitor array 341. The second selection circuit 322 outputs the first reference voltage V1 to the first capacitor portion C1na1 of the first group of capacitors in the second capacitor array 342 or the first capacitor portion C1nb1 of the second group of capacitors in the second capacitor array 342 (step S426). In some embodiments, the first selection circuit 321 can output the second reference voltage V2 to the first capacitor portion C1pa1 of the first capacitor C1pa in the first group of capacitors in the first capacitor array 341 to switch the first capacitor portion C1pa1 back to its reset value (V2), and the second selection circuit 322 can output the first reference voltage V1 to the first capacitor portion C1nb1 of the second capacitor C1nb in the first group of capacitors in the second capacitor array 342 to switch the first capacitor portion C1nb1 back to its reset value (V2), as shown in Table 10.

[0076] Table 10

[0077] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage "V2” V1 V1 V1 V2 V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage V2 V2 "V1” V2 V2 V1 V2 V1

[0078] In other embodiments, the first selection circuit 321 can output the second reference voltage V2 to the first capacitor portion C1pb1 of the second capacitor C1pb of the first group of capacitors in the first capacitor array 341, and the second selection circuit 322 can output the first reference voltage V1 to the first capacitor portion C1na1 of the first capacitor C1na of the first group of capacitors in the second capacitor array 342, as shown in Table 11.

[0079] Table 11

[0080] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage V1 V1 "V2” V1 V2 V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage "V1” V2 V2 V2 V2 V1 V2 V1

[0081] In other embodiments, the first selection circuit 321 and the second selection circuit 322 can output the voltage settings shown in Tables 10 and 11 to the first capacitor array 341 and the second capacitor array 342 in a uniform sequence, respectively. The uniform sequence can be an alternating sequence or a random sequence. When the uniform sequence is an alternating sequence, the first selection circuit 321 and the second selection circuit 322 can output the voltage settings shown in Tables 10 and 11 to the first capacitor array 341 and the second capacitor array 342 in turn during multiple transition periods. When the uniform sequence is a random sequence, the first selection circuit 321 and the second selection circuit 322 can randomly output the voltage settings shown in Tables 10 and 11 to the first capacitor array 341 and the second capacitor array 342 during multiple transition periods, and the probability of the voltage settings shown in Tables 10 and 11 occurring is substantially the same.

[0082] If, in step S424, comparator 16 determines that voltage Vp is not greater than voltage Vn, then the first selection circuit 321 outputs the first reference voltage V1 to the first capacitor C2pa of the second group of capacitors in the first capacitor array 341, and the second selection circuit 322 outputs the second reference voltage V2 to the second capacitor C2nb of the second group of capacitors in the second capacitor array 342, as shown in Table 12 (step S418).

[0083] Table 12

[0084] capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb Lower plate voltage V1 V1 V1 V1 "V1” V1 V2 V1 capacitance C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb Lower plate voltage V2 V2 V2 V2 V2 "V2” V2 V1

[0085] In other embodiments, the first selection circuit 321 and the second selection circuit 322 use a second voltage setting during sampling to reset capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb and capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, as shown in Table 3. The first reference voltage V1 can be the supply voltage and the second reference voltage V2 can be the ground voltage. After the quantization phase begins, during the first conversion period, comparator 16 determines whether voltage Vp is greater than voltage Vn (step S402).

[0086] In the embodiments described above using method 400, the second conversion period is not limited to directly following the first conversion period. In other embodiments, if the number of capacitor arrays is large (e.g., ten digits), the analog-to-digital conversion can be performed in conjunction with method 400 by dividing the first and second capacitors of the larger group of capacitors into multiple capacitor portions, each with a capacitance value substantially equal to the capacitance value of the first capacitor of one or more smaller capacitors.

[0087] Method 400 can be used in conjunction with sampling methods in related technologies or in conjunction with method 200. When used in conjunction with sampling methods in related technologies, method 400 reduces the differential and integral nonlinear errors caused by capacitor mismatch between different groups of capacitors in the first capacitor array 341 and the second capacitor array 342. When method 400 is used in conjunction with method 200, method 200 mainly reduces the nonlinear error caused by capacitor mismatch within the same group of capacitors, while method 400 mainly reduces the nonlinear error caused by capacitor mismatch between different groups of capacitors, thus also improving the overall differential and integral nonlinear errors. In some embodiments, if both the first capacitor array 341 and the second capacitor array 342 are configured with 10-bit binary weighted capacitors, and each group of capacitors has a random drift with a standard deviation of two percent of the capacitance value, when using method 200 in conjunction with method 400, the first and second capacitors of each group of capacitors are operated in a uniform order between different samples, and when the conditions of method 400 are met during non-maximum bit transitions, the corresponding larger capacitor portion of the group is back-cut, the maximum differential nonlinear error will decrease from 0.37 LSB to 0.22 LSB, and the maximum integral nonlinear error will decrease from 0.8 LSB to 0.48 LSB.

[0088] This invention is not limited to the 3-bit SAR ADC used in the embodiments. Those skilled in the art can also apply methods 200 and 400 to SAR ADCs of other sizes based on the spirit of this invention. The analog-to-digital converters 1 and 3 and the operation method 200 uniformly reset the first capacitor arrays 141, 341 and the second capacitor arrays 142, 342 using a first voltage setting and a second voltage setting during multiple sampling periods. The analog-to-digital converter 3 and the operation method 400 use a back-switch technique to switch the first capacitor array 341 and the second capacitor array 342, reducing the differential nonlinearity error and integral nonlinearity error caused by capacitor mismatch between the same group of capacitors or different groups of capacitors, and significantly improving the linearity of the SAR ADC.

[0089] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.

[0090] Explanation of reference numerals in the attached figures:

[0091] 1,3: Analog-to-digital converter

[0092] 121, 321: First selection circuit

[0093] 122,322: Second selection circuit

[0094] 141,341: First capacitor array

[0095] 142,342: Second capacitor array

[0096] 16: Comparator

[0097] 18: Control Logic Circuit

[0098] 200, 400: Method

[0099] S202, S204, S402 to S428: Steps

[0100] C1pa,C1pa1,C1pa2,C1pb,C1pb1,C1pb2,C2pa,C2pb,C3pa,C3pb,C1na,C1na1,C1na2,C1nb,C1nb1,C1nb2,C2na,C2nb,C3na,C3nb: Capacitors

[0101] Dout: Digital output data

[0102] 1a,1a1,1a2,1b,1b1,1b2,2a,2b,3a,3b: Inverters

[0103] M1a, M1a1, M1a2, M1b, M1b1, M1b2, M2a, M2b, M3a, M3b: Multiplexers

[0104] S1a, S1a1, S1a2, S1b, S1b1, S1b2, S2a, S2b, S3a, S3b: Switching circuit

[0105] Sswp: Switching signal

[0106] SW1, SW2, SV1, SV2: Switches

[0107] V1: First reference voltage

[0108] V2: Second reference voltage

[0109] Vip, Vin: Differential input voltage

[0110] Vp, Vn: Voltage

Claims

1. A method of operating an analog-to-digital converter, the analog-to-digital converter comprising a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, and a control logic circuit, wherein the first capacitor array comprises multiple groups of capacitors, each group of capacitors in the first capacitor array comprising a first capacitor and a second capacitor, the second capacitor array comprises multiple groups of capacitors, each group of capacitors in the second capacitor array comprising a first capacitor and a second capacitor, the first selection circuit is coupled to the first capacitor array, the second selection circuit is coupled to the second capacitor array, and the control logic circuit is coupled to the first selection circuit and the second selection circuit, the method of operating the converter comprising: During the first sampling period, the switching signal is switched to a first level so that the first selection circuit outputs a first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs a second reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. as well as During the second sampling period, the switching signal is switched to a second level so that the first selection circuit outputs the second reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs the first reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and the second selection circuit outputs the second reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the first reference voltage to the second capacitor of each group of capacitors in the second capacitor array; The control logic circuit switches the exchange signal between the first level and the second level in a uniform sequence during multiple sampling periods, and the first level and the second level are different.

2. The operation method as described in claim 1, wherein the uniform sequence is an alternating sequence.

3. The operation method as described in claim 1, wherein the uniform order is a random order.

4. The operation method as described in claim 1, wherein the uniform sequence is a predetermined sequence.

5. The operating method as described in claim 1, wherein: In the first capacitor array, the first capacitor and the second capacitor of each group of capacitors have substantially equal capacitance values; and The first capacitor and the second capacitor in each group of capacitors in the second capacitor array have substantially equal capacitance values.

6. The operating method as described in claim 1, wherein: The analog-to-digital converter further includes a comparator, which includes a first input terminal coupled to the first capacitor array and a second input terminal coupled to the second capacitor array. The capacitance value of the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the first capacitor array, and the capacitance value of the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the first capacitor array. The capacitance value of the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the second capacitor array, and the capacitance value of the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the second capacitor array; and The operation method further includes: During the first conversion, if the voltage at the first input terminal of the comparator is greater than the voltage at the second input terminal, the first selection circuit outputs the second reference voltage to the second capacitor of the group of larger capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the first capacitor of the group of larger capacitors in the second capacitor array. as well as During the second conversion period following the first conversion, if the voltage at the first input terminal of the comparator is less than the voltage at the second input terminal, the first selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the larger set of capacitors in the first capacitor array or the first capacitor portion of the second capacitor of the larger set of capacitors in the first capacitor array, and the second selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the larger set of capacitors in the second capacitor array or the first capacitor portion of the second capacitor of the larger set of capacitors in the second capacitor array.

7. The operating method as described in claim 1, wherein: The analog-to-digital converter further includes a comparator, which includes a first input terminal coupled to the first capacitor array and a second input terminal coupled to the second capacitor array. The capacitance value of the first capacitor portion of the first capacitor of the larger capacitor in the first capacitor array is substantially equal to the capacitance value of the first capacitor of the smaller capacitor in the first capacitor array, and the capacitance value of the first capacitor portion of the second capacitor of the larger capacitor in the first capacitor array is substantially equal to the capacitance value of the first capacitor of the smaller capacitor in the first capacitor array. The capacitance value of the first capacitor portion of the larger capacitor in the second capacitor array is substantially equal to the capacitance value of the first capacitor of the smaller capacitor in the second capacitor array, and the capacitance value of the first capacitor portion of the second capacitor of the larger capacitor in the second capacitor array is substantially equal to the capacitance value of the first capacitor of the smaller capacitor in the second capacitor array; and The operation method further includes: During the first conversion, if the voltage at the first input terminal of the comparator is less than the voltage at the second input terminal, the first selection circuit outputs the first reference voltage to the first capacitor of the larger capacitor in the first capacitor array, and the second selection circuit outputs the second reference voltage to the second capacitor of the larger capacitor in the second capacitor array. as well as During the second conversion period following the first conversion period, if the voltage at the first input terminal of the comparator is greater than the voltage at the second input terminal, the first selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the larger capacitor in the first capacitor array or the first capacitor portion of the second capacitor of the larger capacitor in the first capacitor array, and the second selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the larger capacitor in the second capacitor array or the first capacitor portion of the second capacitor of the larger capacitor in the second capacitor array.

8. An analog-to-digital converter, comprising: First selection circuit; Second selection circuit; A first capacitor array, coupled to the first selection circuit, includes multiple groups of capacitors, each group of capacitors in the first capacitor array including a first capacitor and a second capacitor. The second capacitor array, coupled to the second selection circuit, includes multiple sets of capacitors, each set of capacitors in the second capacitor array including a first capacitor and a second capacitor. The comparator includes a first input terminal coupled to the first capacitor array, a second input terminal coupled to the second capacitor array, and an output terminal; as well as A control logic circuit is coupled to the output terminal of the comparator, the first selection circuit, and the second selection circuit; During the first sampling period, the control logic circuit is used to switch the switching signal to a first level, so that the first selection circuit outputs a first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs a second reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array; During the second sampling period, the control logic circuit is used to switch the switching signal to a second level, so that the first selection circuit outputs the second reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs the first reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and so that the second selection circuit outputs the second reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the first reference voltage to the second capacitor of each group of capacitors in the second capacitor array; as well as The control logic circuit switches the exchange signal between the first level and the second level in a uniform sequence during multiple sampling periods, and the first level and the second level are different.

9. The analog-to-digital converter as claimed in claim 8, wherein: The first selection circuit includes multiple multiplexers. Each multiplexer of the first selection circuit includes a first input terminal, a second input terminal, a selection terminal, coupled to the control logic circuit for receiving the switching signal, and an output terminal for outputting the voltage of the first input terminal or the voltage of the second input terminal according to the switching signal. as well as The second selection circuit includes multiple multiplexers. Each multiplexer of the second selection circuit includes a first input terminal, a second input terminal, a selection terminal, coupled to the control logic circuit for receiving the switching signal, and an output terminal for outputting the voltage of the first input terminal or the voltage of the second input terminal according to the switching signal.

10. The analog-to-digital converter of claim 8, wherein: In the first capacitor array, the first capacitor and the second capacitor of each group of capacitors have substantially equal capacitance values; and The first capacitor and the second capacitor in each group of capacitors in the second capacitor array have substantially equal capacitance values.

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