Srv6 header compression method and apparatus

Abstract

The present disclosure provides an SRv6 header compression method and device, and relates to the field of data communication. The method comprises the following steps: converting a segment list in an SRv6 header into a matrix; compressing the matrix by using a preset matrix compression method; and replacing the segment list with the compression result of the matrix and encoding the compression result into the SRv6 header. Thus, the SRv6 header compression method based on the matrix is realized, and the method has good universality.

Description

Technical Field

[0001] This disclosure relates to the field of data communication, and in particular to an SRv6 header compression method and apparatus. Background Technology

[0002] SRv6 (Segment Routing over IPv6) identifies each segment using a SID (Segment ID). An SID is a special IPv6 address that possesses both the routing capabilities of a regular IPv6 address and the unique behavioral capabilities of SRv6. Figure 1 A schematic diagram of SIDs is shown. Because SRv6 uses 128-bit IPv6 addresses as SIDs, there is a problem of large header overhead when the number of SIDs is large.

[0003] One related scheme for SRv6 header compression, namely G-SRv6 (Generalized-SRv6), considers the common prefix part in the segment list to be redundant, and only retains the node ID and function ID as the compressed SID, namely G-SID (Generalized SID).

[0004] However, the above scheme will cause network planning problems. Specifically, the total number of bits of the planned number of Nodes and Functions must not exceed the compression length; otherwise, the G-SID compression scheme cannot be used. In addition, for routers not managed by this unit, their SRv6 locators cannot be controlled. For example, if the locator on the A side is 1001:: / 80 and the locator on the B side is 2002:: / 80, since they do not share a common prefix, the G-SID compression scheme cannot be used. Therefore, it has certain limitations. Summary of the Invention

[0005] This disclosure implements a matrix-based SRv6 header compression method, which has good versatility and can avoid the network planning problems and limitations of the G-SRv6 header compression method.

[0006] This disclosure provides an SRv6 header compression method in some embodiments, including: converting a segment list in the SRv6 header into a matrix; compressing the matrix using a preset matrix compression method; and replacing the segment list with the compressed result of the matrix and encoding it into the SRv6 header.

[0007] In some embodiments, converting the segment list in the SRv6 header into a matrix includes: extracting the segment list from the SRv6 header, the segment list comprising n segments, each segment being a 128-bit IPv6 address; and converting each of the n segments into a matrix. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns.

[0008] For example, converting the segment list in the SRv6 header into a matrix involves: extracting the segment list from the SRv6 header, which consists of n segments, each a 128-bit IPv6 address; dividing each of the n segments into 4-bit elements, resulting in 32 elements per segment; and arranging all the elements of the n segments into an n-row, 32-column matrix.

[0009] In some embodiments, the matrix is ​​compressed using any of the following matrix compression methods: a matrix compression method using a triplet sequential list; a matrix compression method using a row logical linked sequential list; or a matrix compression method using a cross-linked list.

[0010] In some embodiments, a matrix compression method using a triplet sequential list is employed to compress the matrix, which includes: recording the non-zero elements in the matrix as (row index, column index, element value) triples; and arranging the corresponding triples sequentially according to the order of the non-zero elements in the matrix.

[0011] In some embodiments, a matrix compression method using a row-logically linked sequential list is employed to compress the matrix, comprising: recording the non-zero elements in the matrix as (row index, column index, element value) triples; sequentially arranging the corresponding triples according to the order of the non-zero elements in the matrix and storing them in a first array; and using a second array to record the storage position of the first non-zero element in each row of the matrix in the first array.

[0012] In some embodiments, the matrix compression method using the cross-linked list approach compresses the matrix by: storing each row and column of the matrix in a separate linked list, and storing the head of all row linked lists in a third array and the head of all column linked lists in a fourth array. The information of each node in each linked list includes a row index, a column index, an element value, and two pointer fields, where the two pointer fields are used to link to the next element in the current row and the next element in the current column, respectively.

[0013] This disclosure provides an SRv6 header compression apparatus in several embodiments, including: a memory; and a processor coupled to the memory, the processor being configured to execute the SRv6 header compression method of various embodiments based on instructions stored in the memory.

[0014] This disclosure provides an SRv6 header compression device in several embodiments, comprising: a matrix conversion module configured to convert a segment list in the SRv6 header into a matrix; a compression module configured to compress the matrix using a preset matrix compression method; and an encoding module configured to replace the segment list with the compressed result of the matrix and encode it into the SRv6 header.

[0015] In some embodiments, the matrix transformation module is configured to: extract a segment list from the SRv6 header, the segment list comprising n segments, each segment being a 128-bit IPv6 address; and transform each 2 bits of each of the n segments into a single segment. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns.

[0016] In some embodiments, the compression module is configured to compress the matrix using any of the following matrix compression methods: a matrix compression method using a triplet sequential list; a matrix compression method using a row logical linked sequential list; or a matrix compression method using a cross-linked list.

[0017] Some embodiments of this disclosure provide a non-transitory computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps of the SRv6 header compression method of each embodiment. Attached Figure Description

[0018] The accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. This disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings.

[0019] Obviously, the accompanying drawings described below are merely some embodiments of this disclosure. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0020] Figure 1 This is a diagram showing a list of segments.

[0021] Figure 2 A schematic diagram of the SRv6 head is shown.

[0022] Figure 3 A flowchart illustrating an SRv6 header compression method according to some embodiments of this disclosure is shown.

[0023] Figures 4a-4c A schematic diagram of a matrix compression method for a triplet sequential list is shown.

[0024] Figures 4b-4d This diagram illustrates a matrix compression method for sequential lists with logical links.

[0025] Figure 4e-4f A schematic diagram of the matrix compression method using the cross-linked list method is shown.

[0026] Figure 5 This is a schematic diagram of the structure of the SRv6 head compression device according to some embodiments of this disclosure.

[0027] Figure 6 This is a schematic diagram of the structure of the SRv6 head compression device according to other embodiments of this disclosure. Detailed Implementation

[0028] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0029] Unless otherwise stated, the terms "first," "second," etc., used in this disclosure are used to distinguish different objects and are not used to indicate size or sequence.

[0030] Figure 2 This is a diagram illustrating the SRv6 message encapsulation format. (For example...) Figure 2 As shown, an SRv6 message includes an IPv6 header, an SRH (Segment Routing Header), and a data payload. The SRH, also known as the SRv6 header, is used for programming the combination of segments to form an SRv6 path. The fields in the SRH and their meanings are shown in the table below.

[0031]

[0032]

[0033] Figure 3 A flowchart illustrating an SRv6 header compression method according to some embodiments of this disclosure is shown.

[0034] like Figure 3 As shown, the SRv6 header compression method of this embodiment includes steps 310-330.

[0035] In step 310, the segment list in the SRv6 header is converted into a matrix.

[0036] In some embodiments, converting the segment list in the SRv6 header into a matrix includes: extracting the segment list from the SRv6 header, the segment list comprising n segments, each segment being a 128-bit IPv6 address; and converting each of the n segments into a matrix. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns.

[0037] For example, extract the segment list from the SRv6 header. The segment list includes n segments, each segment being a 128-bit IPv6 address; m=2, divide each of the n segments into 4 bits as an element, resulting in 32 elements for each segment; and arrange all the elements of the n segments into an n-row, 32-column matrix.

[0038] For example, extract the segment list from the SRv6 header. The segment list includes n segments, each segment being a 128-bit IPv6 address; m=1, divide every 2 bits in each of the n segments into an element, resulting in 64 elements for each segment; and arrange all the elements of the n segments into an n-row, 64-column matrix.

[0039] In step 320, the matrix is ​​compressed using a preset matrix compression method.

[0040] Compress the matrix using any of the following matrix compression methods:

[0041] The matrix is ​​compressed using a matrix compression method based on a triplet sequential list;

[0042] The matrix is ​​compressed using a matrix compression method based on a sequential list with row logical links;

[0043] The matrix is ​​compressed using a cross-linked list method.

[0044] (1) As Figure 4a As shown, the matrix compression method using a triplet sequential list compresses the matrix by: recording the non-zero elements in the matrix as (row index, column index, element value) triples; and arranging the corresponding triples sequentially according to the order of the non-zero elements in the matrix.

[0045] For example, such as Figure 4b The matrix shown, after being compressed using the matrix compression method of triplet sequential lists, yields the following result: Figure 4c The array shown is the first array. The first array records the (row index, column index, element value) of each non-zero element in the matrix.

[0046] If the triplet sequential list compression method is used, the space occupied by each triplet is... Let k be the number of non-zero elements in the matrix, then the compression efficiency is:

[0047]

[0048] For example, if m = 2, the space occupied by each triplet is Let k be the number of non-zero elements in the matrix, then the compression efficiency is:

[0049]

[0050] The smaller k is, the sparser the matrix is, the higher the compression efficiency.

[0051] (2) The matrix compression method using a sequential list with row logical links includes: recording the non-zero elements in the matrix as triples of (row index, column index, element value); arranging the corresponding triples in the order of the non-zero elements in the matrix and storing them in a first array; and using a second array to record the storage position of the first non-zero element in each row of the matrix in the first array.

[0052] The implementation process of a row-order logically linked sequential list is similar to that of a triplet sequential list, but to improve the efficiency of data retrieval, the former uses an additional array (a second matrix) when storing the matrix. For example, as... Figure 4b The matrix shown, after being compressed using a matrix compression method with row-logical linked sequential lists, yields the following result: Figure 4c The array shown (first array) and as shown Figure 4d The array shown is the second array.

[0053] (3) A matrix compression method using a cross-linked list approach, comprising the following steps to compress the matrix: Figure 4e As shown, each row and column of the matrix is ​​stored using a linked list. The heads of all row linked lists are stored in a third array (rhead), and the heads of all column linked lists are stored in a fourth array (chead). For example... Figure 4f As shown, the information of each node in the linked list includes row index, column index, element value, and two pointer fields. The two pointer fields are used to link to the next element in the current row and the next element in the current column, respectively.

[0054] In step 330, the compression result of the matrix replaces the segment list and is encoded into the SRv6 header.

[0055] The above embodiments implement a matrix-based SRv6 header compression method, which has good versatility and can avoid the network planning problems and limitations of the G-SRv6 header compression method.

[0056] Figure 5 This is a schematic diagram of the structure of the SRv6 head compression device according to some embodiments of this disclosure.

[0057] like Figure 5 As shown, the SRv6 head compression device 500 of this embodiment includes modules 510-530.

[0058] Matrix conversion module 510 is configured to convert the segment list in the SRv6 header into a matrix.

[0059] Compression module 520 is configured to compress the matrix using a preset matrix compression method.

[0060] Encoding module 530 is configured to replace the segment list with the compression result of the matrix and encode it into the SRv6 header.

[0061] Matrix transformation module 510 is configured to: extract the segment list from the SRv6 header, the segment list comprising n segments, each segment being a 128-bit IPv6 address; and transform each of the n segments into a single segment. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns.

[0062] For example, extract the segment list from the SRv6 header. The segment list includes n segments, each segment being a 128-bit IPv6 address; m=2, divide each of the n segments into 4 bits as an element, resulting in 32 elements for each segment; and arrange all the elements of the n segments into an n-row, 32-column matrix.

[0063] For example, extract the segment list from the SRv6 header. The segment list includes n segments, each segment being a 128-bit IPv6 address; m=1, divide every 2 bits in each of the n segments into an element, resulting in 64 elements for each segment; and arrange all the elements of the n segments into an n-row, 64-column matrix.

[0064] Compression module 520 is configured to compress the matrix using any of the following matrix compression methods:

[0065] The matrix is ​​compressed using a matrix compression method based on a triplet sequential list;

[0066] The matrix is ​​compressed using a matrix compression method based on a sequential list with row logical links;

[0067] The matrix is ​​compressed using a cross-linked list method.

[0068] Figure 6 This is a schematic diagram of the structure of the SRv6 head compression device according to other embodiments of this disclosure.

[0069] like Figure 6 As shown, the SRv6 header compression apparatus 600 of this embodiment includes a memory 610 and a processor 620 coupled to the memory 610. The processor 620 is configured to execute the SRv6 header compression method of any of the foregoing embodiments based on instructions stored in the memory 610.

[0070] For example, the segment list in the SRv6 header is converted into a matrix; the matrix is ​​compressed using a preset matrix compression method; the compressed result of the matrix replaces the segment list and is encoded into the SRv6 header.

[0071] For example, converting the segment list in the SRv6 header into a matrix includes: extracting the segment list from the SRv6 header, where the segment list consists of n segments, each a 128-bit IPv6 address; and then dividing each of the n segments into a matrix. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns.

[0072] For example, the matrix can be compressed using any of the following matrix compression methods: matrix compression using a triplet sequential list; matrix compression using a row-logical linked sequential list; or matrix compression using a cross-linked list.

[0073] The memory 610 may include, for example, system memory, fixed non-volatile storage media, etc. The system memory may store, for example, the operating system, application programs, boot loader, and other programs.

[0074] The device 600 may also include an input / output interface 630, a network interface 640, and a storage interface 650. These interfaces 630, 640, and 650, as well as the memory 610 and processor 620, can be connected, for example, via a bus 660. The input / output interface 630 provides a connection interface for input / output devices such as a monitor, mouse, keyboard, and touchscreen. The network interface 640 provides a connection interface for various networked devices. The storage interface 650 provides a connection interface for external storage devices such as SD cards and USB flash drives.

[0075] Some embodiments of this disclosure propose a non-transitory computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps of an SRv6 header compression method.

[0076] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more non-transitory computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer program code.

[0077] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0078] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0079] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0080] The above description is only a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. An SRv6 header compression method, characterized in that, include: Convert the segment list in the SRv6 header into a matrix, including: extracting the segment list from the SRv6 header, where the segment list consists of n segments, each a 128-bit IPv6 address; and separating each of the n segments into a matrix. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns; The matrix is ​​compressed using a preset matrix compression method, which includes any one of the following: a matrix compression method using a triplet sequential list, a matrix compression method using a sequential list linked by row logic, and a matrix compression method using a cross-linked list. The compression result of the matrix replaces the segment list and is encoded into the SRv6 header.

2. The method according to claim 1, characterized in that, Converting the segment list in the SRv6 header into a matrix includes: Extract the segment list from the SRv6 header. The segment list consists of n segments, each of which is a 128-bit IPv6 address. Divide each of the n segments into 4 bits and assign it as an element, resulting in 32 elements per segment; Arrange all the elements of the n segments into an n-row, 32-column matrix.

3. The method according to claim 1, characterized in that, The matrix compression method using triplet sequential lists includes the following steps: The non-zero elements in the matrix are recorded as triples of (row index, column index, element value); Arrange the corresponding triplets in the order of their non-zero elements in the matrix.

4. The method according to claim 1, characterized in that, The matrix compression method using a row-logical linked sequential list includes the following steps to compress the matrix: The non-zero elements in the matrix are recorded as triples of (row index, column index, element value); Arrange the corresponding triplets in the first array according to the order of the non-zero elements in the matrix; The second array is used to record the storage position of the first non-zero element in each row of the matrix within the first array.

5. The method according to claim 1, characterized in that, The matrix compression method using the cross-linked list approach includes the following steps to compress the matrix: Each row and column of the matrix is ​​stored in a linked list. The head of each row linked list is stored in a third array, and the head of each column linked list is stored in a fourth array. The information of each node in the linked list includes row index, column index, element value, and two pointer fields. The two pointer fields are used to link to the next element in the current row and the next element in the current column, respectively.

6. An SRv6 head compression device, characterized in that, include: Memory; as well as A processor coupled to the memory, the processor being configured to execute the SRv6 header compression method of any one of claims 1-5 based on instructions stored in the memory.

7. An SRv6 head compression device, characterized in that, include: The matrix conversion module is configured to convert the segment list in the SRv6 header into a matrix, including: extracting the segment list from the SRv6 header, the segment list consisting of n segments, each segment being a 128-bit IPv6 address; and converting each of the n segments into a matrix. m Each bit (0 <= m <= 7) is divided into an element, and each segment yields 128 / 2. m =2 7-m One element; arrange all elements of n segments into n rows. 7-m A matrix of columns; The compression module is configured to compress the matrix using a preset matrix compression method, wherein the matrix compression method includes any one of the following: a matrix compression method using a triplet sequential list, a matrix compression method using a sequential list linked by row logic, and a matrix compression method using a cross-linked list. The encoding module is configured to replace the segment list with the compressed result of the matrix and encode it into the SRv6 header.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the SRv6 header compression method according to any one of claims 1-5.

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