Video processing apparatus, video processing method, and display system

Abstract

A video processing device, a video processing method and a display system are disclosed. The video processing device comprises M processing modules, each of the M processing modules is configured to process image data of one sub-image of a to-be-displayed video image; the to-be-displayed video image comprises M sub-images; each of the M processing modules comprises an acquisition submodule, a write memory submodule, a cache submodule, a read memory submodule and a sending submodule; the acquisition submodule is configured to acquire N pieces of image data of the sub-image; the write memory submodule is configured to write the N pieces of image data of the sub-image into the cache submodule in parallel; the read memory submodule comprises K*N reading ports, and the read memory submodule is configured to read the N pieces of image data stored in the cache submodule in parallel by using the K*N reading ports and repeatedly reading K times; and the sending submodule is configured to send the image data read by the read memory submodule to a display module.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a video processing apparatus and method, and a display system. Background Technology

[0002] With the development of ultra-high-definition display systems, the resolution and frame rate of display modules are getting higher and higher, but current video processing chips can only support display modules with lower frame rates. Summary of the Invention

[0003] This disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a video processing apparatus, a video processing method, and a display system.

[0004] To achieve the above objectives, this disclosure provides a video processing apparatus, comprising M processing modules, each of the M processing modules being configured to process image data of a sub-image of a video image to be displayed, and different processing modules processing image data of different sub-images; the video image to be displayed includes the M sub-images;

[0005] Each of the M processing modules includes: an acquisition submodule, a memory write submodule, a cache submodule, a memory read submodule, and a sending submodule; wherein,

[0006] The acquisition submodule is configured to acquire N channels of image data of the sub-image;

[0007] The write memory submodule is configured to write N-channel image data of the sub-image into the cache submodule in parallel;

[0008] The caching submodule is configured to cache N-channel image data of the sub-image;

[0009] The read memory submodule includes K*N read ports. The read memory submodule is configured to use the K*N read ports to read the N channels of image data stored in the cache submodule in parallel, and repeat the reading K times.

[0010] The sending submodule is configured to send the image data read by the memory reading submodule to the display module;

[0011] Where M and N are both positive integers, and K is an integer greater than 1.

[0012] In some embodiments, when the read memory submodule reads the sub-image data of the video image to be displayed in the i-th frame from the cache submodule, the data written by the write memory submodule to the cache submodule is: the image data of the sub-image of the video image to be displayed in the (i+j-th)-th frame;

[0013] Where i and j are both positive integers, and j takes a fixed value.

[0014] In some embodiments, the caching submodule includes multiple cache areas, each cache area being used to cache the image data of the sub-image, and the image data of the same sub-image is cached in the same cache area;

[0015] The write memory submodule includes:

[0016] The write control unit is configured to acquire a write address;

[0017] The data writing unit is configured to write the image data of the sub-image to the corresponding buffer according to the write address;

[0018] The memory read submodule includes:

[0019] The read control unit is configured to acquire a read address;

[0020] The data reading unit is configured to read the image data of the sub-image stored in the corresponding buffer according to the read address.

[0021] In some embodiments, M > 1, one of the M processing modules is the master processing module, and the rest are slave processing modules;

[0022] The write control unit in the main processing module is specifically configured to obtain the write address according to a preset read / write rule and send the obtained write address to each slave processing module; the write address obtained by the write control unit in the slave processing module is the write address sent by the write control unit of the main processing module.

[0023] The read control unit in the main processing module is specifically configured to obtain the read address according to the preset read / write rules and send the read address to each slave processing unit; the read address obtained by the read control unit in the slave processing module is the read address sent by the read control unit of the main processing module.

[0024] In some embodiments, M > 1, one of the M processing modules is the master processing module, and the rest are slave processing modules;

[0025] The main processing module's memory read submodule is further configured to send a trigger signal to the slave processing module at the start of reading the image data of each frame of video image to be displayed. This trigger signal is used to trigger the memory read submodule in the slave processing module to read the image data of the sub-image.

[0026] In some embodiments, M > 1, one of the M processing modules is the master processing module, and the rest are slave processing modules;

[0027] The main processing module further includes a clock buffer unit, which is configured to generate an in-phase first clock signal and a second clock signal based on the accompanying clock signal.

[0028] The accompanying clock signal and each of the N channels of image data are obtained by deserializing the original display data of the sub-image. The read memory submodule in the main processing module reads the image data according to the first clock signal, and the read memory submodule in the slave processing module reads the image data according to the second clock signal.

[0029] In some embodiments, the acquisition submodule of each of the M processing modules is further configured to handshake with the system chip before acquiring the image data of the sub-image of the first frame of the video image to be displayed;

[0030] The sending submodule of each of the M processing modules is further configured to: handshake with the display module before sending the image data of the sub-image of the first frame of the video image to be displayed to the display module.

[0031] This disclosure also provides a video processing method applied to a video processing device, the video processing device comprising: M processing modules, each of the M processing modules corresponding to a sub-image of a video image to be displayed, and different processing modules corresponding to different sub-images; the video image to be displayed includes the M sub-images; each of the M processing modules includes: an acquisition sub-module, a memory write sub-module, a cache sub-module, a memory read sub-module, and a transmission sub-module;

[0032] The method includes: for each frame of video image to be displayed, processing the image data of the corresponding sub-image using each of the processing modules;

[0033] The process by which any of the processing modules processes the image data of the corresponding sub-image includes:

[0034] The acquisition submodule acquires N-channel image data of the sub-image;

[0035] The write memory submodule writes the N-way image data of the sub-image into the cache submodule in parallel, so that the cache submodule caches the N-way image data of the sub-image;

[0036] The K*N read ports of the read memory submodule read the N channels of image data stored in the cache submodule in parallel, and repeat the reading K times.

[0037] The sending submodule sends the image data read by the reading submodule to the display module;

[0038] Where M and N are both positive integers, and K is an integer greater than 1.

[0039] In some embodiments, when the read memory submodule reads the sub-image data of the video image to be displayed in the i-th frame from the cache submodule, the data written by the write memory submodule to the cache submodule is: the image data of the sub-image of the video image to be displayed in the (i+j-th)-th frame;

[0040] Where i and j are both positive integers, and j takes a fixed value.

[0041] In some embodiments, the caching submodule includes multiple cache areas, each cache area being used to cache image data of the sub-image, with image data of the same sub-image cached in the same cache area; the write memory submodule includes: a write control unit and a data writing unit.

[0042] The write memory submodule writes N-channel image data of the sub-image into the cache submodule in parallel, specifically including:

[0043] The write control unit obtains the write address;

[0044] The data writing unit writes the image data of the sub-image to the corresponding cache area according to the write address;

[0045] The K*N read ports of the memory read submodule read the N channels of image data stored in the cache submodule in parallel, specifically including:

[0046] The read control unit obtains the read address;

[0047] The K*N read ports of the data reading unit read the image data of the sub-images stored in the corresponding buffer according to the read address.

[0048] In some embodiments, M > 1, one of the M processing modules is the master processing module, and the rest are slave processing modules;

[0049] The write control unit in the main processing module obtains the write address according to the preset read / write rules and sends the obtained write address to each slave processing module; the write address obtained by the write control unit in the slave processing module is the write address sent by the write control unit of the main processing module.

[0050] The read control unit in the main processing module obtains the read address according to the preset read / write rules and sends the read address to each slave processing unit; the read address obtained by the read control unit in the slave processing module is the read address sent by the read control unit of the main processing module.

[0051] In some embodiments, M > 1, one of the M processing modules is the master processing module, and the rest are slave processing modules;

[0052] The main processing module's process for processing the image data of the corresponding sub-images also includes:

[0053] At the start of reading the image data of each frame of video image to be displayed, the read memory submodule in the main processing module sends a trigger signal to the slave processing module. The trigger signal is used to trigger the read memory submodule in the slave processing module to read the image data of the sub-image.

[0054] In some embodiments, M > 1, one of the M processing modules is a master processing module, and the rest are slave processing modules; the master processing module further includes a clock buffer unit.

[0055] The main processing module's process for processing the image data of the corresponding sub-images also includes:

[0056] The clock buffer unit generates a first clock signal and a second clock signal in phase according to the accompanying clock signal, and sends the first clock signal to the read memory submodule of the main processing module and sends the second clock signal to the read memory submodule of the slave processing module.

[0057] The accompanying clock signal and each of the N channels of image data are obtained by deserializing the original display data of the sub-image. The read memory submodule in the main processing module reads the image data according to the first clock signal, and the read memory submodule in the slave processing module reads the image data according to the second clock signal.

[0058] In some embodiments, the method includes:

[0059] Before acquiring the image data of the sub-image of the first frame of the video image to be displayed, the acquisition submodule performs a handshake with the system chip;

[0060] Before sending the image data of the sub-image of the first frame of the video image to be displayed, the sending submodule performs a handshake with the display module.

[0061] This disclosure also provides a display system, including: a display module, a system chip, and the aforementioned video processing device.

[0062] The system chip is configured to send the original display data of each sub-image of the video image to be displayed to the corresponding processing module, wherein the image data of the sub-image is obtained based on the original display data;

[0063] The display module is configured to display image data output by each processing module. Attached Figure Description

[0064] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0065] Figure 1 This is a schematic diagram of a video processing apparatus provided in some embodiments of the present disclosure.

[0066] Figure 2 for Figure 1 A specific implementation of the video processing device shown.

[0067] Figure 3 This is a schematic diagram of a video processing apparatus provided in some other embodiments of the present disclosure.

[0068] Figure 4 This is a schematic diagram illustrating the process by which the processing module provided in some embodiments of this disclosure processes the image data of the corresponding sub-image.

[0069] Figure 5 This is a schematic diagram of a display system provided in some embodiments of the present disclosure. Detailed Implementation

[0070] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0071] Figure 1 This is a schematic diagram of a video processing apparatus provided in some embodiments of the present disclosure, such as... Figure 1 As shown, the video processing apparatus includes M processing modules 100. Each processing module 100 is configured to process image data of a sub-image Im of the video image to be displayed, and different processing modules 100 process image data of different sub-images; the video image to be displayed includes M sub-images Im.

[0072] It should be noted that M can be 1 or an integer greater than 1. When M = 1, the entire video image to be displayed is considered as a sub-image Im; when M > 1, the sub-image Im is at least a portion of the video image to be displayed. For example, when M = 4, each sub-image Im is 1 / 4 of the video image to be displayed. The image data of the sub-image Im includes pixel data, which includes R, G, and B values.

[0073] Each processing module 100 includes: an acquisition submodule 110, a memory write submodule 120, a cache submodule 140, a memory read submodule 130, and a transmission submodule 150. The acquisition submodule 110, memory write submodule 120, memory read submodule 130, and transmission submodule 150 can be integrated into an FPGA.

[0074] The acquisition submodule 110 is configured to acquire N channels of image data from the sub-image Im, where each channel has the same amount of data and N is a positive integer. In some embodiments, the system chip can provide N channels of raw display data for the sub-image, and the acquisition submodule 110 concatenates the raw display data to obtain image data, along with accompanying clock signals, valid data strobe signals, etc. Optionally, the acquisition submodule 110 may include N display data interfaces, each receiving one channel of raw display data.

[0075] The write memory submodule 120 is configured to write N channels of image data of subimage Im to the cache submodule 140 in parallel. For example, the write memory submodule 120 has N write ports, each of which writes one channel of image data to the cache submodule 140, and the N write ports perform data writing in parallel.

[0076] The cache submodule 140 is configured to cache N-channel image data of sub-image Im. Optionally, the cache submodule 140 can cache image data of sub-image Im from multiple frames of video images to be displayed. Optionally, the cache submodule 140 can be DDR (Double Data Rate) memory.

[0077] The read memory submodule 130 includes K*N read ports, where K is an integer greater than 1. The read memory submodule 130 is configured to use the K*N read ports to read N channels of image data of sub-image Im stored in the cache submodule 140 in parallel, and repeat the reading K times.

[0078] The sending submodule 150 is configured to send the image data read by the memory reading submodule 130 to the display module for display.

[0079] In this embodiment, the read memory submodule 130 and the write memory submodule 120 can read and write data based on the same clock signal. When the image data of sub-image Im is written to the cache submodule 140, it is written to the cache submodule 140 in parallel using N write ports. When the read memory submodule 130 reads the image data, it reads in parallel using K*N read ports and reads K times. Therefore, for a frame of video image to be displayed, if the time required to write the image data of sub-image Im of the video image to be displayed to the cache submodule 140 is t, then the time required for the image data of sub-image Im to be read once is t / K, and the time required for it to be read K times is t. In this case, if the system chip provides Q frames of video image data to be displayed to the video processing device, the video processing device can output Q*K frames of video image data to be displayed to the display module, thereby achieving frequency multiplication so that the video processing device can adapt to display modules with higher frame rates.

[0080] In this embodiment, the number of processing modules 100 can be determined based on the resolution of the display module and the resolution of the image that the system chip can process. In one example, the video processing device and the system chip transmit data via the V-BY-ONE transmission protocol. According to the V-BY-ONE transmission protocol, the system chip and the video processing device transmit data via 8 lanes (8 transmission channels). In this case, if the system chip is 4K@60Hz (i.e., the system chip can process images with a resolution of 4K and a frame rate of 60Hz), and the display module is 4K@120Hz (i.e., the display resolution of the display module is 4K and the frame rate is 120Hz), then the video processing device can use one processing module 100, K=2, thereby achieving a frequency multiplication effect from 4K@60Hz to 4K@120Hz. If the system chip is 8K@60Hz and the display module is 8K@120Hz, then four processing modules 100 can be used, K=2, thereby achieving a frequency multiplication effect from 8K@60Hz to 8K@120Hz.

[0081] The following section first introduces the specific structure of the video processing device, which includes a processing module 100.

[0082] Figure 2 for Figure 1 A specific implementation of the video processing device shown is as follows: Figure 1 and Figure 2As shown, in some embodiments, the acquisition submodule 110 in each processing module 100 includes a receiving unit 111 and a clock adjustment unit 112. The receiving unit 111 is configured to receive N channels of raw display data of the sub-image Im sent by the system chip, and deserialize the N channels of raw display data to obtain a clock signal and N channels of image data. The clock adjustment unit 112 is configured to perform phase adjustment on the clock signal to align the clock signal with the phase of the image data. It should be noted that the data can be transmitted in the form of a digital signal. Phase alignment of the clock signal with the image data means that the clock signal is phase-aligned with the digital signal corresponding to the image data. For example, the resolution of the video image to be displayed is 3840×2160, and N is 8.

[0083] When there is only one processing module 100, both the write memory submodule 120 and the read memory submodule 130 in the processing module 100 are connected to the clock adjustment unit 112, so that the read memory submodule 130 reads image data under the control of the accompanying clock signal, and the write memory submodule 120 writes image data to the cache submodule 140 under the control of the accompanying clock signal.

[0084] In some embodiments, to ensure stable operation within the processing module 100, image data of sub-images Im of multiple frames of video images to be displayed can be written into the cache sub-module 140 before the read memory sub-module 130 reads the image data of the sub-image Im of the first frame of video images to be displayed. Specifically, when the read memory sub-module 130 reads the image data of the sub-image of the i-th frame of video images to be displayed from the cache sub-module 140, the data written by the write memory sub-module 120 to the cache sub-module 140 is the image data of the sub-image of the (i+j)-th frame of video images to be displayed. Here, i and j are both positive integers, and j takes a fixed value.

[0085] For example, j=3. First, the write memory submodule 120 writes the image data of the sub-images of the first 3 frames of video images to be displayed into the buffer submodule 140; then, the write memory submodule 120 writes the image data of the sub-image of the 4th frame of video images to be displayed into the buffer submodule 140, while the read memory submodule 130 reads the image data of the sub-image of the 1st frame of video images to be displayed, and repeats this reading K times; then, the write memory submodule 120 writes the image data of the sub-image of the 5th frame of video images to be displayed into the buffer submodule 140, while the read memory submodule 130 reads the image data of the sub-image of the 2nd frame of video images to be displayed, and repeats this reading K times; and so on.

[0086] In some embodiments, the caching submodule 140 includes multiple cache areas, each cache area being used to cache image data of sub-image Im, with image data of the same sub-image Im cached in the same cache area. The write memory submodule 120 specifically includes a write control unit 121 and a data writing unit 122, wherein the write control unit 121 is configured to acquire a write address; and the data writing unit 122 is configured to write image data of sub-image Im into the corresponding cache area according to the write address acquired by the write control unit 121.

[0087] The memory read submodule 130 includes a read control unit 132 and a data read unit 131. The read control unit 132 is configured to acquire a read address. The data read unit 131 is configured to read image data stored in the corresponding buffer according to the read address.

[0088] When there is only one processing module 100, the read control unit 132 can obtain the write address according to preset read / write rules, and the write control unit 121 can obtain the read address according to preset read / write rules. For example, the cache submodule 140 includes four cache areas. When the write control unit 121 receives the image data of the first frame of the video image to be displayed, it uses the address of the first cache area as the write address to write the image data of the first frame of the video image to be displayed into the first cache area; when the cache submodule 140 receives the image data of the second frame of the video image to be displayed, it uses the address of the second cache area as the write address to write the image data of the second frame of the video image to be displayed into the second cache area; when the cache submodule 140 receives the image data of the third frame of the video image to be displayed, it uses the address of the third cache area as the write address to write the image data of the third frame of the video image to be displayed. The image data of the fourth frame of the video image to be displayed is written to the third buffer. When the buffer submodule 140 receives the image data of the fourth frame of the video image to be displayed, it uses the address of the fourth buffer as the write address and the address of the first buffer as the read address, thereby writing the image data of the fourth frame of the video image to be displayed to the fourth buffer and reading the image data in the first buffer. When the buffer submodule 140 receives the image data of the fifth frame of the video image to be displayed, it uses the address of the first buffer as the write address and the address of the second buffer as the read address, thereby writing the image data of the fifth frame of the video image to be displayed to the first buffer and reading the image data in the second buffer, and so on.

[0089] In some embodiments, the acquisition submodule 110 in each processing module 100 is further configured to handshake with the system chip before acquiring the image data of the sub-image Im. The transmission submodule 150 in each processing module 100 is further configured to handshake with the display module before sending the image data to the display module.

[0090] Among them, the acquisition sub-module 110 can handshake with the system-on-chip according to V-By-One. The V-By-One standard protocol is specified as follows: The receiving device has two control pins, HTPDN and LOCKN, which are connected to the transmitting device. When the receiving device is powered on, the voltage signals of the two control pins, HTPDN and LOCKN, are set to high level, and the receiving device enters the reset stage; when the reset is completed, the voltage of the HTPDN pin is pulled down, and then it enters the CDR (Clock Data Recovery) training mode. At this time, the transmitting end sends the CDR training mode signal; when the CDR training ends, the voltage signal of the LOCKN pin is pulled down, and it switches from the CDR training mode to the ALN (Alignment) training mode. In the ALN training mode, the transmitting device sends an ALN signal to the receiving device. When the transmitting device sends the ALN signal for a predetermined time, the original display data is sent.

[0091] Among them, when the system-on-chip handshakes with the acquisition sub-module 110, the system-on-chip acts as the transmitting device, and the acquisition sub-module 110 acts as the receiving device. When the transmitting sub-module 150 handshakes with the display module, the transmitting sub-module 150 acts as the transmitting device, and the display module acts as the receiving device.

[0092] Figure 3 It is a schematic diagram of a video processing device provided in some other embodiments of the present disclosure. Figure 3 The video processing device in Figure 3 includes multiple processing modules 100, as Figure 2 shown, one of the multiple processing modules 100 is the main processing module 100m, and the rest are slave processing modules 100s. The main processing module 100m and the slave processing modules 100s are both similar in structure to the processing module 100 shown in Figure 3 and only the Figure 2 differences will be introduced below.

[0093] Exemplarily, the resolution of the video image Im0 to be displayed is 4320×7680, and the video image Im0 to be displayed includes 4 sub-images Im. The number of processing modules 100 is 4. Among them, the "Sichuan" - shaped segmentation method can be used to segment the video image Im0 to be displayed, obtaining four sub-images Im. As Figure 3 shown, the "Sichuan" - shaped segmentation method is: the video image Im0 to be displayed is segmented into four sub-images Im arranged side by side, and the resolution of each sub-image Im is 4320×1920.

[0094] In Figure 3The main processing module 100m further includes an address sending submodule 161, which specifically includes a write address sending interface and a read address sending interface. The write address sending interface is connected to the write control unit 121 of the main processing module 100m, and the read address sending interface is connected to the read control unit 132 of the main processing module 100m. The slave processing module 100s further includes an address receiving submodule 162, which specifically includes a write address receiving interface and a read address receiving interface. The write address receiving interface is connected to the write control unit 121 of the slave processing module 100s, and the read address receiving interface is connected to the read control unit 132 of the slave processing module 100s. The write address receiving interface of each slave processing module 100s is communicatively connected to the write address sending interface of the main processing module 100m, and the read address receiving interface of each slave processing module 100s is communicatively connected to the read address sending interface of the main processing module 100m.

[0095] In each processing module 100, a write control unit 121 is used to acquire a write address; a data writing unit 122 is used to write image data of a sub-image to the corresponding buffer according to the write address; a read control unit 132 is used to acquire a read address; and a data reading unit 131 is used to read image data of a sub-image stored in the corresponding buffer according to the read address. Specifically, for the main processing module 100m, the write control unit 121 acquires the write address according to preset read / write rules and sends the acquired write address to each slave processing module 100s through the write address sending interface; the read control unit 132 acquires the read address according to preset read / write rules and sends the acquired read address to each slave processing module 100s through the read address sending interface. The process by which the write control unit 121 and the read control unit 132 acquire the write address and read address according to the preset read / write rules is described above. For the slave processing module 100s, the write address acquired by the write control unit 121 is the same as the write address sent by the main processing module 100m, and the read address acquired by the read control unit 132 is the same as the read address sent by the main processing module 100m.

[0096] In some embodiments, the main processing module 100m further includes a trigger signal transmitting interface 171; the slave processing module 100s further includes a trigger signal receiving interface 172. The trigger signal receiving interface 172 is communicatively connected to the trigger signal transmitting interface 171.

[0097] The main processing module 100m's memory read submodule 130 is further configured to send a trigger signal to the slave processing module 100s via trigger signal sending interface 171 at the start of reading a sub-image of each frame of the video image Im0 to be displayed. This trigger signal is used to trigger the memory read submodule 130 in the slave processing module 100s to read image data. Through the trigger signal, each processing module 100 can simultaneously read the image data of the same frame of the video image Im0 to be displayed at the same time.

[0098] In some embodiments, the main processing module 100m further includes: a clock output interface 181 and a clock buffer unit 180 connected to the clock output interface 181. The clock buffer unit 180 is also connected to a clock adjustment unit 112 and is configured to generate a first clock signal and a second clock signal in phase according to the accompanying clock signal output by the clock adjustment unit 112. The first clock signal is sent to the read memory submodule 130 of the main processing module 100m, thereby enabling the read memory submodule 130 of the main processing module 100m to read image data according to the first clock signal. The slave processing module 100s further includes: a clock input interface 182, which is used to receive the second clock signal sent by the clock output interface 181 and transmit the second clock signal to the read memory submodule 130 of the slave processing module 100s, thereby enabling the read memory submodule 130 of the slave processing module 100s to read image data according to the second clock signal.

[0099] In some embodiments, the main processing module 100m further includes a first signal receiving interface 191, and the slave processing module 100s further includes a first signal transmitting interface 192. The first signal receiving interface 191 is used to transmit signals required during the handshake process with the first signal transmitting interface 192. Optionally, multiple processing modules 100 can handshake with the system chip according to the V-By-One protocol. In this case, the handshake process between the multiple processing modules 100 and the system chip includes: the acquisition submodule 110 of each processing module 100 performs a reset in response to a power-on signal, and pulls the HTPDN signal low after the reset is completed. The HTPDN signal of each slave processing module 100s is transmitted to the first signal receiving interface 191 through the first signal transmitting interface 192; when the HTPDN signals of both the main processing module 100m and the slave processing module 100s are pulled low, the main processing module 100m sends a first indication signal to the system chip, so that the system chip sends a CDR training mode signal to each processing module 100 in response to the first indication signal. After receiving the CDR training mode signal, the acquisition submodule 110 of each processing module 100 pulls the LOCKN signal low. When the LOCKN signals of all acquisition submodules 110 of the main processing module 100m are pulled low, the acquisition submodules 110 of the main processing module 100m send a second indication signal to the system chip, so that the system chip responds to the second indication signal and sends an ALN ​​signal to each processing module 100. After the ALN signal is sent for a predetermined time, the system chip sends the original display data of the corresponding sub-image to each processing module 100. Here, the HTPDN signal is the voltage signal output from the HTPDN pin, and the LOCKN signal is the voltage signal output from the LOCKN pin.

[0100] Optionally, multiple processing modules 100 may handshake with the display module according to the V-By-One protocol. In this case, the handshake process between the multiple processing modules 100 and the display module includes: the display module resetting in response to a power-on signal, and sending a low HTPDN signal to the transmitting submodule 150 of the main processing module 100m after the reset; the main processing module 100m responding to the low HTPDN signal and sending a third indication signal to each of the second signal receiving interfaces 194; and each of the transmitting submodules 150 of the slave processing module 100s responding to the power-on signal and the power-on signal. The third indication signal sends a CDR training mode signal to the display module, and the main processing module 100m also sends a CDR training mode signal to the display module. After the display module receives the CDR training mode signal, it sends a low LOCKN signal to the main processing module 100m. In response to the low LOCKN signal, the transmitting submodule 150 of the main processing module 100m sends a fourth indication signal to each slave processing module 100s. After receiving the fourth indication signal, all processing units 100 of the slave processing module 100s simultaneously send image data to the display module.

[0101] This disclosure also provides a video processing method using the aforementioned video processing apparatus. As described above, the video processing apparatus includes M processing modules, each corresponding to a sub-image in a video image to be displayed, with different processing modules corresponding to different sub-images. The video image to be displayed includes M sub-images, where M is a positive integer. Each processing module includes a receiving sub-module, a writing memory sub-module, a buffering sub-module, a reading memory sub-module, and a sending sub-module. The video processing method includes: for each frame of the video image to be displayed, processing the image data of the corresponding sub-image using each of the processing modules.

[0102] Figure 4 This is a schematic diagram illustrating the process by which the processing module provided in some embodiments of this disclosure processes the image data of the corresponding sub-images, such as... Figure 4 As shown, the process by which any processing module processes the image data of the corresponding sub-image includes:

[0103] S11. The acquisition submodule acquires N channels of image data of the sub-image, where N is a positive integer.

[0104] S12. The write memory submodule writes the N-channel image data of the sub-image into the cache submodule in parallel, so that the cache submodule caches the N-channel image data of the sub-image.

[0105] S13. The K*N read ports of the read memory submodule read the N channels of image data stored in the cache submodule in parallel, and repeat the reading K times; K is an integer greater than 1.

[0106] S14. The sending submodule sends the image data read by the reading submodule to the display module.

[0107] In some embodiments, when the read memory submodule reads the sub-image data of the video image to be displayed in the i-th frame from the cache submodule, the data written by the write memory submodule to the cache submodule is: the image data of the sub-image of the video image to be displayed in the (i+j-th frame); where i and j are both positive integers, and j takes a fixed value, for example, j is 3.

[0108] As described above, the caching submodule includes multiple cache areas, each used to cache image data of a sub-image, with image data of the same sub-image cached in the same cache area; the write memory submodule includes a write control unit and a data writing unit. In this case, step S12 includes: S121, the write control unit obtains the write address; S122, the data writing unit writes N channels of image data of the sub-image in parallel into the cache area corresponding to the write address.

[0109] Step S13 includes: S131, the read control unit obtains the read address. S132, the K*N read ports of the data read unit read the image data of the sub-image stored in the corresponding buffer according to the read address.

[0110] In some embodiments, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules. The write control unit in the master processing module obtains the write address according to preset read / write rules and sends the obtained write address to each slave processing module; the write address obtained by the write control unit in the slave processing module is the write address sent by the write control unit of the master processing module. Similarly, the read control unit in the master processing module obtains the read address according to preset read / write rules and sends the read address to each slave processing module. The read address obtained by the read control unit in the slave processing module is the read address sent by the read control unit of the master processing module.

[0111] The process of the main processing module processing the image data of the corresponding sub-image also includes: at the start of reading the image data of each frame of video image to be displayed, the memory reading sub-module in the main processing module sends a trigger signal to the slave processing module. The trigger signal is used to trigger the memory reading sub-module in the slave processing module to read the image data of the sub-image.

[0112] In addition, the process of the main processing module processing the image data of the corresponding sub-images further includes: the clock buffer unit of the main processing module generates a first clock signal and a second clock signal in phase according to the accompanying clock signal, and sends the first clock signal to the read memory submodule of the main processing module, and sends the second clock signal to the read memory submodule of the slave processing module. The accompanying clock signal and each of the N channels of image data are obtained by deserializing the original display data of the sub-image. The read memory submodule of the main processing module reads the image data according to the first clock signal, and the read memory submodule of the slave processing module reads the image data according to the second clock signal.

[0113] In some embodiments, the video processing method further includes: the acquisition submodule performing a handshake with the system chip before acquiring image data of a sub-image of the first frame of the video image to be displayed; and the sending submodule performing a handshake with the display module before sending image data of the sub-image of the first frame of the video image to be displayed. Exemplarily, the acquisition submodule in each processing module can perform a handshake with the system chip according to the V-By-One protocol, and the sending submodule in each processing module can perform a handshake with the display module according to the V-By-One protocol. The specific handshake process can be found in the description above and will not be repeated here.

[0114] This disclosure also provides a display system. Figure 5 A schematic diagram of a display system provided in some embodiments of the present disclosure, as Figure 5 shown, the display system includes: a display module 300, a system chip 200, and the above video processing device.

[0115] Among them, the system chip 200 is configured to send the original display data of each sub-image of the video image to be displayed to the corresponding processing module 100, where the image data of the sub-image is obtained according to the original display data. For example, the original display data includes: serial image data, timing data, and control data. The image data includes pixel data, and the pixel data may include R, G, B values. The timing data includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a valid data strobe signal (DE). The control data includes a clock signal on the same path. By deserializing the original display data, the image data can be obtained.

[0116] In some embodiments, the video image to be displayed may include one sub-image; in other embodiments, the video image to be displayed includes multiple sub-images. For example, it includes four sub-images, and among them, the "Sichuan" - shaped segmentation method can be used to segment the video image to be displayed to obtain four sub-images.

[0117] The display module 300 is configured to display according to the image data output by each processing module 100. In the embodiments of the present disclosure, the display module 300 can especially adopt an ultra - high - definition display module, for example, a 4K display module, an 8K display module.

[0118] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A video processing apparatus, characterized in that, The video processing device is configured to multiply the frequency of the Q-frame video image data to be displayed sent by the system chip to generate... The video processing device includes M processing modules, each of which is configured to process the image data of a sub-image of the video image to be displayed, and different processing modules process the image data of different sub-images. The video image to be displayed includes M sub-images, where M is the total number of sub-images in the video image to be displayed; each of the processing modules reads the image data of the same frame of the video image to be displayed at the same time. Each of the M processing modules includes: an acquisition submodule, a memory write submodule, a cache submodule, a memory read submodule, and a sending submodule; wherein, The acquisition submodule is configured to acquire N channels of image data of the sub-image, wherein the amount of data in each channel of image data is the same; The write memory submodule is configured to write N-channel image data of the sub-image into the cache submodule in parallel; The caching submodule is configured to cache N-channel image data of the sub-image; The read memory submodule includes The read memory submodule is configured to utilize the read port. Each read port reads the N channels of image data stored in the cache submodule in parallel, and repeats the reading K times; the read memory submodule and the write memory submodule read and write data based on the same frequency clock signal, so that the time required for the image data of one sub-image to be read once reaches t / K, where t is the time required for the image data of the sub-image to be written to the cache submodule; The sending submodule is configured to send the image data read by the memory reading submodule to the display module; Where M and N are both positive integers, and K is an integer greater than 1.

2. The video processing apparatus according to claim 1, characterized in that, When the read memory submodule reads the sub-image data of the i-th frame of the video image to be displayed from the cache submodule, the data written by the write memory submodule to the cache submodule is: the image data of the sub-image of the (i+j-th frame of the video image to be displayed); Where i and j are both positive integers, and j takes a fixed value.

3. The video processing apparatus according to claim 1 or 2, characterized in that, The caching submodule includes multiple cache areas, each cache area is used to cache the image data of the sub-image, and the image data of the same sub-image is cached in the same cache area; The write memory submodule includes: The write control unit is configured to acquire a write address; The data writing unit is configured to write the image data of the sub-image to the corresponding buffer according to the write address; The memory read submodule includes: The read control unit is configured to acquire a read address; The data reading unit is configured to read the image data of the sub-image stored in the corresponding buffer according to the read address.

4. The video processing apparatus according to claim 3, characterized in that, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules; The write control unit in the main processing module is specifically configured to obtain the write address according to a preset read / write rule and send the obtained write address to each slave processing module; the write address obtained by the write control unit in the slave processing module is the write address sent by the write control unit of the main processing module. The read control unit in the main processing module is specifically configured to obtain the read address according to the preset read / write rules and send the read address to each slave processing unit; the read address obtained by the read control unit in the slave processing module is the read address sent by the read control unit of the main processing module.

5. The video processing apparatus according to claim 1 or 2, characterized in that, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules; The main processing module's memory read submodule is further configured to send a trigger signal to the slave processing module at the start of reading the image data of each frame of video image to be displayed. This trigger signal is used to trigger the memory read submodule in the slave processing module to read the image data of the sub-image.

6. The video processing apparatus according to claim 1 or 2, characterized in that, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules; The main processing module further includes a clock buffer unit, which is configured to generate an in-phase first clock signal and a second clock signal based on the accompanying clock signal. The accompanying clock signal and each of the N channels of image data are obtained by deserializing the original display data of the sub-image. The read memory submodule in the main processing module reads the image data according to the first clock signal, and the read memory submodule in the slave processing module reads the image data according to the second clock signal.

7. The video processing apparatus according to claim 1 or 2, characterized in that, The acquisition submodule of each of the M processing modules is further configured to handshake with the system chip before acquiring the image data of the sub-image of the first frame of the video image to be displayed; The sending submodule of each of the M processing modules is further configured to: handshake with the display module before sending the image data of the sub-image of the first frame of the video image to be displayed to the display module.

8. A video processing method applied to a video processing device, characterized in that, The video processing device is configured to multiply the frequency of the Q-frame video image data to be displayed sent by the system chip to generate... The video processing device receives data of a frame of video image to be displayed and sends it to the display module. The video processing device includes M processing modules, each corresponding to a sub-image in the video image to be displayed, with different processing modules corresponding to different sub-images. The video image to be displayed includes M sub-images, where M is the total number of sub-images in the video image to be displayed. Each processing module reads image data of the same frame of video image to be displayed simultaneously. Each of the M processing modules includes: an acquisition sub-module, a memory write sub-module, a cache sub-module, a memory read sub-module, and a sending sub-module. The method includes: for each frame of video image to be displayed, processing the image data of the corresponding sub-image using each of the processing modules; The process by which any of the processing modules processes the image data of the corresponding sub-image includes: The acquisition submodule acquires N channels of image data for the sub-image, with each channel of image data having the same amount of data. The write memory submodule writes the N-way image data of the sub-image into the cache submodule in parallel, so that the cache submodule caches the N-way image data of the sub-image; The read memory submodule Each read port reads the N channels of image data stored in the cache submodule in parallel, and repeats the reading K times; the read memory submodule and the write memory submodule read and write data based on the same frequency clock signal, so that the time required for the image data of one sub-image to be read once reaches t / K, where t is the time required for the image data of the sub-image to be written to the cache submodule; The sending submodule sends the image data read by the memory reading submodule to the display module; Where M and N are both positive integers, and K is an integer greater than 1.

9. The method according to claim 8, characterized in that, When the read memory submodule reads the sub-image data of the i-th frame of the video image to be displayed from the cache submodule, the data written by the write memory submodule to the cache submodule is: the image data of the sub-image of the (i+j-th frame of the video image to be displayed); Where i and j are both positive integers, and j takes a fixed value.

10. The method according to claim 8 or 9, characterized in that, The caching submodule includes multiple cache areas, each cache area is used to cache the image data of the sub-image, and the image data of the same sub-image is cached in the same cache area; The write memory submodule includes: a write control unit and a data writing unit. The write memory submodule writes N-channel image data of the sub-image into the cache submodule in parallel, specifically including: The write control unit obtains the write address; The data writing unit writes the image data of the sub-image to the corresponding cache area according to the write address; The read memory submodule includes a read control unit and a data reading unit. Each read port reads the N channels of image data stored in the cache submodule in parallel, specifically including: The read control unit obtains the read address; The data reading unit Each read port reads the image data of the sub-image stored in the corresponding buffer according to the read address.

11. The method according to claim 10, characterized in that, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules; The write control unit in the main processing module obtains the write address according to the preset read / write rules and sends the obtained write address to each slave processing module; the write address obtained by the write control unit in the slave processing module is the write address sent by the write control unit of the main processing module. The read control unit in the main processing module obtains the read address according to the preset read / write rules and sends the read address to each slave processing unit; the read address obtained by the read control unit in the slave processing module is the read address sent by the read control unit of the main processing module.

12. The method according to claim 8 or 9, characterized in that, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules; The main processing module's process for processing the image data of the corresponding sub-images also includes: At the start of reading the image data of each frame of video image to be displayed, the read memory submodule in the main processing module sends a trigger signal to the slave processing module. The trigger signal is used to trigger the read memory submodule in the slave processing module to read the image data of the sub-image.

13. The method according to claim 8 or 9, characterized in that, M > 1, where one of the M processing modules is the master processing module and the rest are slave processing modules; the master processing module also includes a clock buffer unit; The main processing module's process for processing the image data of the corresponding sub-images also includes: The clock buffer unit generates a first clock signal and a second clock signal in phase according to the accompanying clock signal, and sends the first clock signal to the read memory submodule of the main processing module and sends the second clock signal to the read memory submodule of the slave processing module. The accompanying clock signal and each of the N channels of image data are obtained by deserializing the original display data of the sub-image. The read memory submodule in the main processing module reads the image data according to the first clock signal, and the read memory submodule in the slave processing module reads the image data according to the second clock signal.

14. The method according to claim 8 or 9, characterized in that, The method includes: Before acquiring the image data of the sub-image of the first frame of the video image to be displayed, the acquisition submodule performs a handshake with the system chip; Before sending the image data of the sub-image of the first frame of the video image to be displayed, the sending submodule performs a handshake with the display module.

15. A display system, characterized in that, include: The display module, the system chip, and the video processing apparatus according to any one of claims 1 to 7 The system chip is configured to send the original display data of each sub-image of the video image to be displayed to the corresponding processing module, wherein the image data of the sub-image is obtained based on the original display data; The display module is configured to display image data output by each processing module.

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