Memory system and method of controlling the same

Abstract

Embodiments achieve a memory system capable of seeking to reduce the amount of memory resources consumed by a write buffer and a control method thereof. The memory system receives a first write request from a host, the first write request including a first block identifier specifying a first write target block to which first write data is to be written. The memory system acquires the first write data from a write buffer that temporarily holds write data corresponding to each write request, and writes the first write data to a write target page within the first write target block. The memory system releases an area within the write buffer that stores data of a page within the first write target block that precedes the write target page and that is able to be read from the first write target block by writing the first write data to the write target page.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on July 27, 2018, with application number 201810846006.9 and title "Memory System and Control Method Thereof".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2018-14794 (filed on January 31, 2018). This application incorporates the entire contents of that basic application by reference. Technical Field

[0005] The embodiments of the present invention relate to a memory system having non-volatile memory and a control method thereof. Background Technology

[0006] In recent years, memory systems with non-volatile memory have become increasingly popular. One such memory system is the solid-state drive (SSD) based on NAND (Not And) flash memory technology.

[0007] SSDs are also used as storage devices for servers in data centers.

[0008] Storage devices used in host computer systems such as servers require high I / O (Input / Output) performance.

[0009] Therefore, recently, new interfaces between host and storage devices have begun to be proposed.

[0010] In addition, there are situations where modern storage devices require the ability to write different types of data to different write target blocks.

[0011] However, if the number of write target blocks that can be used simultaneously increases, the amount of data that needs to be saved to the write buffer increases, thus increasing the amount of memory resources consumed by the write buffer. Typically, the amount of memory resources available for use as a write buffer is limited, so there is a need to implement techniques designed to reduce the amount of memory resources consumed by the write buffer. Summary of the Invention

[0012] The present invention provides a memory system and its control method that can reduce the amount of memory resources consumed by the write buffer.

[0013] According to an embodiment, a memory system connectable to a host includes: a non-volatile memory comprising a plurality of blocks; and a controller electrically connected to the non-volatile memory, configured to manage a plurality of write target blocks allocated from the plurality of blocks, and to write data to each write target block in order from the first page to the last page. One page of data written to a write target block can be read out after data has been written to one or more subsequent pages of the write target block. Each write request received from the host includes a block identifier specifying the write target block to which the write data should be written. The controller receives a first write request from the host, the first write request including a first block identifier specifying the first write target block to which the first write data should be written. The controller retrieves the first write data from a write buffer that temporarily stores the write data corresponding to each write request. The controller writes the first write data to a write target page within the first write target block. The controller notifies the host of the page address of the write target page to which the first write data has been written. The controller increments the page address within the first write target block to which the next data should be written by one page. The controller releases the area in the write buffer that stores data of pages in the first write target block that precede the write target page and can be read from the first write target block by writing the first write data to the write target page. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating the relationship between the host and the memory system (flash storage device) of the implementation method.

[0015] Figure 2 This is a block diagram illustrating an example configuration of the memory system in this embodiment.

[0016] Figure 3 This is a block diagram illustrating the relationship between the multiple channels and multiple NAND flash memory chips used in the memory system of this embodiment.

[0017] Figure 4 This is a diagram illustrating an example of the configuration of a superblock used in the memory system of this embodiment.

[0018] Figure 5 This is a block diagram illustrating the relationship between the active block pool, the free block pool, and multiple write target blocks managed by the memory system of this embodiment.

[0019] Figure 6 This diagram illustrates the data write operation where the host specifies the target block to be written and the memory system of this embodiment determines the target page to be written, as well as the data read operation where the host specifies the block address and page address.

[0020] Figure 7 This diagram illustrates the block allocation instructions (block allocation requests) used in the memory system of this embodiment.

[0021] Figure 8 It is a diagram used to illustrate the response to block allocation instructions.

[0022] Figure 9 This diagram illustrates the write instructions used in the memory system of this embodiment.

[0023] Figure 10 It is a diagram used to illustrate the response to a write command.

[0024] Figure 11 This is a diagram used to illustrate the read instructions applied in the memory system of this embodiment.

[0025] Figure 12 This is a sequence diagram showing the order of write processes performed by the host and the memory system of this embodiment.

[0026] Figure 13 It is a diagram used to illustrate the action of releasing a region in a write buffer, which stores data that can be read from a write target block by writing data to that write target block.

[0027] Figure 14 It is a diagram that shows the state in which multiple areas within the write buffer are all used to store the written data.

[0028] Figure 15 It is a diagram used to illustrate the action of releasing a region in a write buffer, which stores data that can be read from a write target block by writing virtual data to that write target block.

[0029] Figure 16 This is a diagram used to illustrate an example of multi-stage programming actions.

[0030] Figure 17 It is represented in chronological order. Figure 16 A timing diagram of fuzzy-to-fine programming actions.

[0031] Figure 18 This is a flowchart illustrating the sequence of virtual data write operations performed by the memory system of this embodiment when there are no unused areas in the write buffer.

[0032] Figure 19 This is a flowchart illustrating the sequence of virtual data write operations performed by the memory system of this embodiment when it is detected that a specific number of pages of data have not been written at each specific period.

[0033] Figure 20 This is a diagram illustrating an example of the configuration of the write order management table managed by the memory system of this embodiment. Detailed Implementation

[0034] The embodiments will now be described with reference to the accompanying drawings.

[0035] First, refer to Figure 1 This explains the relationship between the memory system and the host in this embodiment.

[0036] This memory system is a semiconductor memory device configured to write data to and read data from non-volatile memory. This memory system is implemented as a flash memory device 3 based on NAND flash memory technology.

[0037] The host (host device) 2 is configured to control multiple flash storage devices 3. The host 2 is implemented as an information processing device that uses a flash memory array consisting of multiple flash storage devices 3 as its memory. This information processing device can be a personal computer or a server computer.

[0038] Furthermore, the flash storage device 3 can also be used as one of multiple storage devices disposed within a memory array. The memory array can also be connected to an information processing device such as a server computer via cable or network. The memory array includes a controller that controls multiple memories (e.g., multiple flash storage devices 3) within the memory array. When the flash storage device 3 is used in the memory array, the controller of the memory array can also function as the host of the flash storage device 3.

[0039] The following description illustrates an example of an information processing device, such as a server computer, functioning as host 2.

[0040] The host (server) 2 is interconnected with multiple flash storage devices 3 via interface 50 (internal interconnection). The interface 50 used for this interconnection is not limited to this; it may include PCI Express (Peripheral Component Interconnect Express) (PCIe) (registered trademark), NVM Express (Non-Volatile Memory Express) (NVMe) (registered trademark), Ethernet (registered trademark), NVMe over Fabrics (NVMeOF), etc.

[0041] As a typical example of a server computer that functions as host 2, a server computer (hereinafter referred to as a server) in a data center can be cited.

[0042] In an instance where host 2 is implemented via a server within a data center, host 2 can also be connected to multiple end-user terminals (clients) 61 via network 51. Host 2 is able to provide various services to these end-user terminals 61.

[0043] Examples of services that host (server) 2 can provide include (1) Platform as a service (PaaS) which provides a system operating platform to each client (each end user terminal 61); and (2) Infrastructure as a service (IaaS) which provides infrastructure such as virtual servers to each client (each end user terminal 61).

[0044] Multiple virtual machines can also run on the physical server that functions as host (server) 2. Each of these virtual machines running on host (server) 2 can function as a virtual server that provides various services to several clients (end-user terminals 61) corresponding to that virtual machine.

[0045] The host (server) 2 includes memory management functions for managing multiple flash storage devices 3 that constitute a flash array, and front-end functions for providing various services including memory access to each end user terminal 61.

[0046] Flash storage device 3 includes non-volatile memory such as NAND flash memory. Flash storage device 3 manages multiple write target blocks allocated from multiple blocks within the non-volatile memory. A write target block refers to a block where data should be written. A write request (write instruction) sent from host 2 to flash storage device 3 includes a block identifier specifying a write target block to which data should be written. Flash storage device 3 writes data from host 2 (write data) to the write target block containing that block identifier included in the write request. Therefore, host 2 can specify a particular write target block to which data should be written. For example, host 2 can request storage device 3 to write data from a certain end-user terminal 61 (client) to one or more specific write target blocks corresponding to that end-user terminal 61, or it can request storage device 3 to write data from other end-user terminals 61 (clients) to one or more other specific write target blocks corresponding to that end-user terminal 61.

[0047] The block identifier included in the write request sent from host 2 can also be represented by the block address (block number) specifying a particular target block to be written. Alternatively, in an example where flash storage device 3 includes multiple NAND flash memory chips, the block identifier can also be represented by a combination of the block address (block number) and the chip number.

[0048] Multiple write target blocks managed by flash storage device 3 can be used by multiple end users (clients) who share the flash storage device 3. In this case, the number of write target blocks available in flash storage device 3 is the same as or greater than the number of end users who share the flash storage device 3.

[0049] However, if the number of write target blocks that can be used simultaneously increases, the amount of data that needs to be saved to the write buffer increases, and therefore the amount of memory resources consumed by the write buffer increases.

[0050] Therefore, in this embodiment, the flash storage device 3 performs an action to reduce the amount of memory resources consumed by the write buffer. In this embodiment, a specific storage area on the host 2's memory can be used as the write buffer, or a specific storage area on the random access memory within the flash storage device 3 can be used as the write buffer.

[0051] Figure 2 This shows an example of the configuration of flash memory device 3.

[0052] The flash storage device 3 includes a controller 4 and non-volatile memory (NAND flash memory) 5. The flash storage device 3 may also include random access memory, such as DRAM (Dynamic Random Access Memory) 6.

[0053] The NAND flash memory 5 includes a memory cell array comprising multiple memory cells arranged in a matrix. The NAND flash memory 5 can be a two-dimensional NAND flash memory or a three-dimensional NAND flash memory.

[0054] The NAND flash memory 5's cell array contains multiple blocks piece Each contains multiple pages (pages in this case) ).piece It functions as a unit of deletion. A block is sometimes also called a "delete block," "physical block," or "physical delete block." (Page) It is the unit for data writing and data reading actions.

[0055] Controller 4 is electrically connected to the NAND flash memory 5, which is a non-volatile memory, via a NAND interface 13 such as a toggle or an Open NAND Flash Interface (ONFI). Controller 4 operates as a memory controller configured to control the NAND flash memory 5. Controller 4 can also be implemented using circuitry such as a System-on-a-chip (SoC).

[0056] like Figure 3 As shown, the NAND flash memory 5 can also contain multiple NAND flash memory chips (NAND flash memory dies). Each NAND flash memory chip can operate independently. Therefore, the NAND flash memory chips function as units capable of parallel operation. Figure 3 The example shows 16 channels connected to NAND interface 13. And in 16 channels Each connection is to two NAND flash memory chips. In this case, the connection is in the channel. 16 NAND flash memory chips It can also be composed of storage body #0, and is connected to the channel. The remaining 16 NAND flash memory chips It can also be composed of memory bank #1. The memory bank functions as a unit that enables multiple memory modules to operate in parallel through memory bank interleaving. Figure 3 In this configuration example, up to 32 NAND flash memory chips can operate in parallel by using memory interleaving with 16 channels and 2 memory banks.

[0057] Deletion operations can be performed on a single block (physical block) or on a parallel unit (superblock) comprising a collection of multiple physical blocks capable of parallel operations. A parallel unit, i.e., a superblock containing a collection of multiple physical blocks, is not limited to this and can also include NAND flash memory chips. A total of 32 physical blocks were selected one by one. In addition, NAND flash memory chips... Each can also have a multi-plane configuration. For example, in NAND flash memory chips... In the case of a multi-plane configuration, each containing two planes, a superblock can also contain NAND flash memory chips. A total of 64 physical blocks were selected one by one from the corresponding 64 planes.

[0058] Figure 4The example illustrates a superblock (SB) containing 32 physical blocks (here, physical block BLK2 in NAND flash memory chip #1, physical block BLK3 in NAND flash memory chip #2, physical block BLK7 in NAND flash memory chip #3, physical block BLK4 in NAND flash memory chip #4, physical block BLK6 in NAND flash memory chip #5, ..., physical block BLK3 in NAND flash memory chip #32).

[0059] The target block to be written can be a physical block or a superblock. Alternatively, a superblock can be constructed by containing only one physical block, in which case a superblock is equivalent to a physical block.

[0060] Next, for Figure 2 The configuration of controller 4 will be explained.

[0061] The controller 4 includes a host interface 11, a CPU (Central Processing Unit) 12, a NAND interface 13, and a DRAM interface 14. These CPU 12, NAND interface 13, and DRAM interface 14 are interconnected via a bus 10.

[0062] The host interface 11 is a host interface circuit configured to perform communication with the host 2. The host interface 11 can be, for example, a PCIe controller (NVMe controller). Alternatively, in a configuration where the flash storage device 3 is connected to the host 2 via Ethernet (trademark), the host interface 11 can also be an NVMe over Fabrics (NVMeOF) controller. The configuration where the flash storage device 3 is connected to the host 2 via Ethernet (trademark) allows for easy expansion of the number of flash storage devices 3 as needed. Furthermore, it also allows for easy expansion of the number of hosts 2.

[0063] Host interface 11 receives various requests (instructions) from host 2. These requests (instructions) include write requests (write instructions), read requests (read instructions), and various other requests (instructions).

[0064] CPU 12 is a processor configured with a host interface 11, a NAND interface 13, and a DRAM interface 14. In response to power-on of the flash storage device 3, CPU 12 loads control programming (firmware) from NAND flash memory 5 or ROM (Read Only Memory, not shown) into DRAM 6, and then executes the firmware to perform various processes. Alternatively, firmware can be loaded into SRAM (Static Random-Access Memory, not shown) within controller 4. CPU 12 can perform instruction processing, etc., to process various instructions from host 2. The operation of CPU 12 is controlled by the firmware executed by CPU 12. Furthermore, some or all of the instruction processing can also be performed using dedicated hardware within controller 4.

[0065] CPU12 can function as a write action control unit 21 and a read action control unit 22.

[0066] The write operation control unit 21 manages multiple write target blocks allocated from multiple blocks of the NAND flash memory 5, and writes data to each write target block in order from the first page to the last page.

[0067] In multiple NAND flash memories, a page of data written to a write target block cannot be read from the write target block immediately after it is written, but can be read after data has been written to one or more subsequent pages of the write target block.

[0068] For example, in an instance where data is written to pages of a target block using multi-stage programming actions including Stage 1 and Stage 2, data written to a page (page 1) within the target block via Stage 1 programming can be read after data has been written to one or more subsequent pages via Stage 1 programming. This is because Stage 2 programming for page 1 cannot be performed before data is written to one or more subsequent pages via Stage 1 programming. Therefore, even if data is written to page 1 of the target block via Stage 1 programming, that data cannot be read from the target block immediately after it is written, but can only be read after data has been written to one or more subsequent pages via Stage 1 programming.

[0069] As an example of this multi-stage programming action, fuzzy-to-fine programming can be cited. In fuzzy-to-fine programming, data writing to a group of memory cells connected to the same word line is performed through fuzzy programming, which roughly sets the threshold distribution of each memory cell, and fine programming, which adjusts the threshold distribution of each memory cell. To reduce programming interference between adjacent word lines, fine programming of a group of memory cells connected to a certain word line is performed after fuzzy programming of the group of memory cells connected to adjacent word lines.

[0070] Therefore, in instances where data is written via fuzzy-to-fine programming, even if fuzzy programming is performed on the group of memory cells connected to the initial word line (WL0) within the target block, fine programming cannot be performed on the group of memory cells connected to the initial word line (WL0) before the fuzzy programming of the group of memory cells connected to the next word line (WL1) within the target block is completed. Therefore, page data written to the group of memory cells connected to the initial word line (WL0) cannot be read until at least the fuzzy programming of the group of memory cells connected to the next word line (WL1) is completed.

[0071] The write action control unit 21 receives a write request from the host 2. This write request includes a block identifier specifying the target block to which the write data should be written. Upon receiving the write request from the host 2, the write action control unit 21 obtains the write data corresponding to the write request from the write buffer (WB). The write buffer (WB) is a buffer that temporarily stores the write data corresponding to each write request. The write data corresponding to a particular write request is stored in the write buffer (WB) until the write data can be read from the NAND flash memory 5. This write buffer (WB) can be implemented either by a write buffer (WB) 45 located on the host 2's memory or by a write buffer (WB) 31 located on the DRAM 6.

[0072] The write action control unit 21 writes the acquired write data to a page (write target page) within a write target block that has a block identifier specified by the received write request. The write request includes a block identifier (block address) but does not include a page address. The write target page is automatically determined by the write action control unit 21.

[0073] The write action control unit 21 notifies the host 2 of the page address of the page to which write data has been written.

[0074] Furthermore, the write action control unit 21 increments the page address of the target block where the next data should be written by one page. Then, the write action control unit 21 releases a region in the write buffer that stores data of pages within the target block that precede the target page and can be read from the target block by writing data to the target page. Here, "pages preceding the target page" refers to pages whose data was written before the target page in the page writing order of the target block. For example, if writing data to the nth page of the target block allows the reading of, for example, the first page within the target block, which precedes the nth page, the region in the write buffer storing the data of that first page is released. Similarly, if writing data to the (n+1)th page of the target block allows the reading of, for example, the second page within the target block, the region in the write buffer storing the data of that second page is released.

[0075] In instances where data is written to each page through multi-stage programming actions including a first stage and a second stage, the page that can be read from the target block by writing data to the target page of the target block is the page that can be programmed in the second stage by performing the first stage programming action on the target page. For example, if the first page of the target block can be programmed in the second stage (e.g., fine programming action) by performing the first stage programming action (e.g., fuzzy programming action) on the nth page of the target block, then the page that can be read from the target block by writing data to the target page is that first page.

[0076] By controlling the release of regions within the write buffer in this way, the amount of write buffer consumed by each write target block can be suppressed to the minimum required, thereby reducing the amount of memory resources consumed by the write buffer, which stores data of pages in the write target block that precede the write target page and can be read by writing data to a write target page in the write target block.

[0077] Furthermore, this assumes that one page of write data (user data) is written to the write target block. If two new pages of write data (user data) are written to the write target block, the two pages of data (user data) previously written to that write target block can be read. Therefore, in this case, the area in the write buffer storing the two readable pages of data (user data) can be released.

[0078] Similarly, if three pages of newly written data (user data) have been written to the write target block, it is possible to read three pages of data (user data) that were previously written to that write target block. Therefore, in this case, the area in the write buffer storing the readable three pages of data (user data) can be released.

[0079] Furthermore, in order to increase the available area in the write buffer, the write action control unit 21 may also perform an action of writing more than one page of virtual data to the write target block as needed.

[0080] For example, even when there are no unused areas in the write buffer, the write action control unit 21 can write virtual data to more than one page within a write target block. This allows the reading of more than one page of data (user data) previously written to the write target block, and releases the area in the write buffer storing this readable data. Thus, the area in the write buffer can be used for storing the next piece of data (user data). Furthermore, since there is no need to issue a read request for the virtual data from the host 2, the virtual data does not need to be stored in the write buffer. Therefore, even if virtual data is written to the write target block, the write buffer will not be consumed by the virtual data.

[0081] Furthermore, if the write action control unit 21 detects that a specific number of pages of data (user data or virtual data) has not been written to any of the multiple write target blocks during a specific period, it may also write virtual data to one or more pages within that write target block. In this case, for example, the write action control unit 21 may also determine whether the elapsed time since the last write of data (user data or virtual data) to a certain write target block is greater than or equal to a threshold. If the elapsed time is greater than or equal to the threshold, it may also write virtual data to one or more pages within that write target block. As a result, one page of data (user data) previously written to that write target block can be read, and the area in the write buffer storing the one or more pages of data (user data) that can be read can be released. Similarly, for each of the other write target blocks, the write action control unit 21 may also determine whether the elapsed time since the last write of data (user data or virtual data) to that write target block is greater than or equal to a threshold. If the elapsed time is greater than or equal to the threshold, it may also write virtual data to one or more pages within that write target block.

[0082] The read operation control unit 22 receives a read request (read instruction) from the host 2. This read request (read instruction) specifies the physical address (block address, page address) of the physical storage location within the NAND flash memory 5, which represents the data to be read. Then, based on these block addresses and page addresses, the read operation control unit 22 reads data from the physical storage location of the data to be read within the block to be read. The block to be read is identified by the block address. The physical storage location of the data to be read within that block is identified by the page address. Furthermore, in addition to the block address and page address, the read instruction may also include a page offset.

[0083] NAND interface 13 is configured as a memory control circuit that controls NAND flash memory 5 under the control of CPU 12.

[0084] DRAM interface 14 is configured as a DRAM control circuit that controls DRAM 6 under the control of CPU 12. A portion of the storage area of ​​DRAM 6 can also be used to store read buffer (RB) 30, write buffer (WB) 31, block management table 32, and defective information management table 33. Furthermore, these read buffer (RB) 30, write buffer (WB) 31, block management table 32, and defective information management table 33 can also be stored in SRAM (not shown) within controller 4. Block management table 32 contains multiple management tables corresponding to multiple blocks within NAND flash memory 5. Each management table contains multiple valid / invalid management information entries, each corresponding to multiple data entries contained in the block corresponding to that management table. Each valid / invalid management information entry indicates whether the data corresponding to that valid / invalid management information is valid or invalid data. Defective information management table 33 manages a list of defective blocks.

[0085] As described above, host 2 can also be an information processing device (e.g., a computer system) configured to execute various programming methods. The programming executed by the computer system includes application software layer 41, operating system 42, file system 43, and device driver 43, etc.

[0086] As is generally known, the operating system 42 is software configured to manage the host 2 as a whole, control the hardware within the host 2, and perform controls to enable applications to use the hardware and flash storage device 3.

[0087] The file system 43 is used to control the implementation of file operations (creation, saving, updating, deletion, etc.).

[0088] Multiple application software threads run on the application software layer 41. Examples of application software threads include client software, database software, and virtual machines.

[0089] Device driver 44 controls flash storage device 3 under the control of file system 43.

[0090] The file system 43 or device driver 44 may also include a flash translation layer (FTL) 2A for managing a lookup table (LUT) 45 that functions as an address translation table. Figure 2 The example shown is a device driver 44 that includes a Flash Translation Layer (FTL) 2A.

[0091] Lookup table (LUT) 45 manages the mapping between tags used to identify each piece of data and physical addresses representing each physical storage location within flash storage device 3 (i.e., NAND flash memory 5). Tags can be represented using logical addresses such as logical block addresses (LBAs), keys stored as key values, or groups of filenames and file offsets.

[0092] A specific storage area on the host 2's memory can also be used as a write buffer (WB) 45 (UWB: UnifiedWrite Buffer). When the host 2 wants to write data to any write target block within multiple write target blocks, the host 2 stores the data to be written to that write target block (write data) in the write buffer (WB) 45. Then, the host 2 sends a write request containing the block identifier (block address) specifying the write target block to the storage device 3. In addition, the write request may also contain storage location information indicating the region (storage area) within the write buffer (WB) 45 where the write data is stored.

[0093] When writing the write data to the NAND flash memory 5, the flash storage device 3 can retrieve the write data from the write buffer (WB) 46 by sending a transfer request containing the storage location information to the host 2.

[0094] Figure 5 This indicates the relationship between the active block pool, the free block pool, and multiple write target blocks managed by the flash storage device 3.

[0095] The state of each block within the NAND flash memory 5 is roughly divided into active blocks that store valid data and free blocks that do not store valid data. Active blocks are managed by a list called the active block pool 51. On the other hand, free blocks are managed by a list called the free block pool 52.

[0096] Valid data refers to data that is associated with a specific tag (the latest data associated with that tag). Invalid data refers to data that is not associated with any tag.

[0097] When the controller 4 of the flash storage device 3 receives a block allocation request from the host 2, the controller 4 selects one free block from the multiple free blocks in the free block pool 52 and allocates the selected free block as a write target block capable of writing the write data received from the host 2. Each time a block allocation request is received from the host 2, the controller 4 performs the actions of selecting one free block from the multiple free blocks in the free block pool 52 and allocating the selected free block as a write target block. Therefore, multiple usable write target blocks exist simultaneously in the flash storage device 3. Figure 5 In this context, it is assumed that blocks BLK11, BLK12, BLK13, ... are assigned as write target blocks.

[0098] In the process of allocating write target blocks, controller 4 first performs a deletion operation on one block (free block) selected from multiple free blocks in free block pool 52, thereby making the block writable and deleted. The block identifier (block address) of each allocated write target block is notified to host 2 from controller 4. Host 2 selects one of the multiple allocated write target blocks BLK11, BLK12, BLK13, ... and sends a write request containing the block identifier (block address) specifying the selected write target block to flash storage device 3, thereby enabling data to be written to any write target block within write target blocks BLK11, BLK12, BLK13, ...

[0099] If a write target block is completely filled with write data (user data) from host 2, controller 4 moves the write target block to active block pool 51.

[0100] When all valid data in a block within the active block pool 51 becomes invalid due to data updates, mapping releases, garbage collection, etc., the controller 4 moves the block to the free block pool 52.

[0101] Figure 6 This diagram illustrates the data writing operation where host 2 specifies the target block to be written and flash storage device 3 determines the target page to be written, as well as the data reading operation where host 2 specifies the block address and page address.

[0102] Host 2 includes a write processing unit 412 configured to send block allocation requests and write requests to flash storage device 3. This write processing unit 412 may also include... Figure 2 Within FTL2A as described in the document.

[0103] The controller 4 of the flash storage device 3 includes a block allocation unit 701 and a page allocation unit 702. The block allocation unit 701 and page allocation unit 702 may also be included in... Figure 2 The writing action control unit 21 described herein.

[0104] Data writing operations are performed in the following order.

[0105] (1) When the write processing unit 412 of the host 2 needs to write data to the flash storage device 3 (write data), the write processing unit 412 may also request the allocation of free blocks to the flash storage device 3. The controller 4 of the flash storage device 3 includes a block allocation unit 701 that manages the free block group of the NAND flash memory 5. When the block allocation unit 701 receives the request (block allocation request) from the write processing unit 412, the block allocation unit 701 allocates one free block of the free block group to the host 2 and notifies the host 2 of the block address (BLK#) of the allocated block.

[0106] (2) The write processing unit 412 sends a write request containing a tag (such as a logical address like LBA) that identifies the data to be written and the block address (BLK#) that specifies the target block to be written to the flash storage device 3.

[0107] (3) The controller 4 of the flash storage device 3 includes a page allocation unit 702 for allocating pages for writing data. When the page allocation unit 702 receives a write request, it determines the page address of the write target page within the block (write target block) that represents the block address specified by the write request. The controller 4 writes the write data from the host 2 to the determined write target page within the write target block.

[0108] (4) Controller 4 notifies host 2 of the page address representing the target page to be written as a response to the write request. Alternatively, controller 4 may also notify host 2 of the tag included in the write request, the block address included in the write request, and the determined page address as a response to the write request. In host 2, LUT2B is updated in a manner that maps the physical address (block address, page address) representing the physical storage location where the write data was written to the tag of the write data.

[0109] The data reading actions are performed in the following order.

[0110] (1) When host 2 needs to read data from flash storage device 3, host 2 obtains the physical address (block address, page address) corresponding to the tag of the data to be read from LUT411 by referring to LUT2B.

[0111] (2) Host 2 sends the read request for the specified block address and page address to flash storage device 3. When controller 4 of flash storage device 3 receives the read request from host 2, controller 4 reads the data from the physical storage location of the read object within the block of the read object based on the block address and page address.

[0112] Figure 7 This indicates the block allocation instruction used in flash storage device 3.

[0113] A block allocation instruction is an instruction (block allocation request) that flash storage device 3 request the allocation of a write target block (free block). Host 2 requests the allocation of a write target block from flash storage device 3 by sending the block allocation instruction to flash storage device 3, thereby obtaining the block address (the block address of the allocated write target block).

[0114] Figure 8 This indicates a response to a block allocation instruction.

[0115] When receiving a block allocation instruction from host 2, flash storage device 3 selects a free block from the free block list to be allocated to host 2, allocates the selected free block as the write target block, and then returns a response containing the block address of the write target block to host 2.

[0116] Figure 9 This indicates the write command used in flash storage device 3.

[0117] A write command is an instruction that requests data to be written to the flash storage device 3. This write command may also include an instruction ID (Identifier), block address, tag, and length.

[0118] The instruction ID is the ID (instruction code) that indicates that the instruction is a write instruction. The write instruction contains the instruction ID used for the write instruction.

[0119] The block address is the physical address of the target block to which the data should be written.

[0120] A tag is an identifier used to identify the data to be written. As mentioned above, the tag can be a logical address such as an LBA or a key in a key-value store. When the tag is a logical address such as an LBA, the logical address (starting LBA) included in the write instruction represents the logical location (initial logical location) within the logical address space where the data should be written.

[0121] The length indicates the length of the data to be written.

[0122] Upon receiving a write command from host 2, controller 4 determines the write target location (write target page) within the write target block that has the block address specified by the write command. This write target page is determined taking into account constraints such as page write order and bad pages. Then, controller 4 writes the data from host 2 to the write target location (write target page) within the write target block.

[0123] Figure 10 Indicates to Figure 9 The response to the write command.

[0124] The response includes the page address and length. The page address is the physical memory address within the target block where data has been written. This physical address can also be represented using a block offset (i.e., a combination of the page address and the page offset). The length indicates the length of the data written.

[0125] Alternatively, the response may include not only the page address (offset within the block) and length, but also the tag and block address. The tag is... Figure 9 The tag included in the write instruction. The block address is Figure 9 The block address contained in the write instruction.

[0126] Figure 11 This indicates the read command used in flash storage device 3.

[0127] A read command is an instruction to request data to be read from flash storage device 3. This read command includes an instruction ID, tag, block address, page address, and length.

[0128] The instruction ID is the ID (instruction code) that indicates that the instruction is a read instruction. The read instruction contains the read instruction ID.

[0129] The block address specifies the block containing the data to be read. The page address specifies the page containing the data to be read. This page address can also be represented by an offset within the block (i.e., a combination of the page address and the offset within the page) indicating the physical storage location within the block containing the data to be read. The length indicates the length of the data to be read.

[0130] Figure 12 This indicates the sequence of write processes performed by host 2 and flash storage device 3.

[0131] Host 2 first requests the flash storage device 3 to allocate a write target block by sending a block allocation instruction to the flash storage device 3. If data is to be written to an already allocated write target block, host 2 may choose not to send a block allocation instruction to the flash storage device 3.

[0132] Then, host 2 sends a write command containing a tag that identifies the data to be written, the block address of the target block to which the data should be written, and the length of the data to be written to to flash storage device 3 (step S20).

[0133] When the controller 4 of the flash storage device 3 receives the write instruction, the controller 4 determines the write target page within the write target block having the block address specified by the write instruction, and retrieves write data from the write buffer (WB), and writes the write data to the determined write target page within the write target block (step S11). When the write buffer (WB) is implemented by a write buffer (WB) 45 provided on the memory of the host 2, the write instruction may also include storage location information indicating the location (region) within the write buffer where the write data is stored. The controller 4 can retrieve the write data from the write buffer (WB) 45 provided on the memory of the host 2 by sending a transfer request containing this storage location information to the host 2.

[0134] The controller 4 returns a response to the write command to the host 2 (step S12). The response contains at least the page address (e.g., a combination of page address and page offset) where the data has been written.

[0135] When host 2 receives the response, host 2 updates the LUT2B managed by host 2, and maps the physical address (a group of block address, page address, and page offset) representing the physical storage location where written data has been written to the tag of the written data (step S21).

[0136] Then, the controller 4 releases the area within the write buffer (WB), which identifies pages within the write target block that can be read from the write target block prior to the write target page by writing write data to the write target page within the write target block, and stores the data of the identified page (step S13). In an instance where writing data to each page of the write target block is performed through multi-stage programming actions including a first stage and a second stage, the readable page is the page that can be programmed in the second stage by performing the first stage programming action on the write target page.

[0137] The process of releasing the area in the write buffer (WB) can be performed either when the data to be written to the specified page is transferred from the write buffer (WB) to the page buffer of the NAND flash memory 5, or after the second-stage programming operation (e.g., fine programming operation) is performed on the specified page.

[0138] In the case where the write buffer (WB) is implemented by a write buffer (WB) 45 set on the memory of the host 2, in step S13, the controller 4 sends a request to the host 2 to release the area in the write buffer (WB) 45 that stores data of readable pages.

[0139] Figure 13This indicates the action of releasing a region within a write buffer, which stores data that can be read from a write target block by writing data to that block.

[0140] The write buffer (WB) 31 (or 45) stores the write data corresponding to each write request. The write buffer (WB) 31 (or 45) contains multiple areas for storing multiple pages of data. Figure 13 For the sake of simplicity, the area contained in write buffer (WB) 31 (or 45) is illustrated. The situation in these areas. Each has a page size.

[0141] In the write buffer (WB) area If the write data D1, D2, and D3 stored in the file are write data to be written to the target block BLK11, then these write data D1, D2, and D3 are written to pages P0, P1, and P2 of the target block BLK11, respectively.

[0142] If the write data D11, D12, D13, and D14 stored in regions 107, 108, 104, and 105 of the write buffer (WB) contain write data that should be written to the write target block BLK12, then these write data D11, D12, D13, and D14 are, for example, written to pages P0, P1, P2, and P3 of the write target block BLK12, respectively.

[0143] Within each write target block, even if data is written to the first page P0, it cannot be read directly from page P0. Instead, data can be read from page P0 after writing data to several subsequent pages. Similarly, even if data is written to page P1, it cannot be read directly from page P1. Instead, data can be read from page P1 after writing data to several subsequent pages.

[0144] Here, as an example, assume that on the page following page P0... After writing the data, it is possible to access the pages prior to these. An instance of reading data from page P0.

[0145] In this case, after controller 4 writes write data D14 to page P3 of the write target block BLK12, controller 4 releases area 107 in the write buffer (WB), which stores write data D11 of page P0 in the write target block BLK12 that was prior to page P3 and could be read by writing write data D14. Thus, the released area 107 can be used to store newly written data.

[0146] Figure 14 This indicates that multiple areas within the write buffer (WB) are all used to store the state of the written data.

[0147] exist Figure 14 In the write buffer (WB) area It is used to store the write data D1, D2, D3 written to the write target block BLK11, the write data D12, D13, D14 written to the write target block BLK12, and the write data D21, D22, D23 written to the write target block BLK13.

[0148] In this case, if there are no unused areas in the write buffer (WB), host 2 cannot store newly written data into the write buffer (WB).

[0149] In this case, such as Figure 15 As shown, controller 4 writes virtual data to one or more pages of the target block BLK12, for example.

[0150] By writing virtual data to page P4 of the target block BLK12, it is possible to read data from a page within the target block BLK12 that was written before page P4. Here, it is assumed that the write data D12 of page P1 of the target block BLK12 can be read from the target block BLK12. In this case, the controller 4 releases region 108 in the write buffer (WB) storing the write data D12.

[0151] Similarly, by writing virtual data to page P5 of the target block BLK12, data from a page written to the target block BLK12 before page P4 can be read. Here, it is assumed that the write data D13 of page P2 of the target block BLK12 can be read from the target block BLK12. In this case, the controller 4 releases region 104 in the write buffer (WB) storing the write data D13.

[0152] Host 2 can store newly written data into region 108 or region 104 within the write buffer (WB).

[0153] Next, refer to Figure 16 This illustrates an example of writing data to each page of the target block using multi-stage programming actions that include stage 1 and stage 2.

[0154] exist Figure 16 In this context, it is assumed that the NAND flash memory 5 is a three-level cell (TLC) flash memory where 3 bits of data are written to each memory cell. Furthermore, in... Figure 16In this context, we assume a scenario where the program moves back and forth along two adjacent word lines while performing multi-stage programming actions (here, fuzzy to fine programming actions).

[0155] (1) Controller 4 performs the first stage of programming (fuzzy programming action, also known as fuzzy write action) on pages P0, P1, and P2 of word line WL0. Even after the first stage of programming (fuzzy programming action) on pages P0, P1, and P2 is completed, the second stage of programming (fine programming action, also known as fine write action) on pages P0, P1, and P2 cannot be performed before the first stage of programming (fuzzy programming action) on pages P3, P4, and P5 of word line WL1 is performed. Therefore, data on pages P0, P1, and P2 cannot be read after the first stage of programming (fuzzy programming action) on pages P0, P1, and P2 has been completed.

[0156] (2)(3) When the first stage of programming (fuzzy programming) for pages P0, P1, and P2 ends, controller 4 performs the first stage of programming (fuzzy programming) for pages P3, P4, and P5 of word line WL1. When the first stage of programming (fuzzy programming) for pages P3, P4, and P5 of word line WL1 ends, the second stage of programming (fine programming) for pages P0, P1, and P2 can be performed, thereby enabling the reading of data from pages P0, P1, and P2.

[0157] (4)(5) When the second stage programming action (fine programming action) for pages P0, P1, and P2 is completed, controller 4 performs the first stage programming action (fuzzy programming action) for pages P6, P7, and P8 of word line WL2. When the first stage programming action (fuzzy programming action) for pages P6, P7, and P8 of word line WL2 is completed, the second stage programming action (fine programming action) can be performed for pages P3, P4, and P5, thereby enabling the reading of data from pages P3, P4, and P5.

[0158] Figure 17 The time series diagram is represented in chronological order. Figure 16 Programming actions.

[0159] Controller 4 first performs the first stage of programming (fuzzy programming) on ​​pages P0, P1, and P2, and then performs the first stage of programming (fuzzy programming) on ​​subsequent pages P3, P4, and P5. Through the first stage of programming (fuzzy programming) on ​​subsequent pages P3, P4, and P5, the second stage of programming (fine programming) can be performed on the preceding pages P0, P1, and P2. Therefore, through the first stage of programming (fuzzy programming) on ​​pages P3, P4, and P5, the data of the preceding pages P0, P1, and P2 can be read. Then, for example, when performing fuzzy programming on page P5, controller 4 increments the page address where the next data should be written by one page and sets it to page P6.

[0160] Then, after performing the second stage of programming actions (fine programming actions) on the preceding pages P0, P1, and P2, controller 4 performs the first stage of programming actions (fuzzy programming actions) on the subsequent pages P6, P7, and P8.

[0161] Because by performing the first-stage programming action (fuzzy programming action) on subsequent pages P6, P7, and P8, the second-stage programming action (fine programming action) can be performed on preceding pages P3, P4, and P5. Therefore, by performing the first-stage programming action (fuzzy programming action) on pages P6, P7, and P8, the data of preceding pages P3, P4, and P5 can be read.

[0162] In other words, when controller 4 receives a write request containing a block address from host 2, controller 4 retrieves the write data corresponding to the write request from the write buffer and writes the write data to the write target page within the write target block containing the block address included in the write request through a first-stage programming action (fuzzy programming action). Then, controller 4 notifies host 2 of the page address of the write target page containing the write data by returning a response. Then, controller 4 increments the page address within the write target block where the next data should be written by one page. Then, controller 4 releases the area in the write buffer that stores data of the pages within the write target block that precede the write target page, which can be read by performing a second-stage programming action (fine programming action), which is performed through the first-stage programming action (fuzzy programming action) on the write target page.

[0163] Figure 18 The flowchart illustrates the sequence of virtual data write operations performed by the flash storage device 3 when there are no unused areas in the write buffer (WB).

[0164] The controller 4 of the flash storage device 3 determines whether there are unused areas (free areas) in the write buffer (WB) (step S101). If all areas of the write buffer (WB) are filled with write data to the multiple currently open write target blocks, that is, there are no unused areas (free areas) in the write buffer (WB) (step S101 is NO), then the controller 4 selects the write target block to which virtual data should be written from the multiple write target blocks (step S102). For example, the controller 4 may also select the write target block that stores the oldest data (the data that has not been updated for the longest time) as the write target block to which virtual data should be written.

[0165] Controller 4 writes virtual data to one or more pages within the selected target block (step S103), increasing the page address of the next data to be written within the target block by one or more pages (i.e., the number of pages of virtual data already written) (step S104). In step S104, if one page of virtual data has been written, the page address increases by one page; if two pages of virtual data have been written, the page address increases by three pages.

[0166] The controller 4 releases one or more areas in the write buffer (WB) that store data of one or more pages prior to the one or more pages with the virtual data already written, which can be read from the write target block by writing one or more pages of virtual data (step S104).

[0167] In an instance where data writing to pages is performed through multi-stage programming actions, if there are no unused areas in the write buffer, the controller 4 writes virtual data to more than one page within one of multiple write target blocks through a first-stage programming action (fuzzy programming action). This increases the address of the next page in that write target block to be written by the number of pages already written with virtual data. Then, the controller 4 releases more than one area in the write buffer that stores data from more than one page in the write target block prior to that page, which can be read by performing a second-stage programming action (fine programming action) that is executed through the first-stage programming action on the virtual data.

[0168] Furthermore, if all data within the target block except for the virtual data can be read, controller 4 stops writing virtual data to the target block. For example, in Figure 15In the case where virtual data is written to multiple pages of the target block BLK12, thereby enabling the reading of all data (user data) D11, D12, D13, and D14 in the target block BLK12 except for the virtual data, the controller 4 stops writing virtual data to the target block.

[0169] Figure 19 The flowchart illustrates the sequence of virtual data write operations performed by the flash storage device 3 when it is detected that a specific number of pages of data have not been written at each specific period.

[0170] The controller 4 of the flash storage device 3 selects one of the multiple currently open write target blocks (step S201). The controller 4 determines whether a threshold time has elapsed since the last data (user data or virtual data) was written to the selected block (step S202).

[0171] If the threshold time has not elapsed since the last written data (user data or virtual data) (step S202 is no), then the controller 4 determines whether the check process of step S202 for all written target blocks has ended (step S206). If it has not ended (step S206 is no), then proceed to step S201, and select the next written target block in step S201.

[0172] If a threshold time has elapsed since the last data (user data or virtual data) was written (step S202 is YES), then the controller 4 determines that the selected block is the block in which a specific number of pages of data are written every specific period. In order to fill the entire selected block with data within a specific time limit, virtual data is written to more than one page in the selected target block (step S203). Then, the controller 4 increments the page address of the target block to which the next data should be written by more than one page (that is, the number of pages of virtual data already written) (step S204). In step S204, for example, when 1 page of virtual data is written to the selected block, the page address is incremented by 1 page; when 2 pages of virtual data are written to the selected block, the page address is incremented by 2 pages; and when 3 pages of virtual data are written to the selected block, the page address is incremented by 3 pages. Then, controller 4 releases one or more regions in the write buffer that store data of one or more pages in the selected write target block that can be read from the selected write target block before the pages with virtual data already written (step S205). Then, controller 4 determines whether the check process of step S202 for all write target blocks has ended (step S206). If it has not ended (step S206 is no), it proceeds to step S201, where the next write target block is selected.

[0173] In an example of performing data writing to pages through multi-stage programming actions, if a threshold time has elapsed since the last data was written to a certain target block, the controller 4 writes virtual data to more than one page within the target block through a first-stage programming action (fuzzy programming action), increasing the address of the next page in the target block to be written by the number of pages already written with virtual data. Then, the controller 4 releases more than one area in the write buffer that stores data from more than one page within the target block prior to that page, which can be read by performing a second-stage programming action (fine programming action) that is executed through the first-stage programming action on the virtual data.

[0174] Furthermore, if all data within the target block except for the virtual data can be read, controller 4 can also stop writing virtual data to the target block. For example, in Figure 15In the case where virtual data is written to multiple pages of the target block BLK12, thereby enabling the reading of all data (user data) D11, D12, D13, and D14 in the target block BLK12 except for the virtual data, the controller 4 may also stop writing virtual data to the target block.

[0175] Figure 20 This represents an example of the write order management table structure managed by flash storage device 3.

[0176] Controller 4 manages multiple write order management tables corresponding to multiple write target blocks. Each write order management table stores multiple write completion flags corresponding to multiple pages within the write target block corresponding to that write order management table.

[0177] Multiple write completion flags indicate whether data has been written to the page corresponding to that flag. The write completion flag for a page where data has been written is set to a value indicating that data has been written (e.g., "1"). The write completion flag for a page where no data has been written is set to a value indicating that no data has been written (e.g., "0").

[0178] If data has already been written to pages P0, P1, and P2 of a certain target block, such as Figure 20 As shown, controller 4 updates the write order management table corresponding to the write target block, and sets the write completion flags corresponding to page P0, page P1, and page P2 to values ​​indicating that data has been written (e.g., "1").

[0179] If the controller 4 has written virtual data to pages P3, P4, and P5 of the target block, the controller 4 will update the write order management table corresponding to the target block and set the write completion flags corresponding to page P3, page P4, and page P5 to values ​​indicating that data has been written (e.g., "1").

[0180] Since the virtual data does not need to be read by host 2, it is not stored in the write buffer. When virtual data has been written to more than one page of a write target block, more than one write completion flag corresponding to that page is set to a value indicating that data has been written (e.g., "1"). Therefore, even if controller 4 has written virtual data to any write target block, controller 4 can correctly manage the page write order of each write target block by referring to the respective write order management tables.

[0181] As explained above, according to this embodiment, the controller 3 manages multiple write target blocks and writes data to write target blocks having block identifiers specified by write requests from the host 2. In this way, the host 2 can specify the configuration of the write target blocks, for example, enabling control to write data associated with different end users to different write target blocks. Furthermore, the controller 4 performs control to release areas within the write buffer, which stores data of pages in the write target block that are prior to the current write target page and can be read by writing data to a specific write target page within that write target block. Therefore, in an environment with multiple write target blocks, buffer management can be performed, for example, by releasing areas within the write buffer storing write data for a specific write target block and using those areas to store new write data for that write target block or new write data for other write target blocks. This allows the amount of write buffer consumed by each write target block to be minimized, thus reducing the amount of memory resources consumed by the write buffer even in an environment with multiple write target blocks.

[0182] Furthermore, controller 4 also performs the action of writing more than one page of virtual data to the write target block. As a result, the usable area within the write buffer can be easily increased.

[0183] Furthermore, in this embodiment, a write buffer can be set on the memory of the host 2. Therefore, the controller 4 can obtain write data from the write buffer on the memory of the host 2, so it is not necessary to prepare a large-capacity write buffer on the flash storage device 3, and the number of write target blocks that can be used simultaneously can be easily increased. As a result, the number of end users sharing the flash storage device 3 can be easily increased without increasing the cost of the flash storage device 3.

[0184] Furthermore, the write buffer release control described in this embodiment is not only applicable to the configuration of managing the mapping between each tag and each physical address on the host 2 side, but also applicable to the configuration of managing the mapping between each tag (e.g., a logical address like an LBA) and each physical address using a logical physical address translation table on the flash storage device 3 side.

[0185] Furthermore, the write buffer release control described in this embodiment applies not only to determining the composition of the write target block on the host 2 side, but also to determining the composition of the write target block on the flash storage device 3 side. When determining the composition of the write target block on the flash storage device 3 side, each write request sent from the host 2 may not contain a block address. Additionally, when determining the composition of the write target block on the flash storage device 3 side, the controller 4 of the flash storage device 3 may determine both the write target block and the write target page for each write request.

[0186] Therefore, the controller 4 of the flash storage device 3 can also be configured to operate in the following manner.

[0187] Controller 4 retrieves the first write data corresponding to the first write request from host 2 from a write buffer (WB) that temporarily stores write data corresponding to each write request. Controller 4 writes the first write data to a write target page within the first write target block of a plurality of write target blocks. Then, controller 4 releases a region within the write buffer (WB) that stores data of pages in the first write target block that precede the write target page and can be read from the first write target block by writing the first write data to the write target page. The process of releasing this region within the write buffer (WB) can be performed, for example, when the write data to be written to the page in the first write target block that precedes the write target page is transferred from the write buffer (WB) to the NAND flash memory 5, or after performing a second-stage programming operation (e.g., fine programming operation) on the page.

[0188] Furthermore, in this embodiment, NAND flash memory is exemplified as a non-volatile memory. However, the functionality of this embodiment can also be applied to various other non-volatile memories such as MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

[0189] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0190] [Explanation of Symbols]

[0191] 2: Host

[0192] 2A: Flash Transport Layer, Write Buffer

[0193] 3: Flash storage devices

[0194] 4: Controller

[0195] 5: NAND flash memory

[0196] 21: Write to the control unit

[0197] 22: Read Control Unit

[0198] 31, 45: Write to buffer

Claims

1. A memory system connectable to a host computer, comprising: A non-volatile memory comprising multiple blocks, each block being a unit for data deletion operations, each block comprising multiple word lines, and each word line connecting to multiple memory cells; and The controller is electrically connected to the non-volatile memory and is configured as follows: Retrieve the first data from the write buffer. Write the first data into the first storage unit connected to the first word line of the first block, and In response to detecting that no first instruction has been received from the host within a threshold time period from when the first data was written to the first storage unit, virtual data is written to the second storage unit, the first instruction being an instruction to write the second data to the second storage unit connected to the second word line of the first block, the second word line being different from the first word line.

2. The memory system according to claim 1, wherein The controller is further configured as follows: After the first data is written to the first storage unit, the first data is stored in the area of ​​the write buffer without being released, at least until the virtual data is written to the second storage unit. After the virtual data is written to the second storage unit, the area of ​​the write buffer is released.

3. The memory system according to claim 1, wherein The controller is further configured as follows: Data is written to the storage cells of the non-volatile memory using multi-stage programming, which includes at least stage 1 programming and stage 2 programming. The first data is written to the first storage unit using the first stage of programming, and After writing the virtual data to the second storage unit using the first stage programming, the first data is written to the first storage unit again using the second stage programming.

4. The memory system according to claim 3, wherein The controller is further configured as follows: The first data is transferred from the write buffer to the non-volatile memory so that the first data can be written to the first memory cell using the first stage programming. The virtual data is not transferred from the write buffer, and The first data is transferred again from the write buffer to the non-volatile memory to write the first data into the first memory cell using the second stage programming.

5. The memory system according to claim 3, wherein After the first data was written to the first storage unit using the first stage programming, and before the first data was written to the first storage unit again using the second stage programming, the first data was not correctly read from the first storage unit. After the first data was written to the first storage unit using the second stage programming, the first data was correctly read from the first storage unit. The controller is further configured as follows: After writing the first data to the first storage unit using the first stage programming, the first data is stored in the area of ​​the write buffer without releasing the area, and After the first data is written to the first storage unit again using the second stage programming, the area of ​​the write buffer is released.

6. The memory system according to claim 1, wherein The controller is further configured as follows: In response to receiving a second instruction from the host, the first block is allocated to the host from the plurality of blocks, and the identifier of the first block is notified to the host. In response to receiving a write instruction from the host containing the identifier of the first block, the first data is written to the first storage unit of the first block.

7. The memory system according to claim 1, wherein The controller is further configured as follows: In response to receiving a write instruction from the host that does not contain the identifier of the first block, the first block is allocated from the plurality of blocks.

8. The memory system according to claim 1, further comprising: Volatile memory; and The write buffer is implemented in the volatile memory.

9. The memory system according to claim 1, wherein The write buffer is implemented in the host's memory.

10. The memory system of claim 9, wherein The controller is further configured as follows: After the first data is written to the first storage unit, the first data is stored in the area of ​​the write buffer without being released, at least until the virtual data is written to the second storage unit. After the virtual data is written to the second storage unit, the host is requested to release the area of ​​the write buffer.

11. A method for controlling a non-volatile memory, the non-volatile memory comprising a plurality of blocks, each of the plurality of blocks being a unit for data deletion operations, each of the plurality of blocks comprising a plurality of word lines, each of the plurality of word lines being connected to a plurality of memory cells, and the method comprising: Retrieve the first data from the write buffer. Write the first data into the first storage unit connected to the first word line of the first block; and In response to detecting that no first instruction has been received from the host within a threshold time period since the first data was written to the first storage unit, virtual data is written to the second storage unit, the first instruction being an instruction to write the second data to the second storage unit connected to the second word line of the first block, the second word line being different from the first word line.

12. The method of claim 11, further comprising: After the first data is written to the first storage unit, the first data is stored in the area of ​​the write buffer without releasing the area, at least until the virtual data is written to the second storage unit; and After the virtual data is written to the second storage unit, the area of ​​the write buffer is released.

13. The method of claim 11, wherein Data is written to the storage cells of the non-volatile memory using multi-stage programming, which includes at least stage 1 programming and stage 2 programming. The first data is written to the first storage unit using the first stage of programming, and After writing the virtual data to the second storage unit using the first stage programming, the first data is written to the first storage unit again using the second stage programming.

14. The method of claim 13, further comprising: The first data is transferred from the write buffer to the non-volatile memory so that the first data can be written to the first memory cell using the first stage programming. The virtual data is not transferred from the write buffer, and The first data is transferred again from the write buffer to the non-volatile memory to write the first data into the first memory cell using the second stage programming.

15. The method of claim 13, wherein After the first data was written to the first storage unit using the first stage programming, and before the first data was written to the first storage unit again using the second stage programming, the first data was not correctly read from the first storage unit. After the first data was written to the first storage unit using the second stage programming, the first storage unit was correctly read from the first storage unit. The method further includes: After writing the first data to the first storage unit using the first stage programming, the first data is stored in the area of ​​the write buffer without releasing the area, and After the first data is written to the first storage unit again using the second stage programming, the area of ​​the write buffer is released.

16. The method of claim 11, further comprising: In response to receiving a second instruction from the host, the first block is allocated to the host from the plurality of blocks, and the identifier of the first block is notified to the host. In response to receiving a write instruction from the host containing the identifier of the first block, the first data is written to the first storage unit of the first block.

17. The method of claim 11, further comprising: In response to receiving a write instruction from the host that does not contain the identifier of the first block, the first block is allocated from the plurality of blocks.

18. The method of claim 11, wherein The non-volatile memory is implemented in the memory system. The memory system also includes volatile memory, and The write buffer is implemented in the volatile memory.

19. The method of claim 11, wherein The write buffer is implemented in the host's memory.

20. The method of claim 19, further comprising: After the first data is written to the first storage unit, the first data is stored in the area of ​​the write buffer without being released, at least until the virtual data is written to the second storage unit. After the virtual data is written to the second storage unit, the host is requested to release the area of ​​the write buffer.

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