Minimum and sub-minimum value retrieval circuit

Abstract

The present application provides a minimum and sub-minimum value searching circuit, which searches the minimum and sub-minimum values from two different input data input in parallel N N is equal to or greater than 1, comprising N-stage comparison circuits. At each stage, the minimum value is obtained, and the corresponding sub-minimum value is reserved. The sub-minimum value is compared with the minimum value at the current stage, but is greater than the minimum value. In the next stage, the sub-minimum value of the previous stage corresponding to the obtained minimum value is inherited as the sub-minimum value of the minimum value at the current stage. Thus, when the final minimum value is obtained at the Nth stage, the array of the sub-minimum values corresponding to the final minimum value is also obtained. The values in the array are compared with each other, and the minimum sub-minimum value is obtained.

Description

Technical Field

[0001] This invention belongs to the field of communication circuits, and in particular relates to a minimum and second minimum value retrieval circuit. Background Technology

[0002] Comparisons between numbers are involved in many fields, such as finding the minimum and second minimum values ​​of a set of numbers. While there are many solutions in software algorithms, when applying them to FPGA circuits, the complexity of the hardware implementation and the accuracy of the results must be carefully considered.

[0003] For example, in FPGA applications, a tree-structured hardware circuit with direct pairwise comparisons is typically used, such as... Figure 1 As shown, the comparator structure in the diagram consists of five stages. Each stage comprises one or more two-input comparators. Each comparator compares two input values ​​and outputs the smaller one, which is then passed to the next stage for comparison, until the final stage outputs the minimum value. In the final fifth stage, the smaller value is output as the minimum, and the larger value is output as the second smallest. This circuit structure is simple to implement, but it has certain limitations, potentially leading to an inability to accurately find the second smallest value. For example, if the true second smallest value encounters the minimum value in stages 2 through 4, and both the true second smallest and the minimum are simultaneously compared by a two-input comparator, the true second smallest value will be eliminated by the minimum, preventing it from reaching the final stage, the fifth stage. Therefore, the final second smallest value obtained is not the true second smallest value, but a pseudo-second smallest value that is larger than the actual second smallest value. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a minimum and second minimum value retrieval circuit to obtain the minimum value and the true second minimum value, that is, the second minimum value result that is immediately adjacent to the minimum value.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] Provide a minimum and second minimum value retrieval circuit for parallel input 2 N The minimum and second minimum values ​​are retrieved from a set of distinct input data, where N is greater than or equal to 1, and the circuit includes N levels of comparison.

[0007] The first-stage comparator circuit includes 2 N-1 There are three identical first-level comparison units, wherein the first first-level comparison unit includes input terminals [Din_1, Din_2] and output terminals [smin_1_1, min_1_1]. The minimum value of the input data corresponding to input terminals [Din_1, Din_2] is output by min_1_1, and the second smallest value is output by smin_1_1.

[0008] The second first-level comparison unit includes input terminals [Din_3, Din_4] and output terminals [smin_1_2, min_1_2]. The minimum value in the input data corresponding to input terminals [Din_3, Din_4] is output by min_1_2, and the second smallest value is output by smin_1_2.

[0009] And so on, the 2nd N-1 Each first-level comparison unit includes the input terminal [Din_2] N -1、Din_2 N Output terminal [smin_1_2] N-1 min_1_2 N-1 ], Input terminal [Din_2 N -1、Din_2 N The minimum value in the corresponding input data is min_1_2. N-1 Output, the second smallest value is smin_1_2 N-1 Output;

[0010] The second-stage comparator circuit includes 2 N-2 There are two identical second-stage comparator units, wherein the first second-stage comparator unit includes an input terminal that corresponds to the output terminal [smin_1_1, smin_1_2, min_1_1, min_1_2] of the first-stage comparator circuit, and an output terminal [smin_2_1_1, smin_2_1_2, min_2_1].

[0011] The second second-stage comparator includes input terminals that correspond to the output terminals [smin_1_3, smin_1_4, min_1_3, min_1_4] of the first-stage comparator circuit, and output terminals [smin_2_2_1, smin_2_2_2, min_2_2].

[0012] And so on, the 2nd N-2 The second-stage comparator unit and the output of the first-stage comparator circuit [smin_1_(2 N-1 -1), smin_1_2 N-1 min_1_(2 N-1 -1), min_1_2 N-1 Correspondingly, and including the output terminal [smin_2_2] N-2 _1、smin_2_2 N-2 _2、min_2_2 N-2 ];

[0013] The third-stage comparator circuit includes 2 N-3There are three identical third-stage comparator units, wherein the input terminal of the first third-stage comparator unit is the same as the output terminal of the second-stage comparator circuit.

[0014] [smin_2_1_1, smin_2_2_1, smin_2_1_2, smin_2_2_2, min_2_1, min_2_2] correspond to each other, and include the output terminals [smin_3_1_1, smin_3_1_2, smin_3_1_3, min_3_1];

[0015] The second third-stage comparator includes input terminals that correspond to the output terminals of the second-stage comparator circuit [smin_2_3_1, smin_2_4_1, smin_2_3_2, smin_2_4_2, min_2_3, min_2_4], and also includes output terminals [smin_3_2_1, smin_3_2_2, smin_3_2_3, min_3_2].

[0016] And so on, the 2nd N-3 The third-stage comparator unit and the output of the second-stage comparator circuit [smin_2_(2 N-2 -1)_1、smin_2_2 N-2 _1、smin_2_(2 N-2 -1)_2、smin_2_2 N-2 _2、min_2_(2 N-2 -1), min_2_2 N-2 Correspondingly, and including the output terminal [smin_3_2] N-3 _1、smin_3_2 N-3 _2、smin_3_2 N-3 _3、min_3_2 N-3 ];

[0017] Similarly, the Nth stage comparator circuit includes input terminals corresponding to the output terminals of the (N-1)th stage comparator circuit [smin_(N-1)_1_1, smin_(N-1)_2_1, smin_(N-1)_1_2, smin_(N-1)_2_2, ..., smin_(N-1)_1_(N-1), smin_(N-1)_2_(N-1), min_(N-1)_1, min_(N-1)_2], and output terminals [smin_N_1, smin_N_2, ..., smin_N_N, min_N]; wherein the output terminal min_N generates an output 2. N The minimum value among the input data.

[0018] Preferably, the output of the Nth stage comparator circuit [smin_N_1, smin_N_2, ..., smin_N_N] is input to the second smallest value comparator circuit to generate the minimum output value, which is 2. N The second minimum value among the input data.

[0019] Preferably, the first-level comparison unit includes a comparator B1 and a first selector S11 and a second selector S12. The comparator B1 includes two input terminals for inputting two input data, and the output terminal of the comparator B1 is electrically connected to the selection control terminals of the first selector S11 and the second selector S12, respectively.

[0020] Wherein, the first input terminal of the first selector S11 is electrically connected to the first input terminal of the comparator B1, and the second input terminal of the first selector S11 is electrically connected to the second input terminal of the comparator B1.

[0021] The first input terminal of the second selector S12 is electrically connected to the second input terminal of the comparator B1, and the second input terminal of the second selector S12 is electrically connected to the first input terminal of the comparator B1.

[0022] The output of the first selector S11 is used to output the first minimum value of the two input data, and the output of the second selector S12 is used to output the second minimum value of the first accompanying data. Each first minimum value output by the first comparison unit corresponds to one second minimum value of the first accompanying data.

[0023] Preferably, the second-stage comparison unit includes a comparator B2 and a first selector S21, a second selector S22 and a third selector S23. The comparator B2 includes two input terminals for inputting the two minimum values ​​of the first-stage comparison circuit output. The output terminal of the comparator B2 is electrically connected to the selection control terminals of the first selector S21, the second selector S22 and the third selector S23 respectively.

[0024] Specifically, the first input terminal of the first selector S21 is electrically connected to the first input terminal of the comparator B2, and the second input terminal of the first selector S21 is electrically connected to the second input terminal of the comparator B2; the first input terminal of the second selector S22 is electrically connected to the second input terminal of the comparator B2, and the second input terminal of the second selector S22 is electrically connected to the first input terminal of the comparator B2; the first input terminal and the second input terminal of the third selector S23 are respectively used to input the two first-stage secondary minimum values ​​of the first-stage comparator circuit output.

[0025] The output of the first selector S21 is used to output the minimum of the two first-level minimum values ​​as the second-level minimum value. The output of the second selector S22 is used to output the second smallest of the two first-level minimum values ​​as one second-level accompanying second smallest value corresponding to the second-level minimum value. The output of the third selector S23 is used to output the first-level accompanying second smallest value corresponding to the minimum of the two first-level minimum values ​​as another second-level accompanying second smallest value corresponding to the second-level minimum value. The second-level minimum value output by the second-level comparison unit corresponds to two second-level accompanying second smallest values.

[0026] Preferably, the third-stage comparison unit includes a comparator B3 and a first selector S31, a second selector S32, a third selector S33, and a fourth selector S34. The comparator B3 includes two input terminals for inputting the two minimum values ​​of the second-stage comparison circuit output. The output terminal of the comparator B3 is electrically connected to the selection control terminals of the first selector S31, the second selector S32, the third selector S33, and the fourth selector S34, respectively.

[0027] The first input terminal of the first selector S31 is electrically connected to the first input terminal of the comparator B3, and the second input terminal of the first selector S31 is electrically connected to the second input terminal of the comparator B3; the first input terminal of the second selector S32 is electrically connected to the second input terminal of the comparator B3, and the second input terminal of the second selector S32 is electrically connected to the first input terminal of the comparator B3; the first and second input terminals of the third selector S33 and the fourth selector S34 are respectively used to input the two second-stage adjoint minimum values ​​of the output of the second-stage comparator circuit.

[0028] The output of the first selector S31 is used to output the minimum of the two second-level minimum values ​​as the third-level minimum value. The output of the second selector S32 is used to output the second smallest of the two second-level minimum values ​​as one third-level accompanying second smallest value corresponding to the third-level minimum value. The outputs of the third selector S33 and the fourth selector S34 are each used to output the second smallest accompanying second smallest value corresponding to the minimum of the two second-level minimum values ​​as two other third-level accompanying second smallest values ​​corresponding to the third-level minimum value. The third-level minimum value output by the third-level comparison unit corresponds to three third-level accompanying second smallest values.

[0029] Preferably, the Nth stage comparison circuit includes a comparator BN and a first selector SN1 to an N+1th selector SN(N+1), wherein the comparator BN includes two input terminals for inputting the two minimum values ​​of the N-1th stage output of the N-1th stage comparison circuit, and the output terminal of the comparator BN is electrically connected to the selection control terminals of the first selector SN1 to the N+1th selector SN(N+1);

[0030] The first input terminal of the first selector SN1 is electrically connected to the first input terminal of comparator BN, and the second input terminal of the first selector SN1 is electrically connected to the second input terminal of comparator BN; the first input terminal of the second selector SN2 is electrically connected to the second input terminal of comparator BN, and the second input terminal of the second selector SN2 is electrically connected to the first input terminal of comparator BN; the first and second input terminals of the third selector SN3 to the (N+1)th selector SN(N+1) are respectively used to input the two (N-1)th stage secondary minimum values ​​of the N-1th stage comparator circuit; the output terminal of the first selector SN1 is used to output the minimum value of the two (N-1)th stage minimum values, which is the Nth stage minimum value, i.e., 2. N The minimum value among the input data is used to output the second smallest value among the two (N-1)th level minimum values, which serves as the Nth level accompanying second smallest value corresponding to the Nth level minimum.

[0031] The outputs of the third selector SN3 to the N+1th selector SN(N+1) are each used to output the N-1th level secondary minimum value corresponding to the minimum of the two N-1th level minimum values, which are respectively used as the other N-1 Nth level secondary minimum values ​​corresponding to the Nth level minimum value. The Nth level minimum value corresponds to N Nth level secondary minimum values.

[0032] Preferably, the second smallest value comparison circuit includes M levels of tree comparison circuits, where M is an integer greater than 0. Each level of tree comparison circuit consists of one or more two-input comparators. Each comparator compares the two input values, outputs the smaller one, and then inputs it to the next level of tree comparison circuit for comparison, until the last level of tree comparison circuit outputs the minimum value.

[0033] Preferably, for each level of the tree comparison circuit, when the number of values ​​input to the tree comparison circuit is an even number A, the tree comparison circuit includes A / 2 comparators, which are used to compare the A input values ​​pairwise, and input the A / 2 smaller values ​​obtained from the comparison to the next level of the tree comparison circuit, where A is an even number greater than zero.

[0034] Preferably, for each level of the tree comparison circuit, when the number of values ​​input to the tree comparison circuit is an odd number B, the tree comparison circuit includes (B-1) / 2 comparators, which are used to compare the first to the (B-1)th input numbers pairwise to obtain the (B-1) / 2 smaller values, and input the Bth input number and the (B-1) / 2 smaller values ​​to the next level of the tree comparison circuit, where B is an odd number greater than 1.

[0035] Preferably, one or more pipelines are inserted into the minimum and second minimum value retrieval circuits.

[0036] The beneficial effects of this invention are: by designing a minimum and second minimum value retrieval method, and by retaining the accompanying second minimum value compared with the minimum value, more accurate minimum and second minimum value results can be obtained. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the circuit structure for finding the minimum and second smallest values ​​of a set of data in the existing technology;

[0038] Figure 2 This is a flowchart of an embodiment of the retrieval method of the present invention;

[0039] Figure 3 yes Figure 2 Sub-flowchart of step S101;

[0040] Figure 4 This is a schematic diagram of the first to Nth stage comparison circuit framework of an embodiment of the retrieval circuit of the present invention;

[0041] Figure 5 This is a schematic diagram of the first-stage comparison unit structure of an embodiment of the retrieval circuit of the present invention;

[0042] Figure 6 This is a schematic diagram of the second-level comparison unit structure of an embodiment of the retrieval circuit of the present invention;

[0043] Figure 7 This is a schematic diagram of the third-level comparison unit structure of an embodiment of the retrieval circuit of the present invention;

[0044] Figure 8 This is a schematic diagram of the Nth-level comparison circuit structure of an embodiment of the retrieval circuit of the present invention;

[0045] Figure 9 This is a schematic diagram of the fifth-stage comparison circuit structure of an embodiment of the retrieval circuit of the present invention;

[0046] Figure 10 This is a schematic diagram of the N second smallest value comparison circuit structure of an embodiment of the retrieval circuit of the present invention;

[0047] Figure 11 This is a schematic diagram of the structure of a five-value comparison circuit in one embodiment of the retrieval circuit of the present invention;

[0048] Figure 12 This is a schematic diagram of the first to Nth stage comparison circuit framework of an embodiment of the retrieval circuit of the present invention;

[0049] Figure 13 This is a schematic diagram of the second-level comparison unit structure of an embodiment of the retrieval circuit of the present invention;

[0050] Figure 14 This is a schematic diagram of the third-level comparison unit structure of an embodiment of the retrieval circuit of the present invention;

[0051] Figure 15 This is a schematic diagram of the Nth-level comparison circuit structure of an embodiment of the retrieval circuit of the present invention. Detailed Implementation

[0052] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0053] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0054] Example 1

[0055] against Figure 1 The comparator in the input data shows that the second smallest value of the minimum of the 32 input numbers can only exist among the 5 values ​​compared with the minimum. Based on this, the present invention proposes a minimum and second smallest value retrieval method. This retrieval method is based on 2... N The system performs N levels of comparisons on distinct numbers. At each level, the minimum value is obtained, and the accompanying second smallest value corresponding to the minimum value of that level is retained. The accompanying second smallest value is one of the values ​​that has been compared with the minimum value of the current level but is greater than the minimum value. There are usually multiple such accompanying second smallest values.

[0056] Furthermore, at the next level, the second smallest value corresponding to the previous level of the obtained minimum value is inherited as the second smallest value corresponding to the minimum value at this level.

[0057] When we reach level N, when we obtain the final correct minimum value through comparison, we can also obtain the accompanying second smallest value array corresponding to the minimum value. The values ​​in this accompanying second smallest value array are the values ​​that have been compared with the minimum value. The true second smallest value must exist in this accompanying second smallest value array. Then, we find the minimum value from this accompanying second smallest value array, thus ensuring that we obtain the most accurate second smallest value.

[0058] Specifically, refer to Figure 2 The flowchart of an embodiment of the retrieval method of the present invention is shown in the figure. The present invention provides a minimum value and second minimum value retrieval method, including the following steps:

[0059] S101: 2 NThe system performs N levels of comparisons on distinct data points to obtain the minimum value and N adjacent second-smallest values, where N is an integer greater than 0.

[0060] S102: Compare the N adjacent second smallest values ​​pairwise, and obtain the true second smallest value through multi-level tree comparison;

[0061] S103: Output the minimum and second minimum values.

[0062] Further, refer to Figure 3 As shown, step S101 further includes:

[0063] S1011: First-level comparison: Compare 2 N Compare each pair of distinct data points to obtain a length of 2. N-1 The array consists of a first-level minimum value array and a first-level adjoint second minimum value array; where the first-level minimum value is the smaller of the pairwise comparison data, and the first-level adjoint second minimum value is the larger of the pairwise comparison data, so that each first-level minimum value corresponds to one adjoint second minimum value;

[0064] S1012: Second-level comparison: Perform pairwise comparisons on the minimum values ​​of the first level to obtain a value of length 2. N-2 The second-level minimum value array and the second-level adjoint second minimum value array; wherein, the second-level minimum value is the smaller of the pairwise comparison data, and the second-level adjoint second minimum value is the larger of the pairwise comparison data; further, the 2 values ​​corresponding to the second-level minimum value in the first-level adjoint second minimum value array are... N-2 Each data point is added to the corresponding second-level adjoint minimum value array, so that each second-level minimum value has 2 adjoint minimum values;

[0065] S1013: Third-level comparison: Perform pairwise comparisons on the minimum values ​​of the second level to obtain a value of length 2. N-3 The third-level minimum value array and the third-level adjoint second minimum value array; wherein, the third-level minimum value is the smaller of the pairwise comparison data, and the third-level adjoint second minimum value is the larger of the pairwise comparison data; further, the 2 values ​​corresponding to the third-level minimum value in the second-level adjoint second minimum value array are... N-3 Each data point is added to the corresponding third-level adjoint second smallest value array, so that each third-level minimum value corresponds to 3 adjoint second smallest values;

[0066] S1014: By analogy, perform comparisons at each level until the Nth level comparison, to obtain an Nth level minimum value array and an Nth level second minimum value array of length 1; where the Nth level minimum value is the smaller of the pairwise compared data, and the Nth level second minimum value is the larger of the pairwise compared data; further, add the data corresponding to the Nth level minimum value in the (N-1)th level second minimum value array to the corresponding Nth level second minimum value array, thus obtaining a total of N second minimum values.

[0067] In summary, the method provided by this invention addresses the input of 2... N Based on multi-level pairwise comparisons of the numerical values, while obtaining the minimum value at each level, the accompanying second smallest value corresponding to the minimum value at that level is retained. This accompanying second smallest value consists of those values ​​that have been compared with the minimum value in the same level but are greater than the minimum value. Finally, the accompanying second smallest values ​​of the last level are compared pairwise again to obtain the second smallest value result immediately adjacent to the minimum value. Compared with the prior art, the method of this invention can obtain a more accurate second smallest value result. At the same time, the method of this invention is simple in design and easy to implement in circuits, reducing the complexity of circuit design.

[0068] Example 2

[0069] refer to Figure 4 , Figure 4 This is a schematic diagram of stages 1-N of an embodiment of the retrieval circuit of the present invention.

[0070] As shown in the figure, this invention provides a minimum and second minimum value retrieval circuit to implement the retrieval method in Embodiment 1, for parallel input 2 N The minimum and second minimum values ​​are retrieved from a set of distinct input data, where N is greater than or equal to 1, including N levels of comparison circuits.

[0071] The first-stage comparator circuit includes 2 N-1 There are three identical first-level comparison units. The first first-level comparison unit includes input terminals [Din_1, Din_2] and output terminals [smin_1_1, min_1_1]. The minimum value of the input data corresponding to input terminals [Din_1, Din_2] is output by min_1_1, and the second minimum value is output by smin_1_1. The second first-level comparison unit includes input terminals [Din_3, Din_4] and output terminals [smin_1_2, min_1_2]. The minimum value of the input data corresponding to input terminals [Din_3, Din_4] is output by min_1_2, and the second minimum value is output by smin_1_2. And so on. N-1 Each first-level comparison unit includes the input terminal [Din_2] N -1、Din_2 N Output terminal [smin_1_2] N-1 min_1_2 N-1 ], Input terminal [Din_2 N -1、Din_2 N The minimum value in the corresponding input data is min_1_2. N-1 Output, the second smallest value is smin_1_2 N-1 Output;

[0072] The second-stage comparator circuit includes 2 N-2 There are three identical second-stage comparator units. The first second-stage comparator unit includes input terminals corresponding to the output terminals [smin_1_1, smin_1_2, min_1_1, min_1_2] of the first-stage comparator circuit, and includes output terminals [smin_2_1_1, smin_2_1_2, min_2_1]. The second second-stage comparator unit includes input terminals corresponding to the output terminals [smin_1_3, smin_1_4, min_1_3, min_1_4] of the first-stage comparator circuit, and includes output terminals [smin_2_2_1, smin_2_2_2, min_2_2]. And so on. N-2 The second-stage comparator unit and the output of the first-stage comparator circuit [smin_1_(2 N-1 -1), smin_1_2 N-1 min_1_(2 N-1 -1), min_1_2 N-1 Correspondingly, and including the output terminal [smin_2_2] N-2 _1、smin_2_2 N-2 _2、min_2_2 N-2 ];

[0073] The third-stage comparator circuit includes 2 N-3 There are three identical third-level comparison units, wherein the first third-level comparison unit includes input terminals corresponding to the output terminals of the second-level comparison circuit [smin_2_1_1, smin_2_2_1, smin_2_1_2, smin_2_2_2, min_2_1, min_2_2], and includes output terminals [smin_3_1_1, smin_3_1_2, smin_3_1_3, min_3_1]; the second third-level comparison unit includes input terminals corresponding to the output terminals of the second-level comparison circuit [smin_2_3_1, smin_2_4_1, smin_2_3_2, smin_2_4_2, min_2_3, min_2_4], and includes output terminals [smin_3_2_1, smin_3_2_2, smin_3_2_3, min_3_2]; and so on, the second... N-3 The third-stage comparator unit and the output of the second-stage comparator circuit [smin_2_(2 N-2 -1)_1、smin_2_2 N-2 _1、smin_2_(2 N-2 -1)_2、smin_2_2 N -2 _2、min_2_(2 N-2-1), min_2_2 N-2 Correspondingly, and including the output terminal [smin_3_2] N-3 _1、smin_3_2 N-3 _2、smin_3_2 N-3 _3、min_3_2 N-3 ];

[0074] Similarly, the Nth stage comparator circuit includes input terminals corresponding to the output terminals of the (N-1)th stage comparator circuit [smin_(N-1)_1_1, smin_(N-1)_2_1, smin_(N-1)_1_2, smin_(N-1)_2_2, ..., smin_(N-1)_1_(N-1), smin_(N-1)_2_(N-1), min_(N-1)_1, min_(N-1)_2], and output terminals [smin_N_1, smin_N_2, ..., smin_N_N, min_N]; wherein the output terminal min_N generates an output 2. N The minimum value min among the input data.

[0075] In summary, the minimum and second minimum value retrieval circuits provided by this invention, when processing the input 2 N Based on multi-level pairwise comparisons of the values, while obtaining the minimum value at each level, the accompanying second smallest value corresponding to the minimum value at that level is retained. This accompanying second smallest value is those values ​​that have been compared with the minimum value in this level but are greater than the minimum value. Finally, the accompanying second smallest values ​​of the last level are compared pairwise again to obtain the second smallest value result that is immediately adjacent to the minimum value.

[0076] Compared with the prior art, the retrieval circuit of this invention can obtain a more accurate second smallest value result because it retains the accompanying second smallest value compared with the minimum value. At the same time, the circuit of this invention is simple and easy to implement.

[0077] Further, refer to Figure 10 The output of the Nth stage comparator circuit [smin_N_1, smin_N_2, ..., smin_N_N] is input to the second smallest comparator circuit to produce the minimum output value, which is 2. N The second smallest value, smin, among the input data.

[0078] By using the second smallest value comparison circuit of the present invention, a second smallest value result that is closer to the minimum value can be obtained, that is, a more accurate second smallest value result can be obtained.

[0079] Furthermore, Figure 5This is a schematic diagram of the first-stage comparison unit structure of an embodiment of the retrieval circuit of the present invention. As shown in the figure, the first-stage comparison unit includes a B1 and two selectors. B1 includes two input terminals for inputting two input data. The output terminal of B1 is electrically connected to the selection control terminals of the two selectors respectively.

[0080] The selector includes a first selector S11 and a second selector S12. The first input terminal of the first selector S11 is electrically connected to the first input terminal of B1, and the second input terminal of the first selector S11 is electrically connected to the second input terminal of B1. The first input terminal of the second selector S12 is electrically connected to the second input terminal of B1, and the second input terminal of the second selector S12 is electrically connected to the first input terminal of B1. The output terminal of the first selector S11 is used to output the first minimum value of the two input data, and the output terminal of the second selector S12 is used to output the second minimum value of the first accompanying value of the two input data. The second minimum value of the first accompanying value is the second minimum value of the first minimum value. Each first minimum value output by the first comparison unit corresponds to one second minimum value of the first accompanying value.

[0081] Furthermore, Figure 6 This is a schematic diagram of the second-stage comparison unit structure of an embodiment of the retrieval circuit of the present invention. As shown in the figure, the second-stage comparison unit includes a comparator B2 and three selectors. The comparator B2 includes two input terminals for inputting the two minimum values ​​of the first stage output by the first-stage comparison circuit. The output terminal of the comparator B2 is electrically connected to the selection control terminals of the three selectors respectively.

[0082] The selector includes a first selector S21, a second selector S22, and a third selector S23. The first input terminal of the first selector S21 is electrically connected to the first input terminal of comparator B2, and the second input terminal of the first selector S21 is electrically connected to the second input terminal of comparator B2. The first input terminal of the second selector S22 is electrically connected to the second input terminal of comparator B2, and the second input terminal of the second selector S22 is electrically connected to the first input terminal of comparator B2. The first and second input terminals of the third selector S23 are respectively used to input the two first-stage secondary minimum values ​​of the first-stage comparator circuit output.

[0083] In this context, the first-stage adjoint second smallest value input to the third selector S23 corresponds one-to-one with the first-stage minimum value input to the comparator B2. For example, refer to... Figure 6As shown, if the first input of comparator B2 is min_1_1, then the first input of the third selector S23 corresponds to the first-level adjoint second smallest value smin_1_1 of the first-level minimum value min_1_1. Similarly, if the second input of comparator B2 is min_1_2, then the second input of the third selector S23 corresponds to the first-level adjoint second smallest value smin_1_2 of the first-level minimum value min_1_2. The purpose of this arrangement is that each selector chooses from two second smallest values ​​belonging to different minimum values.

[0084] The output of the first selector S21 is used to output the minimum of the two first-level minimum values ​​as the second-level minimum value. The output of the second selector S22 is used to output the second smallest of the two first-level minimum values ​​as one second-level accompanying second smallest value corresponding to the second-level minimum value. The output of the third selector S23 is used to output the second second accompanying second smallest value corresponding to the minimum of the two second-level minimum values ​​as another second-level accompanying second smallest value corresponding to the second-level minimum value. Thus, the second-level minimum value output by the second-level comparison unit corresponds to two second-level accompanying second smallest values.

[0085] For example, refer to Figure 6 As shown, if the minimum value min_2_1 = min_1_1 is obtained from the comparison at this level (second level), then the second minimum value smin_2_1_1 output by the third selector S23 at the second level will be smin_2_1_1 = smin_1_1. This is because, referring to... Figure 5 As shown in the output, smin_1_1 is the first-level conjunct second smallest value of the corresponding first-level minimum value min_1_1.

[0086] Conversely, if the minimum value min_2_1 = min_1_2 is obtained by comparison at this level (second level), then the second minimum value smin_2_1_1 = smin_1_2 is output by the third selector S23.

[0087] In summary, each selector chooses from two second-smallest values ​​that are different minimum values, and the final selected second-smallest value must correspond to the minimum value that was selected, that is, the value that was compared with that minimum value.

[0088] Furthermore, Figure 7 This is a schematic diagram of the third-level comparison unit structure of an embodiment of the retrieval circuit of the present invention. As shown in the figure, the third-level comparison unit includes a comparator B3 and four selectors. The comparator B3 includes two input terminals for inputting the two minimum values ​​of the second-level comparison circuit output. The output terminal of the comparator B3 is electrically connected to the selection control terminals of the four selectors respectively.

[0089] The selectors include a first selector S31, a second selector S32, a third selector S33, and a fourth selector S34. The first input terminal of the first selector S31 is electrically connected to the first input terminal of comparator B3, and the second input terminal of the first selector S31 is electrically connected to the second input terminal of comparator B3. The first input terminal of the second selector S32 is electrically connected to the second input terminal of comparator B3, and the second input terminal of the second selector S32 is electrically connected to the first input terminal of comparator B3. The first and second input terminals of the third and fourth selectors S34 are respectively used to input the two second-stage adjoint minimum values ​​of the output of the second-stage comparator circuit.

[0090] In this context, the second-stage adjoint second smallest value input to the third and fourth selectors S34 corresponds one-to-one with the second-stage minimum value input to the comparator B3. For example, refer to... Figure 7 As shown, if the first input of comparator B3 is the second-level minimum value min_2_1, then the first input of the third selector S33 is the second-level adjoint second-minimum value smin_2_1_1 corresponding to the second-level minimum value min_2_1. Similarly, if the second input of comparator B3 is the second-level minimum value min_2_2, then the second input of the third selector S33 is the second-level adjoint second-minimum value smin_2_2_1 corresponding to the second-level minimum value min_2_2. And so on, the first input of the fourth selector S34 is another second-level adjoint second-minimum value smin_2_1_2 of the second-level minimum value min_2_1, and the second input of the fourth selector S34 is another second-level adjoint second-minimum value smin_2_2_2 of the second-level minimum value min_2_2. This ensures that each selector chooses from two second-minimum values ​​belonging to different minimum values.

[0091] The output of the first selector S31 is used to output the minimum of the two second-level minimum values ​​as the third-level minimum value. The output of the second selector S32 is used to output the second smallest of the two second-level minimum values ​​as one third-level accompanying second smallest value corresponding to the third-level minimum value. The outputs of the third and fourth selectors S34 are used to output the second smallest accompanying second smallest value corresponding to the minimum of the two second-level minimum values ​​as two other third-level accompanying second smallest values ​​corresponding to the third-level minimum value. The third-level minimum value output by the third-level comparison unit corresponds to three third-level accompanying second smallest values.

[0092] For example, refer to Figure 7 As shown, if the minimum value min_3_1 = min_2_1 is obtained from the comparison at this level (the third level), then the third selector S33 will output the second smallest associated value smin_3_1_1 = smin_2_1_1. This is because, referring to... Figure 6As shown in the output, smin_2_1_1 is the first-level adjoint second smallest value of the corresponding second-level minimum value min_2_1.

[0093] Conversely, if the minimum value min_3_1 = min_2_2 is obtained by comparison at this level (the third level), then the third level's second smallest associated value smin_3_1_1 = smin_2_2_1 is output by the third selector S33.

[0094] In summary, each selector chooses from two second-smallest values ​​that are different minimum values, and the final selected second-smallest value must correspond to the minimum value that was selected, that is, the value that was compared with that minimum value.

[0095] Furthermore, and so on, Figure 8 This is a schematic diagram of the Nth-stage comparison circuit structure of an embodiment of the retrieval circuit of the present invention. As shown in the figure, the Nth-stage comparison circuit includes a comparator BN and N+1 selectors. The comparator BN includes two input terminals for inputting the two minimum values ​​of the (N-1)th stage output of the (N-1)th stage comparison circuit. The output terminal of the comparator BN is electrically connected to the selection control terminals of the N+1 selectors.

[0096] The selectors include a first selector SN1, a second selector SN2, ... up to the (N+1)th selector SN(N+1). The first input terminal of the first selector SN1 is electrically connected to the first input terminal of comparator BN, and the second input terminal of the first selector SN1 is electrically connected to the second input terminal of comparator BN. The first input terminal of the second selector SN2 is electrically connected to the second input terminal of comparator BN, and the second input terminal of the second selector SN2 is electrically connected to the first input terminal of comparator BN. The first and second input terminals of the third selector SN3 to the (N+1)th selector SN(N+1) are respectively used to input the two (N-1)th stage adjoint second smallest values ​​of the comparator circuit. The (N-1)th stage adjoint second smallest values ​​input by the third selector SN3 to the (N+1)th selector SN(N+1) correspond one-to-one with the (N-1)th stage minimum value input by comparator BN.

[0097] The output of the first selector SN1 is used to output the minimum of the two (N-1)th level minimums, which is taken as the Nth level minimum. The output of the second selector SN2 is used to output the second smallest of the two (N-1)th level minimums, which is taken as one Nth level accompanying second smallest value corresponding to the Nth level minimum. The outputs of the third selector SN3 to the (N+1)th selector SN(N+1) are used to output the (N-1)th level accompanying second smallest values ​​corresponding to the minimum of the two (N-1)th level minimums. These N-1 output values ​​are taken as the other N-1 Nth level accompanying second smallest values ​​corresponding to the Nth level minimum. The Nth level minimum corresponds to N N Nth level accompanying second smallest values.

[0098] Further, Figure 10 is a schematic diagram of the structure of the second - smallest value comparison circuit in an embodiment of the retrieval circuit of the present invention. As shown in the figure, the output terminals [smin_N_1, smin_N_2, ……, smin_N_N] of the N - th stage comparison circuit are input into the second - smallest value comparison circuit to generate the minimum value of the output, which is the second - smallest value among the 2 N input data, smin.

[0099] Among them, the second - smallest value comparison circuit includes M - stage tree - shaped comparison circuits. Each stage is a pairwise comparison. That is to say, each stage consists of one or more two - input comparators. Each comparator compares the two input values and outputs the smaller one, and then inputs it to the next - stage tree - shaped comparison circuit for comparison until the last - stage tree - shaped comparison circuit outputs the minimum value. It goes through M stages in total, and M is related to the number of input second - smallest values.

[0100] Specifically, referring to Figure 11 , when the number of input second - smallest values is 5, then M = 3. The comparison of these 5 second - smallest values is completed through three - stage tree - shaped comparison circuits, and finally the minimum value among these 5 second - smallest values is obtained as the second - smallest value smin among the 2 N input data. The first - stage tree - shaped comparison circuit includes two comparators, the second - stage tree - shaped comparison circuit includes 1 comparator, and the third - stage tree - shaped comparison circuit (the M - th stage tree - shaped comparison circuit) includes 1 comparator.

[0101] Preferably, for the i - th stage tree - shaped comparison circuit (i is a positive integer and 0 < i < M + 1), there are the following implementation methods:

[0102] When the number of input values is an even number A (A is an even number greater than zero), the i - th stage tree - shaped comparison circuit includes A / 2 comparators, which are used to perform pairwise comparison on the A input values, and input the A / 2 smaller values obtained from the comparison to the next - stage tree - shaped comparison circuit (the (i + 1) - th stage tree - shaped comparison circuit).

[0103] Among them, each comparator includes two input terminals and one output terminal. The input terminals of the comparator are used to input the two second - smallest values to be compared, and the output terminal is used to output the smaller value of the two second - smallest values as the i - th stage second - smallest value, and input the i - th stage second - smallest value to the next - stage tree - shaped comparison circuit.

[0104] When the number of input values is an odd number B (B is an odd number greater than 1), the i - th stage tree - shaped comparison circuit includes (B - 1) / 2 comparators, which are used to perform pairwise comparison on the first to the (B - 1) - th numbers of the input, obtain (B - 1) / 2 smaller values, and input the B - th number of the input and the (B - 1) / 2 smaller values to the next - stage tree - shaped comparison circuit (the (i + 1) - th stage tree - shaped comparison circuit).

[0105] Each comparator includes two input terminals and one output terminal. The input terminals of the comparator are used to input the two second smallest values ​​to be compared, and the output terminal is used to output the smaller of the two second smallest values ​​as the i-th level second smallest value. The i-th level second smallest value is then input to the next level tree comparison circuit.

[0106] Similarly, the M-th level tree comparison circuit (the last level tree comparison circuit) contains one comparator, which has two inputs and one output. The inputs of the comparator are used to input the two second smallest values ​​of the (M-1)-th level to be compared, and the output is used to output the smaller of the two second smallest values ​​of the (M-1)-th level as the second smallest value of the M-th level. The second smallest value of the M-th level is the final second smallest value obtained.

[0107] Figure 11 A specific implementation example of a three-level tree comparison circuit of the present invention is described in detail below:

[0108] refer to Figure 11 In the first-level tree comparison circuit, the number of input values ​​is an odd number, 5, so B = 5 and i = 1. Therefore, the first-level tree comparison circuit includes (5-1) / 2 = 2 comparators. The first-level tree comparison circuit generates two first-level second smallest values, which will be input into the second-level tree comparison circuit. In addition, since only the first four original input values ​​have been compared, the fifth original input value, smin_5_5, has not yet been compared and will also be used as the first-level second smallest value, continuing to be input into the second-level tree comparison circuit.

[0109] refer to Figure 11 In the second-level tree comparison circuit, the number of input values ​​is an odd number, 3. Therefore, B = 3 and i = 2. Thus, the second-level tree comparison circuit includes (3-1) / 2 = 1 comparator. The second-level tree comparison circuit generates one second-smallest value, which will be input to the third-level tree comparison circuit. Furthermore, since only the first two first-smallest values ​​are compared, the uncompared value smin_5_5, which has not yet been compared in the second-level tree comparison circuit, will also be used as the second-smallest value and continue to be input to the third-level tree comparison circuit.

[0110] refer to Figure 11 In the third-level tree-structured comparator circuit, the number of input values ​​is an even number, 2. Therefore, A = 2, i = 3, and M = 3. Thus, the third-level tree-structured comparator circuit includes 2 / 2 = 1 comparator. This circuit produces a third-level second-smallest value, which is the final second-smallest value obtained.

[0111] The above is just one example. The principle of other examples is similar. They all use a tree structure for pairwise comparisons to obtain the minimum value of a set of input data. These will not be elaborated further here.

[0112] Specifically, refer to Figure 5 , 6 Figures 7, 9, and 11 illustrate levels 1-8 of a specific retrieval circuit. (To be continued...) Figure 1 The comparison is performed, and the input is also selected as 32 numbers. Therefore, the comparison circuit contains 5 stages. The second smallest value obtained by the comparison circuit is 5, so the second smallest value comparison circuit is divided into 3 stages. As can be seen from the above, the retrieval circuit for the 32 data is divided into a total of 8 stages.

[0113] refer to Figure 5 In the first level, the 32 input data are compared pairwise. The smaller value is output as the local minimum of the first level, denoted as min_1_i, i = 1, 2, ..., 16, and the larger value is output as the second smallest value that accompanies this local minimum, denoted as smin_1_i, i = 1, 2, ..., 16.

[0114] refer to Figure 6 In the second level, each of the two min_1_i,i=1,2,…,16 is compared. The smaller value is output as the local minimum of the second level, denoted as min_2_i,i=1,2,…,8. The second smallest value of the smaller value is inherited to the second level as the first second smallest value of this local minimum, denoted as smin_2_i_1,i=1,2,…,8. The larger value is output as the second second smallest value of this local minimum, denoted as smin_2_i_2,i=1,2,…,8.

[0115] The same applies to Levels 3 and 4, so I will not repeat them here.

[0116] refer to Figure 9 At level 5, the minimum value is obtained along with five accompanying minor values.

[0117] refer to Figure 11 The true second minimum value is in Figure 8 Among the five accompanying second smallest values ​​obtained, the true second smallest value can be obtained after comparing the five accompanying second smallest values ​​through a three-level tree structure.

[0118] Only the minimum value is obtained Figure 1 Compared to the circuit shown, the retrieval circuit of the present invention only consumes three additional two-input comparators and a three-level tree comparison process, but can obtain a more accurate minimum value and the corresponding second smallest value.

[0119] Furthermore, to accelerate its operating speed, the present invention inserts multi-stage pipelines into the minimum and second minimum value retrieval circuits.

[0120] Pipelining works by systematically dividing logic circuits and inserting registers between these divisions to temporarily store intermediate data. The goal is to break down a large logical operation into several smaller logical operations, each with a shorter processing time and the ability to run in parallel, thereby increasing frequency and ultimately processing speed.

[0121] For example, in the minimum and second minimum value retrieval circuits, the output of each pair of comparison circuits is buffered by a register, so that the comparison circuits before and after the register can perform logic operations in parallel, thereby finding the minimum value and the corresponding second minimum value in a set of data within a short clock cycle.

[0122] Specifically, targeting Figure 5 , 6 A specific 8-level search circuit among 7, 9, and 11 can be used in the 1st, 3rd, and 5th level comparison circuits, as well as... Figure 11 By inserting registers into the second-level tree comparison circuit, a four-stage pipeline can be inserted into the eight-stage retrieval circuit, thereby improving the parallelism of the computation. The number of pipeline stages and the insertion position can be modified according to specific needs, and this invention does not impose any limitations.

[0123] Example 3

[0124] Regarding the retrieval circuit in Embodiment 2, the present invention also provides another implementation scheme.

[0125] like Figure 12 As shown, this invention provides a minimum and second minimum value retrieval circuit for parallel input 2 N The minimum and second minimum values ​​are retrieved from a set of distinct input data, where N is greater than or equal to 1, and the circuit includes N levels of comparison.

[0126] The first-stage comparator circuit includes 2 N-1 There are three identical first-level comparison units. The first first-level comparison unit includes input terminals [Din_1, Din_2] and output terminals [smin_1_1, min_1_1]. The minimum value of the input data corresponding to input terminals [Din_1, Din_2] is output by min_1_1, and the second minimum value is output by smin_1_1. The second first-level comparison unit includes input terminals [Din_3, Din_4] and output terminals [smin_1_2, min_1_2]. The minimum value of the input data corresponding to input terminals [Din_3, Din_4] is output by min_1_2, and the second minimum value is output by smin_1_2. And so on. N-1 Each first-level comparison unit includes the input terminal [Din_2] N -1、Din_2 N Output terminal [smin_1_2]N-1 min_1_2 N-1 ], Input terminal [Din_2 N -1、Din_2 N The minimum value in the corresponding input data is min_1_2. N-1 Output, the second smallest value is smin_1_2 N-1 Output;

[0127] The second-stage comparator circuit includes 2 N-2 There are three identical second-stage comparator units. The first second-stage comparator unit includes input terminals corresponding to the output terminals [smin_1_1, smin_1_2, min_1_1, min_1_2] of the first-stage comparator circuit, and includes output terminals [smin_2_1, min_2_1]. The second second-stage comparator unit includes input terminals corresponding to the output terminals [smin_1_3, smin_1_4, min_1_3, min_1_4] of the first-stage comparator circuit, and includes output terminals [smin_2_2, min_2_2]. And so on, the second... N-2 The second-stage comparator unit and the output of the first-stage comparator circuit [smin_1_(2 N-1 -1), smin_1_2 N-1 min_1_(2 N-1 -1), min_1_2 N-1 Correspondingly, and including the output terminal [smin_2_2] N-2 min_2_2 N-2 ];

[0128] The third-stage comparator circuit includes 2 N-3 There are three identical third-stage comparator units, wherein the first third-stage comparator unit includes input terminals corresponding to the output terminals [smin_2_1, smin_2_2, min_2_1, min_2_2] of the second-stage comparator circuit, and includes output terminals [smin_3_1, min_3_1]; the second third-stage comparator unit includes input terminals corresponding to the output terminals [smin_2_3, smin_2_4, min_2_3, min_2_4] of the second-stage comparator circuit, and includes output terminals [smin_3_2, min_3_2]; and so on, the second... N-3 The third-stage comparator unit and the output of the second-stage comparator circuit [smin_2_(2 N-2 -1), smin_2_2 N-2 min_2_(2 N-2 -1), min_2_2 N-2 Correspondingly, and including the output terminal [smin_3_2]N-3 min_3_2 N-3 ];

[0129] Similarly, the Nth stage comparator circuit includes input terminals corresponding to the output terminals [smin_(N-1)_1, smin_(N-1)_2, min_(N-1)_1, min_(N-1)_2] of the (N-1)th stage comparator circuit, and output terminals [smin, min]; wherein the output terminal min generates output 2. N The minimum value min among the input data is output at smin, which generates 2. N The second smallest value, smin, among the input data.

[0130] The difference from Embodiment 2 is that, starting from the second-level comparison unit, a second-smallest value comparator is added to the output to compare the two accompanying second-smallest values ​​again, so that the number of accompanying second-smallest values ​​output by each level comparison unit is 1 instead of N. Accordingly, each level comparison unit has only 3 selectors, used to output one minimum value and two accompanying second-smallest values.

[0131] Specifically, see the following reference figures. Figure 5 , 13 Sections 14 and 15 describe the comparison unit of this embodiment.

[0132] Figure 5 This is a schematic diagram of the first-level comparison unit structure in this embodiment, which is the same as the first-level comparison unit in Embodiment 2, and will not be described again here.

[0133] Figure 13 This is a schematic diagram of the second-level comparison unit structure in this embodiment, as shown below. Figure 13 As shown,

[0134] The second-stage comparison unit includes two comparators and three selectors. The first comparator B21 has two input terminals for inputting the two minimum values ​​of the first stage output from the first-stage comparison circuit. The output terminal of the first comparator B21 is electrically connected to the selection control terminals of the three selectors. The first input terminal of the first selector S21 is electrically connected to the first input terminal of the first comparator B21, and the second input terminal of the first selector S21 is electrically connected to the second input terminal of the first comparator B21. The first input terminal of the second selector S22 is electrically connected to the second input terminal of the first comparator B21, and the second input terminal of the second selector S22 is electrically connected to the first input terminal of the first comparator B21. The first and second input terminals of the third selector S23 are respectively used to input the two adjacent second minimum values ​​of the first stage output from the first-stage comparison circuit.

[0135] The output of the first selector S21 is used to output the minimum value among the two first-level minimum values, the output of the second selector S22 is used to output the second smallest value among the two first-level minimum values, and the output of the third selector S23 is used to output the second smallest value that is the adjacent value of the previous level corresponding to the minimum value.

[0136] The second comparator B22 includes two input terminals. The output terminal of the first selector S21 is electrically connected to the first input terminal of the second comparator B22, and the output terminal of the second selector S22 is electrically connected to the second input terminal of the second comparator B22. The two input terminals of the second comparator B22 are used to input the two adjacent second smallest values ​​output by the first selector S21 and the second selector S22. The output terminal of the second comparator B22 is used to output the smaller of the two adjacent second smallest values, which is used as the adjacent second smallest value of the minimum value output by the current comparison unit.

[0137] For example, if the minimum value min_2_1 = min_1_1 is obtained from the comparison at this level (second level), then the second smallest value smin_2_1_1 output by the third selector S23 will be smin_2_1_1 = smin_1_1. This is because, reference Figure 5 As shown in the output, smin_1_1 is the second smallest value of the corresponding previous level (first level) minimum value min_1_1, which is also the second smallest value of min_1_1.

[0138] Then, the second smallest associated value output by the third selector S23 and the second smallest value output by the second selector S22 are input to the second comparator B22. After comparison, the smaller one is output as the second smallest associated value smin_2_1 of this stage. For example, if smin_2_1_1 <smin_2_1_2,smin_2_1=smin_2_1_1。

[0139] Figure 14 This is a schematic diagram of the third-level comparison unit structure in this embodiment, as shown below. Figure 14 As shown, the structure is the same Figure 13 The second-level comparison unit structure shown is the same, and will not be described again here.

[0140] Figure 15 This is a schematic diagram of the Nth stage comparator circuit structure in this embodiment, as shown below. Figure 15 As shown, the structure is the same Figure 13 The second-level comparison unit shown has the same structure, but the difference is that at the output of the Nth-level comparison circuit, the minimum value min and the second minimum value smin obtained are the minimum and second minimum values ​​that need to be obtained in the end, and they will not enter the next level circuit.

[0141] Therefore, the difference between this solution and Embodiment 2 is that it does not require a second minimum value comparison circuit, but only an N-level comparison circuit is needed to directly obtain the minimum and second minimum values.

[0142] Compared to the solution in Embodiment 2, the solution in this embodiment consumes an additional N-1 two-input comparators, but eliminates the second-smallest value comparison circuit of the M-level tree comparison, and can still obtain the true minimum value and the corresponding second-smallest value.

[0143] Furthermore, similar to Embodiment 2, in order to speed up its operation, a multi-stage pipeline is inserted into the search circuit. For example, every two stages of the comparison circuit outputs through a register buffer, so that the comparison circuits before and after the register can perform logic operations in parallel, thereby finding the minimum value and the corresponding second smallest value in a set of data within a shorter clock cycle.

[0144] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A minimum and second minimum value retrieval circuit, characterized in that, For parallel input 2 N The minimum and second minimum values ​​are retrieved from a set of distinct input data, where N is greater than or equal to 1, and the circuit includes N levels of comparison. The first-stage comparator circuit includes 2 N-1 There are three identical first-level comparison units, wherein the first first-level comparison unit includes input terminals [Din_1, Din_2] and output terminals [smin_1_1, min_1_1]. The minimum value in the input data corresponding to input terminals [Din_1, Din_2] is output by min_1_1, and the second smallest value is output by smin_1_1. The second first-level comparison unit includes input terminals [Din_3, Din_4] and output terminals [smin_1_2, min_1_2]. The minimum value in the input data corresponding to input terminals [Din_3, Din_4] is output by min_1_2, and the second smallest value is output by smin_1_2. And so on, the 2nd N-1 Each of the first-level comparison units includes an input terminal [Din_2] N -1、Din_2 N Output terminal [smin_1_2] N-1 min_1_2 N-1 ], Input terminal [Din_2 N -1、Din_2 N The minimum value in the corresponding input data is min_1_2. N-1 Output, the second smallest value is smin_1_2 N-1 Output; The second-stage comparator circuit includes 2 N-2 There are two identical second-stage comparison units, wherein the first second-stage comparison unit includes an input terminal that corresponds to the output terminal [smin_1_1, smin_1_2, min_1_1, min_1_2] of the first-stage comparison circuit, and an output terminal [smin_2_1_1, smin_2_1_2, min_2_1]. The second second-stage comparison unit includes an input terminal that corresponds to the output terminal [smin_1_3, smin_1_4, min_1_3, min_1_4] of the first-stage comparison circuit, and an output terminal [smin_2_2_1, smin_2_2_2, min_2_2]. And so on, the 2nd N-2 The second-stage comparison unit and the output terminal of the first-stage comparison circuit [smin_1_(2) N -1 -1), smin_1_2 N-1 min_1_(2 N-1 -1), min_1_2 N-1 Correspondingly, and including the output terminal [smin_2_2] N-2 _1、smin_2_2 N-2 _2、min_2_2 N-2 ]; The third-stage comparator circuit includes 2 N-3 A third-level comparison unit with the same structure, wherein the first third-level comparison unit includes an input terminal corresponding to the output terminal [smin_2_1_1, smin_2_2_1, smin_2_1_2, smin_2_2_2, min_2_1, min_2_2] of the second-level comparison circuit, and includes an output terminal [smin_3_1_1, smin_3_1_2, smin_3_1_3, min_3_1]. The second third-stage comparison unit includes an input terminal that corresponds to the output terminal [smin_2_3_1, smin_2_4_1, smin_2_3_2, smin_2_4_2, min_2_3, min_2_4] of the second-stage comparison circuit, and includes an output terminal [smin_3_2_1, smin_3_2_2, smin_3_2_3, min_3_2]. And so on, the 2nd N-3 The third-stage comparison unit and the output terminal of the second-stage comparison circuit [smin_2_(2) N -2 -1)_1、smin_2_2 N-2 _1、smin_2_(2 N-2 -1)_2、smin_2_2 N-2 _2、min_2_(2 N-2 -1), min_2_2 N-2 Correspondingly, and including the output terminal [smin_3_2] N-3 _1、smin_3_2 N-3 _2、smin_3_2 N-3 _3、min_3_2 N-3 ]; Similarly, the Nth stage comparator circuit includes input terminals corresponding to the output terminals of the (N-1)th stage comparator circuit [smin_(N-1)_1_1, smin_(N-1)_2_1, smin_(N-1)_1_2, smin_(N-1)_2_2, ..., smin_(N-1)_1_(N-1), smin_(N-1)_2_(N-1), min_(N-1)_1, min_(N-1)_2], and includes output terminals [smin_N_1, smin_N_2, ..., smin_N_N, min_N]; wherein the output terminal min_N generates the output of the 2 N The minimum value among the input data; The output of the Nth stage comparator circuit [smin_N_1, smin_N_2, ..., smin_N_N] is input to the second smallest comparator circuit to generate the minimum output value, which is the 2 N The second minimum value among the input data.

2. The minimum and second minimum value retrieval circuit according to claim 1, characterized in that, The first-level comparison unit includes a comparator B1, a first selector S11, and a second selector S12. The comparator B1 includes two input terminals for inputting two input data, and the output terminal of the comparator B1 is electrically connected to the selection control terminals of the first selector S11 and the second selector S12, respectively. Wherein, the first input terminal of the first selector S11 is electrically connected to the first input terminal of the comparator B1, and the second input terminal of the first selector S11 is electrically connected to the second input terminal of the comparator B1; The first input terminal of the second selector S12 is electrically connected to the second input terminal of the comparator B1, and the second input terminal of the second selector S12 is electrically connected to the first input terminal of the comparator B1. The output of the first selector S11 is used to output the first minimum value of the two input data, and the output of the second selector S12 is used to output the second minimum value of the first accompanying data. Each first minimum value output by the first comparison unit corresponds to one second minimum value of the first accompanying data.

3. The minimum and second minimum value retrieval circuit according to claim 2, characterized in that, The second-level comparison unit includes a comparator B2 and a first selector S21, a second selector S22 and a third selector S23. The comparator B2 includes two input terminals for inputting the two minimum values ​​of the first-level comparison circuit output. The output terminal of the comparator B2 is electrically connected to the selection control terminals of the first selector S21, the second selector S22 and the third selector S23 respectively. Wherein, the first input terminal of the first selector S21 is electrically connected to the first input terminal of the comparator B2, and the second input terminal of the first selector S21 is electrically connected to the second input terminal of the comparator B2; the first input terminal of the second selector S22 is electrically connected to the second input terminal of the comparator B2, and the second input terminal of the second selector S22 is electrically connected to the first input terminal of the comparator B2; the first input terminal and the second input terminal of the third selector S23 are respectively used to input the two first-stage adjoint second smallest values ​​output by the first-stage comparator circuit. The output of the first selector S21 is used to output the minimum of the two first-level minimum values ​​as the second-level minimum value. The output of the second selector S22 is used to output the second smallest of the two first-level minimum values ​​as one second-level accompanying second smallest value corresponding to the second-level minimum value. The output of the third selector S23 is used to output the first-level accompanying second smallest value corresponding to the minimum of the two first-level minimum values ​​as another second-level accompanying second smallest value corresponding to the second-level minimum value. The second-level minimum value output by the second-level comparison unit corresponds to two second-level accompanying second smallest values.

4. The minimum and second minimum value retrieval circuit according to claim 3, characterized in that, The third-level comparison unit includes a comparator B3 and a first selector S31, a second selector S32, a third selector S33, and a fourth selector S34. The comparator B3 has two input terminals for inputting the two minimum values ​​of the second-level comparison circuit output. The output terminal of the comparator B3 is electrically connected to the selection control terminals of the first selector S31, the second selector S32, the third selector S33, and the fourth selector S34, respectively. The first input terminal of the first selector S31 is electrically connected to the first input terminal of the comparator B3, and the second input terminal of the first selector S31 is electrically connected to the second input terminal of the comparator B3; the first input terminal of the second selector S32 is electrically connected to the second input terminal of the comparator B3, and the second input terminal of the second selector S32 is electrically connected to the first input terminal of the comparator B3; the first and second input terminals of the third selector S33 and the fourth selector S34 are respectively used to input the two second-stage adjoint sub-small values ​​output by the second-stage comparator circuit. The output of the first selector S31 is used to output the minimum of the two second-level minimum values ​​as the third-level minimum value. The output of the second selector S32 is used to output the second smallest of the two second-level minimum values ​​as one third-level accompanying second smallest value corresponding to the third-level minimum value. The outputs of the third selector S33 and the fourth selector S34 are each used to output the second smallest accompanying second smallest value corresponding to the minimum of the two second-level minimum values ​​as two other third-level accompanying second smallest values ​​corresponding to the third-level minimum value. The third-level minimum value output by the third-level comparison unit corresponds to three third-level accompanying second smallest values.

5. The minimum and second minimum value retrieval circuit according to claim 4, characterized in that, The Nth stage comparison circuit includes a comparator BN and a first selector SN1 to an N+1th selector SN(N+1). The comparator BN has two input terminals for inputting the two minimum values ​​of the N-1th stage output of the N-1th stage comparison circuit. The output terminal of the comparator BN is electrically connected to the selection control terminals of the first selector SN1 to the N+1th selector SN(N+1). The first input terminal of the first selector SN1 is electrically connected to the first input terminal of the comparator BN, and the second input terminal of the first selector SN1 is electrically connected to the second input terminal of the comparator BN; the first input terminal of the second selector SN2 is electrically connected to the second input terminal of the comparator BN, and the second input terminal of the second selector SN2 is electrically connected to the first input terminal of the comparator BN; the first and second input terminals of the third selector SN3 to the (N+1)th selector SN(N+1) are respectively used to input the two (N-1)th stage secondary minimum values ​​of the N-1th stage comparator circuit; the output terminal of the first selector SN1 is used to output the minimum value of the two (N-1)th stage minimum values, which is the Nth stage minimum value, i.e., the 2 N The minimum value among the input data, the output of the second selector SN2 is used to output the second smallest value among the two (N-1)th level minimum values, as the Nth level accompanying second smallest value corresponding to the Nth level minimum value. The output terminals of the third selector SN3 to the N+1th selector SN(N+1) are each used to output the N-1th level secondary minimum value corresponding to the minimum value of the two N-1th level minimum values, which are respectively used as the other N-1 Nth level secondary minimum values ​​corresponding to the Nth level minimum value. The Nth level minimum value corresponds to N Nth level secondary minimum values.

6. The minimum and second minimum value retrieval circuit according to claim 5, characterized in that, The second smallest value comparison circuit includes M levels of tree comparison circuits, where M is an integer greater than 0. Each level of the tree comparison circuit consists of one or more two-input comparators. Each comparator compares the two input values, outputs the smaller one, and then inputs it to the next level of the tree comparison circuit for comparison, until the last level of the tree comparison circuit outputs the minimum value.

7. The minimum and second minimum value retrieval circuit according to claim 6, characterized in that, For each level of the tree comparison circuit, when the number of values ​​input to the tree comparison circuit is an even number A, the tree comparison circuit includes A / 2 comparators, which are used to compare the A input values ​​pairwise, and input the A / 2 smaller values ​​obtained from the comparison to the next level of the tree comparison circuit, where A is an even number greater than zero.

8. The minimum and second minimum value retrieval circuit according to claim 7, characterized in that, For each level of the tree comparison circuit, when the number of values ​​input to the tree comparison circuit is an odd number B, the tree comparison circuit includes (B-1) / 2 comparators, which are used to compare the first to the (B-1)th input numbers pairwise to obtain the (B-1) / 2 smaller values, and input the Bth input number and the (B-1) / 2 smaller values ​​to the next level of the tree comparison circuit, where B is an odd number greater than 1.

9. The minimum and second minimum value retrieval circuit according to claim 6, characterized in that, One or more pipelines are inserted into the minimum and second minimum value retrieval circuits.

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