Multiplier circuit and electronic device

Abstract

The application discloses a kind of multiplier circuit comprising multiple full adders, multiple flip-flops and multiple two-way selectors, wherein each of the multiple full adders includes addend input, addend input, carry input, output and carry output;Each full adder is cascaded by flip-flop, the carry output of each full adder is connected to the carry input by flip-flop, and the addend input of each full adder and the addend input of the first stage full adder are connected to the output of the corresponding two-way selector;Thus, when multiple bit multiplication is carried out, it can make the resource consumption less, the area is small;At the same time, pipeline structure can be realized, can be expanded, and the reconfigurability is strong.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a multiplier circuit and an electronic device. Background Technology

[0002] In related technologies, AI CNN neural networks utilize a large number of convolution operations. Convolution is a multiplication-addition process, and its performance is often determined by the speed of multiplication operations. Multiplication is costly and slow. Existing array multipliers are complex arrays of adders, generally consisting of three parts: generating partial products, accumulating partial products, and finally adding them. For example, an N×M array multiplier requires (N-2)×M full adders, N half adders, and N×M AND gates. Thus, existing array multipliers require a large number of full adders, half adders, and AND gates, resulting in high resource consumption and large area. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, one object of the present invention is to provide a multiplier circuit that consumes fewer resources and has a smaller area when performing multi-bit multiplication.

[0004] To achieve the above objectives, an embodiment of the present invention proposes a multiplier circuit, comprising: multiple full adders, multiple flip-flops, and multiple 2-to-1 multiplexers. Each full adder includes an augend input, an addend input, a carry input, an output, and a carry output. The full adders are cascaded together via flip-flops. The carry output of each full adder is connected to the carry input via a flip-flop. The addend input of each full adder and the augend input of the first-stage full adder are both connected to the output of the corresponding 2-to-1 multiplexer.

[0005] The multiplier circuit proposed in this embodiment of the invention includes multiple full adders, multiple flip-flops, and multiple 2-to-1 multiplexers. Each full adder includes an augend input, an addend input, a carry input, an output, and a carry output. Each full adder is cascaded with flip-flops, and the carry output of each full adder is connected to the carry input via a flip-flop. The addend input of each full adder and the augend input of the first-stage full adder are both connected to the output of the corresponding 2-to-1 multiplexer. Thus, when performing multi-bit multiplication, it can consume less resources and have a smaller area.

[0006] In addition, the multiplier circuit proposed above according to embodiments of the present invention may also have the following additional technical features:

[0007] Optionally, the output of the full adder is connected to the input of the augend of the next stage full adder via a flip-flop.

[0008] Optionally, the plurality of 2-to-1 multiplexers further include a first input terminal and a second input terminal, wherein the first input terminal of the 2-to-1 multiplexer connected to the augend input terminal of the first-stage full adder corresponds to the input of the multiplicand data, and the second input terminal corresponds to the input of 0s with the same number of digits as the multiplicand.

[0009] Optionally, in each of the 2-to-1 multiplexers connected to the addend input of each full adder, the first input of each 2-to-1 multiplexer corresponds to the input of the shifted multiplicand data, wherein the corresponding shift number is the same as the number of levels of the corresponding cascade, and the second input corresponds to the input of 0 after the multiplicand bit is increased, wherein the corresponding increase number is the same as the number of levels of the corresponding cascade.

[0010] Optionally, the plurality of 2-to-1 multiplexers further include a third input terminal, wherein when the input signal of the third input terminal is logic 1, the output terminal of the 2-to-1 multiplexer sequentially outputs the input data of the first input terminal, and when the input signal of the third input terminal is logic 0, the output terminal of the 2-to-1 multiplexer sequentially outputs the input data of the second input terminal.

[0011] Optionally, the third input terminal of each of the plurality of 2-to-1 multiplexers corresponds to one bit of the input multiplier data according to the number of levels of the cascaded connection.

[0012] Optionally, the number of full adders is determined by the number of bits in the multiplier.

[0013] Optionally, if the number of bits in the multiplier is n, then the number of full adders is n-1, where n is an integer greater than 2.

[0014] Optionally, the trigger is a D trigger.

[0015] To achieve the above objectives, a second aspect of the present invention provides an electronic device including the multiplier circuit described above.

[0016] According to embodiments of the present invention, when performing multi-bit multiplication using a multiplier circuit, the electronic device can consume fewer resources and occupy less space. Attached Figure Description

[0017] Figure 1 Here is the circuit schematic of an existing 4×4 array multiplier;

[0018] Figure 2 The circuit diagram is shown below for a multiplier circuit according to an embodiment of the present invention.

[0019] Figure 3The circuit diagram is a schematic diagram of a 4×4 multiplier circuit according to an embodiment of the present invention. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0021] In related technologies, such as Figure 1 As shown, existing array multipliers have complex structures, requiring numerous full adders, half adders, and AND gates, resulting in high resource consumption and large area. To address this, this invention proposes a multiplier circuit comprising multiple full adders, multiple flip-flops, and multiple 2-to-1 multiplexers. Each full adder includes an augend input, an addend input, a carry input, an output, and a carry output. The full adders are cascaded through flip-flops, and the carry output of each full adder is connected to the carry input via a flip-flop. The addend input of each full adder and the augend input of the first-stage full adder are both connected to the output of the corresponding 2-to-1 multiplexer. This design reduces resource consumption and area when performing multi-bit multiplication. During partial product accumulation, a pipelined structure can be implemented, outputting one bit of the final result per cycle, allowing for partial results to be obtained in advance without waiting for all bits to be summed, facilitating simultaneous subsequent calculations and shortening computation time. Furthermore, only full adder units need to be cascaded at the end, simplifying reconfiguration.

[0022] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0023] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0024] The multiplier circuit of an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0025] refer to Figure 2 As shown, the multiplier circuit proposed in this embodiment of the invention includes multiple full adders, multiple flip-flops D1, and multiple 2-to-1 multiplexers.

[0026] Each of the multiple full adders includes an augend input terminal a, an addend input terminal b, a carry input terminal cin, an output terminal s, and a carry output terminal c. The full adders are cascaded together by flip-flops, and the carry output terminal c of each full adder is connected to the carry input terminal cin through a flip-flop. The addend input terminal b of each full adder and the augend input terminal a of the first-stage full adder are both connected to the output terminal y of the corresponding 2-to-1 multiplexer.

[0027] As an example, the output terminal s of the full adder is connected to the input terminal of the augend of the next stage full adder via a flip-flop.

[0028] In other words, the outputs s of the multiple full adders in the multiplier circuit are connected to the augend input a of the next stage full adder through flip-flops, while the augend input a of the first stage full adder is connected to the output y of a 2-to-1 multiplexer. In addition, the addend input b of each of the multiple full adders is connected to a 2-to-1 multiplexer.

[0029] It should be noted that the corresponding data is selected by a 2-to-1 multiplexer and sequentially input to the corresponding full adder. A flip-flop baffles and feeds back the carry output of the full adder, while baffles the local bit and output of the full adder and propagates this feedback to the next stage. This delays the output result by one CLK, allowing each data item to be distributed to each stage of the full adder. During execution, each cycle outputs one bit of the final result (from least significant bit to most significant bit), creating a continuous, pipeline-like output. Thus, the carry output baffle feedback (serial) allows for advance accumulation of the carry, reducing the carry delay from the least significant bit to the most significant bit. The local bit and output baffle propagation to the next stage (parallel) allows for efficient and continuous output of the summation result in the last stage. The cascaded series has good scalability and a simple circuit structure. The calculation process starts directly from the least significant bit output, obtaining a partial result in advance without waiting for all bits to be summed, facilitating simultaneous subsequent calculations and shortening the calculation time.

[0030] As one embodiment, the multiple 2-to-1 multiplexers further include a first input terminal and a second input terminal, wherein the first input terminal of the 2-to-1 multiplexer connected to the augend input terminal of the first-stage full adder corresponds to the input of the multiplicand data, and the second input terminal corresponds to the input of 0 with the same number of bits as the multiplicand.

[0031] In other words, the data input to the first input terminal of the 2-to-1 multiplexer connected to the augend input terminal a of the first-stage full adder is the multiplicand data; the data input to the second input terminal of the 2-to-1 multiplexer connected to the augend input terminal a of the first-stage full adder is 0 with the same number of bits as the multiplicand.

[0032] It should be noted that the output of all 2-to-1 multiplexers outputs one bit of data every CLK, and the bits are input to the full adder sequentially from the least significant bit to the most significant bit.

[0033] As an example, in each of the 2-to-1 multiplexers connected to the addend input b of each full adder, the first input of each 2-to-1 multiplexer corresponds to the input of the shifted multiplicand data, wherein the corresponding shift number is the same as the number of levels of the corresponding cascade, and the second input corresponds to the input of 0 after the multiplicand bit is increased, wherein the corresponding increase number is the same as the number of levels of the corresponding cascade.

[0034] In other words, if the output terminal y of the 2-to-1 multiplexer is connected to the addend input terminal a of the first-stage full adder, then the data input to the first input terminal of the 2-to-1 multiplexer is the multiplicand data shifted left by one bit and padded with zeros at the end, and the data input to the second input terminal is the bit 0 of the multiplicand after adding one bit; if the output terminal y of the 2-to-1 multiplexer is connected to the addend input terminal a of the second-stage full adder, then the data input to the first input terminal of the 2-to-1 multiplexer is the multiplicand data shifted left by two bits and padded with zeros at the end, and the data input to the second input terminal is the same bit as the multiplicand after adding two bits, with 0 bits at the same position; and so on.

[0035] As one embodiment, the multiple 2-to-1 multiplexers also include a third input terminal, wherein when the input signal of the third input terminal is logic 1, the output terminal of the 2-to-1 multiplexer sequentially outputs the input data of the first input terminal, and when the input signal of the third input terminal is logic 0, the output terminal of the 2-to-1 multiplexer sequentially outputs the input data of the second input terminal.

[0036] In other words, a 2-to-1 multiplexer selects the input data from the first or second input terminal as the output based on whether the data input to the third input terminal is 0 or 1.

[0037] As an example, the third input of each of the multiple 2-to-1 multiplexers corresponds to one bit of the input multiplier data according to the number of levels of the cascaded connection.

[0038] In other words, the multiplier data, from the least significant bit to the most significant bit, is input to the third input of a cascaded 2-to-1 multiplexer with a series of levels from low to high. This allows the 2-to-1 multiplexer to select the corresponding data based on the multiplier data and input it into a full adder for accumulating partial products.

[0039] As an example, the number of full adders is determined by the number of bits in the multiplier.

[0040] As an example, if the number of bits in the multiplier is n, then the number of full adders is n-1, where n is an integer greater than 2.

[0041] As an example, the trigger is a D trigger.

[0042] As a specific embodiment, Figure 3 The circuit schematic of a 4×4 multiplier circuit according to an embodiment of the present invention is shown below. Figure 3 As shown, the multiplier circuit includes 3 full adders, 5 flip-flops, and 4 2-to-1 multiplexers.

[0043] Assuming the multiplicand is 1101 and the multiplier is 1011, the input data of the first input terminal of the first 2-to-1 multiplexer is 1101, the input data of the second input terminal is 0000, the input data B[0] of the third input terminal is 1, and the corresponding output data is 1101; the input data of the first input terminal of the second 2-to-1 multiplexer is 11010, the input data of the second input terminal is 00000, the input data B[1] of the third input terminal is 1, and the corresponding output data is 11010; the third 2-to-1 multiplexer... The input data of the first input terminal is 110100, the input data of the second input terminal is 000000, the input data of the third input terminal B[2] is 0, and the corresponding output data is 000000; the input data of the first input terminal of the fourth 2-to-1 multiplexer is 1101000, the input data of the second input terminal is 0000000, the input data of the third input terminal B[3] is 1, and the corresponding output data is 1101000; finally, the product after pipeline summation by the cascaded full adder is 10001111.

[0044] It should be noted that if the number of bits in the multiplier to be operated on needs to be increased by one, then only one full adder, one 2-to-1 multiplexer, and two flip-flops need to be cascaded.

[0045] In other words, the circuit of this invention consumes fewer resources and has a smaller area; at the same time, it can realize a pipeline structure, has a fast computing speed, can be expanded, and has strong reconfigurability.

[0046] In summary, the multiplier circuit includes multiple full adders, multiple flip-flops, and multiple 2-to-1 multiplexers. Each full adder includes an augend input, an addend input, a carry input, an output, and a carry output. The full adders are cascaded together via flip-flops, and the carry output of each full adder is connected to the carry input via a flip-flop. The addend input of each full adder and the augend input of the first-stage full adder are both connected to the output of the corresponding 2-to-1 multiplexer. Therefore, when performing multi-bit multiplication, it can consume fewer resources and has a smaller area.

[0047] In addition, embodiments of the present invention also provide an electronic device including the multiplier circuit described above.

[0048] According to embodiments of the present invention, when performing multi-bit multiplication using a multiplier circuit, the electronic device can consume fewer resources and occupy less space.

[0049] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0051] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0052] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0053] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0054] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A multiplier circuit, characterized in that, include: The system comprises multiple full adders, multiple flip-flops, and multiple 2-to-1 multiplexers. Each full adder includes an augend input, an addend input, a carry input, an output, and a carry output. The full adders are cascaded together via flip-flops. The carry output of each full adder is connected to the carry input via a flip-flop. The addend input of each full adder and the augend input of the first-stage full adder are both connected to the output of the corresponding 2-to-1 multiplexer. The plurality of 2-to-1 multiplexers further include a first input terminal and a second input terminal, wherein the first input terminal of the 2-to-1 multiplexer connected to the augend input terminal of the first stage full adder corresponds to the input of the multiplicand data, and the second input terminal corresponds to the input of 0 with the same number of digits as the multiplicand; In this process, the first input of each of the two-to-one multiplexers connected to the addend input of each full adder corresponds to the input of the multiplicand data after shifting, wherein the corresponding shift number is the same as the number of levels of the corresponding cascade; and the second input corresponds to the input of 0 after the multiplicand bit is increased, wherein the corresponding increase number is the same as the number of levels of the corresponding cascade. The plurality of 2-to-1 multiplexers further includes a third input terminal. When the input signal of the third input terminal is logic 1, the output terminal of the 2-to-1 multiplexer sequentially outputs the input data of the first input terminal. When the input signal of the third input terminal is logic 0, the output terminal of the 2-to-1 multiplexer sequentially outputs the input data of the second input terminal. In this context, the third input terminal of each of the plurality of 2-to-1 multiplexers corresponds to one bit of the input multiplier data according to the number of levels of the cascaded connection.

2. The multiplier circuit according to claim 1, characterized in that, The output of the full adder is connected to the input of the augend of the next stage full adder via a flip-flop.

3. The multiplier circuit according to claim 1, characterized in that, The number of full adders is determined by the number of bits in the multiplier.

4. The multiplier circuit according to claim 3, characterized in that, If the number of bits in the multiplier is n, then the number of full adders is n-1, where n is an integer greater than 2.

5. The multiplier circuit according to claim 1, characterized in that, The trigger is a D trigger.

6. An electronic device, characterized in that, Includes a multiplier circuit according to any one of claims 1-5.

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