A method and apparatus for managing applications in a chip
Patent Information
- Application Number
- CN202210945631.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-08
- Publication Date
- 2026-10-16
- Estimated Expiration
- 2042-08-08
AI Technical Summary
[0002]基于成本和功耗的考虑，低功耗嵌入式设备(如，物联网设备)，通常不具备MMU(Memory Management Unit，内存管理单元)，因此难以实现类似Linux和Windows系统中在内存中运行超出物理内存大小的应用程序，为了能够动态加载更大的应用程序，通常是选用具备更大内存的芯片或通过外扩内存的方式来扩大内存空间，硬件成本较高
[0020] By utilizing application space smaller than that required for application execution, code data can run normally. When the application fails to respond to commands, the application's execution is paused, and the response data required to respond to commands is stored in the application's runtime space. This allows the application to process commands normally, ensuring the application's normal requirements. This achieves the goal of dynamically loading user programs and running the application using less application space than required by the application itself, reducing the application's demand on system memory and thus reducing hardware costs.
Smart Images
Figure CN115421902B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of information processing, and more particularly to a method and apparatus for managing applications in a chip. Background Technology
[0002] Due to cost and power consumption considerations, low-power embedded devices (such as IoT devices) typically do not have an MMU (Memory Management Unit). Therefore, it is difficult to implement applications that exceed the physical memory size in memory, similar to Linux and Windows systems. In order to dynamically load larger applications, chips with larger memory are usually selected or the memory space is expanded by external memory expansion, which results in higher hardware costs. Summary of the Invention
[0003] To address any of the aforementioned technical problems, embodiments of this application provide a method and apparatus for managing applications within a chip.
[0004] On one hand, embodiments of this application provide a method for managing applications in a chip, characterized in that the chip includes mutually isolated system space and application space; wherein:
[0005] The system space is used for the operation and management of applications;
[0006] The application space is used to load some of the application's data;
[0007] The application space includes:
[0008] Application runtime space, used to run a portion of the code data of a loaded application;
[0009] The method includes:
[0010] During chip initialization, the code data required for the application to start is loaded according to the size of the application's runtime space;
[0011] Launch the application;
[0012] If the application cannot respond to the current instructions in the application runtime space, then the application execution is paused;
[0013] Obtain the response data required to respond to the instruction, and load the response data into the application runtime space;
[0014] Based on the data loading results of the application runtime space, the current instructions are reset;
[0015] Resume the application running and control the application to continue processing instructions in the application runtime space.
[0016] On the other hand, embodiments of this application provide a management device for applications in a chip, including:
[0017] Memory, which stores computer programs;
[0018] The processor is configured to run the computer program to perform the methods described above.
[0019] One of the above technical solutions has the following advantages or beneficial effects:
[0020] By utilizing application space smaller than that required for application execution, code data can run normally. When the application fails to respond to commands, the application's execution is paused, and the response data required to respond to commands is stored in the application's runtime space. This allows the application to process commands normally, ensuring the application's normal requirements. This achieves the goal of dynamically loading user programs and running the application using less application space than required by the application itself, reducing the application's demand on system memory and thus reducing hardware costs.
[0021] Other features and advantages of the embodiments of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the embodiments of this application. The objects and other advantages of the embodiments of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description
[0022] The accompanying drawings are used to provide a further understanding of the technical solutions of the embodiments of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0023] Figure 1 This is a schematic diagram of the chip's hardware structure.
[0024] Figure 2 A flowchart illustrating the chip application management method provided in this application embodiment;
[0025] Figure 3(a) is a schematic diagram of the first exception handling method provided in the embodiment of this application;
[0026] Figure 3(b) is a schematic diagram of the second exception handling method provided in the embodiments of this application;
[0027] Figure 3(c) is a schematic diagram of the third exception handling method provided in the embodiments of this application;
[0028] Figure 3(d) is a schematic diagram of the fourth exception handling method provided in the embodiments of this application. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.
[0030] In the process of developing this application, a technical analysis of the relevant technologies was conducted, and it was found that the relevant technologies have at least the following problems, including:
[0031] This invention uses an MPU (Memory Protection Unit) to dynamically load and run programs exceeding the specified memory capacity on low-cost systems without an MMU, thereby expanding the scope of use of the original system, avoiding situations that require higher-specification chips or more external memory, and reducing product costs.
[0032] Figure 1 This is a schematic diagram of the chip's hardware structure. (For example...) Figure 1 As shown, the chip includes a microcontroller unit (MCU), random access memory (RAM), flash memory, and an interface for communicating with peripherals. The flash memory is used to run the system firmware. After the system boots up, the firmware will run and load and execute the user application through the firmware. The interface is used to read the application. The object connected to this interface can be a storage device (such as a USB flash drive, SD card, or non-volatile flash memory) or another terminal device with communication capabilities (such as a network server). The user application data is downloaded to the system's designated RAM space through a communication protocol that both parties can recognize.
[0033] This application provides a scheme for dynamically loading user programs on an embedded system. This scheme can execute programs larger than the memory space on the embedded platform using a smaller memory space, thereby reducing the application's memory requirements and thus reducing the overall cost of the system.
[0034] Figure 2 A flowchart illustrating a method for managing applications in a chip, as provided in an embodiment of this application. Figure 2 As shown, the chip includes mutually isolated system space and application space; wherein:
[0035] The system space is used for the operation and management of applications;
[0036] Specifically, the system space is used to execute system programs to perform operations such as loading and running applications and handling interrupts.
[0037] The application space is the space used when running the application. Each loading operation only loads a portion of the application's data, thereby reducing the application's demand on chip space.
[0038] Furthermore, this application space includes the Application Run Space (ARS); wherein:
[0039] The application runtime space is the space where the application code is executed. It is used to run a portion of the code data of the loaded application. The size of the application runtime space is the page unit used to read the application's code data.
[0040] In the spatial architecture of the aforementioned chip, the method includes:
[0041] Step 201: During chip initialization, load the code data required for the application to start, according to the size of the application's runtime space;
[0042] Specifically, the first page of code data can be read into the application runtime space via an interface.
[0043] Step 202: Launch the application;
[0044] Specifically, the application is launched by running the code data already loaded in the application's runtime space.
[0045] Step 203: If the application cannot respond to the current instructions in the application runtime space, then suspend the application's execution;
[0046] Because the application runtime only loads a portion of the application's code data, the data stored in the application runtime is incomplete. Therefore, situations may arise where the response data required for an instruction is not stored. When the application runtime does not currently store the response data required for an instruction, the application cannot respond to the current instruction in the application runtime; pausing the application's execution can resolve this exception.
[0047] Step 204: Obtain the response data required to respond to the instruction, and load the response data into the application runtime space;
[0048] By loading response data into the application's runtime space, the application is able to respond to the current command.
[0049] Step 205: Based on the data loading results of the application runtime space, reset the current instructions;
[0050] After loading response data into the application runtime space, the application address corresponding to the data in the application runtime space may change, or the processing progress of the instructions may also change. To address these changes, the current instructions can be adaptively updated so that the application can successfully execute the instructions in the application runtime space.
[0051] Step 206: Resume the application from running and control the application to continue processing instructions in the application runtime space;
[0052] In cases where an application is unable to respond to commands, the application runtime space has been adapted so that the application can process commands normally. Therefore, the application can resume operation and continue to control the commands in the application runtime space.
[0053] The method provided in this application embodiment utilizes application space smaller than that required for application operation to ensure normal operation of code data. When the application cannot respond to instructions, it pauses the application's operation and stores the response data required to respond to the instructions in the application's runtime space, enabling the application to process instructions normally and ensuring the normal requirements of the application. This achieves the purpose of dynamically loading user programs and running the application using application space smaller than that required by the application, reducing the application's demand for system memory and thus reducing hardware costs.
[0054] The method provided in the embodiments of this application is described below:
[0055] In one exemplary embodiment, the memory protection unit (MPU) is used to divide the chip's space into a system space and an application space. The chip's operating modes support privileged mode and user mode. The system space is configured to be accessible only in privileged mode; the application space is configured to be accessed only in user mode.
[0056] The chip initialization is performed in privileged mode. After the application code data is loaded, the working mode is set to user mode.
[0057] Specifically, the chip is initialized in privileged mode, the first page of the application's code data is loaded into the ARS through the interface, the size of the data page is equal to the size of the ARS, the program stack pointer is configured to point to the starting address of the ARS and enter user mode to start running the application.
[0058] When the application cannot respond to the current instructions in the application runtime space, the working mode is set to privileged mode;
[0059] Specifically, when an application is executed, the system is in user mode. Therefore, when the application executes beyond the address range of the ARS, it will enter the MPU's exception interrupt handler. In the MPU's interrupt handler, the system is in privileged mode, thus having access to all address spaces and interfaces, enabling it to load response data and reset the current instructions.
[0060] Furthermore, the application space also includes: an application stack space, which serves as the stack space used by the application program; the registers used when the interrupt was triggered are stored only when the interrupt context is saved. Upon entering an interrupt, registers are pushed onto the stack to save the context, so that the context can be restored by popping registers from the stack after interrupt handling is complete. Additionally, the source register address / data and the target register address / data can be obtained and set using pointers to the application stack.
[0061] After loading the response data and resetting the current instructions, the working mode is set to user mode.
[0062] Specifically, exiting the MPU interrupt puts the system into user mode, allowing applications to resume running.
[0063] In one exemplary embodiment, the application space further includes an application cache space for storing some constant data of the application.
[0064] Both application code data and constant data are integer multiples of the application runtime space and application data cache space.
[0065] Preferably, during chip initialization, an MPU protection zone is configured. In this MPU protection zone, all RAM background modes are privileged mode for reading, writing, and execution, while user mode is prohibited from reading, writing, and execution. The configurations of other regions are shown in Table 1.
[0066]
[0067]
[0068] Table 1
[0069] The global variable space shown in Table 1 includes:
[0070] The first global variable space is used to store the corresponding page number in a pre-defined page index queue when cross-page calls occur in the application; and / or,
[0071] The second global variable space is used to record the mapping between application addresses and cache addresses.
[0072] In one exemplary embodiment, if the instruction is used to perform a cross-page function interface call on the application, the input parameter of the target address is in absolute address format.
[0073] If the instruction is not used to perform a cross-page function call to the application, the input parameters for the function call can be passed in either an absolute address or a relative address.
[0074] Specifically, when generating the application, global variables and stack depth should be allocated according to the system's resource availability. Furthermore, instructions that pass parameters via relative addresses (such as ADR) should be avoided when making cross-page function calls. When a page switch target address is involved, such instructions should be replaced with those that pass parameters via absolute addresses (such as MOV, LDR, etc.).
[0075] The application's data format can be either ELF or a custom format. Different file formats will affect how the system initializes the application's global variable space and reads code data when loading the application, but the above differences do not affect how the application executes in the application's runtime space.
[0076] After initialization, loading the first page of the application's code data into the ARS via the interface, and completing operations such as global variable and user stack settings, the application runs in user mode. When an application execution encounters an error exceeding the ARS address range, an MPU exception interrupt will be entered. In the interrupt handler, the system first determines whether the target address in the instruction belongs to the application's address range. If it does, it parses the registers in the stack to confirm the instruction that triggered the exception and the target address. It then reads the application data corresponding to the target address or loads the application page corresponding to the address that triggered the exception into the ARS. After that, it resets the registers saved in the stack, exits the interrupt, and resumes application execution.
[0077] For example, the Cortex-M3 is a 32-bit processor core. The Cortex-M3 has a Configurable Fault Status Register (CFSR) and a MemManageFault Address Register (MMFAR), which can be used to parse exception instructions and target addresses. In processors without these registers, the interrupt instruction and address can be identified by parsing the register values pushed onto the stack when the MPU interrupt context is protected, as shown in Figure 3(d).
[0078] The step of obtaining the response data required to respond to the instruction includes:
[0079] Based on the instruction content of the instruction, determine the page number corresponding to the stored response data to obtain the target page number;
[0080] Obtain the data corresponding to the target page number.
[0081] The response data can be either code data or constant data, and the required response data can be determined based on the page number.
[0082] See Figures 3(a) to 3(d) This will be explained through the following four situations.
[0083] Figure 3(a) is a schematic diagram of the first exception handling method provided in the embodiment of this application. As shown in Figure 3(a), the instruction is an execution instruction for code data, and the application has completed the execution of the code data stored in the application runtime space. This indicates that the operation that triggers the exception is an out-of-bounds error caused by the PC executing beyond the range of the ARS. In this case, the next page of the current page number is taken as the target page number, and the application data of the next page is loaded into the ARS as response data.
[0084] Figure 3(b) is a schematic diagram of the second exception handling method provided in the embodiment of this application. As shown in Figure 3(b), if the instruction is to jump from the current page number of the code data to another page number of the code data, indicating that the operation that triggers the exception is a jump instruction (such as BL instruction), then the other page number of the code data is used as the target page number, and the data corresponding to the other page number is loaded into the ARS as response data.
[0085] Figure 3(c) is a schematic diagram of the third exception handling method provided in the embodiment of this application. As shown in Figure 3(c), if the instruction is to return from the current page number of the code data to another page number of the code data, indicating that the operation that triggers the exception is a function return instruction, then the other page number of the code data is used as the target page number; and the data corresponding to the other page number is loaded into the ARS as response data.
[0086] Figure 3(d) is a schematic diagram of the fourth exception handling method provided in the embodiment of this application. As shown in Figure 3(d), if the instruction is to store the constant data corresponding to the target address into the target address, and the application cache space does not store the constant data corresponding to the target address, the operation that triggers the exception is to read the constant data of the application (e.g., LDR instructions) and use the cache page number corresponding to the target address as the target page number.
[0087] Specifically, the target address and destination register accessed by the source register in the instruction are parsed from the registers saved in the stack. It is determined whether the target address is within the address range of the currently loaded page in the application data cache space. If it is not within the address range, the application data page corresponding to the target address is read through the interface and loaded into the application data cache page. The data corresponding to the target address in the page is then written into the corresponding destination register in the stack.
[0088] For the cases shown in Figures 3(a) to 3(c), the value of the other page number of the code data is obtained in the following way:
[0089] Based on the content of the instruction and the current page number, determine the value of the other page number from the page index queue.
[0090] By utilizing the page numbers recorded in the page index queue, the processing efficiency of cross-page operations can be improved.
[0091] For the situation shown in Figure 3(d), the cache page number corresponding to the target address is obtained in the following ways:
[0092] Based on the correspondence between the addresses of applications and cache addresses stored in the system space, obtain the target cache address corresponding to the target address;
[0093] Obtain the constant data corresponding to the target page number from the target cache address.
[0094] By leveraging the mapping between application addresses and cache addresses, the required cached pages can be determined, improving data retrieval efficiency.
[0095] In one exemplary embodiment, resetting the current instructions based on the data loading result of the application runtime space includes:
[0096] Determine whether the page number of the code data in the application's runtime space has changed;
[0097] If the page number of the code data has not changed, and the current instruction has completed its response, then the next instruction is set to the current instruction;
[0098] If the page number of the code data changes, a new target address is set for the current instruction according to the instruction content.
[0099] Specifically, if the page number of the code data does not change, it indicates that the instruction is not used to implement cross-page calls. Therefore, the address range of the application corresponding to the code data in the application runtime space does not change, and thus, the target address of the current instruction does not change. Furthermore, after the response data is stored in the application runtime space, the next instruction can be set by determining whether the current instruction has been completed. Conversely, if the page number does not change, it indicates that the instruction is used to implement cross-page calls. Therefore, a new target address for instruction execution needs to be set according to the address range of the application corresponding to the new code data in the application runtime space.
[0100] Referring to Figure 3(a), if the instruction is an execution instruction for code data, and the application has completed the execution of the code data stored in the application runtime space, then the new target address is the starting address of the application runtime space;
[0101] Referring to Figure 3(b), if the instruction is to jump from the current page number to another page number, then the new target address is the offset address of the destination address in the application runtime space, wherein the destination address is the address of the target address corresponding to the other page number;
[0102] Referring to Figure 3(c), if the instruction is to return from the current page number to another page number, then the new target address is the offset address of the return address in the application runtime space, wherein the return address is the address of the target address corresponding to the other page number.
[0103] The above method can be applied to the ARMv7m architecture or other architectures with equivalent or higher capabilities.
[0104] In summary, the method provided in this application embodiment enables applications to run in less than the required RAM space on devices without an MMU, thereby reducing device hardware costs. In addition, by controlling the application to run in the space protected by the MPU, the application's access to the system space can be restricted, thus protecting the system space and improving security.
[0105] This application also provides a device for managing applications in a chip, including:
[0106] Memory, which stores computer programs;
[0107] A processor configured to run the computer program to perform the method described in any of the preceding descriptions.
[0108] This application provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described in any of the preceding descriptions when it runs.
[0109] This application provides an electronic device including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the method described in any of the preceding descriptions.
[0110] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
Claims
1. A method for managing applications in a chip, characterized in that, The chip does not have a memory management unit (MMU) and includes mutually isolated system space and application space divided by a memory protection unit (MPU); wherein: The system space is used for the operation and management of applications; The application space is used to load some of the application's data; The application space includes: Application runtime space is a page unit for reading application code data, used to run the code data contained in the page of the application currently loaded into the application runtime space; The method includes: During chip initialization, the first page of code data required for the application to start is loaded into the application runtime space according to the size of the application runtime space. Launch the application; If the application runtime space does not currently store the response data required for the current instruction, causing the application to be unable to respond to the current instruction in the application runtime space, then the application is paused and the MPU is triggered to perform an interrupt handling operation; The interrupt handling operations performed by the MPU include: Determine whether the target address in the current instruction belongs to the application address range. If it does, obtain the instruction that triggered the exception and the target address, obtain the application data corresponding to the target address or the application page data corresponding to the instruction that triggered the exception, and use it as the response data required to respond to the instruction. Load the response data into the application runtime space. Based on the data loading result of the application runtime space, the current instruction is reset, including: determining whether the page number of the code data in the application runtime space has changed; if the page number of the code data has not changed, and the current instruction has completed the response, then the next instruction is set as the current instruction; if the page number of the code data has changed, a new target address is set for the current instruction according to the instruction content of the instruction. After the MPU exits the interrupt handling operation, it resumes the application's execution and controls the application to continue processing instructions in the application runtime space.
2. The method according to claim 1, characterized in that: The chip supports privileged mode and user mode in its operation. The chip initialization is performed in privileged mode; After the application's code data has been loaded, set the working mode to user mode; After the application fails to respond to the current instructions in the application runtime space, the working mode is set to privileged mode; After resetting the current instructions, the operating mode is set to user mode.
3. The method according to claim 1, characterized in that: If the instruction is used to perform a cross-page function call to the application, the input parameters of the function call are passed in via absolute addresses.
4. The method according to claim 1, characterized in that: The application space also includes an application cache space, which is used to store some constant data of the application. The step of obtaining the response data required to respond to the instruction includes: Based on the instruction content of the instruction, determine the page number corresponding to the stored response data to obtain the target page number; Obtain the data corresponding to the target page number.
5. The method according to claim 4, characterized in that, The step of determining the page number corresponding to the stored response data based on the content of the instruction, and obtaining the target page number, includes: If the instruction is an execution instruction for code data, and the application has completed the execution of the code data stored in the application runtime space, then the next page of the current page number will be used as the target page number. If the instruction is to jump from the current page number of the code data to another page number of the code data, then the other page number of the code data is used as the target page number; If the instruction is to return from the current page number of the code data to another page number of the code data, then the other page number of the code data is used as the target page number; If the instruction is to store the constant data corresponding to the target address in the target address, and the application cache space does not store the constant data corresponding to the target address, then the cache page number corresponding to the target address is used as the target page number.
6. The method according to claim 5, characterized in that: The application space also includes: The first global variable space is used to store the corresponding page number in a preset page index queue when cross-page calls occur in the application. The value of the other page number of the code data is obtained in the following way: Based on the content of the instruction and the current page number, determine the value of the other page number from the page index queue.
7. The method according to claim 5, characterized in that: The application space also includes: The second global variable space is used to record the correspondence between the application's address and the cache address; The cache page number corresponding to the target address is obtained in the following ways: Based on the correspondence between the addresses of applications and cache addresses stored in the system space, obtain the target cache address corresponding to the target address; Obtain the constant data corresponding to the target page number from the target cache address.
8. The method according to claim 1, characterized in that, The step of setting a new target address for the current instruction based on the type of the instruction includes: If the instruction is an execution instruction for code data, and the application has completed the execution of the code data stored in the application runtime space, then the new target address is the starting address of the application runtime space; If the instruction is to jump from the current page number to another page number, then the new target address is the offset address of the destination address in the application runtime space, wherein the destination address is the address of the target address corresponding to the other page number; If the instruction is to return from the current page number to another page number, then the new target address is the offset address of the return address in the application runtime space, wherein the return address is the address of the target address corresponding to the other page number.
9. A management device for an application program in a chip, characterized in that, include: Memory, which stores computer programs; A processor configured to run the computer program to perform the method as described in any one of claims 1 to 8.