A non-aligned data error handling method, control component and storage device

Abstract

The application discloses a non-aligned data error processing method, a control component and a storage device. The method comprises the following steps: in response to a non-aligned write storage command, obtaining to-be-written data based on the non-aligned write storage command; reading out to-be-merged data from a NAND and verifying whether the to-be-merged data is correct; if the to-be-merged data is correct, processing the merged data of the to-be-merged data and the to-be-written data by using a first scrambling mode; if there is an error, processing the merged data of the to-be-merged data and the to-be-written data by using a second scrambling mode different from the first scrambling mode, and marking a sector of the read-out error data. By using the technical scheme, the discovered non-aligned data error of an address not read by a host is hidden, and even if a read-out data error occurs when a non-aligned write command is processed, the processing of the non-aligned write command can be normally completed, and the reliability of the storage device is relatively improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a method for handling unaligned data errors, a control component, and a storage device. Background Technology

[0002] In storage devices, the FTL (Flash Translation Layer) is used to maintain mapping information from logical addresses to physical addresses. The FTL is implemented by, for example, software, firmware running in the CPU of the control unit, and / or hardware as part of an ASIC.

[0003] Figure 1 This is a schematic diagram of FTL (Framework Layer Transport), where the storage device provides a logical address space to the host. The host uses logical addresses to access the storage device. FTL maps the logical addresses provided by the host to physical addresses. Logical addresses constitute the storage space of the solid-state storage device as perceived by upper-layer software such as the operating system. The smallest unit addressable by a logical address is called, for example, a logical block or sector (for simplicity, unless otherwise specified, the terms logical block and sector are used interchangeably below), and the logical address that addresses a logical block is also called the Logical Block Address (LBA). Logical blocks have a specified size, such as 512 bytes, 2KB, 4KB, or 16KB. A physical address is the address of a physical storage unit (e.g., a physical page) used to access the storage device's NVM. In related technologies, address mapping can also be implemented using intermediate address formats. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address.

[0004] The table structure that stores mapping information from logical addresses to physical addresses is called the FTL table. The FTL table is important metadata in storage devices. Typically, FTL table entries record address mappings in units of logical blocks within the storage device. Optionally, each entry in the FTL table represents one or more logical blocks, balancing the size of the FTL table with the granularity of storage space management; for example, eight logically contiguous blocks. An FTL table includes, for example, multiple FTL entries, each corresponding to one or more contiguous logical blocks. The value of each FTL entry records the address of the storage space provided for that one or more contiguous logical blocks (for clarity, this storage space is referred to as an NVM data frame, and the address of this storage space is referred to as the NVM data frame address). The NVM data frame address has, for example, a size of 4KB, or can hold 4KB of user data.

[0005] The FTL table is stored in, for example, DRAM or SRAM. Based on the accessed logical address, the index of the corresponding FTL entry is obtained, and the NVM data frame providing storage space for the logical block is retrieved from the FTL entry. The NVM data frame address is, for example, the physical address of accessing a physical page of the NVM chip, the physical address of accessing multiple combined physical pages of the NVM chip (combined physical pages are, for example, physical pages located on multiple planes of the same or different logical units (LUNs), or the physical address of a portion of the data units within a physical page of the NVM chip. For some storage devices, the FTL is provided by the host coupled to the storage device; the host's memory stores the FTL table, and the host's CPU executes the software to provide the FTL. Other times, a storage management device positioned between the host and the storage device provides the FTL.

[0006] In SSD systems, 4KB data mapping (NVM dataframe size is 4KB, and each entry in the FTL table maps to one NVM dataframe) is the most common practice. However, to support 512B sector sizes, non-4KB aligned commands must always be handled. When the sector size described in the host-provided storage command is 512B, the logical addresses of some accessed sectors are not aligned to 4KB; such storage commands are called non-4KB aligned storage commands or unaligned storage commands.

[0007] The current procedure for handling non-4KB aligned memory commands (taking write commands as an example) is as follows: Figure 2 As shown, it specifically includes:

[0008] a. For the sector to be accessed, obtain its 4KB-aligned logical address La;

[0009] b. Query the FTL table based on the logical address La to obtain the NVM data frame address, and read 4KB of data (also known as pre-read data) from the corresponding NVM data frame;

[0010] c. Merge the sectors to be written into the 4KB of data read;

[0011] d. Allocate an NVM data frame and write the merged 4KB data into the allocated NVM data frame.

[0012] A technical problem in the existing technology is that when processing unaligned storage commands, the data read from the NVM data frame may contain errors. These errors are identified through errors in error correction codes (ECC) or other fault-tolerance mechanisms. However, the user is currently providing, for example, a write command, so errors in the read data should not be reported to the user, nor is it necessary to report them; the erroneous data may also be invalid data, and there is no need to report the error to the user; the user may rewrite the erroneous data in the future, and the error will then be eliminated. After merging the pre-read data read from the NVM data frame with the data to be written by the user's unaligned storage command, the data written to the new NVM data frame is re-encoded, thereby eliminating errors that can be identified by error correction codes or other fault-tolerance mechanisms (i.e., the data formally conforms to, for example, the requirements of error correction codes, but its content is different from correct data). This results in some sectors of the new data frame having correct content, while some sectors have erroneous content (and this erroneous data cannot be identified by error correction codes).

[0013] Figure 3 An example illustrating the aforementioned technical problem is provided. An NVM data frame comprises, for example, 8 sectors (each sector being 512 bytes). An unaligned store command (with its 4KB aligned logical address La) writes data to sector 1, while sectors 0 and 2-7 originate from the old NVM data frame corresponding to logical address La. During the reading process from the old NVM data frame, data in sector 2 is found to contain errors. The data to be written by the unaligned store command is merged with the data read from the old NVM data frame and then written to the newly allocated NVM data frame. Figure 3 (The NVM data frame). For sector 2 with an error, some data is used to fill it in. The fill data is, for example, a random number, specified data, or data output by the error correction unit. In any case, the fill data can no longer represent the data that the user expected stored in the old NVM data frame.

[0014] However, when writing data to a newly allocated NVM data frame (sectors 0 to 7), the data is re-encoded (e.g., error-corrected encoding). This results in the data being read from sector 2 passing through the error-corrected decoding process without being identified as erroneous. In this situation, if a user happens to need to read data located in sector 2, the storage device will provide the user with incorrect data because it cannot recognize the error in sector 2. This is unacceptable for the storage device. Summary of the Invention

[0015] This invention provides a method for handling unaligned data errors during the data writing phase, comprising:

[0016] In response to an unaligned write storage command, the data to be written is obtained based on the unaligned write storage command;

[0017] Read the data to be merged from the NAND flash memory and verify that the data to be merged is correct;

[0018] If the data to be merged read from NAND is correct, then the first scrambling method is used to process the merged data of the data to be merged and the data to be written.

[0019] If there is an error in the data to be merged read from NAND, a second scrambling method, different from the first scrambling method, is used to process the merged data of the data to be merged and the data to be written, and the sector where the erroneous data was read is marked.

[0020] In the unaligned data error handling method described above, the sector marked for reading erroneous data includes:

[0021] Record a bitmap indicating the faulty sector where the data to be merged is located in the metadata associated with that data;

[0022] After processing the merged data (data to be merged and data to be written) using a second scrambling method different from the first scrambling method, and marking the sectors where erroneous data was read, the process further includes:

[0023] Error correction encoding is performed on the data to be merged and the metadata to generate verification data. The data to be merged, the metadata, and the verification data are then written into the NAND flash memory.

[0024] In the above-described method for handling unaligned data errors, if an unaligned write storage command indicates that data to be written is to be written to the first sector of the NAND, then the data to be merged is read from all sectors of the NAND.

[0025] Identify the second sector containing the error from the data to be merged;

[0026] The data to be merged read from the NAND flash memory is merged with the data to be written by the non-aligned write storage command, and the second sector where the error occurred is filled with random numbers or a specified data pattern.

[0027] In the above-described method for handling unaligned data errors, the first scrambling method and the second scrambling method are two different functions, or different random number seeds used for the scrambling operation, or different random number seed calculation methods.

[0028] In the above-described method for handling unaligned data errors, the physical address P of the NVM data frame is used as the randomization seed for the first scrambling method, and the physical address P+1 of the NVM data frame is used as the randomization seed for the second scrambling method.

[0029] This invention also provides a method for handling unaligned data errors during the data reading stage, comprising:

[0030] In response to a data read command or garbage collection operation, read the NVM data frame from the NAND and perform LDPC decoding on the NVM data frame;

[0031] The correct decoded data obtained by descrambling LDPC decoding using the first scrambling method;

[0032] If descrambling is successful, the descrambling data obtained is correct.

[0033] If descrambling fails, the correct decoded data obtained by LDPC decoding is descrambled using the second scrambling method.

[0034] If descrambling is successful, the bitmap containing erroneous sectors is obtained from the descrambling data, and the corresponding erroneous sectors are identified.

[0035] In the unaligned data error handling method described above, in response to a host's data read command, an NVM data frame is read from the NVM. Error checking and decoding are performed on the NVM data frame to obtain a scrambled data frame and a random number seed. Descrambling is performed using a first descrambling method. If descrambling is successful, the data is sent to the user or garbage collection continues. If descrambling fails, a second descrambling method is used. If descrambling is successful, erroneous sectors are identified using a bitmap marking which sectors have errors. If the data to be read comes from an erroneous sector, the error is reported to the user or another fault-tolerant mechanism is used to attempt data recovery. If the data to be read by the user comes from a correct sector, the data to be read is provided to the user without reporting an error.

[0036] In the above-described method for handling unaligned data errors, when performing garbage collection, if a data frame is found to contain erroneous sectors, and the valid data of the data frame is rewritten to the NVM, the data frame containing erroneous sectors is scrambled using a second scrambling method, while the data frame not containing erroneous sectors is scrambled using a first scrambling method.

[0037] The present invention also provides a control component for executing an unaligned data error handling method as described in any of the preceding claims during data writing.

[0038] The present invention also provides a storage device, including the above-described control component and a storage chip; when an unaligned data error occurs on the storage chip, the control component performs an unaligned data error processing method on the unaligned data error on the storage chip.

[0039] The beneficial effects achieved by this invention are as follows:

[0040] (1) For addresses not read by the host, the discovered unaligned data errors are hidden, and the processing of unaligned write commands can be completed normally even if a read data error occurs, which relatively improves the reliability of the storage device.

[0041] (2) The discovered data errors are marked with a second scrambling code, which does not affect the read command processing flow. Reading normal data from other addresses in the presence of erroneous data does not increase processing overhead.

[0042] (3) Data marked with the second scrambling code can be detected by the descrambling hardware in the normal read command process, but no firmware intervention is required in the error identification stage. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0044] Figure 1 A schematic diagram of FTL provided for the background art;

[0045] Figure 2 A flowchart of a method for processing non-4KB aligned memory commands, provided for the background technology.

[0046] Figure 3 A schematic diagram illustrating the structure of an NVM data frame for processing non-4KB aligned memory commands, provided for background technology.

[0047] Figure 4 This is a schematic diagram illustrating the changes in data during the data writing or reading process provided in an embodiment of this application.

[0048] Figure 5 A flowchart of a method for handling unaligned data errors provided in this application embodiment;

[0049] Figure 6 This is a schematic diagram illustrating the handling method for errors caused by unaligned data.

[0050] Figure 7This is a flowchart illustrating the LDPC decoding process for the read NVM data frames.

[0051] Figure 8 A flowchart illustrating the process of handling errors in unaligned data.

[0052] Figure 9 This is a schematic diagram of the data writing and reading process according to another embodiment of this application;

[0053] Figure 10 This is a schematic diagram of the data writing and reading process according to another embodiment of this application;

[0054] Figure 11 This is a schematic diagram of the data writing and reading process according to yet another embodiment of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] Figure 4 This is a diagram illustrating how data changes during the writing or reading process.

[0057] When writing data to a storage device, the data is first scrambled by the controller, or the storage device itself can be used to scramble the data. When reading data from the storage device, the scrambled data is descrambled using a randomization algorithm that performs the opposite operation, yielding the data before randomization.

[0058] Optionally, during randomization scrambling, a specified random number seed is used, such as a user-provided custom seed format and generation method, or a randomization seed related to the logical or physical address. The scrambled data is then encoded using ECC (Error Correcting Code), such as LDPC (Low Density Parity Check Code), to obtain check data. Finally, the scrambled data and check data are written together into NAND (computer flash memory device).

[0059] In addition, when reading data from NAND, LDPC decoding is performed first, and then the seed used when writing data is used for descrambling (that is, random descrambling) to obtain the original data.

[0060] Example 1

[0061] Figure 5 This is a flowchart of a non-aligned data error handling method provided in Embodiment 1 of this application, used for handling non-aligned data errors during the data writing stage, specifically including:

[0062] Step 510: In response to the unaligned write storage command, obtain the data to be written in the command and read the data to be merged from the NAND.

[0063] Step 520: Determine whether the data to be merged read from NAND is correct. If it is correct, proceed to step 530; if it is incorrect, proceed to step 540.

[0064] Step 530: If the data to be merged read from NAND is correct, then use the first scrambling method to process the merged data of the data to be merged and the data to be written.

[0065] Step 540: If there is an error in the data to be merged read from NAND, the merged data of the data to be merged and the data to be written is processed using the second scrambling method, and the sector where the erroneous data was read is marked.

[0066] Figure 6 This is a schematic diagram illustrating the processing of non-aligned data errors provided in an embodiment of this application.

[0067] When processing unaligned write storage commands, if there are errors in the data to be merged read from NAND, a randomization scrambling method is used to process the merging of the data to be merged and the data written in the write storage command. Errors in the read data are marked without affecting the normal data reading process.

[0068] Specifically, this embodiment processes the merged data by setting multiple randomization scrambling methods, including:

[0069] If the data to be merged read from NAND is erroneous when processing non-alignment commands, a different scrambling format than the default scrambling format is used to process the merged data. Then, a bitmap indicating the erroneous sector of the data to be merged is recorded in the metadata associated with the data to be merged. The data to be merged and the metadata are then error-corrected and encoded to generate check data. Finally, the data to be merged, the metadata, and the check data are written into NAND.

[0070] For example, Figure 6The default scrambling format is set to scrambling format 1, denoted as f1(x), where x is, for example, 4KB of data to be merged. When processing non-aligned commands, if errors exist in the data to be merged read from the NAND, the merged data is processed using scrambling format 2 (denoted as f2(x)), which is different from the default scrambling format (scrambling format 1). A sector bitmap indicating which sector in the 4KB of data to be merged contains the error is recorded in the metadata associated with the data to be merged. The data to be merged and the metadata are then subjected to error correction encoding (e.g., LDPC) to generate check data. The data to be merged, the metadata, and the check data are then written to the NAND. Thus, the data written to the NAND includes both the correct data processed using the default scrambling format 1 and the non-aligned error data processed using scrambling format 2. Since the correct and error data are processed using different scrambling formats, the storage device can easily identify the error data during subsequent data reads using the descrambling methods corresponding to different scrambling formats, thereby relatively improving the reliability of the storage device.

[0071] Here, scrambling format 1 and scrambling format 2 can be considered as two different functions, different randomization seeds used for the scrambling operation, or different methods of calculating the randomization seed. For example, in one instance, the physical address P of the NVM data frame is used as the randomization seed for scrambling format 1, while P+1 is used as the randomization seed for scrambling format 2. By setting different scrambling formats, an NVM data frame scrambled with one format can only be correctly descrambled using the same scrambling code; if a different scrambling code is used for descrambling, an error will be detected.

[0072] This invention utilizes two scrambling formats to process misaligned erroneous data, rewrites it into NAND, and marks each sector. This approach does not affect normal data decoding and can accurately locate specific sectors when errors are detected in the misaligned data. Two different data scrambling methods are used to scramble normal data and the identified erroneous data respectively. A second scrambling method, different from the default first scrambling method, is used to mark erroneous data. Therefore, even if the storage device can perform error correction decoding during data reading, it can still identify data errors without reporting them, improving user experience and performance.

[0073] Example 2

[0074] Figure 7 Through Example 1 Figure 6 The method shown is for handling unaligned data errors. After processing the NAND, the read NVM data frame is then decoded by LDPC.

[0075] Specifically, when reading out the NVM data frame, the NVM is first LDPC decoded and then descrambled using scrambling code format 1, which includes the following steps:

[0076] Step 710: Perform LDPC decoding on the NVM data frame. If the decoding is successful, proceed to step 720; otherwise, proceed to step 760.

[0077] Step 720: Descramble the data obtained by LDPC decoding using scrambling format 1. If descrambling is successful, proceed to step 730; if descrambling fails, proceed to step 740.

[0078] Step 730: The descrambling data is correct; return the correct data.

[0079] Step 740: Further descramble the data obtained by LDPC decoding using scrambling format 2. If descrambling is successful, proceed to step 750; if descrambling fails, proceed to step 760.

[0080] Step 750: Obtain the bitmap containing erroneous sectors from the descrambled data and identify the corresponding erroneous sectors;

[0081] Step 760: Return to error status;

[0082] If LDPC decoding is correct in step 710, and an error occurs in descrambling with scrambling format 1 in step 720, it represents two possible reasons: (1) there is an undetectable LDPC error in the NVM data frame; (2) the NVM data frame is not scrambled with scrambling format 1. According to an embodiment of this application, in this case, step 740 further descrambles the LDPC-decoded data frame again with scrambling format 2. If descrambling is successful, it indicates that the reason for the error in descrambling with scrambling format 1 is the second reason; if descrambling fails, it indicates that the reason for the error in descrambling with scrambling format 1 is the first reason. For the first reason, other fault-tolerant mechanisms such as RAID reconstruction are needed to recover the erroneous data. For the second reason, it indicates that there is an erroneous sector in the data frame that was previously identified when processing the non-aligned write command. The erroneous sector is then identified, for example, by a bitmap indicating which sector in the 4KB data frame has an error.

[0083] If LDPC decoding fails in step 710 or descrambling using scrambling format 2 fails in step 740, it indicates that there is an undetectable LDPC error in the NVM data frame, or an error caused by other reasons. In this case, further processing should be performed using other error handling mechanisms, and an error status should be returned. Additionally, if data marked with errors is subsequently updated with correct data, its scrambling method should be changed back to the default scrambling format.

[0084] The core of this embodiment lies in the process of handling errors in non-aligned data. Upon encountering a scrambling error, it switches to scrambling format 2 for rereading. Adding another format is crucial. The bitmap containing the erroneous sector is written into the metadata to verify the data status. If the data status is correct and the required sector data is also normal, the correct data is returned. Otherwise, an error status is returned.

[0085] Specifically, Figure 8 This is a flowchart illustrating the process of handling errors in non-aligned data. After reading the MVM data frame, it is first descrambled using scrambling format 1. The system then checks if the descrambled data is correct. If correct, it returns the correct data. If incorrect, it checks if the scrambling code is faulty. If the scrambling code is correct, it indicates another error and returns an error status. If the scrambling code is faulty, it obtains the scrambling seed and compares it with scrambling format 2. The system checks if the seed matches scrambling format 2. If it doesn't match, it returns an error status. If the seed matches scrambling format 2, it checks if the required sector data is also correct. If correct, it returns the correct data; otherwise, it returns an error status.

[0086] This invention requires a descrambling method corresponding to the scrambling method to successfully descramble data after it has been scrambled using two different scrambling methods. By determining whether a descrambling method can successfully descramble the data, it can identify which method was used to scramble the data and thus identify whether there are data errors. This invention is particularly suitable for processing non-aligned write storage commands.

[0087] Example 3

[0088] Figure 9 This is a schematic diagram of the data writing and reading process according to another embodiment of this application. Figure 9 The left side shows the data writing process, and the right side shows the data reading process.

[0089] (i) The data writing process can occur in response to an unaligned write command issued by the host. Upon receiving an unaligned write command, such as writing new data to sector 1, data (including, for example, 8 sectors, sectors 0-7) is read from the corresponding NVM data frame. If there are no errors in the combined data of the read data and the data to be written, the combined data is scrambled using a first descrambling method (i.e., scrambling format 1). If errors exist in the combined data, it is scrambled using a second descrambling method (i.e., scrambling format 2). For example, the first and second scrambling methods use different methods for generating random number seeds. Error check encoding (e.g., BCH or LDPC) is performed on the scrambled data frame along with the random number seed to generate check data. The scrambled data frame and check data are then written to the NVM. The data written to the NVM here is called an NVM data frame.

[0090] Specifically, if error correction decoding succeeds but descrambling using scrambling format 1 fails, an error is identified in sector 2. The data read from the NVM data frame is merged with the new data to be written by the non-aligned write command. Sector 2, containing the merged data, also contains data; however, due to the error, its content is no longer relevant and can be filled with random numbers or a specified data pattern. In response to the presence of an error in sector 2 (and the new data to be written is located in sector 1 and will not overwrite sector 2), a bitmap is used to mark the error in sector 2. The bitmap is, for example, 8 bits, where each bit represents whether an error exists in the corresponding sector of the NVM data frame.

[0091] One approach is to set a seed for each sector, which allows for the identification of different sectors during data reading, or to set a single seed for each sector of the entire NVM data frame, thereby reducing storage space and facilitating seed maintenance.

[0092] (ii) The data reading process can occur in response to a read command from the host or in response to an internal operation of the storage device, such as garbage collection.

[0093] In response to the host's read command, the previously written NVM data frame is read from the NVM, and error checking and decoding are performed on the NVM data frame. The decoding result is a scrambled data frame and a random number seed. Since it's unknown whether the scrambled data frame contains faulty sectors, a unified process is used: first, descrambling is performed using the first descrambling method (the reverse of the first scrambling method). If descrambling is successful, the obtained data frame is correct and can be sent to the user or continue garbage collection. If descrambling fails, the obtained data frame may contain faulty sectors or other errors (e.g., LDPC undetectable errors). In this case, a second descrambling method is used (the reverse of the second scrambling method). If the second descrambling method is successful, it indicates that the data frame contains faulty sectors, and the second scrambling method was intentionally used during the previous write. In this case, faulty sectors are identified using a bitmap marking which sectors contain errors. If the data the user wants to read comes from faulty sectors, the error is reported to the user or another fault-tolerant mechanism is used to attempt data recovery. If the data the user wants to read comes from the correct sector, the user is provided with the data to read without reporting an error. In the case of operations such as garbage collection, if a data frame is found to contain an erroneous sector, when rewriting the valid data of the data frame to the NVM, data frames containing erroneous sectors are still scrambled using the second scrambling method, while data frames not containing erroneous sectors are scrambled using the first scrambling method.

[0094] Example 4

[0095] Figure 10This is a schematic diagram of the data writing and reading process according to another embodiment of this application.

[0096] exist Figure 10 In the example, the NVM data frame includes four sectors (denoted as sector 0, sector 1, sector 2, and sector 3), each sector being, for example, 1KB in size. During data scrambling, each sector is scrambled separately. The seeds used for sectors 0-3 during scrambling are denoted as seed 0, seed 1, seed 2, and seed 3, respectively. Seeds 0-3 can be the same or different. Optionally, each seed 0-3 is a function of the physical address of its corresponding sector. By providing a corresponding seed for each sector, faulty sectors in the NVM data frame can be identified solely by the seed used for each sector, without using a bitmap.

[0097] See Figure 10 In response to receiving an unaligned write command, new data needs to be written to sector 1. In response, data is read from the corresponding NVM data frame. Through error correction decoding, based on the failure of the first descrambling method and the success of the second descrambling method, an error is identified in the data of sector 2. Sectors 0-3 read from the NVM frame, along with the new data to be written by the unaligned write command, are merged with data also recorded in sector 2. Since this data contains errors, its content is no longer relevant; sector 2 can be filled with random numbers or a specified data pattern.

[0098] For each sector of the merged data, a scrambling method is selected based on whether an error exists. In response to an error in sector 2 (and the new data to be written is located in sector 1 and will not overwrite sector 2), sector 2 is scrambled using seed 2' (instead of seed 2) corresponding to the second scrambling method. For sectors 0, 1, and 3, seeds 0, 1, and 3 corresponding to the first scrambling method are used. Random number seeds 0, 1, and 3 can be the same or different, but random number seeds 2 and seed 2' must be different.

[0099] As an example, the first scrambling method and the second scrambling method use different methods to generate random number seeds. Again, as an example, in the first scrambling method, one bit sequence is used to calculate the data in the sector, while in the second scrambling method, a different bit sequence is used. Therefore, the data scrambled by the two methods can be distinguished during descrambling. The first descrambling method can only successfully descramble data obtained using the first scrambling method, and the second descrambling method can only successfully descramble data obtained using the second scrambling method; they cannot be interchanged.

[0100] Error check data is generated by encoding the scrambled data frame together with the random number seed used (e.g., BCH or LDPC). The scrambled data frame and the check data are then written into the NVM.

[0101] In response to reading the previously written NVM data frame from the NVM, error checking decoding is performed on the NVM data frame. The decoding result is the scrambled sectors and their corresponding random number seeds. For each sector, it is first descrambled using the first descrambling method (corresponding to the first scrambling method, which is the reverse process of the first scrambling method). If descrambling is successful, it indicates that the obtained sector is correct. If descrambling fails, it indicates that the obtained sector is incorrect, or other errors may have occurred (e.g., the presence of an undetectable LDPC error). In this case, the second descrambling method is used (corresponding to the second scrambling method, which is the reverse process of the second scrambling method). If the second descrambling method is successful, it indicates that the sector contained an error, and the second scrambling method was intentionally used during the previous writing to identify the erroneous sector.

[0102] Return to view Figure 10 In the data writing process, optionally, if a non-aligned write command needs to update sector 1, and sector 1 in the NVM data frame read for merging contains an error (e.g., sector 1 was successfully descrambled using the second descrambling method), while other sectors are error-free. In this case, since the sector 1 updated by the non-aligned write command overwrites the erroneous sector 1, the updated sector 1 is error-free. Therefore, when scrambling each sector, the first scrambling method is used to scramble each sector including sector 1.

[0103] Example 5

[0104] Figure 11 This is a schematic diagram of the data writing and reading process according to yet another embodiment of this application.

[0105] exist Figure 11 In this example, the NVM data frame includes four sectors (denoted as sector 0, sector 1, sector 2, and sector 3). During the data writing process, error checking encoding is performed on the data, but scrambling is optional, or in other words, whether or not scrambling is performed is not limited in this embodiment.

[0106] In error checking coding, it is performed on a whole data frame or on a sector-by-sector basis. For normal data, the first method is used for error checking coding; for data with errors, the second method is used. For example, when using BCH encoding, the generator matrices used in the two methods are different. During decoding, when the number of error bits is within the error correction capability of the error checking coding, data encoded using the first method can only be decoded using the decoding method corresponding to the first method, and data encoded using the second method can only be decoded using the decoding method corresponding to the second method. When the number of error bits exceeds the error correction capability of the error checking coding, decoding will fail regardless of the method used. When the number of error bits in an NVM data frame increases due to factors such as NVM storage medium degradation, exceeding the error correction capability of the error checking coding, it is unlikely that one method will decode successfully while the other fails. Based on this analysis, according to... Figure 10 In one embodiment, error correction decoding is performed using a second method to identify data errors in one or more sectors.

[0107] See Figure 11 In response to receiving an unaligned write command, new data is to be written to sector 1. In response, data is read from the corresponding NVM data frame. Error correction decoding (failure with first-mode error correction decoding, success with second-mode error correction decoding) identifies an error in the data of sector 2. The data read from the NVM data frame is then merged with the new data to be written by the unaligned write command.

[0108] In response to an error in sector 2 (and the new data to be written is in sector 1 and will not overwrite sector 2), the error in sector 2 is also marked by a bitmap or other marker method.

[0109] If no errors are found in the merged data, error correction encoding is performed using the first method. If errors are found in the merged data, error correction encoding is performed using the second method, and the merged data is written to the NVM. The data written to the NVM here is called an NVM data frame.

[0110] In response to reading a previously written NVM data frame from the NVM, error-checking decoding is performed on the NVM data frame. Since the presence of errors in the scrambled data frame is unknown at this stage, a unified process is used: first, error correction decoding (corresponding to first-mode error correction encoding) is applied. If decoding succeeds, the obtained data frame is correct. If decoding fails, the obtained data frame may contain errors, or other errors may have occurred (e.g., too many error bits exceeding the error correction decoding's correction capability). In this case, second-mode error correction decoding (corresponding to second-mode error correction encoding) is applied. If second-mode error correction decoding succeeds, it indicates that the data frame contains errors, and second-mode error correction encoding was intentionally used during the previous writing. In this case, error sectors are identified using a bitmap marking which sectors have errors. If second-mode error correction decoding still fails, it indicates that the number of error bits in the read NVM data frame exceeds the error correction decoding's correction capability. Accordingly, an error is reported as a response to the read command.

[0111] In summary, the method for handling unaligned data errors provided by this invention uses two different scrambling methods to scramble normal data and the identified erroneous data respectively. This allows the storage device to identify data errors even if it can perform error correction decoding during data reading, thus hiding the discovered unaligned data errors. Furthermore, it ensures that even if a read data error occurs when processing an unaligned write command, the processing of the unaligned write command can still be completed normally, thereby relatively improving the reliability of the storage device.

[0112] Example 6

[0113] Embodiment 6 of the present invention provides a control component, which is used to execute an unaligned data error handling method described in Embodiments 1 to 5 when data is written.

[0114] Example 7

[0115] Embodiment 7 of the present invention also provides a storage device, the storage device including the control unit and a storage chip, wherein an unaligned data error occurs on the storage chip, and the control unit performs the unaligned data error handling method described in Embodiments 1 to 5 on the unaligned data error on the storage chip.

[0116] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for handling unaligned data errors, used in the data writing phase to handle unaligned data errors, characterized in that, include: In response to an unaligned write storage command, the data to be written is obtained based on the unaligned write storage command; Read the data to be merged from the NAND flash memory and verify that the data to be merged is correct; The data to be merged read from the NAND flash memory is merged with the data to be written by the non-aligned write storage command; If the data to be merged read from NAND is correct, the first scrambling method is used to process the merged data of the data to be merged and the merged data of the non-aligned write storage command. If there is an error in the data to be merged read from NAND, a second scrambling method, different from the first scrambling method, is used to process the merged data of the data to be merged and the data to be written by the non-aligned write storage command, and the sector where the erroneous data was read is marked.

2. The method for handling unaligned data errors as described in claim 1, characterized in that, The sector marked with read error data includes: Record a bitmap indicating the faulty sector where the data to be merged is located in the metadata associated with that data; After processing the merged data (data to be merged and data to be written) using a second scrambling method different from the first scrambling method, and marking the sectors where erroneous data was read, the process further includes: Error correction encoding is performed on the data to be merged and the metadata to generate verification data. The data to be merged, the metadata, and the verification data are then written into the NAND flash memory.

3. The method for handling unaligned data errors as described in claim 1, characterized in that, If a non-aligned write storage command instructs that data to be written be written to the first sector of the NAND, then the data to be merged is read from all sectors of the NAND. Identify the second sector containing the error from the data to be merged; The data to be merged read from the NAND flash memory is merged with the data to be written by the non-aligned write storage command, and the second sector where the error occurred is filled with random numbers or a specified data pattern.

4. The method for handling unaligned data errors as described in claim 1, characterized in that, The first scrambling method and the second scrambling method are two different functions, or different random number seeds used for scrambling operations, or different methods of calculating random number seeds.

5. The method for handling unaligned data errors as described in claim 4, characterized in that, The physical address P of the NVM data frame is used as the randomization seed for the first scrambling method, and the physical address P+1 of the NVM data frame is used as the randomization seed for the second scrambling method.

6. A method for handling unaligned data errors, used in the data reading stage to handle unaligned data errors, characterized in that, include: In response to a data read command or garbage collection operation, read the NVM data frame from the NAND and perform LDPC decoding on the NVM data frame; The NVM data frame is the data written to the NVM according to any one of claims 1 to 5; The correct decoded data obtained by descrambling LDPC decoding using the first scrambling method; If descrambling is successful, the descrambling data obtained is correct. If descrambling fails, the correct decoded data obtained by LDPC decoding is descrambled using the second scrambling method. If descrambling is successful, the bitmap containing erroneous sectors is obtained from the descrambling data, and the corresponding erroneous sectors are identified.

7. The method for handling unaligned data errors as described in claim 6, characterized in that, In response to the host's data read command, the system reads the NVM data frame from the NVM, performs error checking and decoding on the NVM data frame to obtain the scrambled data frame and random number seed, and uses the first descrambling method to descramble it. If descrambling is successful, the data is sent to the user or garbage collection continues. If descrambling fails, the second descrambling method is used. If descrambling is successful, the system identifies the erroneous sector by marking which sectors have errors. If the data to be read comes from the erroneous sector, the system reports the error to the user or attempts to recover the data using other fault-tolerant mechanisms. If the data to be read by the user comes from the correct sector, the system provides the data to be read to the user without reporting an error.

8. The method for handling unaligned data errors as described in claim 6, characterized in that, When performing garbage collection, if a data frame is found to contain erroneous sectors, the valid data of the data frame is rewritten to the NVM. For data frames containing erroneous sectors, the second scrambling method is used for scrambling, and for data frames not containing erroneous sectors, the first scrambling method is used for scrambling.

9. A control component, characterized in that, The control unit is configured to execute a non-aligned data error handling method as described in any one of claims 1-5 when writing data; the control unit is further configured to execute a non-aligned data error handling method as described in any one of claims 6-8 when reading data.

10. A storage device, characterized in that, include: The control component as described in claim 9, and the memory chip; When an unaligned data error occurs on the memory chip, the control unit performs an unaligned data error handling method on the memory chip.

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