A method and apparatus for handling an interrupt request

Abstract

This invention discloses a method and apparatus for processing interrupt requests. The method is applied to a bridge chip and includes: receiving a first interrupt request from a PCIe endpoint through a second port of the bridge chip, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint; searching in a mapping table for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier; generating a second interrupt request based on the first interrupt vector identifier and the first interrupt request; and sending the second interrupt request to the CPU through a first port of the bridge chip. This method establishes a one-to-one mapping between the interrupt vector identifier, the device identifier, and the interrupt request type through the uplink port and at least one downlink port of the bridge chip, transforming the original interrupt request into a new interrupt request with a unique interrupt vector identifier through the mapping relationship. This avoids the need to search for and confirm the interrupt source after reporting to the CPU, thus avoiding additional overhead.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and in particular to a method and apparatus for processing interruption requests. Background Technology

[0002] Network devices are widely used across various industries to achieve interconnection and interoperability within and between various backbone networks. The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI-Express), or "PCIe" for short, differs from previous input / output (I / O) buses. It uses a serial, point-to-point interconnection method to achieve communication between devices, providing a high-speed, high-performance, full-duplex communication method for network device interconnection. The main characteristics of the PCIe bus, such as its application model, storage structure, and software interface, remain consistent with the traditional PCI / PCI-X bus, while fully utilizing advanced point-to-point interconnection and switching and packet-based protocols to achieve new bus performance and features.

[0003] Because the PCIe bus is a point-to-point switching bus architecture, each device in the system has its own bus, allowing point-to-point communication to be established by directly connecting to a bridge (switch) device. PCIe maintains the same memory, I / O, and configuration address space model as traditional PCI, so existing operating systems and driver software can run on PCIe systems without any modification or with minimal adaptation.

[0004] Interrupts play a crucial role in the computing unit of a PCIe network device, used to notify the computing unit to receive and process network data, protocol, and control messages. Traditional PCI devices generate interrupt requests via the INTx sideband signal. INTx can be any of four interrupt types: INTA, INTB, INTC, or INTD. When there are many PCIe endpoint devices, interrupt sharing is required to submit the same type of interrupt. After passing through the interrupt controller, it is converted into an INTR signal and then sent to the CPU. Using interrupt sharing, if the message is large, the CPU needs to use software to locate and confirm the PCIe endpoint device submitting the interrupt request, thus impacting message service efficiency and incurring additional overhead. Summary of the Invention

[0005] Based on the above background, this invention mainly addresses the technical problem that in a PCIe network device PCIe system, when PCIe endpoint devices (EPs) interconnected by the downlink ports of a bridge chip submit interrupt requests, the uplink ports of the bridge chip need to submit interrupt requests from each PCIe endpoint in a shared manner, leading to additional overhead for the CPU to locate and confirm the interrupt source. To solve this technical problem, the embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, embodiments of the present invention provide a method for processing interruption requests. This method is applied to a network bridge chip, the bridge chip including a first port and at least one second port, the first port being an uplink port and the second port being a downlink port. The method includes:

[0007] The system receives a first interrupt request from a PCIe endpoint via the second port. The first interrupt request includes a first interrupt request type and a first device identifier of the PCIe endpoint. Based on the first interrupt request type and the first device identifier, the system searches a mapping table for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier. The mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier. Based on the first interrupt vector identifier and the first interrupt request, the system generates a second interrupt request. The system then sends the second interrupt request to the CPU via the first port.

[0008] The first interrupt request is an INTx interrupt request.

[0009] In conjunction with the first aspect, in one possible implementation of the first aspect, before searching the mapping table for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier, the method further includes:

[0010] Receive the mapping table sent from the CPU; or generate the mapping table based on the type of at least one interrupt request, the device identifier of each PCIe endpoint, and at least one interrupt vector identifier.

[0011] In conjunction with the first aspect, in another possible implementation of the first aspect, the interrupt vector identifier includes message signal interrupt MSI capability set message data and an interrupt vector number; wherein, the MSI capability set message data is used to indicate a message address and data that have a unique mapping relationship with a device identifier and interrupt request type of a PCIe endpoint; the interrupt vector number and the MSI capability set message data are used to jointly indicate the interrupt request of the PCIe endpoint.

[0012] Optionally, the device identifier includes: the bus number, device number, and function number of the INTx message.

[0013] In conjunction with the first aspect, in another possible implementation of the first aspect, the method further includes: if the first interrupt request is an MSI interrupt request, then sending the first interrupt request to the CPU through the first port.

[0014] Secondly, embodiments of the present invention also provide a method for processing interrupt requests, the method being applied to a CPU, the CPU being connected to a first port of a bridge chip, the method comprising:

[0015] Receive the second interrupt request sent from the first port of the bridge chip;

[0016] Parse the second interrupt request to obtain the first interrupt vector identifier. The first interrupt vector identifier has a one-to-one correspondence with the first device identifier and the first interrupt request type of the PCIe endpoint. The first interrupt vector identifier indicates the MSI capability set message data and interrupt vector number of the PCIe endpoint.

[0017] Based on the MSI capability set message data and the interrupt vector number, the corresponding interrupt service routine is invoked to provide services to the PCIe endpoint.

[0018] In conjunction with the second aspect, in one possible implementation of the second aspect, the method further includes: obtaining at least one interrupt vector identifier bound to the first port of the bridge chip;

[0019] Obtain at least one device identifier and at least one interrupt request type bound to at least one second port of the bridge chip; generate a mapping table based on the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type, wherein the mapping table includes at least one of the following correspondences: one-to-one correspondence between interrupt request type, device identifier, and interrupt vector identifier;

[0020] The mapping table is sent to the first port of the bridge chip so that the bridge chip determines a matching first interrupt vector identifier for the PCIe endpoint that sends the first interrupt request based on the mapping table, the first interrupt vector identifier being one of the at least one interrupt vector identifier.

[0021] In conjunction with the second aspect, in another possible implementation of the second aspect, obtaining at least one interrupt vector identifier bound to the first port of the bridge chip includes: obtaining at least one MSI capability set message data and at least one interrupt vector number; generating the at least one interrupt vector identifier based on the at least one MSI capability set message data and the at least one interrupt vector number.

[0022] Thirdly, embodiments of the present invention provide an interrupt request processing apparatus, the apparatus being connected to a CPU and at least one PCIe endpoint, the apparatus comprising:

[0023] A receiving unit is configured to receive a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint;

[0024] The lookup unit is configured to search for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in a mapping table, wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier;

[0025] The generation unit is configured to generate a second interrupt request based on the first interrupt vector identifier and the first interrupt request;

[0026] The sending unit is used to send the second interrupt request to the CPU.

[0027] Furthermore, the unit module in the interrupt request processing device is also used to implement the method described in various implementations of the first aspect.

[0028] Fourthly, embodiments of the present invention provide another processing apparatus for interruption requests, the apparatus comprising:

[0029] The receiving unit is used to receive the second interrupt request sent by the first port of the bridge chip;

[0030] The parsing unit is used to parse the second interrupt request to obtain a first interrupt vector identifier. The first interrupt vector identifier has a one-to-one correspondence with the first device identifier and the first interrupt request type of the PCIe endpoint. The first interrupt vector identifier indicates the MSI capability set message data and interrupt vector number of the PCIe endpoint.

[0031] The processing unit is configured to call the corresponding interrupt service routine to provide services to the terminal device based on the MSI capability set message data and the interrupt vector number.

[0032] Furthermore, the unit module in the interrupt request processing device is also used to implement the method described in various implementations of the aforementioned second aspect.

[0033] Fifthly, embodiments of the present invention also provide a bridge chip, comprising: a processing module, a first port and at least one second port, wherein the first port is an uplink port and the second port is a downlink port;

[0034] The second port is used to receive a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint;

[0035] The processing module is configured to search for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in a mapping table, and to generate a second interrupt request based on the first interrupt vector identifier; wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier;

[0036] The first port is used to send the second interrupt request to the CPU.

[0037] In a sixth aspect, embodiments of the present invention also provide a processor coupled to a memory; wherein the memory stores computer program instructions executable by the processor, the instructions being executed by the processor to cause the processor to perform an interrupt request processing method as described in the second aspect or any implementation thereof.

[0038] In addition, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the interrupt request processing method as described in the first aspect or any implementation thereof, or the second aspect or any implementation thereof.

[0039] In a seventh aspect, embodiments of the present invention also provide a network device, the network device comprising: a bridge chip, a CPU, and at least one PCIe endpoint, the bridge chip comprising a first port and at least one second port, the first port being interconnected with the CPU, and the at least one second port being interconnected with the at least one PCIe endpoint;

[0040] The at least one PCIe endpoint is used to send at least one interrupt request to the bridge chip; the bridge chip is used to execute the interrupt request processing method described in the first aspect or any implementation thereof; the CPU is used to execute the interrupt request processing method described in the second aspect and any implementation thereof.

[0041] Optionally, the network device may be a network switch.

[0042] The interrupt request processing method and apparatus provided in this embodiment of the invention establish a one-to-one mapping between an uplink interrupt vector identifier and a downlink device identifier and interrupt request type through the uplink port and at least one downlink port of the bridge chip. This mapping relationship is used to transform the original interrupt request reported by the PCIe endpoint into a new interrupt request with a unique interrupt vector identifier, which is then reported to the CPU. This allows the CPU to directly parse and determine the PCIe endpoint corresponding to the original interrupt request after receiving the new interrupt request, thereby avoiding the CPU from having to search for and confirm the interrupt source again, thus avoiding additional overhead.

[0043] This method addresses the issue in PCIe network systems where different PCIe endpoint devices send interrupt requests to the bridge chip. The bridge chip's uplink port submits interrupt request messages of the same type to the CPU in a shared manner. The CPU system computing unit needs to query and confirm the shared interrupt before submitting the result to each PCIe endpoint, thus introducing additional overhead. Attached Figure Description

[0044] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0045] Figure 1 This is a scenario diagram of a PCIe system cabinet interrupt request submission provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram illustrating the remapping of INTx in a PCIe system bridge chip, provided as an embodiment of the present invention;

[0047] Figure 3 A schematic diagram of INTx mapping MSI in a PCIe bridge chip provided for an embodiment of the present invention;

[0048] Figure 4 A flowchart illustrating a method for processing interruption requests provided in an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram illustrating a PCIe bridge INTx mapping to MSI TLP transactions provided in an embodiment of the present invention;

[0050] Figure 6 A flowchart illustrating the processing logic for an interrupt request provided in an embodiment of the present invention;

[0051] Figure 7 A flowchart illustrating another method for processing interruption requests provided in an embodiment of the present invention;

[0052] Figure 8 A structural block diagram of an interrupt request processing device provided in an embodiment of the present invention;

[0053] Figure 9 A structural block diagram of another interrupt request processing device provided in an embodiment of the present invention;

[0054] Figure 10 This is a structural example diagram of a CPU provided in an embodiment of the present invention. Detailed Implementation

[0055] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] First, the technical scenario of the technical solution in this application will be introduced.

[0057] See Figure 1 This diagram illustrates a scenario of interrupt request submission in a network device PCIe system cabinet, as provided in an embodiment. The scenario includes a CPU 10, a bridge chip 20, and at least one PCIe endpoint 30. The CPU 10 includes components such as a root node and memory. Further, the root node includes an interrupt controller for receiving and processing at least one interrupt request sent from at least one PCIe endpoint 30, parsing the interrupt request, converting it into a message format recognizable by the CPU 10, and reporting it to the CPU. Additionally, the memory may be located outside the CPU 10.

[0058] Optionally, the root node is a root complex (RC). The RC is used to interconnect with the uplink port of the bridge chip 20. In this case, the RC serves as a connection port between the CPU 10 and the bridge chip 20, such as a PCIe port.

[0059] Bridge 20, or Switch device, includes at least one port, such as an uplink port and a downlink port, and is connected to CPU 10 via the uplink port and to at least one PCIe endpoint 30 via at least one downlink port.

[0060] The PCIe endpoint, also known as a PCIe endpoint device (EP) or PCIe terminal device, includes devices such as PCs, mobile terminals, tablets, portable devices, and wearable devices. Furthermore, the PCIe endpoint can also be a PCIe interface network card used to connect peripherals.

[0061] In addition, since the PCIe endpoints inherit all the interrupt features of PCI, including INTx, Message Signaled Interrupt (MSI) or other MSIx, at least one PCIe endpoint 30 can send one or more interrupt requests to the bridge chip 20 via methods such as INTA to INTD, MSI or PCIe-PCI bridge.

[0062] It should be noted that the PCIe system is compatible with the traditional PCI interrupt method, and mainly uses interrupt messages to simulate PCI interrupt signals (also known as virtual INTx signals). Generally, the virtual interrupt number INTx can be any one of the four types: INTA, INTB, INTC, and INTD.

[0063] In PCIe network systems, PCIe bridge chips are typically used to extend PCIe links, enabling interconnection between the RC and multiple PCIe endpoint devices, such as... Figure 1 As shown. Given that different PCIe endpoint devices submit interrupt requests in different ways, such as using INTx interrupts or MSI interrupts, when the PCIe endpoint connected to the bridge chip's downlink port submits an interrupt request using an INTx interrupt, different PCIe endpoints may use the same virtual interrupt signal (INTA / INTB INTC / INTD). Therefore, during the interrupt request submission process to the CPU, the bridge chip will inevitably have to use an interrupt sharing method, resulting in larger packets. The CPU will then need to use software to locate and confirm the EP device submitting the interrupt, which will affect the packet service efficiency.

[0064] Currently, PCIe-based bridge chips transmit INTx interrupt messages transparently. Specifically, the PCIe endpoint (EP) submits an INTx interrupt request to one of the bridge chip's downlink ports, which is then routed to the bridge chip's unique uplink port. The bridge chip then submits the request to the RC (Regulator) via a shared mechanism on the uplink port. For example... Figure 2 As shown in the diagram on the left, before port resource remapping, both PCIe endpoints send interrupt requests to the bridge chip using the INTA message type. The requests are then passed through the bridge chip to its uplink port, and both endpoints share the INTA message type.

[0065] To avoid the bridge chip submitting the same INTx interrupt request on its downlink port, which would lead to the sharing of virtual INTx interrupt messages submitted to the RC by the bridge chip's uplink port, the bridge chip employs a downlink port remapping INTx method, such as... Figure 2 As shown in the diagram on the right, the bridge chip receives interrupt requests for INTA from two PCIe endpoints on the downlink port and remaps them into one INTB type and another INTC type interrupt request. This ensures that the remapped INTB and INTC type interrupt requests are different from the INTA type originally reported by the PCIe endpoints.

[0066] Although this bridge chip remaps the INTx interrupt submitted by the downlink port, compared to the PCIe system directly passing the INTx interrupt to the RC ( Figure 2The "before remapping" method can solve many PCIe endpoint sharing INTx interrupt problems. However, since network devices support a variety of INTx interrupt requests for PCIe endpoints, the INTx type interrupts submitted by the downlink port cannot be fixed to a certain INTx type. This still results in sharing overhead and cannot solve the problem that the CPU needs to confirm the submission of interrupt requests through software due to the interrupt sharing INTx type messages, resulting in additional overhead.

[0067] The technical solution provided in this application mainly solves the technical problem that when the PCIe endpoints interconnected by the downlink ports of the bridge chip in the PCIe system of the network device submit various INTx type interrupt requests, the uplink port of the bridge chip needs to submit each INTx interrupt request in a shared manner, which leads to additional overhead when the CPU searches for and confirms the interrupt source.

[0068] To address the aforementioned technical issues, this application proposes a mapping relationship between the downlink port INTx message type and the uplink port MSI capability set message data of a network device PCIe system bridge chip. This mapping allows each PCIe endpoint's INTx interrupt request to be mapped to a unique MSI interrupt message type and submitted to the CPU's interrupt controller. The interrupt controller then delivers the interrupt request to the CPU via a dedicated PCIe method. Upon receiving the request, the CPU calls the corresponding PCIe endpoint's interrupt service routine to provide service to the PCIe endpoint device requesting the interrupt.

[0069] Specifically, in a possible application scenario, as shown in Figure 3, the bridge chip 20 includes: a first port 201, at least one second port 202, and a processing module 203. The first port 201 is an uplink port used to interconnect with the root node of the CPU 10, the second port 202 is a downlink port used to interconnect with the first PCIe endpoint 31 and / or the second PCIe endpoint 32, and the processing module 203 is used to execute the interrupt request processing method provided in this embodiment.

[0070] The processing module 203 can be a logic circuit or a processing chip, etc., and can control the first port 201 and at least one second port 202 to perform message or data receiving or sending operations.

[0071] See Figure 4 This is a flowchart illustrating a method for processing interruption requests provided in an embodiment of this application. This method can be applied to, for example... Figure 3 In the bridge chip 20 shown, and more specifically in the processing module 203 of the bridge chip 20, the method includes:

[0072] Step 101: Receive a first interrupt request from the PCIe endpoint through the second port. The first interrupt request includes a first interrupt request type and a first device identifier of the PCIe endpoint.

[0073] The PCIe endpoint sends a first interrupt request to the bridge chip. The first interrupt request is an INTx interrupt request, and the type of the first interrupt request is any one of INTA, INTB, INTC, and INTD.

[0074] In addition, the first device identifier of the PCIe endpoint is used to uniquely identify the PCIe endpoint. Specifically, the first device identifier includes at least one of the following: the PCIe message bus number of the interrupt request, the device number, and the function number. The first device identifier can uniquely determine which PCIe endpoint sent the first interrupt request.

[0075] When there is only one PCIe endpoint in the system, the first device identifier includes the bus number and the function number, but may not include the device number; when there are two or more PCIe endpoints in the system, the device identifier of each PCIe endpoint includes the bus number, the device number, and the function number.

[0076] In one implementation, the bridge chip can obtain the first device identifier by parsing the first interrupt request message. For example, the bridge chip receives an INTA interrupt message sent by PCIe endpoint 1, and by parsing the INTx interrupt message, it obtains the device identifier of PCIe endpoint 1 and the message type used, which is INTA type.

[0077] In addition, the first interrupt request also includes other information, such as payload, message data, etc.

[0078] Step 102: Based on the first interrupt request type and the first device identifier, search the mapping table for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier.

[0079] The mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier. The interrupt vector identifier includes: MSI capability set message data and interrupt vector number (or interrupt vector identifier); further, the MSI capability set message data is used to indicate a message address and data that have a unique mapping relationship with the device identifier and interrupt request type of a PCIe endpoint; the interrupt vector number and the MSI capability set message data are used to jointly indicate the interrupt request of the PCIe endpoint.

[0080] Furthermore, the interrupt vector identifier has a first binding relationship with the first port of the bridge chip, and the device identifier and interrupt request type have a second binding relationship with a second port. Through the first binding relationship and the second binding relationship, resource mapping of uplink port and at least one downlink port can be established, for example, see Table 1, which shows a mapping table.

[0081] Table 1. Mapping Relationship between Bridge Chip INTx Messages and Interrupt Vector Identifiers

[0082]

[0083] It should be understood that Table 1 above may include more or fewer mapping relationships, and this embodiment does not limit this.

[0084] In a specific example, according to step 101 above, if PCIe endpoint 1 sends a first interrupt request to the bridge chip, the first interrupt request type is INTC, and the corresponding device identifier is bus number, dev number, fun number, then based on the mapping relationship in Table 1 above, a matching first interrupt vector identifier is obtained, which includes: MSI capability set message data 3 and interrupt vector number 2.

[0085] Optionally, the interrupt vector number can be any value from 0 to 31.

[0086] Step 103: Generate a second interrupt request based on the first interrupt vector identifier and the first interrupt request.

[0087] Specifically, based on the first interrupt vector identifier determined in the previous step (e.g., including MSI capability set message data 3 and interrupt vector number 2), and combined with the data and information in the original first interrupt request, a second interrupt request is encapsulated and generated. The second interrupt request includes the mapped message address and message data, as well as the corresponding interrupt vector number.

[0088] The second interrupt request is an MSI TLP message.

[0089] Step 104: Send the second interrupt request to the CPU through the first port.

[0090] The bridge chip will send the generated second interrupt request, such as an MSI TLP message, to the CPU's interrupt controller through the first port, so that the interrupt controller can parse and process the second interrupt request.

[0091] Correspondingly, the method further includes: the CPU receiving a second interrupt request sent by the first port of the bridge chip; parsing the second interrupt request to obtain a first interrupt vector identifier, wherein the first interrupt vector identifier has a one-to-one correspondence with the first device identifier and the first interrupt request type of the PCIe endpoint, and the first interrupt vector identifier indicates the MSI capability set message data and the interrupt vector number of the PCIe endpoint; and calling the corresponding interrupt service routine to provide services to the PCIe endpoint according to the MSI capability set message data and the interrupt vector number.

[0092] For example, in this example, the CPU parses the second interrupt request, obtains MSI capability set message data 3 and interrupt vector number 2, and obtains the interrupt request as 5 (5 = 3 + 2). Then it determines that the first interrupt request sent by the PCIe endpoint is the 5th interrupt request (or marked as "interrupt request 5"). Then, based on the interrupt request 5, it determines the service request that needs to be called and provides interrupt service to the PCIe endpoint.

[0093] The method provided in this embodiment establishes a one-to-one mapping between an uplink interrupt vector identifier and a downlink device identifier and interrupt request type through the uplink port and at least one downlink port of the bridge chip. This mapping relationship is used to transform the original interrupt request reported by the PCIe endpoint into a new interrupt request with a unique interrupt vector identifier, which is then reported to the CPU. After receiving the new interrupt request, the CPU can directly parse and determine the PCIe endpoint corresponding to the original interrupt request, thereby avoiding the CPU side from searching for and confirming the interrupt source and avoiding additional overhead.

[0094] Optionally, in another embodiment, step 102 above, obtaining the mapping table, can be achieved in one of the following two ways:

[0095] The first method: The bridge chip receives the mapping table sent by the CPU and stores the mapping table.

[0096] In the second method, the bridge chip obtains the parameter information of each parameter in the mapping table, including: the type of at least one interrupt request, the device identifier of each PCIe endpoint, and at least one interrupt vector identifier; and then generates the mapping table based on the obtained type of at least one interrupt request, the device identifier of each PCIe endpoint, and at least one interrupt vector identifier.

[0097] First, the process of the CPU generating the mapping table in the first method will be explained in detail, including:

[0098] Step 1: Obtain at least one interrupt vector identifier bound to the first port of the bridge chip.

[0099] Each interrupt vector identifier includes: an MSI capability message data set and an interrupt vector number. The MSI capability message data reflects the data of the MSI capability set, as shown in Table 2, including MSI message data, message address, and extended message data. Table 1 shows the structure of an MSI capability data set with a 32-bit message address. It should be understood that 64-bit or more message addresses can also be set; this embodiment does not impose such limitations.

[0100] Table 2. MSI Capability Set Data Structure (32-bit Message Address)

[0101]

[0102] The interrupt vector number is an offset, and in the configuration of a 32-bit address message, the range of the interrupt vector number is 0 to 31. Additionally, the first port can be identified by a port number, such as port ID 1.

[0103] The method for obtaining at least one interrupt vector identifier in the aforementioned "first step" can be obtained when the CPU system is enabled.

[0104] Step 2: Obtain at least one device identifier and at least one interrupt request type bound to at least one second port of the bridge chip.

[0105] The device identifier and terminal request type bound to each second port are also known as the second binding relationship. Each second binding relationship includes the correspondence between a second port and a PCIe endpoint's device identifier and an interrupt request type. Each second port can also be represented by a port number, for example, a second port corresponding to port ID 2.

[0106] Since each PCIe endpoint device can use four INTx message types, a PCIe endpoint device identifier can establish four secondary binding relationships with the four INTx message types. If there are m secondary ports, then m × 4 secondary binding relationships will be established. Therefore, the bridge chip can establish binding relationships between the device identifiers of all PCIe endpoints and the m secondary ports through enumeration.

[0107] It should be noted that the order of the first and second steps can be interchanged, that is, the order in which the bridge chip obtains the first binding relationship and establishes at least one second binding relationship is not limited in this embodiment.

[0108] Step 3: Generate a mapping table based on the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type. The mapping table includes at least one of the following correspondences: a one-to-one correspondence between interrupt request type, device identifier, and interrupt vector identifier.

[0109] Specifically, the CPU first acquires at least one MSI capability set message data and at least one interrupt vector number, and then generates the at least one interrupt vector identifier based on the at least one MSI capability set message data and the at least one interrupt vector number.

[0110] Step 4: Send the mapping table to the first port of the bridge chip.

[0111] Specifically, the CPU sends the generated mapping table to the first port of the bridge chip via RC.

[0112] The method provided in this embodiment establishes a binding between an uplink port and at least one downlink port through a first binding relationship of the uplink port and at least one second binding relationship of at least one downlink port of the PCIe bridge chip. This results in a unique mapping relationship between the device identifier, INTx message type, and MSI capability set message data and interrupt vector number of each PCIe endpoint device, thereby realizing resource sharing between at least one downlink port and uplink port of the PCIe bridge chip.

[0113] It should be noted that when an interrupt is triggered, the CPU initiates a memory write transaction. The memory address to be written is specially allocated by the system and used for interrupt submission (the data to be written is the interrupt vector corresponding to the interrupt requesting device). The target is the interrupt controller of the root node (RC), which is used to distinguish it from other write transactions and deliver it to the CPU in a PCIe-specific manner. After receiving it, the CPU calls the interrupt service routine according to the interrupt vector number, thereby providing services to the device that requested the interrupt.

[0114] Furthermore, as a possible implementation, the PCIe bridge chip utilizes the uplink port (first port) to initiate MSI capability set configuration, enable MSI interrupt messages, and construct MSI capability set message data during the process, such as... Figure 5 As shown, it specifically includes:

[0115] When starting and initializing the PCIe system, the PCIe MSI capability set of the uplink port of the PCIe bridge chip is configured, and MSI multi-message configuration is enabled (for example, according to the PCIe specification, MSI supports a maximum of 32-bit address) and the address and data required for MSI messages are enabled. Since the number of interrupt vectors used by network devices to extend the PCIe link downlink port through the PCIe bridge chip is usually no more than 8, in this embodiment, the network device system configures the MSI PCIe 32-bit address on the uplink port MSI capability register group of the PCIe system bridge chip, that is, the lower 32 bits of the message address register, which corresponds to the write transaction header of the uplink port MSI register. The lower 32 bits of the bridge chip's MSI message address configured by the MSI capability set is [31:2].

[0116] In this embodiment, 32 MSI interrupt vector numbers (numbered 0 to 31) are set, which can meet the needs of general network devices. It should be understood that MSI addresses and interrupt vector numbers with more bits can also be set, and this embodiment does not impose any restrictions on this.

[0117] The "second method" mentioned above will be explained in detail below.

[0118] like Figure 6 As shown, the bridge chip obtains MSI capability set message data and at least one interrupt vector number, as well as enable MSI capability set message data, through the first port (PCIe uplink port). The bridge chip uses at least one downlink port's possible INTx message type to establish a unique mapping relationship with the MSI capability set message data and interrupt vector number, including establishing a one-to-one correspondence between the device identifier (bus number, dev number, fun number) and INTx message type of at least one downlink port, and at least one MSI capability set message data and interrupt vector number of the uplink port; generating the mapping table as shown in Table 1.

[0119] When the downlink port of the PCIe bridge chip receives a first request message (e.g., an INTx TLP transaction message) from a PCIe endpoint, it searches the established mapping table for a mapping relationship that matches the INTx interrupt request type and device identifier carried in the message. This mapping relationship is used to determine a unique MSI capability set message data and interrupt vector number, resulting in an interrupt vector identifier with a unique mapping relationship. Based on this interrupt vector identifier, a second request message corresponding to the first request message is generated; this second request message is an MSI TLP (Transaction Layer Packet) message. Finally, the PCIe bridge chip sends this second request message to the interrupt controller of the RC via the uplink port. For a more detailed process, please refer to steps 101 to 104 of the aforementioned embodiment; these steps will not be repeated here.

[0120] The method provided in this embodiment establishes a mapping relationship between at least one PCIe endpoint of the downlink port and the MSI capability set message data and interrupt vector number of the uplink port based on the resource information of the uplink and downlink ports. Through this mapping relationship, a unique interrupt vector identifier, i.e., a uniquely assigned message address and interrupt vector number, is provided to the requesting PCIe endpoint. This solves the problem that when different terminal devices send interrupt request messages to the bridge chip, the uplink port of the bridge chip submits the same type of interrupt request messages to the CPU in a shared manner, which causes additional overhead in the process of the CPU querying and confirming the interrupt source.

[0121] In addition, for at least one downlink port of the PCIe system bridge chip interconnection EP of network equipment, a method is adopted to establish the mapping of INTx message type and terminal device identifier to MSI capability set message data by software configuration. This enables the bridge chip to support up to 32 MSI interrupt vector numbers, thereby realizing a one-to-one mapping relationship between the interrupt vector identifier of the root node and the INTx message message submitted by the EP.

[0122] See Figure 7 This is a flowchart illustrating an interruption request handling method according to another embodiment of this application. The method includes:

[0123] Step 301: During initialization, the CPU enables the MSI capability set of the bridge chip, configures the MSI capability set message address, data, and at least one interrupt vector number.

[0124] Step 302: Based on at least one MSI capability set message data, at least one interrupt vector number, at least one downlink port message type, and the device identifier of the PCIe endpoint, establish a mapping table with unique mapping relationships.

[0125] Step 303: The CPU sends the mapping table to the bridge chip. Correspondingly, the bridge chip receives the mapping table through the uplink port.

[0126] Step 304: The bridge chip receives a first interrupt request sent by any PCIe endpoint. Specifically, the bridge chip receives the first interrupt request through a downlink port.

[0127] Step 305: The bridge chip determines whether the first interrupt request is an INTx message; if yes, proceed to step 306; if no, proceed to step 310.

[0128] Step 306: If it is an INTx message, such as any one of INTA to INTD, then look up the matching interrupt vector identifier in the mapping table according to the device identifier and INTx message type in the first interrupt request.

[0129] The mapped MSI message address and data can be uniquely determined by using the interrupt vector number in the found interrupt vector identifier and the MSI capability set message data. For details, please refer to the aforementioned process. Figure 4 The embodiments described in the previous examples will not be repeated here.

[0130] Step 307: The bridge chip generates a second interrupt request based on the MSI message address, data, interrupt vector number, and payload information in the first interrupt request. The second interrupt request is an MSI TLP message.

[0131] Step 308: The bridge chip sends a second interrupt request to the CPU's interrupt controller via the uplink port. Correspondingly, the interrupt controller receives the second interrupt request.

[0132] Step 309: After receiving the second interrupt request, the CPU's interrupt controller executes the interrupt request processing flow.

[0133] Specifically, the processing flow includes: parsing and processing the second interrupt request in the PCIe proprietary mode, and then reporting it to the CPU. After receiving the report, the CPU calls the corresponding interrupt handler and completes the interrupt request task.

[0134] Furthermore, the interrupt controller converts the second interrupt request into the address and data of the PCIe bridge chip MSI capability set configured according to the PCIe system initialization of the network device, identifies which PCIe endpoint is the source of the interrupt request, and sends the interrupt request message corresponding to the PCIe endpoint to the CPU through a PCIe-specific method. After receiving the message, the CPU calls the corresponding interrupt handler to execute and complete the interrupt request task of the PCIe endpoint.

[0135] In addition, the judgment in step 305 above also includes:

[0136] Step 310: If not, that is, if it is determined that the request message is not an INTx message message, but an MSI interrupt message, then the bridge chip uses the uplink port to send the received MSI message message (i.e. the first interrupt request) to the CPU.

[0137] The CPU's interrupt controller receives the MSI message and performs interrupt processing according to the preset procedure.

[0138] It should be noted that the CPU's processing of the MSI message packets reported by the bridge chip in step 310 is the same as or similar to the processing of MSI messages by the PCIe system of the network device, and this application will not describe it in detail.

[0139] The method provided in this embodiment establishes a unique mapping relationship between the requested INTx message type, the device identifier of the PCIe endpoint, the MSI capability set message data, and the interrupt vector number. This solves the problem that when a PCIe system endpoint device submits an INTx interrupt request, it submits the same type of interrupt request to the CPU through the uplink port of the bridge chip in a shared manner. The CPU needs to query and confirm the interrupt source for the shared interrupt, which introduces additional overhead.

[0140] This method uses a unique mapping relationship to delegate the CPU's query and confirmation of interrupt EP messages to the bridge chip for processing, thereby avoiding additional overhead. By mapping the INTx message type to the MSI capability set message data interrupt method, the bridge chip can map the INTx interrupt message to the CPU as an MSI interrupt message with a unique interrupt vector before submitting the INTx interrupt message to the CPU. The CPU can directly confirm the interrupt request source based on the submitted MSI interrupt request and directly call the interrupt service routine, avoiding the introduction of additional overhead.

[0141] This invention also discloses an interrupt request processing apparatus, which is connected to a CPU and at least one PCIe endpoint, for implementing the interrupt request processing method of the foregoing embodiments.

[0142] Specifically, such as Figure 8 As shown, the interrupt request processing device 800 includes a receiving unit 810, a searching unit 820, a generating unit 830, and a sending unit 840. In addition, the device may include other units or modules, such as a storage unit or a mapping unit, etc. This embodiment does not limit this.

[0143] The receiving unit 810 is configured to receive a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint.

[0144] The lookup unit 820 is configured to look up a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in a mapping table, wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier.

[0145] The generation unit 830 is used to generate a second interrupt request based on the first interrupt vector identifier and the first interrupt request.

[0146] The sending unit 840 is used to send the second interrupt request to the CPU.

[0147] In addition, the interrupt request processing device 800 is also used to implement other method steps of the interrupt request processing method in the foregoing embodiments.

[0148] Optionally, the interrupt request processing device 800 is a bridge chip, such as a PCIe bridge chip.

[0149] Furthermore, in another embodiment, another interrupt request processing apparatus is provided for implementing the aforementioned method steps in the CPU. Specifically, as shown... Figure 9 As shown, the interrupt request processing device 900 includes a receiving unit 910, a parsing unit 920, a processing unit 930, and a sending unit 940. In addition, it may include other more or fewer units or modules, which are not limited in this embodiment.

[0150] The receiving unit 910 is used to receive the second interrupt request sent by the first port of the bridge chip.

[0151] The parsing unit 920 is used to parse the second interrupt request to obtain a first interrupt vector identifier. The first interrupt vector identifier has a one-to-one correspondence with the first device identifier and the first interrupt request type of the PCIe endpoint. The first interrupt vector identifier indicates the MSI capability set message data and interrupt vector number of the PCIe endpoint.

[0152] The processing unit 930 is configured to call the corresponding interrupt service routine to provide services to the terminal device based on the MSI capability set message data and the interrupt vector number.

[0153] Furthermore, in one specific embodiment, the processing unit 930 is also configured to obtain at least one interrupt vector identifier bound to a first port of the bridge chip; obtain at least one device identifier and at least one interrupt request type bound to at least one second port of the bridge chip; and generate a mapping table based on the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type, wherein the mapping table includes at least one of the following correspondences: a one-to-one correspondence between interrupt request type, device identifier, and interrupt vector identifier.

[0154] The sending unit 940 is configured to send the mapping table to the first port of the bridge chip, so that the bridge chip determines a matching first interrupt vector identifier for the PCIe endpoint that sends the first interrupt request according to the mapping table, wherein the first interrupt vector identifier is one of the at least one interrupt vector identifier.

[0155] Optionally, the number of MSI interrupt vector numbers supported by the MSI capability set message data does not exceed 32.

[0156] Optionally, the interrupt request handling device 900 described above is a processor, such as a CPU.

[0157] It should be noted that this embodiment is about Figure 8 and Figure 9The specific limitations of the interrupt request processing device shown can be found in the limitations of the interrupt request processing device method in the above embodiments, and will not be repeated here. In this embodiment, each unit and module of the interrupt request processing device can be implemented entirely or partially through software, hardware, or a combination thereof. The above modules can be embedded in hardware or independently of the processor of the electronic device, or stored in software in the memory of the electronic device, so that the processor can call and execute the operations corresponding to the above modules.

[0158] At the hardware implementation level, this embodiment also provides a bridge chip, the structure of which can be as described above. Figure 3 As shown, it includes: a first port 201, at least one second port 202, and a processing module 203.

[0159] Furthermore, the above Figure 8 The receiving unit 810 in the interrupt request processing device shown can be implemented through at least one second port 202 to receive a first interrupt request from a PCIe endpoint; the lookup unit 820 and the generation unit 830 can be implemented through the processing module 203 to look up a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in the mapping table, and to generate a second interrupt request based on the first interrupt vector identifier; the function of the sending unit 840 can be implemented through the first port 201.

[0160] In addition, embodiments of the present invention also provide a processor, such as Figure 10 As shown, the processor 110 and memory 120 are coupled, and the processor 110 and memory 120 can be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0161] In addition, the processor can be connected to at least one port, including a PCIe port, etc. Figure 10 At least one port is not shown. It should be understood that the processor may also be other hardware modules or units, or connected to other hardware modules, and this embodiment does not limit this.

[0162] The processor 110 can be a central processing unit (CPU). The processor 110 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0163] The memory 120, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the interrupt request handling method in the embodiments of the present invention. The processor 110 executes various functional applications and data processing of the processor 110 by running the non-transitory software program instructions stored in the memory 120, that is, it implements the interrupt request handling method in the above method embodiments.

[0164] Memory 120 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function. The data storage area may store data created by processor 110, MSI capability set message data, interrupt vector numbers, device identifiers, and INTx message types, etc. Furthermore, memory 120 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 120 may optionally include memory remotely located relative to processor 110, and these remote memories may be connected to processor 110 via a network. Examples of such networks include, but are not limited to, various network devices in a PCIe network system.

[0165] In addition, at least one port can also be used to connect other external devices, such as communicating with various terminal devices or remote network devices. Optionally, at least one port can also be used to connect peripheral input / output devices, such as a keyboard or display screen.

[0166] The one or more modules are stored in the memory 120, and when executed by the processor 110, they perform the following: Figure 4 and Figure 7 The interrupt request handling method in the illustrated embodiment.

[0167] This embodiment also provides a network device, the structure of which is described above. Figures 1 to 3As shown, the network device includes a CPU 10, a bridge chip 20, and at least one PCIe endpoint 30. Further, the bridge chip 20 is interconnected with the CPU 10 through the first port and interconnected with at least one PCIe endpoint 30 through at least one second port.

[0168] The at least one PCIe endpoint 30 is used to send at least one interrupt request, such as a first interrupt request, to the bridge chip 20; the bridge chip 20 is used to execute the above-described embodiments. Figure 4 or Figure 7 The interrupt request handling method described above; the CPU 10 is used to execute the methods described in the foregoing embodiments. Figure 4 or Figure 7 The method for handling interruption requests.

[0169] The structure of CPU 10 can be compared with... Figure 10 The structures shown are the same.

[0170] The structure of the PCIe endpoint can also be similar to... Figure 10 The structure shown is similar, including components such as a processor and memory.

[0171] Optionally, the network device can be a network switch or a PCIe device.

[0172] For specific details regarding the aforementioned network systems, please refer to the relevant documents. Figure 1 The relevant descriptions and effects in the illustrated embodiments are for understanding purposes only and will not be repeated here.

[0173] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0174] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for handling interruption requests, characterized in that, The method is applied to a bridge chip, the bridge chip including a first port and at least one second port, the first port being an uplink port and the second port being a downlink port, the method comprising: The second port receives a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint. Based on the first interrupt request type and the first device identifier, a first interrupt vector identifier that matches the first interrupt request type and the first device identifier is searched in a mapping table, wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier and interrupt vector identifier; A second interrupt request is generated based on the first interrupt vector identifier and the first interrupt request; The second interrupt request is sent to the CPU through the first port.

2. The method according to claim 1, characterized in that, Before searching the mapping table for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier, the method further includes: Receive the mapping table sent from the CPU; or, The mapping table is generated based on the type of at least one interrupt request, the device identifier of each PCIe endpoint, and at least one interrupt vector identifier.

3. The method according to claim 2, characterized in that, The interrupt vector identifier includes message signal interruption MSI capability set message data and interrupt vector number; The MSI capability set message data is used to indicate a message address and data that have a unique mapping relationship with a PCIe endpoint's device identifier and interrupt request type; the interrupt vector number and the MSI capability set message data are used to jointly indicate the interrupt request of the PCIe endpoint.

4. The method according to any one of claims 1-3, characterized in that, The device identifier includes: the bus number, device number, and function number of the INTx message.

5. The method according to any one of claims 1-3, characterized in that, The method further includes: If the first interrupt request is an MSI interrupt request, then the first interrupt request is sent to the CPU through the first port.

6. A method for handling interruption requests, characterized in that, The method is applied to a CPU connected to a first port of a bridge chip, and the method includes: Receive the second interrupt request sent from the first port of the bridge chip; Parse the second interrupt request to obtain the first interrupt vector identifier. The first interrupt vector identifier has a one-to-one correspondence with the first device identifier and the first interrupt request type of the PCIe endpoint. The first interrupt vector identifier indicates the MSI capability set message data and interrupt vector number of the PCIe endpoint. Based on the MSI capability set message data and the interrupt vector number, the corresponding interrupt service routine is invoked to provide services to the PCIe endpoint; The second interrupt request is generated in the following manner: The bridge chip receives a first interrupt request from a PCIe endpoint through its second port. The first interrupt request includes a first interrupt request type and a first device identifier of the PCIe endpoint. Based on the first interrupt request type and the first device identifier, a first interrupt vector identifier that matches the first interrupt request type and the first device identifier is searched in a mapping table, wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier and interrupt vector identifier; A second interrupt request is generated based on the first interrupt vector identifier and the first interrupt request.

7. The method according to claim 6, characterized in that, The method further includes: Obtain at least one interrupt vector identifier bound to the first port of the bridge chip; Obtain at least one device identifier and at least one interrupt request type bound to at least one second port of the bridge chip; A mapping table is generated based on the at least one interrupt vector identifier, the at least one device identifier, and the at least one interrupt request type. The mapping table includes at least one of the following correspondences: a one-to-one correspondence between interrupt request type, device identifier, and interrupt vector identifier. The mapping table is sent to the first port of the bridge chip so that the bridge chip determines a matching first interrupt vector identifier for the PCIe endpoint that sends the first interrupt request based on the mapping table, the first interrupt vector identifier being one of the at least one interrupt vector identifier.

8. The method according to claim 7, characterized in that, The step of obtaining at least one interrupt vector identifier bound to the first port of the bridge chip includes: Acquire at least one MSI capability set message data and at least one interrupt vector number; The at least one interrupt vector identifier is generated based on the at least one MSI capability set message data and the at least one interrupt vector number.

9. An apparatus for processing interrupt requests, characterized in that, The device is connected to a CPU and at least one PCIe endpoint, and the device includes: A receiving unit is configured to receive a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint; The lookup unit is configured to search for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in a mapping table, wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier; The generation unit is configured to generate a second interrupt request based on the first interrupt vector identifier and the first interrupt request; The sending unit is used to send the second interrupt request to the CPU.

10. An apparatus for processing interrupt requests, characterized in that, The device includes: The receiving unit is used to receive the second interrupt request sent by the first port of the bridge chip; The parsing unit is used to parse the second interrupt request to obtain a first interrupt vector identifier. The first interrupt vector identifier has a one-to-one correspondence with the first device identifier and the first interrupt request type of the PCIe endpoint. The first interrupt vector identifier indicates the MSI capability set message data and interrupt vector number of the PCIe endpoint. The processing unit is configured to call the corresponding interrupt service routine to provide services to the PCIe endpoint based on the MSI capability set message data and the interrupt vector number; The second interrupt request is generated in the following manner: The bridge chip receives a first interrupt request from a PCIe endpoint through its second port. The first interrupt request includes a first interrupt request type and a first device identifier of the PCIe endpoint. Based on the first interrupt request type and the first device identifier, a first interrupt vector identifier that matches the first interrupt request type and the first device identifier is searched in a mapping table, wherein the mapping table includes at least one of the following correspondences: interrupt request type, device identifier and interrupt vector identifier; A second interrupt request is generated based on the first interrupt vector identifier and the first interrupt request.

11. A bridge plate, characterized in that, include: The system includes a processing module, a first port, and at least one second port, wherein the first port is an uplink port and the second port is a downlink port. The second port is used to receive a first interrupt request from a PCIe endpoint, the first interrupt request including a first interrupt request type and a first device identifier of the PCIe endpoint; The processing module is configured to search for a first interrupt vector identifier that matches the first interrupt request type and the first device identifier in a mapping table, and to generate a second interrupt request based on the first interrupt vector identifier. The mapping table includes at least one of the following correspondences: interrupt request type, device identifier, and interrupt vector identifier; The first port is used to send the second interrupt request to the CPU.

12. A processor coupled to a memory, characterized in that, The memory stores computer-readable program instructions. When the instruction is executed by the processor, the interrupt request processing method as described in any one of claims 6 to 8 is implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the interrupt request processing method as described in any one of claims 1 to 8.

14. A network device, characterized in that, The network device includes: a bridge chip, a CPU, and at least one PCIe endpoint. The bridge chip includes a first port and at least one second port. The first port is interconnected with the CPU, and the at least one second port is interconnected with the at least one PCIe endpoint. The at least one PCIe endpoint is used to send at least one interrupt request to the bridge chip; The bridge chip is used to execute the method for processing an interruption request as described in any one of claims 1 to 5; The CPU is used to execute the interrupt request processing method as described in any one of claims 6 to 8.

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