Fast switching word line drive circuit suitable for wide supply voltage range

Abstract

The application discloses a fast switching word line driving circuit suitable for a wide range of power supply voltages, including a working mode and a standby mode. The working mode includes a working mode charge pump power stage, a dynamic frequency modulation voltage stabilizing circuit, a power supply voltage detection module, a fast switching precharge module, two level shift circuits and a level transmission circuit; the standby mode includes a standby mode charge pump power stage and a SKIP modulation voltage stabilizing circuit. In addition, an ultra-low power consumption voltage reference source continuously provides a reference voltage in the two modes. The application adds a power supply voltage detection module in the working mode, which can reduce the output word line voltage overshoot and ripple in a wide range of power supply voltages, avoiding unnecessary power consumption loss; the added fast switching precharge module optimizes the switching time from the standby mode to the working mode according to the special requirements of NOR Flash fast random reading.

Description

Technical Field

[0001] This invention relates to the field of non-volatile memory technology, and more particularly to a fast word line switching drive circuit suitable for a wide power supply voltage range. Background Technology

[0002] Semiconductor memory is mainly divided into volatile memory and non-volatile memory. The most mainstream non-volatile memory is Flash memory, which is further divided into NOR Flash and NAND Flash. Compared with the mainstream NAND Flash, NOR Flash has disadvantages such as low capacity density, slow write and erase speeds, and high price. However, it is difficult to be eliminated from the market because of its faster read speed, stronger reliability, and longer lifespan. Especially due to the rapid development of 5G, IoT, Bluetooth headsets, AMOLED screens, and smart cars in recent years, NOR Flash has once again received attention.

[0003] Write and erase operations of NOR Flash memory require applying bias voltage to the control gate and drain of the NOR Flash memory cell so that electrons can be injected or extracted from the floating gate; while read operation applies voltage to the control gate, and the switching state of the channel can be used as the basis for determining the data value of "0" and "1"; the bias voltage applied to the control gate is called the word line voltage, and the bias voltage applied to the drain is called the bit line voltage.

[0004] Since NOR Flash only provides a single power supply voltage, while various memory operations require different word line and bit line voltages, an on-chip boost system is needed. Charge pumps are well-suited for floating gate memories due to their advantages such as low integration difficulty, moderate ripple, and high efficiency.

[0005] Currently, the fluctuation range of ordinary power supply voltage is generally maintained at... The design of charge pump stages often requires ensuring that the target word line voltage value can be output even at the lowest power supply voltage. Therefore, for higher power supply voltage inputs, a fixed number of charge pump stages will inevitably result in a large overshoot voltage and ripple in the output voltage. Both of these will adversely affect the NOR Flash in various operations and also cause unnecessary power consumption waste.

[0006] Because NOR Flash has the characteristic of fast random access, when it exits standby mode and resumes the operating mode that requires reading, the memory access time must not be lost. However, the reference voltage source, charge pump, and voltage regulation circuit require tens of microseconds to generate a stable word line voltage, which is simply insufficient to meet the nanosecond-level random access time of NOR Flash. Therefore, even in standby mode, the word line voltage node needs to be at a certain level of high voltage to meet the requirements of word line voltage during read operations. It is worth noting that when the word line voltage recovers from standby to operating mode, since two different feedback loops charge the output node, the switching will cause some stray transients in the output node. This makes it difficult to meet the nanosecond-level access time requirement, so it is necessary to minimize the impact of stray transients at the moment of switching. Summary of the Invention

[0007] In order to enable the word line driver circuit to provide a stable output voltage over a wide input power supply voltage range and to maintain access time when returning from standby mode to operating mode, this invention provides a fast-switching word line driver circuit suitable for a wide power supply voltage range.

[0008] A fast-switching word line driver circuit suitable for a wide power supply voltage range. It includes two modes: working mode and standby mode; The circuit in the described operating mode includes: an operating mode charge pump power stage, a dynamic frequency modulation voltage regulator circuit, a power supply voltage detection module, a fast switching precharge module, an ultra-low power voltage reference source, a level shift circuit 1, a level shift circuit 2, a level transmission circuit, and a PMOS high-voltage device M1; the operating mode charge pump power stage includes a three-stage cross-coupled charge pump and a single-stage gated cross-coupled charge pump for generating high voltage; The dynamic frequency modulation voltage regulator circuit includes, in sequence, a voltage-controlled oscillator, a non-overlapping clock generation circuit module, an error amplifier EA, and resistor dividers R1 and R2, which are used to output the high voltage generated by the charge pump stably and with low ripple under all PVT conditions. The power supply voltage detection module includes, in sequence, resistor dividers R3 and R4, comparator COM1, two-stage rectifier inverter and NMOS device M2, which are used to detect the input power supply voltage and generate signals CP_ON and CP_OFF. The fast-switching precharge module, consisting of a transmission gate, a buffer, an RC delay circuit, three inverters and a NAND gate, is used to precharge the sampling point VFB_ACT to the reference voltage VREF the instant the system returns from standby mode to operating mode. An ultra-low power voltage reference source provides the reference voltage VREF for the error amplifier EA and comparator COM1; Level shifting circuit 1 is used to convert the signals CP_ON and CP_OFF ​​generated by the power supply voltage detection module into voltage signals CP_ON_HV and CP_ON_LHV with a high level of Vwl, so as to control the on / off state of the gated cross-coupled charge pump and the level transmission circuit. Level shifting circuit 2 is used to convert the enable signals ACT_EN and ACT_EN_L into high-level voltage signals ACT_EN_HV and ACT_EN_LHV, respectively. The ACT_EN_LHV signal is used to control the on / off state of the PMOS high-voltage device M1. The level transmission circuit, controlled by the signal CP_ON_HV, is used to transmit the output voltage of the first three cross-coupled charge pumps. The PMOS high-voltage device M1, as a switching transistor, is controlled by the signal ACT_EN_LHV and is used to switch the current in the branch of resistors R1 and R2. The circuit in standby mode includes: a standby mode charge pump power stage, a SKIP modulation voltage regulator circuit, and an ultra-low power voltage reference source; Standby mode charge pump power stages, including DICKSON charge pumps, are used to generate high voltages; The SKIP modulation voltage regulator circuit includes, in sequence, a current-starved oscillator, a non-overlapping clock generation circuit, a comparator COM2, a down counter, a rectifier inverter, a NOR gate, and a diode voltage divider feedback circuit composed of PMOS transistors M3~M10, which is used to maintain the output voltage in standby mode. An ultra-low power voltage reference source is used to provide the reference voltage VREF for comparator COM2 and the bias voltage VBIAS for current-starved oscillators.

[0009] The gated cross-coupled charge pump in the aforementioned operating mode is equipped with an NMOS high-voltage switch controlled by control signals CP_ON_HV and CP_OFF_HV to transmit or block clock signals ACT_CLK and ACT_CLKB.

[0010] The fast switching pre-charge module generates pulse signals BUF and BUF_L with a pulse width of tens of ns, which are triggered simultaneously with the rising edge of the ACT_EN signal by RC delay and then through logic gates and rectifier inverters. These pulse signals are used to control the buffer self-bias current and the on / off state of the transmission gate.

[0011] In the aforementioned operating mode, the bias current of the error amplifier EA and comparator COM1 is provided by the reference current source in the operating mode, which is controlled by the enable signals ACT_EN and ACT_EN_L.

[0012] The bias current of comparator COM2 in standby mode is provided by a reference current source in standby mode controlled by enable signals STB_EN and STB_EN_L.

[0013] In the standby mode, the PMOS devices M3~M10 are high-voltage PMOS devices with the same width-to-length ratio connected by diodes, and the MOS transistors operate in the subthreshold region with static power consumption in the nA range.

[0014] The PMOS device, NMOS device, MOS device, switching MOS transistor, and switching transistor mentioned above are all metal-oxide-semiconductor MOS transistors.

[0015] The high-voltage PMOS device, high-voltage NMOS device, and high-voltage switching MOS transistor are all laterally diffused metal-oxide-semiconductor MOS transistors.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: In the operating mode, for a wide power supply voltage input of 1.5~2.1V, the fixed-stage charge pump power stage has been adjusted to a charge pump power stage combining a three-stage fixed charge pump and a one-stage gated charge pump. A power supply voltage detection module has also been added to determine whether the gated charge pump is working by detecting the power supply voltage. This improvement optimizes the output voltage ripple and overshoot while avoiding unnecessary power loss.

[0017] Meanwhile, since NOR Flash memory has a very fast read speed, with random read time on the order of nanoseconds, the recovery from standby mode to working mode must not lose access time. To address this requirement, this invention adds a fast switching precharge module to the working mode, which precharges the resistor sampling points in the feedback network to the reference voltage VREF through a feedforward method. This not only optimizes the access time but also avoids the adverse effects of stray transients generated during switching. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a fast word line switching drive circuit applicable to a wide power supply voltage range in this invention.

[0019] Figure 2 This is a circuit diagram of the gated cross-coupled charge pump in the charge pump power stage of the character line driving circuit in the present invention during the working mode.

[0020] Figure 3 This is a schematic diagram comparing the overshoot voltage of a traditional word line driving circuit and the improved driving circuit in this invention under different power supply voltages. Figure 4 This is a schematic diagram comparing the output voltage ripple of a traditional word line driving circuit and the improved driving circuit in this invention under different power supply voltages.

[0021] Figure 5 This is a schematic diagram of the transient simulation results of the character line driving circuit in this invention when it returns to the working mode from standby mode. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but the examples given are not intended to limit the present invention.

[0023] As attached Figure 1 The diagram shows a fast-switching word line driving circuit suitable for a wide power supply voltage range, including two modes: working mode and standby mode.

[0024] The circuit in the aforementioned operating mode includes: The operating mode charge pump power stage includes a three-stage cross-coupled charge pump and a single-stage gated cross-coupled charge pump for generating high voltage. The dynamic frequency modulation voltage regulator circuit includes, in sequence, a voltage-controlled oscillator, a non-overlapping clock generation circuit module, an error amplifier EA, and resistor dividers R1 and R2, which are used to output the high voltage generated by the charge pump stably and with low ripple under all PVT conditions. The power supply voltage detection module includes, in sequence, resistor dividers R3 and R4, comparator COM1, two-stage rectifier inverter and NMOS device M2, which are used to detect the input power supply voltage and generate signals CP_ON and CP_OFF. The fast-switching precharge module, consisting of a transmission gate, a buffer, an RC delay circuit, three inverters and a NAND gate, is used to precharge the sampling point VFB_ACT to the reference voltage VREF the instant the system returns from standby mode to operating mode. An ultra-low power voltage reference source provides the reference voltage VREF for the error amplifier EA and comparator COM1; Level shifting circuit 1 is used to convert the signals CP_ON and CP_OFF ​​generated by the power supply voltage detection module into voltage signals CP_ON_HV and CP_ON_LHV with a high level of Vwl, so as to control the on / off state of the gated cross-coupled charge pump and the level transmission circuit. Level shifting circuit 2 is used to convert the enable signals ACT_EN and ACT_EN_L into high-level voltage signals ACT_EN_HV and ACT_EN_LHV, respectively. The ACT_EN_LHV signal is used to control the on / off state of the PMOS high-voltage device M1. The level transmission circuit, controlled by the signal CP_ON_HV, is used to transmit the output voltage of the first three cross-coupled charge pumps. The PMOS high-voltage device M1, as a switching transistor, is controlled by the signal ACT_EN_LHV to switch the current in the branch of resistors R1 and R2.

[0025] The circuit in standby mode includes: Standby mode charge pump power stages, including DICKSON charge pumps, are used to generate high voltages; The SKIP modulation voltage regulator circuit includes, in sequence, a current-starved oscillator, a non-overlapping clock generation circuit, a comparator COM2, a down counter, a rectifier inverter, a NOR gate, and a diode voltage divider feedback circuit composed of PMOS transistors M3~M10, which is used to maintain the output voltage in standby mode. An ultra-low power voltage reference source is used to provide the reference voltage VREF for comparator COM2 and the bias voltage VBIAS for current-starved oscillators.

[0026] The fast-switching word line drive circuit applicable to a wide power supply voltage range, wherein the gated cross-coupled charge pump in the operating mode is equipped with an NMOS high-voltage switch controlled by control signals CP_ON_HV and CP_OFF_HV to transmit or block clock signals ACT_CLK and ACT_CLKB.

[0027] The fast switching word line driving circuit applicable to a wide power supply voltage range, wherein the fast switching pre-charge module generates pulse signals BUF and BUF_L with a pulse width of tens of ns that are triggered simultaneously with the rising edge of the ACT_EN signal by RC delay of the ACT_EN signal and then through logic gates and rectifier inverters, thereby controlling the buffer self-bias current and the on / off state of the transmission gate.

[0028] The aforementioned fast-switching word line drive circuit suitable for a wide power supply voltage range, wherein the bias current of the error amplifier EA and comparator COM1 in the operating mode is provided by a reference current source in the operating mode controlled by the enable signals ACT_EN and ACT_EN_L.

[0029] The fast-switching word line drive circuit suitable for a wide power supply voltage range is described above, wherein the bias current of comparator COM2 in standby mode is provided by a reference current source in standby mode controlled by enable signals STB_EN and STB_EN_L.

[0030] The aforementioned fast switching word line driving circuit suitable for a wide power supply voltage range, wherein in standby mode, PMOS devices M3~M10 are high-voltage PMOS devices with the same width-to-length ratio connected by diodes, and the MOS transistors operate in the subthreshold region with static power consumption in the nA level.

[0031] The aforementioned fast-switching word line driving circuit suitable for a wide power supply voltage range includes PMOS devices, NMOS devices, MOS devices, switching MOS transistors, and switching transistors, all of which are metal-oxide-semiconductor MOS transistors.

[0032] The aforementioned fast-switching word line driving circuit suitable for a wide power supply voltage range includes high-voltage PMOS devices, high-voltage NMOS devices, and high-voltage switching MOS transistors, all of which are laterally diffused metal-oxide-semiconductor MOS transistors.

[0033] The implementation method of the entire word line driving circuit is described below: When the word line driver circuit receives a command to start, the circuit enters the working mode. The ACT_EN signal is high, and the power supply voltage detection module starts working. When the power supply voltage is higher than the rated voltage, the voltage is divided by resistors R3 and R4 and then passed through comparator COM1 with the reference voltage VREF to generate CP_OFF ​​(high) and CP_ON (low). After passing through level shifting circuit 1, the two signals are converted to CP_OFF_HV and CP_ON_HV, thereby turning off the gated cross-coupled charge pump. The level transmission circuit is controlled by the signal CP_ON_HV and is turned on, pulling the output of the first three stages of cross-coupled charge pumps to Vwl. Conversely, when the power supply voltage is lower than the rated voltage, CP_OFF ​​is low and CP_ON is high, the gated cross-coupled charge pump will turn on, and all four stages of charge pumps will work simultaneously to generate the output voltage Vwl. Meanwhile, since normal fluctuations in the power supply voltage are also a form of noise, comparator COM1 uses a hysteresis comparator to ensure the circuit has good noise margin. Finally, the output voltage Vwl is regulated by a dynamic frequency modulation system to stabilize the high voltage generated by the charge pump at Vwl = VREF * (R1+R2) / R2.

[0034] After the operating mode ends, the circuit enters standby mode. The operating enable signal ACT_EN goes low, and the standby enable signal STB_EN goes high. In standby mode, the DICKSON charge pump starts working, and after being regulated by the SKIP modulation regulator circuit, it continues to charge the output voltage node, keeping the output voltage close to the voltage required for read operations. It is worth noting that, because standby mode must maintain low power consumption, the ultra-low power reference voltage source, the current-starved oscillator, the MOSFET in comparator COM2, and the diode dividers M3~M10 all operate in the subthreshold region.

[0035] After a period of standby mode, the system receives a command to operate and resumes from standby mode to operating mode. At this time, the operating mode enable signal ACT_EN returns to a high level, while the standby mode enable signal STB_EN goes low. Since NOR Flash requires a random read time in the nanosecond range (ns), the oscillator in operating mode can achieve the stable and precise output voltage required for read operations within a few cycles of the ACT_EN signal switching to high level. In standby mode, the ACT_EN_LHV signal is raised to Vwl after passing through level shifter 2, causing MOSFET M1 to turn off and the resistor divider point VFB_ACT to discharge to ground. Once operating mode is entered, VFB_ACT needs to be recharged to VREF voltage to ensure the feedback loop reaches a stable state. When the system returns to operating mode from standby mode, the error amplifier will detect a high error input (stable reference voltage and ground voltage). This will cause the voltage-controlled oscillator to generate an excessively high frequency to charge the charge pump, resulting in spurious transients in the output word line voltage Vwl, which will inevitably reduce access time.

[0036] To address this issue, this invention incorporates a fast-switching pre-charge module for the instantaneous transition from standby mode to operating mode. Specifically, the ACT_EN signal is RC-delayed and then passed through logic gates and a rectifier-inverter to generate pulse signals BUF and BUF_L, triggered simultaneously with the rising edge of the ACT_EN signal, with delays of tens of nanoseconds. These pulse signals control the buffer's self-bias current and the switching on / off state of the transmission gate. Upon entering operating mode, the buffer and transmission gate force point VFB_ACT to charge to the reference voltage VREF, allowing the loop to stabilize rapidly. The output node can output a precise voltage value within a few clock cycles without incurring excessive switching power consumption, meeting nanosecond-level access times. After loop stabilization, the BUF signal shuts off the buffer and transmission gate, stopping the charging of point VFB_ACT.

[0037] As attached Figure 2The diagram shows a gated cross-coupled charge pump in the power stage of the charge pump in the word line drive circuit of this invention during operation. The cross-coupled charge pump was chosen because, compared to other types of charge pumps, it has advantages such as simple structure, low output voltage ripple, and the port voltages of each switch not exceeding the power supply voltage VDD, making it suitable for low-voltage processes. The NMOS devices MN1 and MN2 and the PMOS devices MP1 and MP2 alternately conduct under the drive of two inverted clock signals to charge the pump capacitors C1 and C2, thereby raising the output voltage Vout. The addition of PMOS devices MP10 and MP20 ensures that the substrate potential of MP1 and MP2 remains high, thus suppressing reverse leakage current and improving pump efficiency. Since the charge pump cannot perform boost operation if the clock signal cannot be input to the capacitor, NMOS high-voltage switches MN3 and MN5, whose gate voltage is controlled by the signal CP_ON_HV, and high-voltage switches MN4 and MN6, whose gate voltage is controlled by the signal CP_OFF_HV, are added to the original charge pump at the clock signals CLK and CLKB. In this way, the power supply voltage detection module realizes the control of the on / off of this gated cross-coupled charge pump.

[0038] As attached Figure 3 The diagram shows a comparison of overshoot voltage between a traditional word line driving circuit and the improved driving circuit of this invention under different power supply voltages. It can be observed that the overshoot voltage is significantly improved across the entire power supply voltage range, especially when the power supply voltage is greater than 1.8V. This is because the gated cross-coupled charge pump is turned off when the power supply voltage input is above 1.8V, so only the first three stages of the charge pump are working, thus optimizing the output voltage overshoot.

[0039] As attached Figure 4 The diagram shows a comparison of the output voltage ripple of a traditional word line driving circuit and the improved driving circuit of this invention under different power supply voltages. For a charge pump driven load circuit, voltage ripple is a form of noise. Excessive voltage ripple can cause the load circuit to malfunction. For Flash memory, it can affect the erasure and programming of memory cells, causing the threshold voltage to deviate from the expected value and resulting in data read errors. For the purely capacitive load in this invention, the ripple originates from the ripple caused by the charging and discharging of the unregulated charge pump and the ripple at the output of the charge pump caused by changes in the error amplifier output. Therefore, the formula for the ripple can be expressed as: (1); Where Vr is the voltage ripple. This is the output current of the charge pump. The current consumed by the load. For the delay of the charge pump, Let be the load capacitance. Since this invention is for a purely capacitive load, only the resistive voltage division will bring a small current, which is much smaller than the charging current of the charge pump and can be ignored. Therefore, the above formula can be approximated as: (2); According to the model of the charge pump (3); in It is the output resistance of the charge pump. Substituting equation (3) into equation (2) yields... (4); As can be seen, the ripple voltage is directly proportional to the difference between the maximum value and the stable voltage value of the charge pump output voltage. Therefore, optimizing the overshoot voltage is also optimizing the voltage ripple. Figure 4 As can be seen, compared with the traditional structure, the improved structure in this invention optimizes the voltage ripple under different power supply voltages.

[0040] As attached Figure 5 The diagram shows the Spectre simulation results of the character line driving circuit in this invention during the transition from standby mode to operating mode. When the operating mode enable signal ACT_EN randomly triggers and goes high, the standby mode ends, and the system enters the operating mode. This invention generates a BUF signal pulse (approximately 10ns low level) triggered simultaneously with the rising edge of the ACT_EN signal through RC delay and logic gates. This pulse controls the buffer and transmission gate, ensuring that at the instant of entering the operating mode, the forced resistor voltage divider sampling point VFB_ACT is charged to the reference voltage VREF. The output VOUT_EA of the error amplifier can also quickly switch to control the frequency of the voltage-controlled oscillator, thus enabling the loop to stabilize rapidly. The output voltage stabilizes to the precise voltage value VOUT within a few cycles of the clock signal ACT_CLK. After the output voltage stabilizes, the BUF signal goes high, turning off the buffer and transmission gate, and stopping the charging of the sampling point VFB_ACT. As we can see from the figure, it takes about 12ns from the signal ACT_EN rising to a high level to the output voltage stabilizing. This results in almost no loss of access time and no spurious transients or power loss caused by switching, fully meeting the requirements of fast random reads of NOR Flash.

[0041] The embodiments described above can be further combined or replaced, and these embodiments are merely descriptions of preferred embodiments of the present invention, not limitations on the concept and scope of the present invention. Various changes and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the inventive concept are all within the protection scope of the present invention. The protection scope of the present invention is given by the appended claims and any equivalents.

Claims

1. A fast-switching word line driving circuit suitable for a wide power supply voltage range, characterized in that, It includes two modes: working mode and standby mode; The circuit in the aforementioned operating mode includes: a working mode charge pump power stage, a dynamic frequency modulation voltage regulator circuit, a power supply voltage detection module, a fast switching precharge module, an ultra-low power voltage reference source, a level shift circuit 1, a level shift circuit 2, a level transmission circuit, and a PMOS high-voltage device M1. The operating mode charge pump power stage includes a three-stage cross-coupled charge pump and a single-stage gated cross-coupled charge pump for generating high voltage. The dynamic frequency modulation voltage regulator circuit includes, in sequence, a voltage-controlled oscillator, a non-overlapping clock generation circuit module, an error amplifier EA, and resistor dividers R1 and R2, used to output the high voltage generated by the charge pump stably and with low ripple under all PVT conditions; the resistor dividers R1 and R2 are connected in series between the word line voltage Vwl node and ground, the intermediate node between R1 and R2 is the sampling point VFB_ACT, the sampling point VFB_ACT is connected to one input terminal of the error amplifier EA, the other input terminal of the error amplifier EA is connected to the output terminal reference voltage VREF of the ultra-low power voltage reference source, and the output terminal of the error amplifier EA is connected to the voltage-controlled oscillator; The power supply voltage detection module includes, in sequence, resistor dividers R3 and R4, comparator COM1, a two-stage rectifier-inverter, and an NMOS device M2. One end of resistor R3 is connected to the input power supply voltage VDD, and the other end of resistor R3 is connected to one end of resistor R4. The other end of resistor R4 is grounded. The common terminal of resistors R3 and R4 is connected to the first input terminal of comparator COM1. The second input terminal of comparator COM1 is connected to the reference voltage VREF. The output terminal of comparator COM1 generates signals CP_ON and CP_OFF ​​through the two-stage rectifier-inverter. The gate of the NMOS device M2 is connected to the enable signal ACT_EN, and the source is grounded. The fast-switching precharge module includes a transmission gate, a buffer, an RC delay circuit, three inverters, and a NAND gate. It is used to precharge the sampling point VFB_ACT to the reference voltage VREF the instant the system returns to operating mode from standby mode. The input of the RC delay circuit is connected to the enable signal ACT_EN. The output of the RC delay circuit, after being processed by the three inverters and NAND gates, generates pulse signals BUF and BUF_L, which are triggered simultaneously with the rising edge of the ACT_EN signal. The pulse signals BUF and BUF_L control the on / off state of the transmission gate and the buffer, respectively. The input of the transmission gate is connected to the reference voltage VREF, and the output of the transmission gate is connected to the sampling point VFB_ACT. An ultra-low power voltage reference source provides the reference voltage VREF for the error amplifier EA and comparator COM1; The level shifting circuit 1 has its input terminals connected to the signals CP_ON and CP_OFF ​​generated by the power supply voltage detection module, and its output terminals generate high-level voltage signals CP_ON_HV and CP_ON_LHV, which are the word line voltage Vwl, to control the on / off state of the gated cross-coupled charge pump and the level transmission circuit. The level shifting circuit 2 has an input terminal connected to the enable signals ACT_EN and ACT_EN_L, and an output terminal that generates high-level voltage signals ACT_EN_HV and ACT_EN_LHV, which are the word line voltage Vwl. The ACT_EN_LHV signal is connected to the gate of the PMOS high-voltage device M1. The level transmission circuit, controlled by the signal CP_ON_HV, is used to transmit the output voltage of the first three cross-coupled charge pumps to the word line voltage Vwl node. The PMOS high-voltage device M1, as a switching transistor, is controlled by the signal ACT_EN_LHV and is used to switch the current in the branch of resistors R1 and R2. The circuit in standby mode includes: a standby mode charge pump power stage, a SKIP modulation voltage regulator circuit, and an ultra-low power voltage reference source; Standby mode charge pump power stages, including DICKSON charge pumps, are used to generate high voltages; The SKIP modulation voltage regulator circuit includes, in sequence, a current-starved oscillator, a non-overlapping clock generation circuit, a comparator COM2, a down counter, a rectifier inverter, a NOR gate, and a diode voltage divider feedback circuit composed of PMOS transistors M3~M10, which is used to maintain the output voltage in standby mode. An ultra-low power voltage reference source is used to provide the reference voltage VREF for comparator COM2 and the bias voltage VBIAS for current-starved oscillators.

2. The fast-switching word line driving circuit suitable for a wide power supply voltage range as described in claim 1, characterized in that: The gated cross-coupled charge pump in the aforementioned operating mode is equipped with an NMOS high-voltage switch controlled by control signals CP_ON_HV and CP_OFF_HV to transmit or block clock signals ACT_CLK and ACT_CLKB.

3. The fast-switching word line driving circuit suitable for a wide power supply voltage range as described in claim 1, characterized in that: The fast switching precharge module generates pulse signals BUF and BUF_L with a pulse width of tens of ns, which are triggered simultaneously with the rising edge of the ACT_EN signal by RC delay and then through logic gates and rectifier inverters. These pulse signals are used to control the buffer self-bias current and the on / off state of the transmission gate.

4. The fast-switching word line driving circuit suitable for a wide power supply voltage range as described in claim 1, characterized in that: In the aforementioned operating mode, the bias current of the error amplifier EA and comparator COM1 is provided by the reference current source in the operating mode, which is controlled by the enable signals ACT_EN and ACT_EN_L.

5. A fast-switching word line driving circuit suitable for a wide power supply voltage range as described in claim 1, characterized in that: The bias current of comparator COM2 in standby mode is provided by a reference current source in standby mode controlled by enable signals STB_EN and STB_EN_L.

6. The fast-switching word line driving circuit suitable for a wide power supply voltage range as described in claim 1, characterized in that: In the standby mode, the PMOS devices M3~M10 are high-voltage PMOS devices with the same width-to-length ratio connected by diodes, and the MOS transistors operate in the subthreshold region with static power consumption in the nA range.

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