Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The fabrication method includes providing a substrate having an array region and a peripheral region; forming an initial material layer covering the substrate; removing a portion of the initial material layer on the array region to form a bit line structure in the array region, and forming a memory node contact structure between adjacent bit line structures; and removing the initial material layer on the peripheral region to form a gate structure in the peripheral region. This disclosure first forms the bit line structure and memory node contact structure on the array region, and then forms the gate structure on the peripheral region. This avoids damage to the gate structure caused by multiple thermal processing steps during the formation of the bit line structure and memory node contact structure, improving the yield of the gate structure and thus improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) typically consists of an array region and a peripheral region. The array region is used to set up multiple memory cells and data lines (e.g., bit line structures and word line structures). The peripheral region contains logic circuitry, which is electrically connected to the data lines in the array region to enable the storage and retrieval of data.

[0003] However, the fabrication of devices within the array region can damage the logic circuitry in the peripheral region, reducing the yield of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a semiconductor structure and a method for fabricating the same, which is used to improve the yield of semiconductor structures.

[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0006] Provide a substrate with an array region and a peripheral region;

[0007] Form an initial material layer covering the substrate;

[0008] A portion of the initial material layer located on the array region is removed to form a bit line structure in the array region, and a memory node contact structure is formed between adjacent bit line structures;

[0009] The initial material layer located on the peripheral region is removed to form a gate structure in the peripheral region.

[0010] In some embodiments, a substrate having an array region and a peripheral region is provided, comprising: forming a plurality of spaced-apart active regions in the substrate, and forming an initial contact structure above the active regions located in the array region.

[0011] In some embodiments, forming an initial material layer covering the substrate includes depositing an initial semiconductor layer, an initial conductive layer, and an initial insulating layer sequentially stacked over the substrate.

[0012] In some embodiments, the thickness of the initial insulating layer formed is 40 nm to 60 nm.

[0013] In some embodiments, forming the bit line structure includes: etching the initial material layer and initial contact structure located in the array region to form a plurality of bit lines and bit line contact structures arranged at intervals, wherein each bit line is connected to the active region through the bit line contact structure; wherein each bit line includes a first semiconductor layer, a first conductive layer and a first insulating layer stacked sequentially.

[0014] In some embodiments, forming the bit line structure further includes forming an isolation layer on the sidewall of each bit line.

[0015] In some embodiments, after the bit line structure is formed, a first heat treatment is performed, wherein the conditions for the first heat treatment are: annealing at 620°C to 680°C for 12 to 18 hours.

[0016] In some embodiments, forming the memory node contact structure includes: filling a dielectric layer in a region located between adjacent isolation layers, etching the dielectric layer to form a plurality of vias arranged in an array, each via exposing the surface of the active region, and filling the vias with semiconductor material to form the memory node contact structure.

[0017] In some embodiments, forming the gate structure includes: forming a mask layer covering the substrate located in the array region and the peripheral region; patterning the mask layer located in the peripheral region; and forming a gate stack above the active region in the peripheral region, the gate stack including a second semiconductor layer, a second conductive layer and a second insulating layer sequentially stacked.

[0018] In some embodiments, forming the gate structure further includes: forming a first isolation structure on the sidewall of the gate stack and performing ion implantation on the first doped region of the active region.

[0019] In some embodiments, the method further includes: forming a second isolation structure covering the sidewall of the first isolation structure, and performing ion implantation on a second doped region of the active region.

[0020] In some embodiments, the ion doping concentration of the second doped region is greater than that of the first doped region.

[0021] In some embodiments, after the second doping treatment is completed, a second heat treatment is performed. The conditions for the second heat treatment are: heat treatment at 1250℃~1350℃ for 0.4h~0.6h; followed by annealing at 320℃~380℃ for 8h~12h.

[0022] In some embodiments, the method further includes: forming a capping layer on the substrate in the peripheral region, etching the capping layer to form a contact hole, the contact hole exposing the second doped region.

[0023] A second aspect of this disclosure provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure provided in the first aspect.

[0024] In the semiconductor structure and fabrication method provided in this disclosure, bit line structures and memory node contact structures are first formed on the array region, and then the gate structure is formed on the peripheral region. This avoids damage to the gate structure caused by multiple heat treatment processes during the formation of the bit line structures and memory node contact structures, improving the yield of the gate structure and thus improving the yield of the semiconductor structure.

[0025] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a semiconductor structure provided in related technologies;

[0028] Figure 2 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0029] Figure 3 A schematic diagram of the formation of an initial contact structure in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0030] Figure 4 This is a schematic diagram of the formation of an initial material layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0031] Figure 5 This is a schematic diagram of bit line formation in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0032] Figure 6A schematic diagram of the formation of bit line structures in the method for fabricating semiconductor structures provided in this embodiment of the disclosure;

[0033] Figure 7 This is a schematic diagram of the semiconductor material formation process in the method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0034] Figure 8 This is a schematic diagram of the formation of a memory node contact structure in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0035] Figure 9 This is a schematic diagram of the formation of a material layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0036] Figure 10 A schematic diagram of the formation of a mask layer in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0037] Figure 11 A schematic diagram of forming a gate stack in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0038] Figure 12 A schematic diagram of the formation of a first isolation structure in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0039] Figure 13 A schematic diagram of the formation of the first doped region in the method for fabricating a semiconductor structure provided in this embodiment of the present disclosure;

[0040] Figure 14 In the method for fabricating the semiconductor structure provided in this embodiment, a second isolation structure is formed;

[0041] Figure 15 This is a schematic diagram of the formation of a second doped region in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0042] Figure 16 This is a schematic diagram of forming contact holes in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0043] Figure label:

[0044] 10: Source region; 20: Drain region;

[0045] 100: Substrate; 110: Active region; 111: Channel region; 112: First doped region; 113: Second doped region; 120: Shallow trench isolation structure; 130: Array region; 140: Peripheral region;

[0046] 200: Bit line contact structure; 210: Initial contact structure;

[0047] 300: Initial material layer; 310: Initial semiconductor layer; 320: Initial conductive layer; 330: Initial insulating layer;

[0048] 400: Bit line structure; 410: Bit line; 411: First semiconductor layer; 412: First conductive layer; 413: First insulating layer; 420: Isolation layer; 421: First isolation layer; 422: Second isolation layer; 423: Third isolation layer;

[0049] 500: Dielectric layer; 510: Through-hole; 520: Filled area;

[0050] 600: Memory node contact structure; 610: Semiconductor material;

[0051] 700: Mask layer; 710: Spin-coated hard mask layer; 720: Anti-reflective layer;

[0052] 800: Gate structure; 810: Gate stack; 820: First isolation structure; 830: Second isolation structure;

[0053] 900: Cover layer; 910: Contact hole. Detailed Implementation

[0054] When fabricating devices located within an array region, damage to transistors in the peripheral region is often caused. The inventors discovered that this problem arises because certain processes in semiconductor structure fabrication are shared. For example, the film layer used to fabricate bit line contact structures and bit lines within the array region can be the same as the film layer for the gate structure of logic transistors in the peripheral region. Furthermore, the process in related technologies typically involves: first forming an initial material layer that simultaneously covers both the array region and the peripheral region; then, using a mask layer to shield the array region, etching the initial material layer on the peripheral region to form the gate structure of the transistor; next, ion-doping the active region within the peripheral region to form the source and drain regions; finally, etching the initial material layer on the array region again to form the bit line contact structure and bit lines. However, the formation of the bit line contact structure and bit lines involves multiple heat treatment processes, which can damage the source / drain regions or channel regions of the transistors in the peripheral region, causing thermal interference, for example, as... Figure 1 As shown, the dopant ions in the source region 10 and drain region 20 of the transistor in the peripheral region undergo thermal diffusion, causing the dopant ions in the source region 10 and drain region 20 to diffuse into the substrate, reducing the yield of the semiconductor structure.

[0055] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and its fabrication method. By first forming a bit line structure and a memory node contact structure on the array region, and then forming a gate structure on the peripheral region, damage to the gate structure caused by multiple heat treatment processes during the formation of the bit line structure and memory node contact structure can be reduced or even avoided, improving the yield of the gate structure and thus improving the yield of the semiconductor structure.

[0056] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0057] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0058] Please refer to the attached document. Figure 2 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0059] Step S100: Provide a substrate with an array region and a peripheral region.

[0060] Please refer to the attached document. Figure 3 The substrate 100 is used to support the semiconductor device disposed thereon. The substrate 100 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0061] In this design, a plurality of active regions 110 are formed in a spaced-apart manner in the substrate 100. Shallow trench isolation (STI) structures 120 can be provided between the multiple active regions 110 to separate them and ensure that each active region 110 is independent of the others. For example, shallow trenches are formed in the substrate using a patterning process, and insulating material is filled into the shallow trenches, thereby defining multiple active regions 110 separated by the shallow trench isolation structures 120 on the substrate. The patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process. The insulating material can include silicon oxide, but is not limited to this.

[0062] The substrate 100 has an array region 130 and a peripheral region 140. The array region 130 is used to arrange multiple memory cells and data lines (e.g., bit line structures and word line structures). The peripheral region 140 contains logic circuitry that is electrically connected to the data lines in the array region 130 to store or retrieve data. Each memory cell includes a transistor and a capacitor connected to the transistor; the capacitor stores data.

[0063] It should be noted that both array region 130 and peripheral region 140 have active regions 110, but the number and size of the active regions 110 differ between the array region 130 and peripheral region 140. Furthermore, array region 130 and peripheral region 140 are located on the same substrate 100. To simplify the accompanying drawings, only a portion of the array region and a portion of the peripheral region are shown in each figure in this embodiment; the structures between the two wavy lines are not shown.

[0064] After the active region 110 is formed, an initial contact structure 210 is formed above the active region 110 located in the array region 130. Exemplarily, the active region 110 located in the array region 130 is graphically represented to form a bit line contact region within the active region 110 of the array region 130. The bottom of this bit line contact region is located within the substrate 100. This bit line contact region is used to form a bit line contact structure (BLC) to achieve electrical connection between the subsequently formed bit line structure and the active region 110. It should be understood that multiple bit line contact regions are arranged in an array, and the same bit line structure is used to connect bit line contact regions located in the same row or column.

[0065] An initial contact structure 210 is deposited on a substrate 100 using a deposition process, filling the entire bit line contact area. The initial contact structure 210 may be made of polysilicon, but is not limited to this.

[0066] An initial contact structure 210 is formed in the bit line contact area using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The initial contact structure 210 extends beyond the bit line contact area and covers the upper surface of the substrate 100.

[0067] In this embodiment, the initial contact structure is simultaneously etched during the subsequent etching of the various film layers used to form the bit line structure to form the bit line contact structure 200 (see Appendix). Figure 5 The bit line contact structure 200 is partially located within the substrate 100 to increase the sensitivity of the electrical connection between the bit line contact structure 200 and the active region 110, thereby improving the sensitivity of the electrical connection between the bit line structure and the active region 110 and enhancing the performance of the semiconductor structure.

[0068] It should be noted that the initial contact structure 210 in this embodiment also covers the substrate 100 located in the peripheral region 140, which will be used as part of the gate structure in the subsequent etching process.

[0069] Step S200: Form an initial material layer covering the substrate.

[0070] Please continue to refer to the appendix. Figure 3 and attached Figure 4 An initial material layer 300 is formed using a deposition process. The initial material layer 300 covers the substrate 100, that is, the initial material layer 300 covers the initial contact structure 210. It should be noted that in this step, the initial material layer 300 covers not only the substrate 100 located in the array region 130, but also the substrate 100 located in the peripheral region 140.

[0071] The initial material layer 300 is a material layer used to form the bit line structure and the gate structure. For example, an initial semiconductor layer 310, an initial conductive layer 320 and an initial insulating layer 330 are deposited sequentially on the substrate 100.

[0072] An initial semiconductor layer 310 is disposed on the initial contact structure 210. The initial semiconductor layer 310 is made of titanium nitride. The initial semiconductor layer 310 has both conductive and barrier properties. For example, titanium nitride can prevent the conductive material in the initial conductive layer 320 from penetrating between itself and the substrate 100, thus ensuring the conductivity of the subsequently formed bit line structure and gate structure.

[0073] An initial conductive layer 320 is disposed on the initial semiconductor layer 310. The initial conductive layer 320 is made of tungsten or polysilicon. Tungsten and polysilicon have strong conductivity, which can ensure the conductivity of the subsequently formed bit line structure and gate structure.

[0074] An initial insulating layer 330 is disposed on the initial conductive layer 320. Specifically, the initial insulating layer 330 is formed on the initial conductive layer 320 using a deposition process at 700°C-800°C. The deposition time for the initial insulating layer 330 is approximately 12 hours. The initial insulating layer 330 serves to electrically insulate the initial conductive layer 320 from other semiconductor devices subsequently disposed on the initial insulating layer 330. The material of the initial insulating layer 330 includes silicon nitride, but is not limited to this.

[0075] The initial insulating layer 330 has a thickness of 40 nm to 60 nm. Since a portion of the initial insulating layer 330 is used to form the first insulating layer of the bit line structure, the thickness of the subsequently formed first insulating layer is also between 40 nm and 60 nm. Compared to the thickness of the first insulating layer in related technologies, which is between 110 nm and 120 nm, the thickness of the first insulating layer is significantly reduced. This greatly reduces the aspect ratio of the subsequently formed bit line structure, prevents the formed bit line structure from having necking or tilting defects, improves the yield of the bit line structure, and thus improves the yield of the semiconductor structure.

[0076] Furthermore, reducing the thickness of the initial material layer 300 can decrease the requirement for bit line etching capabilities, which helps to further reduce the size of the semiconductor structure. It also facilitates the subsequent fabrication of memory node contact structures, reducing the difficulty of fabricating them.

[0077] Step S300: Remove part of the initial material layer located on the array region to form a bit line structure in the array region and form a memory node contact structure between adjacent bit line structures.

[0078] For example, a photoresist layer (not shown) can be formed on the initial material layer 300, and the photoresist layer located on the array region 130 can be patterned to form a plurality of openings within the photoresist layer located on the array region 130. The plurality of openings are spaced apart along a first direction, and each opening extends along a second direction, wherein the first direction and the second direction intersect. The first direction can be an adjacent... Figure 5 In the X direction, the second direction can be the appended direction. Figure 5 in the Y direction.

[0079] Using an etching solution or etching gas, the initial material layer 300 and initial contact structure 210 exposed in the opening are removed to form multiple bit lines 410 and bit line contact structures 200 arranged at intervals in the array region 130. Each bit line 410 is connected to the active region 110 through the bit line contact structure 200.

[0080] Each bit line 410 includes a first semiconductor layer 411, a first conductive layer 412, and a first insulating layer 413 stacked sequentially. In other words, in the array region 130, the retained initial semiconductor layer 310 constitutes the first semiconductor layer 411. The retained initial conductive layer 320 constitutes the first conductive layer 412. The retained initial insulating layer 330 constitutes the first insulating layer 413. The retained initial contact structure 210 constitutes the bit line contact structure 200.

[0081] Next, please refer to the appendix. Figure 6 An isolation layer 420 is formed on the sidewall of each bit line 410, covering the sidewall of each bit line 410 in a first direction to achieve mutual insulation between adjacent bit lines 410. The isolation layer 420 includes a first isolation layer 421, a second isolation layer 422, and a third isolation layer 423 stacked sequentially. The first isolation layer 421 is disposed on the sidewall of the bit line 410. The first isolation layer 421 and the third isolation layer 423 are made of the same material. For example, the first isolation layer 421 and the third isolation layer 423 are both made of silicon nitride, but are not limited to this. The second isolation layer 422 is made of silicon oxide, but is not limited to this.

[0082] The deposition temperature for the isolation layer 420 is 650℃-750℃, and the deposition time is 7.5h-8.5h.

[0083] After the bitline structure 400 is formed, it needs to undergo a first heat treatment. For example, the bitline structure 400 is annealed at 620°C to 680°C for 12 to 18 hours. This setting can increase the performance stability of the bitline structure 400.

[0084] Please continue to refer to the appendix. Figure 6 A dielectric layer 500 is filled in the region between adjacent isolation layers 420. The dielectric layer 500 is etched along a direction perpendicular to the substrate 100 to form a plurality of vias 510 arranged in an array, each via 510 exposing the surface of the active region 110.

[0085] A semiconductor material 610 is filled into the via 510 using a deposition process to form a memory node contact structure 600. The semiconductor material 610 includes polycrystalline silicon.

[0086] For example, please refer to the appendix. Figure 7 and attached Figure 8 A semiconductor material 610 is deposited within the via 510 using a deposition process. The semiconductor material 610 fills the via 510 and covers the top surface of the bit line structure 400, extending above it. The semiconductor material is then etched back, retaining a portion of the semiconductor material within the via 510 to form the memory node contact structure 600. The top surface of the memory node contact structure 600 is lower than the top surface of the bit line structure 400.

[0087] In this embodiment, the bottom of the via 510 can also be located within the substrate 100. This increases the area of ​​the active region 110 exposed by the via 510, thereby increasing the contact area between the storage node contact structure 600 and the active region, and thus improving the performance of the semiconductor structure.

[0088] Furthermore, the thickness of the first insulating layer formed in this embodiment is less than that of the first insulating layer in related technologies. This results in a smaller aspect ratio for the bit line structure 400, ensuring that the vias 510 formed between adjacent bit line structures 400 also have a smaller aspect ratio. This reduces the difficulty of depositing semiconductor material 610 into the vias 510, reduces or even avoids the formation of voids in the bottom of the vias 510, thereby preventing voids in the memory node contact structure 600, reducing the resistance of the memory node contact structure 600, and also reducing or even avoiding the formation of high-temperature defects and hot spots in subsequent high-temperature processes, thus improving the conductivity of the memory node contact structure 600.

[0089] It should be noted that, in this embodiment, semiconductor materials can be deposited at 650℃-750℃ to improve the compactness of the memory node contact structure 600.

[0090] While removing the semiconductor material 610 located on the array region 130, the semiconductor material located on the peripheral region 140 is also removed until the top surface of the initial insulating layer 330 on the peripheral region 140 is exposed.

[0091] Please refer to the attached document. Figure 9 After forming the memory node contact structure 600, a portion of the thickness of the bit line structure 400 is removed to reduce the thickness of the final bit line structure 400, thereby reducing the size of the semiconductor structure and facilitating the development of semiconductor structures towards miniaturization and integration.

[0092] A filling region 520 is formed between the storage node contact structure 600 and the dielectric layer 500. An atomic layer deposition process is used to form a material layer 530 on the sidewalls of the filling region 520 to prevent damage to the storage node contact structure 600 during subsequent formation of a mask layer or other films, thereby improving the performance of the storage node contact structure 600. It should be noted that the material layer 530 also covers the film layer located in the peripheral region 140. The material of the material layer 530 includes silicon nitride, but is not limited to this.

[0093] Step S400: Remove the initial material layer located on the peripheral region to form a gate structure in the peripheral region.

[0094] For example, please refer to the appendix. Figure 10 A mask layer 700 is formed, which covers the substrate 100 located in the array region 130 and the peripheral region 140.

[0095] The mask layer 700 can be a single film layer or a stacked structure. For example, the mask layer 700 includes a spin-on hard mask layer (SOH) 710 and an anti-reflective layer 720.

[0096] Please refer to the attached document. Figure 11 A photoresist layer 730 is formed on the anti-reflection layer 720. A mask layer 700 located in the peripheral region 140 is patterned. Using the patterned mask layer 700 as a mask, a portion of the initial material layer 300 located in the peripheral region 140 is removed to form a gate stack 810 above the active region 110 of the peripheral region 140. The gate stack 810 includes a second semiconductor layer 811, a second conductive layer 812, and a second insulating layer 813 sequentially stacked. In the peripheral region 140, the second semiconductor layer 811 is composed of the remaining initial semiconductor layer 310. The second conductive layer 812 is composed of the remaining initial conductive layer 320. The second insulating layer 813 is composed of the remaining initial insulating layer 330. It should be noted that the gate stack 810 may further include a gate oxide layer 814 located between the second semiconductor layer 811 and the substrate 100. The gate oxide layer 814 has a high dielectric constant, which reduces the leakage current between the gate stack 810 and the subsequently formed source and drain regions, thereby improving the performance of the semiconductor structure.

[0097] The anti-reflection layer 720 can alleviate or eliminate the standing wave effect of the photoresist layer 730, thereby increasing the accuracy of transferring the mask pattern from the mask to the photoresist layer 730, and thus improving the accuracy of the pattern transfer process.

[0098] After forming the gate stack 810, please refer to the appendix. Figure 12A first isolation structure 820 is formed on the sidewall of the gate stack 810. Exemplarily, a first initial isolation structure (not shown) is formed using a deposition process, covering the sidewalls and top surface of the gate stack 810, and the top surface of the exposed substrate 100. Subsequently, the first initial isolation structure is etched back to remove the first initial isolation structure located on the top surface of the gate stack 810 and the top surface of the exposed substrate 100, retaining the first initial isolation structure located on the sidewalls of the gate stack 810, thus forming the first isolation structure 820.

[0099] It should be noted that during the back etching of the first initial isolation structure, the first initial isolation structure located on the side of the gate stack 810 will also be etched, so that the side of the first isolation structure 820 facing away from the gate stack 810 is an arc-shaped surface.

[0100] Please refer to the attached document. Figure 13 The active region 110 includes a channel region 111. The projection region of the gate stack 810 onto the active region 110 is the channel region 111. The channel region 111 is capable of current flow, and the current flow in the channel region 111 is influenced by the gate stack 810. The doped ions in the channel region 111 are P-type ions to facilitate the formation of NMOS (N-Metal-Oxide-Semiconductor). The doped ions in the channel region 111 are also N-type ions to facilitate the formation of PMOS (P-Metal-Oxide-Semiconductor).

[0101] Please refer to the attached document. Figure 13 Ion implantation is performed on the first doped region of the active region 110. For example, ion implantation is performed on a portion of the region located on both sides of the channel region 111 using a plasma implantation process to form the first doped region 112. There are two first doped regions 112, each located on one side of the channel region 111.

[0102] During ion implantation, the implantation direction of the dopant ions can be perpendicular to the substrate 100 or at a certain angle to the plane of the substrate 100.

[0103] The type of dopant ions in the first doped region 112 differs from that in the channel region 111. In one example, the dopant ions in the channel region 111 are P-type ions, and correspondingly, the dopant ions in the first doped region 112 are N-type ions. In another example, the dopant ions in the channel region 111 are N-type ions, and correspondingly, the dopant ions in the first doped region 112 are P-type ions.

[0104] Please refer to the attached document. Figure 14 After completing the ion implantation process on the first doped region, the semiconductor structure fabrication method further includes: forming a second isolation structure 830, which covers the sidewalls of the first isolation structure 820. It should be noted that the formation process of the second isolation structure 830 is the same as that of the first isolation structure 820, and will not be described further in this embodiment.

[0105] The gate stack 810, together with a first isolation structure 820 and a second isolation structure 830 disposed on its sidewalls, constitutes a gate structure 800. The first isolation structure 820 and the second isolation structure 830 may be made of the same or different materials. For example, the first isolation structure 820 may be made of silicon oxide, and the second isolation structure 830 may be made of silicon nitride.

[0106] Please refer to the attached document. Figure 15 Ion implantation is performed on the second doped region 113 of the active region 110. Exemplarily, ion implantation is performed on a portion of the first doped region 112 located away from the channel region 111 using a plasma implantation process to form the second doped region 113. There are two second doped regions 113, each located on opposite sides of the first doped region 112. One of the two second doped regions serves as the source region, and the other as the drain region.

[0107] The doped ion type of the second doped region 113 is the same as that of the first doped region 112, except that the ion doping concentration of the second doped region 113 is greater than that of the first doped region 112. By setting a first doped region 112 with a lower ion doping concentration between the second doped region 113 and the channel region 111, this embodiment effectively weakens the electric field between the channel region 111 and the second doped region 113, improving the hot electron degradation phenomenon in both second doped regions. This reduces or even avoids leakage current problems caused by hot electron degradation between the second doped region 113 and the gate stack 810, ensuring transistor stability and thus improving the reliability of the semiconductor structure during operation.

[0108] After the second doping process, a second heat treatment is performed. The conditions for the second heat treatment are: heat treatment at 1250℃~1350℃ for 0.4h~0.6h, followed by annealing at 320℃~380℃ for 8h~12h. This setup can repair lattice defects caused by the ion implantation process and improve the performance of the semiconductor structure.

[0109] The semiconductor structure fabrication method provided in this disclosure involves first forming a bit line structure 400 and a memory node contact structure 600 on an array region 130, and then forming a gate structure 800 on a peripheral region 140. This avoids damage to the gate structure caused by multiple heat treatment processes during the formation of the bit line structure 400 and the memory node contact structure 600. Specifically, it reduces or even eliminates the thermal migration of dopant ions in the first doped region 112 and the second doped region 113 in the peripheral region 140, and fixes the dopant ions in the first doped region 112 and the second doped region 113 in the peripheral region 140, thereby improving the yield of the gate structure and ultimately improving the yield of the semiconductor structure.

[0110] In addition, in this embodiment, a bit line structure 400 is first formed on the array region 130. At this time, the thickness of the first insulating layer 413 in the bit line structure 400 is smaller than that of the bit line insulating layer in the related art, which greatly reduces the aspect ratio of the bit line structure formed subsequently, prevents the formed bit line structure from having necking or tilting defects, improves the yield of the bit line structure, and thus improves the yield of the semiconductor structure.

[0111] Please refer to the attached document. Figure 16 The method for fabricating the semiconductor structure further includes: forming a capping layer 900 on a substrate 100 in the peripheral region 140, etching the capping layer 900 to form a contact hole 910, and exposing a second doped region through the contact hole 910. The capping layer 900 may be made of silicon oxide, but is not limited to this.

[0112] After the contact hole is formed, a conductive plug can be formed in the contact hole 910 by a deposition process. The conductive plug is used to realize the electrical connection between the second doped region and the subsequently formed interconnect layer, so as to transmit external electrical signals to the second doped region.

[0113] In this embodiment, the conductive plug process is performed after the bit line structure 400 and memory node contact structure 600 located in the array region 130 and the gate structure 800 located in the peripheral region 140 are completed. Compared with related technologies, it is possible to avoid forming a silicon nitride layer of a certain thickness on the capping layer 900, thereby reducing the thickness of the patterned film layer required and improving the alignment accuracy of the pattern. That is, it is possible to improve the fabrication accuracy of the contact hole 910, which facilitates further reduction of the size of the semiconductor structure and increases the storage area of ​​the semiconductor structure.

[0114] And from the appendix Figure 16 and attached Figure 1The comparison clearly shows that the doped ions in the first doped region 112 and the second doped region 113 of the semiconductor structure provided in this disclosure can avoid thermal migration caused by heating, sintering and annealing during the fabrication process of the bit line structure and the memory node contact structure 600, thus fixing the doped ions in the first doped region 112 and the second doped region 113 and improving the performance of the semiconductor structure.

[0115] This disclosure also provides a semiconductor structure, which is prepared by the method described in the above embodiments. Therefore, the semiconductor structure possesses the functions and beneficial effects of any of the above embodiments, and will not be elaborated further here.

[0116] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0117] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0118] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, Includes the following steps: A substrate having an array region and a peripheral region is provided, wherein a plurality of active regions are formed in the substrate at intervals, and an initial contact structure is formed above the active regions located in the array region; Form an initial material layer covering the substrate; Forming an initial material layer covering the substrate includes: depositing an initial semiconductor layer, an initial conductive layer, and an initial insulating layer sequentially stacked on the substrate; A portion of the initial material layer located on the array region is removed to form a bit line structure in the array region, and a memory node contact structure is formed between adjacent bit line structures; The initial material layer located on the peripheral region is removed to form a gate structure in the peripheral region.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The thickness of the initial insulating layer formed is 40 nm to 60 nm.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The formation of the bit line structure includes: etching the initial material layer and initial contact structure located in the array region to form multiple bit lines and bit line contact structures arranged at intervals, wherein each bit line is connected to the active region through the bit line contact structure; wherein each bit line includes a first semiconductor layer, a first conductive layer and a first insulating layer stacked sequentially.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The formation of the bit line structure also includes forming an isolation layer on the sidewall of each bit line.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: After the bit line structure is formed, a first heat treatment is performed. The conditions for the first heat treatment are: annealing at 620℃~680℃ for 12h~18h.

6. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The method of forming the memory node contact structure includes: filling a dielectric layer in a region located between adjacent isolation layers, etching the dielectric layer to form a plurality of vias arranged in an array, each via exposing the surface of the active region, and filling the vias with semiconductor material to form the memory node contact structure.

7. The method of claim 5, wherein the semiconductor structure is formed by a method comprising: The formation of the gate structure includes: forming a mask layer covering the substrate located in the array region and the peripheral region; patterning the mask layer located in the peripheral region; and forming a gate stack above the active region in the peripheral region, the gate stack including a second semiconductor layer, a second conductive layer and a second insulating layer sequentially stacked.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The formation of the gate structure further includes: forming a first isolation structure on the sidewall of the gate stack, and performing ion implantation on the first doped region of the active region.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The method further includes: forming a second isolation structure, the second isolation structure covering the sidewall of the first isolation structure, and performing ion implantation on the second doped region of the active region.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: The ion doping concentration in the second doped region is greater than that in the first doped region.

11. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: After ion implantation into the second doped region of the active region, a second heat treatment is performed. The conditions for the second heat treatment are: heat treatment at 1250℃~1350℃ for 0.4h~0.6h; followed by annealing at 320℃~380℃ for 8h~12h.

12. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: The method further includes: forming a capping layer on the substrate in the peripheral region, etching the capping layer to form a contact hole, the contact hole exposing the second doped region.

13. A semiconductor structure, characterized by The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1-12.

Images