Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor storage device and a manufacturing method thereof include a first stack and a second stack stacked on a semiconductor substrate in a cell region of the semiconductor storage device and a slit region of the semiconductor storage device adjacent to the cell region. The semiconductor storage device further includes a plurality of cell plugs at least partially penetrating the second stack and the first stack and extending in a vertical direction in the cell region, a slit at least partially penetrating the second stack and the first stack in the slit region, and a protection pattern arranged between the slit and a dummy cell plug adjacent to the slit among the plurality of cell plugs.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more specifically, to a semiconductor memory device with a vertical channel structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices are generally classified into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are those in which stored data is lost when power is cut off. Volatile memory devices can include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are those in which stored data is retained even when power is cut off. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is generally classified into NOR and NAND types.

[0004] Recently, with the increasing use of portable electronic devices, the use of non-volatile semiconductor memory devices has also increased. To achieve portability and large capacity, high integration and large capacity of semiconductor memory devices are required. To achieve this high integration and large capacity, three-dimensional semiconductor memory devices have been proposed. Summary of the Invention

[0005] Embodiments of this disclosure relate to a semiconductor memory device and a method of manufacturing the same, which can improve operational reliability by mitigating bridging phenomena in gate patterns adjacent to slits.

[0006] According to an embodiment of this disclosure, a semiconductor memory device includes: a first stack and a second stack, the first stack and the second stack being stacked on a semiconductor substrate in a cell region of the semiconductor memory device and a slot region of the semiconductor memory device adjacent to the cell region. The semiconductor memory device further includes: a plurality of cell plugs, the plurality of cell plugs at least partially passing through the second stack and the first stack in the cell region and extending in a vertical direction; a slot, the slot at least partially passing through the second stack and the first stack in the slot region; and a protective pattern, the protective pattern being disposed between the slot and a dummy cell plug adjacent to the slot among the plurality of cell plugs.

[0007] According to embodiments of this disclosure, a method for manufacturing a semiconductor memory device includes: forming a first stack on a semiconductor substrate, wherein a first interlayer insulating layer and a first sacrificial layer are alternately stacked in the first stack, the semiconductor memory device including a slit region, a dummy cell region, and a normal cell region. The method further includes: removing the first stack from the dummy cell region by etching the first stack, and forming a protective pattern in the space where the first stack has been removed; forming a second stack over the entire structure including the first stack and the protective pattern, wherein a second interlayer insulating layer and a second sacrificial layer are alternately stacked in the second stack. The method further includes: forming a plurality of cell plugs at least partially penetrating the second stack and the first stack in the normal cell region, and forming at least one dummy cell plug penetrating the second stack and the protective pattern in the dummy cell region; and etching the second stack and the first stack in the slit region to form a slit.

[0008] According to embodiments of this disclosure, a method for manufacturing a semiconductor memory device includes: stacking and forming a first interlayer insulating layer, a first source layer, a source sacrificial structure, a third source layer, and a first stack on a semiconductor substrate, wherein a second interlayer insulating layer and a first sacrificial layer are alternately stacked in the first stack, and the semiconductor memory device includes a slot region, a dummy cell region, and a normal cell region. The method further includes: removing the first stack from the dummy cell region by etching the first stack, and forming a protective pattern in the space where the first stack has been removed; forming a second stack over the entire structure including the first stack and the protective pattern, wherein a third interlayer insulating layer and a second sacrificial layer are alternately stacked in the second stack. The method further includes: forming a plurality of cell plugs in the normal cell region that at least partially penetrate the second stack, the first stack, the third source layer, and the source sacrificial structure, and forming at least one dummy cell plug in the dummy cell region that penetrates the second stack, the protective pattern, the third source layer, and the source sacrificial structure. The method further includes etching the second stack, the first stack, and the third source layer in the slit region to form a slit through which the source sacrificial structure is exposed.

[0009] According to an embodiment of this technology, the stack used to form the gate pattern of the source selection transistor is removed by etching the stack adjacent to the slit region in the memory cell region, and a protective pattern is formed in the space where the stack has been removed. Therefore, because the gate pattern of the source selection transistor is not formed in the region adjacent to the slit, even if the lower part of the slit is bent and etched during the etching process used to form the slit, bridging of the gate pattern adjacent to the slit will not occur. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 The circuit diagram of the memory cell array.

[0012] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 4 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, showing a portion of the memory cell array of the semiconductor memory device.

[0014] Figures 5A to 5I These are cross-sectional and plan views of a semiconductor memory device according to embodiments of the present disclosure, illustrating a method for manufacturing the semiconductor memory device.

[0015] Figure 6 This is a block diagram illustrating the configuration of a storage system according to an embodiment of the present disclosure.

[0016] Figure 7 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure are described below. In the accompanying drawings, thickness and distance are shown for ease of description and may be exaggerated relative to actual physical thickness. In describing this disclosure, well-known configurations unrelated to the spirit of this disclosure may be omitted. It should be noted that when adding reference numerals to components in the various drawings, the same reference numerals are used where possible, even if the same component is shown in different drawings.

[0018] Throughout this specification, the phrase "connected" to another part includes not only direct connection but also indirect connection with another part where another element is inserted between them. Throughout this specification, the phrase "a part includes a component" means that the part may further include other components, without excluding them, unless otherwise specifically stated.

[0019] Figure 1 This is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0020] Reference Figure 1 The semiconductor memory device 10 includes peripheral circuitry PC and memory cell array 20.

[0021] The peripheral circuit PC can be configured to control programming operations for storing data in the memory cell array 20, reading operations for outputting data stored in the memory cell array 20, and erasing operations for erasing data stored in the memory cell array 20.

[0022] As an implementation, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0023] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 may be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0024] Control circuit 35 can control voltage generator 31, line decoder 33 and page buffer group 37 in response to command CMD and address ADD.

[0025] Voltage generator 31 can generate various operating voltages in response to the control of control circuit 35, such as erase voltage, ground voltage, programming voltage, verification voltage, pass voltage and read voltage for programming operation, read operation and erase operation.

[0026] The line decoder 33 can select a memory block in response to the control circuit 35. The line decoder 33 can be configured to apply an operating voltage to the word line WL connected to the selected memory block.

[0027] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. Page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations in response to control of control circuitry 35. Page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations in response to control of control circuitry 35. Page buffer group 37 can select bit line BL in response to control of control circuitry 35.

[0028] Structurally, the storage cell array 20 can overlap with a portion of the peripheral circuit PC.

[0029] Figure 2 It is shown Figure 1 The circuit diagram of the memory cell array 20.

[0030] Reference Figure 2 The memory cell array 20 may include multiple cell strings CS1 and CS2 connected between the source line SL and multiple bit lines BL. The multiple cell strings CS1 and CS2 may be connected together to multiple word lines WL1 to WLn.

[0031] Each of the multiple cell strings CS1 and CS2 may include: at least one source selection transistor SST connected to the source line SL; at least one drain selection transistor DST connected to the bit line BL; and multiple memory cells MC1 to MCn connected in series between the source selection transistor SST and the drain selection transistor DST.

[0032] The gates of multiple memory cells MC1 to MCn can be connected to multiple word lines WL1 to WLn that are spaced apart and stacked. The multiple word lines WL1 to WLn can be arranged between the source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same height.

[0033] The gate of the source-select transistor (SST) can be connected to the source-select line (SSL). The gate of the drain-select transistor (DST) can be connected to the drain-select line corresponding to the gate of the drain-select transistor (DST).

[0034] The source line SL can be connected to the source of the source select transistor SST. The drain of the drain select transistor DST can be connected to the bit line corresponding to the drain of the drain select transistor DST.

[0035] Multiple unit strings CS1 and CS2 can be divided into string groups connected to two or more drain select lines DSL1 and DSL2 respectively. Unit strings connected to the same word line and the same bit line can be independently controlled by different drain select lines. Furthermore, unit strings connected to the same drain select line can be independently controlled by different bit lines.

[0036] In one implementation, two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. Multiple unit strings CS1 and CS2 may include: a first unit string CS1 connected to a first string group of the first drain select line DSL1; and a second string CS2 connected to a second string group of the second drain select line DSL2.

[0037] Figure 3 This is a perspective view schematically showing a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0038] Reference Figure 3 The semiconductor memory device 10 may include: a peripheral circuit PC disposed on a substrate SUB; and a gate stack GST overlapping the peripheral circuit PC.

[0039] Each gate stack (GST) may include: a source select line SSL, multiple word lines WL1 to WLn; and two or more drain select lines DSL1 and DSL2 separated from each other at the same height by means of a second slit SI2.

[0040] The source select line SSL and multiple word lines WL1 to WLn can extend in a first direction X and a second direction Y, and can be formed into a flat plate shape parallel to the upper surface of the substrate SUB. The first direction X can be the direction pointed to by the X-axis of the XYZ coordinate system, and the second direction Y can be the direction pointed to by the Y-axis of the XYZ coordinate system. Figure 3 In this configuration, a source select line (SSL) is arranged in a gate stack (GST), but a gate stack (GST) may include at least one source select line (SSL) stacked on a third-direction Z.

[0041] Multiple word lines WL1 to WLn can be spaced apart from each other and stacked in the third direction Z. The third direction Z can be the direction pointed to by the Z-axis of the XYZ coordinate system. Multiple word lines WL1 to WLn can be arranged between two or more drain select lines DSL1 and DSL2 and source select line SSL.

[0042] The gate stacks GST can be separated from each other by means of a first slit SI1. A second slit SI2 can be formed on the third direction Z, shorter than the first slit SI1, and can overlap with multiple word lines WL1 to WLn.

[0043] Each of the first slit SI1 and the second slit SI2 can extend in a straight line, a zigzag shape, or a wavy shape. The width of each of the first slit SI1 and the second slit SI2 can vary depending on the design.

[0044] According to the implementation method, the source selection line SSL can be arranged closer to the peripheral circuit PC than two or more drain selection lines DSL1 and DSL2.

[0045] The semiconductor memory device 10 may include: a source line SL disposed between a gate stack GST and a peripheral circuit PC; and a plurality of bit lines BL spaced further apart than the source line SL and the peripheral circuit PC. The gate stack GST may be disposed between the plurality of bit lines BL and the source line SL.

[0046] Figure 4 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, showing a portion of the memory cell array of the semiconductor memory device.

[0047] Reference Figure 4 The semiconductor memory device may include a source layer SL, a first stack ST1, a second stack ST2, multiple cell plugs CP, multiple dummy cell plugs D_CP, and a first slit SI1.

[0048] The source layer SL can be disposed on the substrate SUB and can include a conductive material. For example, the source layer SL can be configured as a single layer or multiple layers. For example, the source layer SL can include polysilicon.

[0049] The substrate SUB can be a single-crystal semiconductor substrate. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method.

[0050] The first stack ST1 can be disposed on the source layer SL and can include a plurality of alternately stacked second interlayer insulating layers ILD2 and a plurality of first gate patterns GP1. The plurality of first gate patterns GP1 can be the gate electrodes of source-select transistors or source-select lines. The first gate patterns GP1 can include conductive materials such as polysilicon, tungsten, molybdenum, or metals. The plurality of second interlayer insulating layers ILD2 can be used to insulate the plurality of stacked first gate patterns GP1 from each other. The plurality of second interlayer insulating layers ILD2 can include insulating materials such as oxides, nitrides, or air gaps.

[0051] The second stack ST2 can be disposed on the first stack ST1 and can include alternating layers of multiple second gate patterns GP2 and third interlayer insulating layers ILD3. The multiple second gate patterns GP2 can be gate electrodes or word lines of memory cells, and can be gate electrodes or drain select lines of drain select transistors. The second gate patterns GP2 can include conductive materials such as polysilicon, tungsten, molybdenum, or metals. The multiple third interlayer insulating layers ILD3 can be used to insulate the multiple stacked second gate patterns GP2 from each other. The multiple third interlayer insulating layers ILD3 can include insulating materials such as oxides, nitrides, or air gaps.

[0052] Multiple cell plugs CP and multiple dummy cell plugs D_CP pass through the second stack ST2 and the first stack ST1 and extend into the source layer SL. The multiple cell plugs CP and multiple dummy cell plugs D_CP can be arranged between the first slit SI1 passing through the second stack ST2 and the first stack ST1. The multiple dummy cell plugs D_CP can be arranged relatively adjacent to the first slit SI1.

[0053] Each of the multiple cell plugs CP and multiple dummy cell plugs D_CP may include: a core insulating layer CO extending in a vertical direction; a channel layer CH surrounding the sidewalls and lower surface of the core insulating layer CO; and a storage layer ML surrounding the sidewalls and lower surface of the channel layer CH. The storage layer ML may expose a portion of the sidewalls of the channel layer CH in the source layer SL, so that a portion of the sidewalls of the channel layer CH may contact the source layer SL.

[0054] A protective pattern PTP is arranged between the first stack ST1 and the plurality of dummy cell plugs D_CP. Furthermore, the protective pattern PTP can be arranged in the regions defined between the first slit SI1 and the plurality of dummy cell plugs D_CP, and between the source layer SL and the second stack ST2. The protective pattern PTP can be arranged at the height of the first stack ST1 between the first slit SI1 and the plurality of dummy cell plugs D_CP.

[0055] In the etching process for forming the first stack ST1 and the second stack ST2 of the first slit SI1, due to the difference in pattern density, the lower part of the first slit SI1 may be bent and etched in the direction in which multiple dummy cell plugs D_CP are arranged. A protective pattern PTP can be arranged in the space where the first stack ST1 is removed, in the area where multiple dummy cell plugs D_CP are formed and the first stack ST1 is removed. Therefore, even if the lower part of the first slit SI1 is bent and etched, the protective pattern PTP can prevent abnormal etching of the multiple first gate patterns GP1. Thus, bridging caused by pattern defects in the multiple first gate patterns GP1 can be prevented in advance.

[0056] A first interlayer insulating layer ILD1, including an etch stop pattern EP, can be disposed between the substrate SUB and the source layer SL. The etch stop pattern EP can be disposed below multiple dummy cell plugs D_CP and can prevent... Figure 3 The peripheral circuit PC was damaged due to over-etching during the etching process used to form multiple dummy cell plugs D_CP.

[0057] Figures 5A to 5I These are cross-sectional and plan views of a semiconductor memory device according to embodiments of the present disclosure, illustrating a method for manufacturing the semiconductor memory device.

[0058] The manufacturing method described below is only a basis for manufacturing. Figure 4 One possible method for a semiconductor memory device, and according to Figure 4 The manufacturing methods for semiconductor memory devices are not limited to those described below.

[0059] Reference Figure 5A A first interlayer insulating layer 101 is formed on a semiconductor substrate 100, and a lower structure (not shown) is formed on the semiconductor substrate 100. The lower structure (not shown) may include a transistor, a resistor, a capacitor, and other components. Figure 3 Multiple wirings in the peripheral circuit PC.

[0060] For example, a first interlayer insulating layer 101 is formed on a semiconductor substrate 100 defined as a normal cell plug region NMC_R, a dummy cell plug region DMC_R, and a slit region SI_R. The first interlayer insulating layer 101 may be formed of an oxide layer. An etch stop pattern 103 may be formed in the first interlayer insulating layer 101. The etch stop pattern 103 may be arranged in the dummy cell plug region DMC_R.

[0061] The normal element plug region NMC_R can be arranged between two slit regions SI_R, and the dummy element plug region DMC_R can be arranged at the boundary between the normal element plug region NMC_R and one slit region SI_R. The normal element plug region NMC_R is formed Figure 4 The area of ​​the cell plug CP, the dummy cell plug area DMC_R is formed Figure 4 The dummy unit plugs the region of D_CP, and the slit region SI_R is formed Figure 4 The area of ​​the first slit SI1.

[0062] Subsequently, a first source layer 105, a source sacrificial structure 107, and a third source layer 109 may be sequentially stacked and formed on the first interlayer insulating layer 101. For example, the first source layer 105 and the third source layer 109 may comprise polysilicon. For example, the source sacrificial structure 107 may comprise an oxide or a high-k material.

[0063] Subsequently, a first stack ST1 is formed on the third source layer 109. The first stack ST1 may include alternating layers of a second interlayer insulating layer 111 and a first gate sacrificial layer 113.

[0064] For example, the second interlayer insulating layer 111 may include silicon oxide. The first gate sacrificial layer 113 may include a material with high etch selectivity relative to the second interlayer insulating layer 111. For example, the first gate sacrificial layer 113 may include silicon nitride.

[0065] Reference Figure 5B and Figure 5C A separation pattern 115 is formed to separate the gate pattern of the source select line to be formed subsequently. The separation pattern 115 can be formed in a line shape in the cell region MC_R and the thinning region SLIM_R.

[0066] For example, a trench exposing the third source layer 109 is formed by etching the first stack ST1 in the region separated between the cell region MC_R and the thinned region SLIM_R, where the gate pattern for the source select line is to be placed. Thereafter, a separation pattern 115 is formed by filling the trench with an insulating layer comprising oxide.

[0067] In the process of forming the aforementioned separation pattern 115, a protective pattern 117 can be formed together in the area where the dummy cell plug is to be formed. For example, the first laminate ST1 is etched to remove the first laminate formed in the area adjacent to the thinned area SLIM_R in the dummy cell plug area DMC_R of the cell area MC_R. Thereafter, the protective pattern 117 is formed by filling the space where the first laminate ST1 has been removed with an insulating layer including oxide.

[0068] The protective pattern 117 can be formed in the region of the dummy unit plug region DMC_R that is adjacent to the slit region SI_R and the thinning region SLIM_R, and a portion of the protective pattern 117 can overlap with the thinning region SLIM_R of the slit region SI_R.

[0069] Reference Figure 5D and Figure 5EThe second stack ST2 is formed on the entire structure including the first stack ST1, the separation pattern 115, and the protection pattern 117. The second stack ST2 may include an alternately stacked second gate sacrificial layer 121 and a third interlayer insulating layer 123. For example, the third interlayer insulating layer 123 may include silicon oxide. The second gate sacrificial layer 121 may include a material with high etch selectivity relative to the third interlayer insulating layer 123. For example, the second gate sacrificial layer 121 may include silicon nitride.

[0070] The second gate sacrificial layer 121 of the second stack ST2 may be formed of the same material as the first gate sacrificial layer 113 of the first stack ST1, and the third interlayer insulating layer 123 of the second stack ST2 may be formed of the same material as the second interlayer insulating layer 111 of the first stack ST1.

[0071] Subsequently, a channel hole H is formed for forming a unit plug that passes through the second stack ST2, the first stack ST1, the third source layer 109, and the source sacrificial structure 107.

[0072] In addition, a dummy hole DH is formed for forming a dummy unit plug that passes through the second stack ST2, the first stack ST1, the separation pattern 115, the third source layer 109 and the source sacrifice structure 107, as well as a dummy hole DH that passes through the second stack ST2, the protection pattern 117, the third source layer 109 and the source sacrifice structure 107.

[0073] Reference Figure 5F ,exist Figure 5E In the channel hole H used to form the unit plug and in Figure 5E The plug 137 is formed in the dummy hole DH used to form the dummy cell plug. For example, the plug 137 can be formed by sequentially stacking the storage layer 131, the channel layer 133 and the core insulation layer 135 on the sidewall of each of the channel hole H and the dummy hole DH.

[0074] Storage layer 131 may include a barrier insulating layer, a data storage layer, and a tunnel insulating layer. For example, storage layer 131 can be formed by sequentially stacking the barrier insulating layer, the data storage layer, and the tunnel insulating layer on the sidewalls of each of the vias and dummy vias. The barrier insulating layer may be formed on the sidewalls of each of the vias and dummy vias. The barrier insulating layer may include an oxide layer capable of blocking charge. As an embodiment, the barrier insulating layer may be formed of aluminum oxide (Al2O3). The data storage layer may be formed on the sidewalls of the barrier insulating layer. The data storage layer may be formed of a charge trapping layer, a material layer comprising conductive nanodots, or a phase change material layer. For example, the data storage layer may use the Fowler-Nordheim tunneling method to store changing data. For this purpose, the data storage layer may be formed of a silicon nitride layer capable of trapping charge. The tunnel insulating layer may be formed on the sidewalls of the data storage layer. The tunnel insulating layer may be formed of a silicon oxide layer capable of tunneling charge.

[0075] The channel layer 133 may be formed on the sidewall of the tunnel insulating layer. The channel layer 133 may include a semiconductor layer. As an embodiment, the channel layer 133 may include silicon.

[0076] The core insulation layer 135 can be formed by filling the central region of the channel holes and dummy holes. The core insulation layer 135 can be formed of an oxide layer.

[0077] The plug 137 that fills the channel hole can be defined as a unit plug, while the plug 137 that fills the dummy hole can be defined as a dummy plug.

[0078] The dummy plug may include: a plug 137 passing through the separation pattern 115; and a plug 137 passing through the protective pattern 117. Because the plug 137 is formed in... Figure 5E The density of the pattern in the cell region MC_R is higher than the density of the pattern in the thinned region SLIM_R.

[0079] Reference Figure 5G and Figure 5H A line-shaped slit SI can be formed by etching the second stack ST2, the first stack ST1, and the third source layer 109 formed on the slit region SI_R. Figure 5F The source electrode sacrificial structure 107 is exposed via this slit. During the process of forming the slit SI, due to... Figure 5E The density difference in the boundary between the cell region MC_R and the thinning region SLIM_R shown in the figure indicates that the lower part of the slit SI may be bent and etched in the direction of the cell region MC_R.

[0080] Subsequently, the area exposed by the slit SI was removed. Figure 5FThe source sacrifice structure 107. Therefore, the storage layer 131 can be exposed on the sidewall of the lower end of the plug 137, and the exposed storage layer 131 is etched to expose the channel layer 133 of the sidewall of the lower end of the plug 137.

[0081] Reference Figure 5I ,exist Figure 5F The space where the source sacrifice structure 107 is removed is filled with a second source layer 141. The second source layer 141 can contact the channel layer 133 of the sidewall at the lower end of the plug 137.

[0082] Subsequently, the area exposed by the slit SI was removed. Figure 5G The first gate sacrificial layer 113 and the second gate sacrificial layer 121 are formed, and a gate pattern 151 is formed in the created space.

[0083] In the gate pattern 151, the gate pattern 151 included in the first stack ST1, for example, the gate pattern 151 formed in the space between the second interlayer insulating layers 111, can be a gate pattern for a source-select transistor. Furthermore, in the gate pattern 151, the gate pattern 151 included in the second stack ST2, for example, the gate pattern 151 formed in the space between the third interlayer insulating layers 123, can be a gate pattern for a memory cell and a gate pattern for a drain-select transistor.

[0084] In the dummy cell plug region DMC_R adjacent to slit SI, at the boundary between the cell region MC_R and the thinned region SLM_R formed by bending during the gate patterning process described above, the first laminate ST1 is removed, and a protective pattern 117 is formed. Therefore, no gate pattern 151 is formed in the region adjacent to slit SI. Thus, even if the lower part of slit SI is bent, bridging due to gate pattern 151 will not occur.

[0085] According to the above embodiment, a dummy cell plug is formed in a dummy cell plug region, and a plurality of cell plugs are formed in a normal memory cell region. However, the dummy cell plug or the plurality of cell plugs may be formed at the boundary between the dummy cell plug region and the normal cell plug region. Furthermore, at least one of the plurality of cell plugs may be formed in the dummy cell plug region adjacent to the normal memory cell region.

[0086] Figure 6 This is a block diagram illustrating the configuration of a storage system 1100 according to an embodiment of the present disclosure.

[0087] Reference Figure 6 The storage system 1100 includes a semiconductor storage device 1120 and a storage controller 1110.

[0088] Semiconductor memory device 1120 can be with Figures 1 to 4 The semiconductor memory device shown is configured similarly.

[0089] The semiconductor storage device 1120 can be a multi-chip package configured with multiple flash memory chips.

[0090] The storage controller 1110 can be configured to control the semiconductor storage device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a storage interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the storage system 1100. Furthermore, the error correction block 1114 detects and corrects errors included in data read from the semiconductor storage device 1120, and the storage interface 1115 performs interfacing with the semiconductor storage device 1120. Additionally, the storage controller 1110 may further include a read-only memory (ROM) that stores code data for interfacing with the host.

[0091] Figure 7 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0092] Reference Figure 7 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a storage system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0093] The storage system 1210 may include a semiconductor storage device 1212 and a storage controller 1211. The semiconductor storage device 1212 may be configured to... Figures 1 to 4 The semiconductor memory device shown is the same.

[0094] Although the detailed description of this disclosure describes specific embodiments, various changes and modifications are possible without departing from the scope and spirit of this disclosure. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be determined by the equivalents of the claims of this disclosure and the appended claims.

[0095] Cross-reference to related applications

[0096] This application claims priority to Korean Patent Application 10-2021-0061376, filed with the Korean Intellectual Property Office on May 12, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first laminate and a second laminate are laminated on a semiconductor substrate in a cell region of the semiconductor memory device and in a slot region of the semiconductor memory device adjacent to the cell region. A plurality of unit plugs, the plurality of unit plugs passing at least partially through the second stack and the first stack in the unit region and extending in a vertical direction; A slit that at least partially passes through the second laminate and the first laminate in the slit region; as well as A protective pattern is arranged between the slit and the plurality of unit plugs, specifically between the dummy unit plugs adjacent to the slit. In the plan view, the slit extends beyond the protective pattern.

2. The semiconductor memory device according to claim 1, wherein, The protective pattern is arranged at the height of the first layer between the dummy unit plug and the slit.

3. The semiconductor memory device according to claim 1, further comprising: The source layer is disposed between the semiconductor substrate and the first laminate.

4. The semiconductor memory device of claim 3, wherein the protective pattern is arranged between the dummy cell plug and the slit and between the second laminate and the source layer.

5. The semiconductor memory device according to claim 3, further comprising: A first interlayer insulating layer is disposed between the semiconductor substrate and the source layer; as well as An etch stop pattern is provided, which is arranged in the first interlayer insulating layer below the dummy unit plug.

6. The semiconductor memory device of claim 1, wherein the first stack comprises at least one second interlayer insulating layer and at least one first gate pattern alternately stacked, and The at least one first gate pattern includes a source select line and a gate pattern of a source select transistor.

7. The semiconductor memory device of claim 1, wherein the second stack comprises alternating layers of a plurality of third interlayer insulating layers and a plurality of second gate patterns, and The plurality of second gate patterns include word lines and gate patterns for memory cells.

8. The semiconductor memory device of claim 1, wherein the protective pattern is disposed in the region of the semiconductor memory device adjacent to the slit in the cell region and adjacent to the thinned region of the semiconductor memory device adjacent to the cell region.

9. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A first stack is formed on a semiconductor substrate, wherein a first interlayer insulating layer and a first sacrificial layer are alternately stacked in the first stack, and the semiconductor memory device includes a slit region, a dummy cell region and a normal cell region; The first stack is removed from the dummy cell region by etching the first stack, and a protective pattern is formed in the space where the first stack has been removed. A second laminate is formed over the entire structure including the first laminate and the protective pattern, wherein a second interlayer insulating layer and a second sacrificial layer are alternately laminated in the second laminate; A plurality of cell plugs are formed in the normal cell region, at least partially passing through the second stack and the first stack, and at least one dummy cell plug is formed in the dummy cell region, passing through the second stack and the protective pattern; as well as The second laminate and the first laminate are etched in the slit region to form a slit. In the plan view, the slit extends beyond the protective pattern.

10. The method according to claim 9, wherein, The slit region, the dummy unit region, and the normal unit region are arranged adjacent to each other.

11. The method of claim 9, wherein the step of forming the protective pattern comprises the following steps: A groove with a linear shape is formed, which passes through the first stack in the normal cell region; as well as The trenches are filled with insulating material to form a source selection line separation pattern.

12. The method according to claim 11, wherein, The protective pattern and the source selection line separation pattern are formed together.

13. The method of claim 9, further comprising the following steps after the step of forming the slit: Remove the first and second sacrificial layers exposed by means of the slit; as well as A gate pattern is formed by filling the spaces between the removed first and second sacrificial layers with a conductive material.

14. The method of claim 13, wherein the gate pattern formed in the space where the first sacrificial layer has been removed is a gate pattern for a source-select transistor, and The gate pattern formed in the space where the second sacrificial layer has been removed is a gate pattern for a memory cell.

15. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A first interlayer insulating layer, a first source layer, a source sacrificial structure, a third source layer, and a first stack are stacked and formed on a semiconductor substrate. In the first stack, a second interlayer insulating layer and a first sacrificial layer are stacked alternately. The semiconductor memory device includes a slit region, a dummy cell region, and a normal cell region. The first stack is removed from the dummy cell region by etching the first stack, and a protective pattern is formed in the space where the first stack has been removed. A second laminate is formed over the entire structure including the first laminate and the protective pattern, wherein a third interlayer insulating layer and a second sacrificial layer are alternately laminated in the second laminate; Multiple cell plugs are formed in the normal cell region, at least partially passing through the second stack, the first stack, the third source layer, and the source sacrifice structure, and at least one dummy cell plug is formed in the dummy cell region, passing through the second stack, the protective pattern, the third source layer, and the source sacrifice structure. as well as The second stack, the first stack, and the third source layer are etched in the slit region to form a slit through which the source sacrificial structure is exposed. In the plan view, the slit extends beyond the protective pattern.

16. The method of claim 15, further comprising the following steps: Remove the exposed source sacrifice structure and form a second source layer in the space where the source sacrifice structure has been removed.

17. The method of claim 16, further comprising the following steps after the step of forming the second source layer: Remove the first and second sacrificial layers exposed by means of the slit; as well as A gate pattern is formed by filling the space where the first and second sacrificial layers have been removed with a conductive material.

18. The method of claim 17, wherein the gate pattern formed in the space where the first sacrificial layer has been removed is a gate pattern for a source-select transistor, and The gate pattern formed in the space where the second sacrificial layer has been removed is a gate pattern for a memory cell.

19. The method of claim 15, wherein the step of forming the protective pattern comprises the following steps: A groove with a linear shape is formed, which passes through the first stack in the normal cell region; as well as The trenches are filled with insulating material to form a source selection line separation pattern.

20. The method according to claim 19, wherein, The protective pattern and the source selection line separation pattern are formed together.

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