A trench field effect transistor and a method of manufacturing the same

Abstract

Disclosed are a trench field effect transistor and a preparation method thereof, comprising: a substrate; an epitaxial layer located on the substrate; a trench located in the epitaxial layer and extending from a surface of the epitaxial layer to an interior of the epitaxial layer; a gate dielectric layer located on a sidewall of the trench; a gate conductor located on the gate dielectric layer in the trench, the gate conductor and the epitaxial layer being separated from each other by the gate dielectric layer; a first dielectric layer located above the gate conductor and aligned with the gate conductor; a sidewall located on both sides of the first dielectric layer; and a conductive channel located within a position defined by the sidewall. The trench field effect transistor and the preparation method thereof increase the sidewall aligned with the gate conductor as a self-alignment structure, and accurately define the position of the conductive channel.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a trench field-effect transistor and its fabrication method. Background Technology

[0002] A trench field-effect transistor (FET) typically consists of a trench, a gate dielectric layer within the trench, a gate conductor, and conductive channels. In the manufacturing process of trench FETs, the hard mask used for trench etching is often removed after trench etching and before polysilicon filling to allow for adjustments to the trench morphology and the thickness of the gate dielectric layer. Since a self-aligned structure cannot be formed during the subsequent formation of the conductive channels, the accuracy of the conductive channel's position depends on factors such as the alignment precision between the photolithography and the preceding layer, as well as substrate deformation.

[0003] Normally, deviations in the yellow light and deformation of the substrate itself can cause shifts in the conductive channels, resulting in electrical differences. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a trench field-effect transistor and its manufacturing method, which adds a sidewall as a self-aligning structure to accurately define the position of the conductive channel.

[0005] The first aspect of the present invention provides a trench field-effect transistor, comprising:

[0006] Substrate;

[0007] An epitaxial layer is located on the substrate;

[0008] A trench, located in the epitaxial layer, extends from the surface of the epitaxial layer to the interior of the epitaxial layer;

[0009] A gate dielectric layer is located on the sidewall of the trench;

[0010] A gate conductor is located on a gate dielectric layer in the trench, and the gate conductor and the epitaxial layer are separated from each other by the gate dielectric layer;

[0011] A first dielectric layer is located above the gate conductor and aligned with the gate conductor;

[0012] Sidewalls, located on both sides of the first dielectric layer; and

[0013] A conductive channel located within the position defined by the sidewall.

[0014] Preferably, it further includes an isolation layer located between the gate dielectric layer and the gate conductor, isolating the gate dielectric layer and the gate conductor;

[0015] The isolation layer includes a first isolation layer and a second isolation layer stacked together, wherein the first isolation layer covers the gate dielectric layer and the second isolation layer covers the first isolation layer.

[0016] Preferably, the first isolation layer is a silicon nitride layer, and the second isolation layer is a silicon oxide layer.

[0017] Preferably, the first dielectric layer is formed by oxidizing the gate conductor.

[0018] Preferably, the upper surface of the gate conductor is lower than the upper surface of the isolation layer, and the upper surface of the first dielectric layer is higher than the upper surface of the isolation layer.

[0019] Preferably, the gate dielectric layer and the isolation layer further extend to cover a portion of the surface of the epitaxial layer on both sides of the trench.

[0020] Preferably, the isolation layer above the epitaxial layer between the trenches has an opening that penetrates the isolation layer and exposes the surface of the gate dielectric layer;

[0021] The sidewall is located on the isolation layer above the epitaxial layer and exposes the opening of the isolation layer.

[0022] Preferably, the sidewall includes a first sidewall and a second sidewall;

[0023] The first sidewall includes a first portion covering the sidewall of the first dielectric layer and a second portion on an isolation layer above the epitaxial layer. The first portion covering the sidewall of the first dielectric layer and the second portion on the isolation layer above the epitaxial layer constitute an L-shaped first sidewall.

[0024] The second sidewall is located above the second portion of the first sidewall.

[0025] Preferably, the first sidewall is a silicon nitride layer with a thickness of 10 nanometers to 50 nanometers.

[0026] Preferably, the second sidewall is a silicon oxide layer with a thickness of 20 nanometers to 100 nanometers.

[0027] Preferably, it further includes:

[0028] The source region, located between the trenches, extends from the surface of the epitaxial layer into the interior of the epitaxial layer; and

[0029] A second dielectric layer covers the surface of the first dielectric layer, the surface of a first portion of the first sidewall, the surface of the second sidewall, and the gate dielectric layer exposed by the opening of the isolation layer.

[0030] A portion of the conductive channel extends through the second dielectric layer into the gate conductor, and a portion of the conductive channel extends through the second dielectric layer and the gate dielectric layer into the source region.

[0031] Preferably, the cross-sectional shape of the conductive channel extending through the second dielectric layer and the gate dielectric layer into the source region includes:

[0032] The upper trapezoid extends from the surface of the second dielectric layer toward the substrate, with its bottom located on the surface of the second portion of the first sidewall;

[0033] The lower trapezoid extends from the surface of the second portion of the first sidewall into the source region inside the epitaxial layer.

[0034] Preferably, it further includes a drain electrode, which is located on the surface of the substrate away from the epitaxial layer and is electrically connected to the substrate.

[0035] Preferably, it further includes:

[0036] A shielding conductor, wherein the gate conductor is located above the shielding conductor;

[0037] A shielding dielectric layer covers the bottom of the trench and the lower sidewalls of the trench;

[0038] The shielding conductor is located within the cavity formed by the shielding dielectric layer surrounding the trench;

[0039] The gate dielectric layer is located on the sidewall of the upper part of the trench, the surface of the shielding dielectric layer, and the surface of the shielding conductor.

[0040] A second aspect of the present invention provides a method for fabricating a trench field-effect transistor, comprising:

[0041] Provide substrate;

[0042] An epitaxial layer is formed on the substrate;

[0043] A trench is formed in the epitaxial layer, extending from the surface of the epitaxial layer into the interior of the epitaxial layer;

[0044] A grid dielectric layer is formed on the sidewall of the trench;

[0045] A gate conductor is formed in the trench, and the gate conductor and the epitaxial layer are separated from each other by the gate dielectric layer;

[0046] A first dielectric layer is formed above the gate conductor, and the first dielectric layer is aligned with the gate conductor;

[0047] Sidewalls are formed on both sides of the first dielectric layer; and

[0048] The conductive channel is formed within the location defined by the sidewall.

[0049] Preferably, before forming the gate conductor, the method further includes: forming an isolation layer, the isolation layer being located between the gate dielectric layer and the gate conductor, to isolate the gate dielectric layer and the gate conductor;

[0050] The isolation layer includes a first isolation layer and a second isolation layer stacked together, wherein the first isolation layer covers the gate dielectric layer and the second isolation layer covers the first isolation layer.

[0051] Preferably, the first isolation layer is a silicon nitride layer, and the second isolation layer is a silicon oxide layer.

[0052] Preferably, the first dielectric layer is formed by oxidizing the gate conductor.

[0053] Preferably, the upper surface of the gate conductor is lower than the upper surface of the isolation layer, and the upper surface of the first dielectric layer is higher than the upper surface of the isolation layer.

[0054] Preferably, the gate dielectric layer and the isolation layer further extend to cover the surface of the epitaxial layer between the trenches.

[0055] Preferably, the method for forming the sidewall includes:

[0056] An etch stop layer is formed, which covers the surface of the isolation layer, the surface of the first dielectric layer, and the sidewalls;

[0057] A mask layer is formed on the surface of the etching stop layer;

[0058] The mask layer is etched using the etching stop layer as a barrier layer to form the second sidewall;

[0059] The second sidewall covers the etching barrier layer on the side of the first dielectric layer and part of the etching barrier layer above the epitaxial layer;

[0060] The etching stop layer is etched through the second sidewall to form the first sidewall, and the first sidewall and the second sidewall constitute a sidewall.

[0061] The first sidewall includes a first portion covering the sidewall of the first dielectric layer and a second portion on an isolation layer above the epitaxial layer. The first portion covering the sidewall of the first dielectric layer and the second portion on the isolation layer above the epitaxial layer constitute an L-shaped first sidewall.

[0062] The second sidewall is located above the second portion of the first sidewall.

[0063] Preferably, the first sidewall is a silicon nitride layer with a thickness of 10 nanometers to 50 nanometers.

[0064] Preferably, the second sidewall is a silicon oxide layer with a thickness of 20 nanometers to 100 nanometers.

[0065] Preferably, the method further includes: etching a portion of the isolation layer above the epitaxial layer via the sidewall to form an opening in the isolation layer, the opening penetrating the isolation layer and exposing the surface of the gate dielectric layer; the sidewall is located on the remaining isolation layer above the epitaxial layer and exposes the opening in the isolation layer.

[0066] Preferably, the method of forming an opening within the insulating layer includes:

[0067] Using the first isolation layer as the etch stop layer, the second isolation layer is etched through the second sidewall to form a first opening penetrating the second isolation layer;

[0068] Using the gate dielectric layer as the etch stop layer, the first isolation layer is etched through the second sidewall to form a second opening penetrating the first isolation layer. The first opening and the second opening are connected to form an opening penetrating the isolation layer.

[0069] Preferably, it further includes:

[0070] A source region is formed before or after the formation of the trenches, the source region being located between the trenches and extending from the surface of the epitaxial layer into the interior of the epitaxial layer; and

[0071] After the opening is formed, a second dielectric layer is formed, which covers the surface of the first dielectric layer, the surface of the first portion of the first sidewall, the surface of the second sidewall, and the gate dielectric layer exposed by the opening of the isolation layer.

[0072] A portion of the conductive channel extends through the second dielectric layer into the gate conductor, and a portion of the conductive channel extends through the second dielectric layer and the gate dielectric layer into the source region.

[0073] Preferably, the cross-sectional shape of the conductive channel extending through the second dielectric layer and the gate dielectric layer into the source region includes:

[0074] The upper trapezoid extends from the surface of the second dielectric layer toward the substrate, with its bottom located on the surface of the second portion of the first sidewall;

[0075] The lower trapezoid extends from the surface of the second portion of the first sidewall into the source region inside the epitaxial layer.

[0076] Preferably, the substrate further includes forming a drain electrode on the surface of the substrate away from the epitaxial layer, the drain electrode being electrically connected to the substrate.

[0077] Preferably, before forming the gate conductor, the method further includes:

[0078] A shielding medium layer is formed, which covers the bottom of the trench and the lower sidewalls of the trench;

[0079] A shielding conductor is formed, wherein the gate conductor is located above the shielding conductor, and the shielding conductor is located within the cavity formed by the shielding dielectric layer surrounding the trench;

[0080] The gate dielectric layer is located on the sidewall of the upper part of the trench, the surface of the shielding dielectric layer, and the surface of the shielding conductor.

[0081] The trench field-effect transistor and its fabrication method provided by the present invention include sidewalls located on both sides of the first dielectric layer. The sidewalls serve as self-aligned structures for the conductive channels, defining the position of the conductive channels so that the position of the conductive channels does not change with yellow light, thereby reducing the influence of yellow light deviation on the position of the conductive channels and further preventing electrical differences in the subsequently formed metal interconnect structures.

[0082] Furthermore, by oxidizing the polysilicon layer to form the first dielectric layer, the first dielectric layer is strictly aligned with the gate conductor. The step difference is made by utilizing the oxidation expansion characteristics of polysilicon, and the step difference is used to form sidewalls on both sides of the first dielectric layer. There are no special requirements for the front layer structure, the process is simple and easy to implement.

[0083] Furthermore, an isolation layer is provided between the gate dielectric layer and the gate conductor. The isolation layer is used to isolate the gate dielectric layer and the gate conductor, protect the gate dielectric layer, and prevent the oxidation process of the subsequent formation of the first dielectric layer from affecting the morphology and thickness of the gate dielectric layer.

[0084] Furthermore, removing the hard mask after trench etching allows for adjustments to the trench morphology and the thickness of the gate dielectric layer. Attached Figure Description

[0085] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0086] Figure 1 A schematic diagram of the structure of a trench field-effect transistor in the prior art is shown;

[0087] Figure 2 A schematic diagram of the trench field-effect transistor according to the first embodiment of the present invention is shown;

[0088] Figures 3a to 3i Cross-sectional views of the trench field-effect transistor of the first embodiment of the present invention at various stages of its fabrication process are shown.

[0089] Figure 4 A schematic diagram of the trench field-effect transistor according to a second embodiment of the present invention is shown;

[0090] Figures 5a to 5f Cross-sectional views of various stages in the fabrication process of the trench field-effect transistor according to the second embodiment of the present invention are shown. Detailed Implementation

[0091] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0092] This invention can be presented in various forms, some of which will be described below.

[0093] Figure 1 A schematic diagram of the structure of a trench field-effect transistor in the prior art is shown; as follows: Figure 1 As shown, the trench field-effect transistor 100 includes: a substrate 110, an epitaxial layer 120, a gate dielectric layer 140, a gate conductor 130, a dielectric layer 150, and a conductive channel 160.

[0094] The epitaxial layer 120 is located on the substrate 110, and a trench is formed in the epitaxial layer 120. The gate dielectric layer 140 covers the sidewalls and bottom of the trench and the first surface of the epitaxial layer 120. The gate conductor 130 fills the cavity formed by the gate dielectric layer 140 around the sidewalls and bottom of the trench, that is, the gate dielectric layer 140 isolates the gate conductor 130 and the epitaxial layer 120. The dielectric layer 150 covers the upper surface of the gate conductor 130 and the surface of the gate dielectric layer 140. The conductive channel 160 penetrates the dielectric layer 150 and the gate dielectric layer 140 and extends into the epitaxial layer 120.

[0095] In this embodiment, the conductive channel 160 has a trapezoidal cross-sectional shape. During the formation of the conductive channel 160, the dielectric layer 150, the gate dielectric layer 140, and a portion of the epitaxial layer 120 are etched using photolithography and etching processes to form contact holes (not shown). Then, conductive material is filled into the contact holes to form the conductive channel 160. During the formation of the contact holes, the position of the contact holes depends on the alignment of the photolithography beam; deviations in the position of the photolithography beam will cause electrical differences in the conductive channel 160.

[0096] Figure 2 A schematic diagram of the trench field-effect transistor according to the first embodiment of the present invention is shown; as follows: Figure 2 As shown, the trench field-effect transistor 200 includes: a substrate 210, an epitaxial layer 220, a gate dielectric layer 240, an isolation layer 270, a gate conductor 230, a source region 290, a first dielectric layer 230a, a sidewall 280, a second dielectric layer 250, and a conductive channel 260.

[0097] The epitaxial layer 220 is located on the substrate 210, which serves as the drain region of the trench field-effect transistor 200. The drain electrode of the trench field-effect transistor 200 (not shown) is formed on the surface of the substrate 210 away from the epitaxial layer 220. The epitaxial layer 220 has multiple trenches extending from its first surface (upper surface) towards the substrate 210 and into the interior of the epitaxial layer 220. The source region 290 is located between the trenches and extends from the surface of the epitaxial layer 220 into its interior.

[0098] The gate dielectric layer 240 covers a portion of the first surface of the epitaxial layer 220, the sidewalls of the trench, and the bottom of the trench. The isolation layer 270 includes a stacked first isolation layer 271 and a second isolation layer 272. The first isolation layer 271 covers the surface of the gate dielectric layer 240, and the second isolation layer 272 covers the surface of the first isolation layer 271. The first isolation layer 271 and the second isolation layer 272 cover a portion of the gate dielectric layer 240 located on the epitaxial layer 220. The gate conductor 230 fills the trench, and in the trench, the gate conductor 230 is separated from the epitaxial layer 220 by the gate dielectric layer 240 and the isolation layer 270.

[0099] In this embodiment, the isolation layer 270 is located between the gate dielectric layer 240 and the gate conductor 230, isolating the gate dielectric layer 240 and the gate conductor 230. The first isolation layer 271 within the isolation layer 270 protects the gate dielectric layer 240, preventing the subsequent formation of the first dielectric layer 230a from affecting the morphology and thickness of the gate dielectric layer 240. In a specific embodiment, the first isolation layer 271 is, for example, a silicon nitride layer, and the second isolation layer 272 is, for example, a silicon oxide layer.

[0100] The first dielectric layer 230a is located on the upper surface of the gate conductor 230. In this embodiment, the first dielectric layer 230a is formed by oxidizing the gate conductor 230, such that the first dielectric layer 230a is aligned with the gate conductor 230. The oxidative expansion characteristics of the gate conductor 230 (polysilicon layer) cause the first dielectric layer 230a to extend to the outside of the trench, that is, the upper surface of the first dielectric layer 230a is higher than the upper surface of the isolation layer 270, and the upper surface of the gate conductor 230 is lower than the upper surface of the isolation layer 270.

[0101] The sidewalls 280 are located on both sides of the gate conductor 230 and the first dielectric layer 230a, defining the position of the conductive channel 260. The sidewalls 280 include a first sidewall 281a and a second sidewall 282a. The first sidewall 281a includes a first portion covering the sidewall of the first dielectric layer 230a and a second portion located on the isolation layer 270 above the epitaxial layer 220, such that the cross-sectional shape of the first sidewall 281a is "L". The second sidewall 282a is located above the second portion of the first sidewall 281a and adjacent to the first portion of the first sidewall 281a.

[0102] Furthermore, the isolation layer 270 located above the epitaxial layer 220 has an opening that penetrates the isolation layer 270 and exposes the surface of the gate dielectric layer 240. In this embodiment, the opening is formed in the isolation layer 270, and the position of the opening corresponds to the position of the conductive channel 260, wherein the position of the opening is defined by the sidewall 280.

[0103] The second dielectric layer 250 covers the surface of the first dielectric layer 230a and the surface of the sidewall 280, and fills the opening of the isolation layer 270, covering the surface of the gate dielectric layer 240 exposed by the isolation layer 270. The conductive channel 260 includes at least a gate conductive channel and a source conductive channel; specifically, the second dielectric layer 250 has a first contact hole (not shown) and a second contact hole (not shown), the first contact hole penetrates the second dielectric layer 250 and the gate dielectric layer 240, and extends to the source region in the epitaxial layer 220, the source conductive channel fills the first contact hole; the second contact hole penetrates the second dielectric layer 250 and the first dielectric layer 230a, and extends to the gate conductor 230 in the trench, the gate conductive channel fills the second contact hole. In this embodiment, the position of the conductive channel 260 is defined by the first sidewall 281a.

[0104] The cross-sectional shape of the first contact hole and the source conductive channel includes a stacked upper trapezoid and a lower trapezoid. The upper trapezoid is larger and extends from the surface of the second dielectric layer 250 toward the substrate 210. Its bottom is located on the surface of the second portion of the first sidewall 281a. The first sidewall 281a serves as a barrier layer for etching the first contact hole. The first contact hole located above the first sidewall 281a cannot extend further downward. The portion of the first contact hole without the barrier of the first sidewall 281a continues to extend toward the substrate 210, penetrating the second dielectric layer. 250 and the gate dielectric layer 240 extend into the source region inside the epitaxial layer 220; in this embodiment, the upper trapezoid is larger in size, and its position and linewidth are defined by the yellow light, which may result in left and right offsets; the lower trapezoid has a smaller cross-sectional area, and its position and linewidth depend on the first sidewall 281a, thus reducing the influence of the yellow light deviation on the position of the lower trapezoid. That is, only the part without the first sidewall 281a can be etched to form the lower trapezoid, and its position is located in the center between the two trenches, which does not change with the position of the yellow light. Even if the position of the upper trapezoid is offset, it will not affect the position of the lower trapezoid.

[0105] The sidewall 280 serves as a self-aligning structure for the conductive channel 260, ensuring that the position of the conductive channel 260 does not change with the yellow light, thereby reducing the impact of the yellow light deviation on the position of the source conductive channel.

[0106] Figures 3a to 3i The diagram shows cross-sectional views of the trench field-effect transistor of the first embodiment of the present invention at various stages of its fabrication process.

[0107] like Figure 3a As shown, an epitaxial layer 220 is formed on a substrate 210, and a trench 201 is formed in the epitaxial layer 220.

[0108] In this step, the epitaxial layer 220 is formed on the substrate 210, wherein the substrate 210 serves as the drain region of the trench field-effect transistor 200. The materials of the substrate 210 and the epitaxial layer 220 are, for example, silicon or germanium, but are not limited thereto. Next, a patterned hard mask (not shown) is formed on the first surface of the epitaxial layer 220, and trenches 201 are formed in the epitaxial layer 220 via the hard mask. In a specific embodiment, the depth of the trenches 201 is, for example, 1 μm to 6 μm, and the spacing between the trenches 201 is, for example, 0.1 μm to 0.6 μm. After the trenches 201 are formed, the hard mask is removed to adjust the morphology of the trenches 201 and the thickness of the subsequently formed gate dielectric layer, etc.

[0109] Next, for example, ion implantation is used to form a source region 290 in the epitaxial layer 220, the source region 290 being located between the trenches 201 and extending from the surface of the epitaxial layer 220 toward the interior of the epitaxial layer 220. In other embodiments, the source region 290 may also be formed prior to the formation of the trenches 201.

[0110] like Figure 3b As shown, a gate dielectric layer 240 is formed at the bottom, sidewalls, and first surface of the epitaxial layer 220 of the trench 201. The gate dielectric layer 240 is, for example, a silicon oxide layer.

[0111] Furthermore, an isolation layer 270 is formed on the surface of the gate dielectric layer 240.

[0112] In this embodiment, the isolation layer 270 includes a stacked first isolation layer 271 and a second isolation layer. For example, the first isolation layer 271 is deposited on the surface of the gate dielectric layer 240 using a CVD deposition process. The first isolation layer 271 completely covers the gate dielectric layer 240. In a specific embodiment, the first isolation layer 271 is, for example, a silicon nitride layer, and its thickness is, for example, 10 nanometers to 50 nanometers. The first isolation layer 271 protects the gate dielectric layer 240, preventing subsequent oxidation processes from affecting the thickness and morphology of the gate dielectric layer 240.

[0113] Next, a second isolation layer 272 is formed on the surface of the first isolation layer 271, for example, using a wet oxygen growth or deposition process, the second isolation layer 272 completely covering the first isolation layer 271. In a specific embodiment, the second isolation layer 272 is, for example, a silicon oxide layer, and the thickness of the second isolation layer 272 is, for example, 1 nanometer to 1000 nanometers.

[0114] After the gate dielectric layer 240 and the isolation layer 270 are sequentially formed at the bottom and sidewall of the trench 201, the gate dielectric layer 240 and the isolation layer 270 form a cavity 201a around the trench 201.

[0115] like Figure 3c As shown, a polysilicon layer 236 is formed within the cavity 201a formed by the gate dielectric layer 240 and the isolation layer 270 surrounding the trench 201.

[0116] In this step, for example, a polysilicon layer 236 is formed on the surface of the isolation layer 270 (specifically the second isolation layer 272) using a deposition process. The polysilicon layer 236 fills the cavity 201a in the trench 201 and covers the surface of the second isolation layer 272. Next, the polysilicon layer 236 is chemically mechanically polished, leaving only the polysilicon layer 236 inside the cavity 201a. The second isolation layer 272 is exposed above the epitaxial layer 220, and the surface of the polysilicon layer 236 inside the cavity 201a is flush with the surface of the second isolation layer 272 above the epitaxial layer 220.

[0117] like Figure 3d As shown, the polysilicon layer 236 is oxidized to form a gate conductor 230 and a first dielectric layer 230a located above the gate conductor 230.

[0118] In this step, the polysilicon layer 236 is oxidized. The thickness of the oxidized polysilicon layer 236 is adjusted by controlling parameters such as temperature, time, and gas ratio during the oxidation process. The unoxidized polysilicon layer 236 forms the gate conductor 230, while the oxidized polysilicon layer 236 forms silicon oxide, i.e., a first dielectric layer 230a covering the gate conductor 230. In this embodiment, due to the oxidation expansion characteristics of the polysilicon layer 236, a step difference is formed between the first dielectric layer 230a and the surface of the isolation layer 270 above the surface of the epitaxial layer 220. That is, the first dielectric layer 230a extends to the outside of the trench, the upper surface of the gate conductor 230 is lower than the upper surface of the isolation layer 270, and the upper surface of the first dielectric layer 230a is higher than the upper surface of the isolation layer 270.

[0119] In this embodiment, since the first dielectric layer 230a is formed by oxidizing the polysilicon layer 236, a strict alignment is formed between the first dielectric layer 230a and the gate conductor 230, and a step difference is formed between the first dielectric layer 230a and the surface of the isolation layer 270 above the surface of the epitaxial layer 220, which can play a role in limiting alignment during the subsequent formation of the sidewall 280.

[0120] Furthermore, in this step, due to the protection of the isolation layer 270 (especially the first isolation layer 271), the morphology and thickness of the gate dielectric layer 240 are not affected.

[0121] like Figures 3e to 3f As shown, sidewalls 280 are formed on both sides of the first dielectric layer 230a.

[0122] In this step, firstly, an etch stop layer 281 is formed, for example, using a deposition process. The etch stop layer 281 covers the surface of the second isolation layer 272, the surface of the first dielectric layer 230a, and the sidewalls. Next, a mask layer 282 is formed on the surface of the etch stop layer 281, such as... Figure 3e As shown.

[0123] The etch stop layer 281 is a silicon nitride layer with a thickness of, for example, 10 nm to 50 nm; the mask layer 282 is a silicon oxide layer with a thickness of, for example, 20 nm to 100 nm; and in the direction perpendicular to the first surface of the epitaxial layer 220, the thickness of the etch stop layer 281 located on the sidewall of the first dielectric layer 230a is greater than the thickness of the etch stop layer 281 located on the surface of the first dielectric layer 230a and the thickness of the etch stop layer 281 located on the surface of the second isolation layer 272. Similarly, in the direction perpendicular to the first surface of the epitaxial layer 220, the thickness of the mask layer 282 located on the sidewall of the first dielectric layer 230a is greater than the thickness of the mask layer 282 located above the surface of the first dielectric layer 230a and the thickness of the mask layer 282 located above the surface of the second isolation layer 272.

[0124] Further, the mask layer 282 is etched to form a second sidewall 282a, as shown. Figure 3f As shown.

[0125] In this step, an anisotropic dry etching process is used to etch the mask layer 282. Since the mask layer 282 and the etching stop layer 281 have different etching selectivity, the etching stop layer 281 acts as a barrier layer during the etching of the mask layer 282, so that the etching stops at the surface of the etching stop layer 281.

[0126] In this case, since the thickness of the mask layer 282 located on the sidewall of the first dielectric layer 230a is greater than the thickness of the mask layer 282 located above the surface of the first dielectric layer 230a and the thickness of the mask layer 282 located above the surface of the second isolation layer 272 in the direction perpendicular to the first surface of the epitaxial layer 220, the mask layer 282 located above the surface of the first dielectric layer 230a and the mask layer 282 located above the surface of the second isolation layer 272 are removed, and part of the mask layer 282 located on the sidewall of the first dielectric layer 230a is retained, and the retained part forms the second sidewall 282a.

[0127] Further, the etching stop layer 281 is etched via the second sidewall 282a to form a first sidewall 281a. The first sidewall 281a and the second sidewall 282a constitute a sidewall 280, as shown below. Figure 3gAs shown.

[0128] In this step, the exposed etching stop layer 281 is etched, and the etching stop layer 281 above the first dielectric layer 230a and the etching stop layer 281 above the second isolation layer 272 not covered by the second sidewall 282a are removed. Since the etch stop layer 281 covering the sidewall of the first dielectric layer 230a is relatively thick in the direction perpendicular to the first surface of the epitaxial layer 220, a portion of the etch stop layer 281 covering the sidewall of the first dielectric layer 230a is retained, and the etch stop layer 281 covered by the second sidewall 282a is also retained, forming a first sidewall 281a. The etch stop layer located on the sidewall of the first dielectric layer 230a serves as the first part of the first sidewall 281a, and the etch stop layer located above the epitaxial layer 220 serves as the second part of the first sidewall 281a. The second sidewall 282a is located on the second part of the first sidewall 281a, and the first sidewall 281a is L-shaped.

[0129] Next, an opening 270a is formed within the isolation layer 270.

[0130] Specifically, the exposed second isolation layer 272 (the portion of the second isolation layer 272 located above the epitaxial layer 220 between the trenches) is first etched to form a first opening. In this step, the second sidewall 282a serves as a mask, and the first isolation layer 271 serves as a stop layer for etching. In this step, a portion of the second sidewall 282a is etched away; however, in the direction perpendicular to the first surface of the epitaxial layer 220, the second sidewall 282a is thicker than the second isolation layer 272. When the etching of the second isolation layer 272 is complete, only a portion of the second sidewall 282a is etched away, while the second isolation layer 272 below the second sidewall 282a is retained.

[0131] Further, the exposed first isolation layer 271 (the portion of the first isolation layer 271 located above the epitaxial layer 220 between the trenches) is etched to form a second opening penetrating the first isolation layer 271. The first opening and the second opening communicate to form an opening 270a penetrating the isolation layer 270, and the opening 270a exposes the gate dielectric layer 240. In this step, the second sidewall 282a serves as a mask, and the gate dielectric layer 240 serves as a stop layer for etching. Specifically, in this step, a portion of the upper surfaces of the first sidewall 281a and the first dielectric layer 230a are etched away. However, because the first sidewall 281a and the first dielectric layer 230a are relatively thick, only a portion of the first sidewall 281a and the first dielectric layer 230a is etched away when the etching of the first isolation layer 271 is completed.

[0132] like Figure 3h As shown, a second dielectric layer 250 is formed, and the surface of the second dielectric layer 250 is planarized.

[0133] In this step, for example, a deposition process is used to form the second dielectric layer 250, wherein the second dielectric layer 250 covers the surface of the gate dielectric layer 240 exposed through the opening 270a, the sidewalls of the isolation layer 270, the first sidewall 281a, the top and sidewalls of the second sidewall 282a, and the surface of the first dielectric layer 230a. Next, for example, a chemical mechanical polishing process is used to planarize the surface of the second dielectric layer 250. It should be noted that the materials of the second dielectric layer 250 and the second sidewall 282a can be the same or different. When the materials are the same, the second sidewall 282a can be incorporated as part of the second dielectric layer 250 in subsequent processes.

[0134] like Figure 3i As shown, a contact hole 261 is formed using the first sidewall 281a as a mask, wherein the contact hole 261 includes a first contact hole 261a and a second contact hole 261b.

[0135] In this step, the contact hole pattern is first defined by photolithography and development. Then, a dry etching process is used to etch the second dielectric layer 250, the gate dielectric layer 240 and the epitaxial layer 220 through a photolithography mask to form the first contact hole 261a. The second dielectric layer 250, the first dielectric layer 230a and part of the gate conductor 230 are etched to form the second contact hole 261b.

[0136] In this embodiment, the cross-sectional shape of the first contact hole 261a typically includes a stacked upper trapezoid and a lower trapezoid. The upper trapezoid is larger, and its position and linewidth are defined by the yellow light. The lower trapezoid is smaller, and its position and linewidth depend on the first sidewall 281a. That is, the first sidewall 281a defines the position of the lower trapezoid in the first contact hole 261a. The position of the lower trapezoid in the first contact hole 261a does not change with the deviation of the yellow light, thereby reducing the influence of the yellow light deviation on the position of the first contact hole 261a. When the size of the first contact hole 261a is small, the cross-sectional shape of the first contact hole 261a can also be trapezoidal, and the position and linewidth of the trapezoid are defined by the first sidewall 281a. The cross-sectional shape of the second contact hole 261b is typically trapezoidal.

[0137] Specifically, in this step, the first sidewall 281a serves as a hard mask to form an etched self-aligned structure, such that the first contact hole 261a is located within the position defined by the first sidewall 281a, preventing the position of the first contact hole 261a from shifting in a direction parallel to the surface of the epitaxial layer 220, and further preventing electrical differences in the conductive channels subsequently formed.

[0138] Next, metal material is filled into the first contact hole 261a and the second contact hole 261b, and the metal material is planarized using a chemical mechanical polishing process to form a conductive channel 260, such as... Figure 2 As shown. Furthermore, a passivation layer, metal interconnect structure, etc. (not shown) are formed on the conductive channel 260, which will not be described in detail here.

[0139] Figure 4 A schematic diagram of the trench field-effect transistor according to a second embodiment of the present invention is shown; as follows: Figure 4 As shown, the trench field-effect transistor 300 includes: a substrate 310, an epitaxial layer 320, a shielding dielectric layer 3311, a shielding conductor 331, a gate dielectric layer 340, an isolation layer 370, a gate conductor 332, a source region 390, a first dielectric layer 330a, a sidewall 380, a second dielectric layer 350, and a conductive channel 360.

[0140] The epitaxial layer 320 is located on the substrate 310, which serves as the drain region of the trench field-effect transistor 200. The drain electrode of the trench field-effect transistor 300 (not shown) is formed on the surface of the substrate 310 away from the epitaxial layer 320. The epitaxial layer 320 has multiple trenches. The trenches extend from the first surface of the epitaxial layer 320 toward the substrate 310 and into the interior of the epitaxial layer 320. The source region 390 is located between the trenches and extends from the surface of the epitaxial layer 320 into its interior.

[0141] The shielding dielectric layer 3311 covers the bottom of the trench and the lower sidewalls of the trench. The shielding conductor 331 is located within the cavity formed by the shielding dielectric layer 3311 around the trench. The shielding dielectric layer 3311 isolates the shielding conductor 331 from the epitaxial layer 320. Further, the shielding conductor 331 is substantially flush with the top of the shielding dielectric layer 3311. In other embodiments, an insulating layer may also be provided, which covers the shielding conductor 331 and the top of the shielding dielectric layer 3311, and the insulating layer and the shielding dielectric layer 3311 together surround the shielding conductor 331.

[0142] The gate dielectric layer 340 covers a portion of the first surface of the epitaxial layer 320 on both sides of the trench, the upper sidewall of the trench, the shielding dielectric layer 3311, and the surface of the shielding conductor 331. When an insulating layer is present, the gate dielectric layer 340 covers a portion of the first surface of the epitaxial layer 320 on both sides of the trench, the upper sidewall of the trench, and the surface of the insulating layer. The gate conductor 332 is located in the upper part of the trench, and within the trench, the gate conductor 332 is separated from the epitaxial layer 320 and from the shielding conductor 331 by the gate dielectric layer 340.

[0143] In this embodiment, the isolation layer 370 is located between the gate dielectric layer 340 and the gate conductor 332. The isolation layer 370 covers the surface of the gate dielectric layer 340 and includes a first isolation layer 371 and a second isolation layer 372 stacked together. The first isolation layer 371 covers the surface of the gate dielectric layer 340, and the second isolation layer 372 covers the surface of the first isolation layer 371. The first isolation layer 371 and the second isolation layer 372 cover a portion of the gate dielectric layer 340 located on the epitaxial layer 320. The isolation layer 370 isolates the gate dielectric layer 340 and the gate conductor 332. The first isolation layer 371 in the isolation layer 370 protects the gate dielectric layer 340, preventing the subsequent formation of the first dielectric layer 330a from affecting the morphology and thickness of the gate dielectric layer 340. In a specific embodiment, the first isolation layer 371 is, for example, a silicon nitride layer, and the second isolation layer 372 is, for example, a silicon oxide layer.

[0144] The first dielectric layer 330a is located on the upper surface of the gate conductor 332. In this embodiment, the first dielectric layer 330a is formed by oxidizing the gate conductor 332, such that the first dielectric layer 330a is aligned with the gate conductor 330. The oxidative expansion characteristics of the gate conductor 332 (polysilicon layer) cause the first dielectric layer 330a to extend to the outside of the trench, that is, the upper surface of the first dielectric layer 330a is higher than the upper surface of the isolation layer 370, and the upper surface of the gate conductor 332 is lower than the upper surface of the isolation layer 370.

[0145] The sidewalls 380 are located on both sides of the gate conductor 332 and the first dielectric layer 330a, defining the position of the conductive channel 360. The sidewalls 380 include a first sidewall 381a and a second sidewall 382a. The first sidewall 381a includes a first portion covering the sidewall of the first dielectric layer 330a and a second portion located on the isolation layer 370 above the epitaxial layer 320, such that the cross-sectional shape of the first sidewall 381a is "L". The second sidewall 382a is located above the second portion of the first sidewall 381a and adjacent to the first portion of the first sidewall 381a.

[0146] Furthermore, the isolation layer 370 located above the epitaxial layer 320 has an opening that penetrates the isolation layer 370 and exposes the surface of the gate dielectric layer 340. In this embodiment, the opening is formed in the isolation layer 370, and the position of the opening corresponds to the position of the conductive channel 360, wherein the position of the opening is defined by the sidewall 380.

[0147] The second dielectric layer 350 covers the surface of the first dielectric layer 330a and the surface of the sidewall 380, and fills the opening of the isolation layer 370, covering the surface of the gate dielectric layer 340 exposed by the isolation layer 370. The conductive channel 360 includes at least a gate conductive channel and a source conductive channel; specifically, the second dielectric layer 350 has a first contact hole (not shown) and a second contact hole (not shown), the first contact hole penetrates the second dielectric layer 350 and the gate dielectric layer 340, and extends to the source region in the epitaxial layer 320, the source conductive channel fills the first contact hole; the second contact hole penetrates the second dielectric layer 350 and the first dielectric layer 330a, and extends to the gate conductor 332 in the trench, the gate conductive channel fills the second contact hole. In this embodiment, the position of the conductive channel 360 is defined by the first sidewall 381a.

[0148] The cross-sectional shape of the first contact hole and the source conductive channel includes a stacked upper trapezoid and a lower trapezoid. The upper trapezoid is larger and extends from the surface of the second dielectric layer 350 toward the substrate 310. Its bottom is located on the surface of the second portion of the first sidewall 381a. The first sidewall 381a serves as a barrier layer for etching the first contact hole. The first contact hole located above the first sidewall 381a cannot extend further downward. The portion of the first contact hole without the barrier of the first sidewall 381a continues to extend toward the substrate 310, penetrating the second dielectric layer. 350 and the gate dielectric layer 340 extend into the source region inside the epitaxial layer 320; in this embodiment, the upper trapezoid is larger in size, and its position and linewidth are defined by the yellow light, which may result in left and right offsets; the lower trapezoid has a smaller cross-sectional area, and its position and linewidth depend on the first sidewall 381a, thus reducing the influence of the yellow light deviation on the position of the lower trapezoid. That is, only the part without the first sidewall 381a can be etched to form the lower trapezoid, and its position is located in the exact center between the two trenches, which does not change with the position of the yellow light. Even if the position of the upper trapezoid is offset, it will not affect the position of the lower trapezoid.

[0149] The sidewall 380 serves as a self-aligning structure for the conductive channel 360, ensuring that the position of the conductive channel 360 does not change with the yellow light, thereby reducing the impact of the yellow light deviation on the position of the source conductive channel.

[0150] Figures 5a to 5f Cross-sectional views of various stages in the fabrication process of the trench field-effect transistor according to the second embodiment of the present invention are shown.

[0151] like Figure 5a As shown, an epitaxial layer 320 is formed on the substrate 310, and a trench 301 is formed in the epitaxial layer 320.

[0152] In this step, the epitaxial layer 320 is formed on the substrate 310, wherein the substrate 310 serves as the drain region of the trench field-effect transistor 300. The materials of the substrate 310 and the epitaxial layer 320 are, for example, silicon or germanium, but are not limited thereto. Next, a patterned hard mask (not shown) is formed on the first surface of the epitaxial layer 320, and trenches 301 are formed in the epitaxial layer 320 via the hard mask. In a specific embodiment, the depth of the trenches 301 is, for example, 1µm to 6µm, and the spacing between the trenches 301 is, for example, 0.1µm to 0.6µm. After the trenches 201 are formed, the hard mask is removed to adjust the morphology of the trenches 201 and the thickness of the subsequently formed gate dielectric layer, etc.

[0153] Next, for example, ion implantation is used to form a source region 390 in the epitaxial layer 320, the source region 390 being located between the trenches 301 and extending from the surface of the epitaxial layer 320 toward the interior of the epitaxial layer 320. In other embodiments, the source region 390 may also be formed prior to the formation of the trenches 301.

[0154] like Figure 5b As shown, a shielding dielectric layer 3311 and a shielding conductor 331 are formed in the trench 301.

[0155] In this step, a shielding dielectric layer 3311 is formed inside the trench 301. The shielding dielectric layer 3311 covers the sidewalls and bottom of the trench 301 and extends above the first surface of the epitaxial layer 320. After the shielding dielectric layer 3311 is formed inside the trench 301, the shielding dielectric layer 3311 forms a cavity around the trench 301. Further, a polysilicon layer is formed in the cavity formed by the shielding dielectric layer 3311 around the trench 301. The polysilicon layer fills the cavity formed by the shielding dielectric layer 3311 around the trench 301 and extends on the shielding dielectric layer 3311 on the first surface of the epitaxial layer 320.

[0156] Further, the shielding dielectric layer 3311 and the polysilicon layer are etched back to remove the shielding dielectric layer 3311 and the polysilicon layer on the first surface of the epitaxial layer 320, and the shielding dielectric layer 3311 and the polysilicon layer located above the trench 301 are also etched away, exposing the upper part of the trench 301. By etching back the polysilicon layer, the remaining polysilicon layer is located in the lower part of the trench 301, serving as the shielding conductor 331 in the final device. For convenience, the polysilicon layer after the back etching will be referred to as the shielding conductor 331. After etching, the surface height of the shielding dielectric layer 3311 in the trench is approximately the same as the surface height of the shielding conductor 331.

[0157] In other embodiments, an insulating layer may also be formed on the surface of the shielding dielectric layer 3311 and the shielding conductor 331.

[0158] In this step, a deposition process is used to deposit an insulating layer of a certain thickness in the trench. The material of the insulating layer is the same as that of the shielding dielectric layer 3311, and the insulating layer and the shielding dielectric layer 3311 together surround the shielding conductor 331. Specifically, the shielding dielectric 3311 is etched back to a height approximately equal to the surface height of the shielding conductor 331, and then the insulating layer is deposited. This allows the thickness of the insulating layer to be controlled by adjusting the deposition rate, thereby controlling the distance between the shielding conductor 331 and the gate conductor 332 formed in subsequent steps, thus improving the yield and reliability of the final device.

[0159] like Figure 5cAs shown, a gate dielectric layer 340 is formed on the surfaces of the shielding dielectric layer 3311 and the shielding conductor 331, the upper sidewall of the trench 301, and the first surface of the epitaxial layer 320. In one specific embodiment, the shielding dielectric layer 3311 and the gate dielectric layer 340 are made of the same material, for example, a silicon oxide layer.

[0160] like Figure 5d As shown, a first isolation layer 371 and a second isolation layer 372 are formed on the surface of the gate dielectric layer 340.

[0161] In this step, for example, a CVD deposition process is used to deposit a first isolation layer 371 on the surface of the gate dielectric layer 340. The first isolation layer 371 completely covers the gate dielectric layer 340. In a specific embodiment, the first isolation layer 371 is, for example, a silicon nitride layer, and the thickness of the first isolation layer 371 is, for example, 10 nanometers to 50 nanometers. The first isolation layer 371 is used to protect the gate dielectric layer 340 and prevent subsequent oxidation processes from affecting the thickness and morphology of the gate dielectric layer 340.

[0162] Next, a second isolation layer 372 is formed on the surface of the first isolation layer 371.

[0163] In this step, a second isolation layer 372 is formed on the surface of the first isolation layer 371, for example, using a wet oxygen growth or deposition process. The second isolation layer 372 completely covers the first isolation layer 371. In a specific embodiment, the second isolation layer 372 is, for example, a silicon oxide layer, and its thickness is, for example, 1 nanometer to 1000 nanometers. The first isolation layer 371 and the second isolation layer 372 together constitute the isolation layer 370.

[0164] like Figure 5e As shown, a polysilicon layer 3362 is formed within the cavity formed around the upper part of the trench 301 by the gate dielectric layer 340 and the isolation layer 370.

[0165] In this step, for example, a polysilicon layer 3362 is formed on the surface of the second isolation layer 372 using a deposition process. The polysilicon layer 3362 fills the cavity formed around the upper part of the trench 301 by the gate dielectric layer 340 and the isolation layer 370, and covers the surface of the second isolation layer 372. Next, the polysilicon layer 3362 is chemically mechanically polished, leaving only the polysilicon layer 3362 inside the cavity. The second isolation layer 372 is exposed above the epitaxial layer 320, and the surface of the polysilicon layer 3362 inside the cavity is flush with the surface of the second isolation layer 372 above the epitaxial layer 320.

[0166] like Figure 5f As shown, the polysilicon layer 3362 is oxidized to form a gate conductor 332 and a first dielectric layer 330a located above the gate conductor 332.

[0167] In this step, the polysilicon layer 3362 is oxidized. The thickness of the oxidized polysilicon layer 3362 is adjusted by controlling parameters such as temperature, time, and gas ratio during the oxidation process. The unoxidized polysilicon layer 3362 forms the gate conductor 332, while the oxidized polysilicon layer 3362 forms silicon oxide, i.e., the first dielectric layer 330a. The first dielectric layer 330a covers the gate conductor 332 and extends outside the trench. Specifically, the upper surface of the first dielectric layer 330a is higher than the upper surface of the isolation layer 370, and the upper surface of the gate conductor 332 is lower than the upper surface of the isolation layer 370.

[0168] Next, the processes of forming sidewalls 380, forming openings 370a in the isolation layer 370, forming a second dielectric layer 350, forming contact holes 361, and forming conductive channels 360 are the same as in the first embodiment. Figures 3e to 3i The same applies as shown in the example, and will not be repeated here.

[0169] The trench field-effect transistor and its fabrication method provided by the present invention include sidewalls located on both sides of the first dielectric layer. The sidewalls serve as self-aligned structures for the conductive channels, defining the position of the conductive channels so that the position of the conductive channels does not change with yellow light, thereby reducing the influence of yellow light deviation on the position of the conductive channels and further preventing electrical differences in the subsequently formed metal interconnect structures.

[0170] Furthermore, by oxidizing the polysilicon layer to form the first dielectric layer, the first dielectric layer is strictly aligned with the gate conductor. The step difference is made by utilizing the oxidation expansion characteristics of polysilicon, and the step difference is used to form sidewalls on both sides of the first dielectric layer. There are no special requirements for the front layer structure, the process is simple and easy to implement.

[0171] Furthermore, an isolation layer is provided between the gate dielectric layer and the gate conductor. The isolation layer is used to isolate the gate dielectric layer and the gate conductor, protect the gate dielectric layer, and prevent the oxidation process of the subsequent formation of the first dielectric layer from affecting the morphology and thickness of the gate dielectric layer.

[0172] Furthermore, removing the hard mask after trench etching allows for adjustments to the trench morphology and the thickness of the gate dielectric layer.

[0173] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A trench field-effect transistor, comprising: Substrate; An epitaxial layer is located on the substrate; A trench, located in the epitaxial layer, extends from the surface of the epitaxial layer to the interior of the epitaxial layer; A gate dielectric layer is located on the sidewall of the trench; A gate conductor is located on a gate dielectric layer in the trench, and the gate conductor and the epitaxial layer are separated from each other by the gate dielectric layer; A first dielectric layer is located above the gate conductor and aligned with the gate conductor; Sidewalls are located on both sides of the first dielectric layer. The sidewalls include a first sidewall, which includes a first portion covering the sidewall of the first dielectric layer and a second portion located above the epitaxial layer. The first portion and the second portion form an L-shaped first sidewall. The source region is located between the trenches and extends from the surface of the epitaxial layer into the interior of the epitaxial layer. A second dielectric layer covers the surface of the first dielectric layer and the surface of the first portion of the first sidewall; as well as A conductive channel, wherein the conductive channel is located within the position defined by the sidewall; The cross-sectional shape of the conductive channel extending through the second dielectric layer and the gate dielectric layer into the source region includes: The upper trapezoid extends from the surface of the second dielectric layer toward the substrate, with its bottom located on the surface of the second portion of the first sidewall; The lower trapezoid extends from the surface of the second portion of the first sidewall into the source region inside the epitaxial layer, and is smaller in size than the upper trapezoid.

2. The trench field-effect transistor according to claim 1, wherein, It also includes an isolation layer located between the gate dielectric layer and the gate conductor, which isolates the gate dielectric layer and the gate conductor; The isolation layer includes a first isolation layer and a second isolation layer stacked together, wherein the first isolation layer covers the gate dielectric layer and the second isolation layer covers the first isolation layer.

3. The trench field-effect transistor according to claim 2, wherein, The first isolation layer is a silicon nitride layer, and the second isolation layer is a silicon oxide layer.

4. The trench field-effect transistor according to claim 1, wherein, The first dielectric layer is formed by oxidizing the gate conductor.

5. The trench field-effect transistor according to claim 2, wherein, The upper surface of the gate conductor is lower than the upper surface of the isolation layer, and the upper surface of the first dielectric layer is higher than the upper surface of the isolation layer.

6. The trench field-effect transistor according to claim 2, wherein, The gate dielectric layer and the isolation layer also extend to cover a portion of the surface of the epitaxial layer on both sides of the trench.

7. The trench field-effect transistor according to claim 6, wherein, The isolation layer above the epitaxial layer between the trenches has an opening that penetrates the isolation layer and exposes the surface of the gate dielectric layer; The sidewall is located on the isolation layer above the epitaxial layer and exposes the opening of the isolation layer.

8. The trench field-effect transistor according to claim 7, wherein, The sidewall also includes a second sidewall, which is located above a second portion of the first sidewall.

9. The trench field-effect transistor according to claim 8, wherein, The first sidewall is a silicon nitride layer with a thickness of 10 nanometers to 50 nanometers.

10. The trench field-effect transistor according to claim 8, wherein, The second sidewall is a silicon oxide layer with a thickness of 20 nanometers to 100 nanometers.

11. The trench field-effect transistor according to claim 8, wherein, The second dielectric layer covers the surface of the first dielectric layer, the surface of the first portion of the first sidewall, the surface of the second sidewall, and the gate dielectric layer exposed by the opening of the isolation layer; A portion of the conductive channel extends through the second dielectric layer into the gate conductor, and a portion of the conductive channel extends through the second dielectric layer and the gate dielectric layer into the source region.

12. The trench field-effect transistor according to claim 1, wherein, It also includes a drain electrode, which is located on the surface of the substrate away from the epitaxial layer and is electrically connected to the substrate.

13. The trench field-effect transistor according to any one of claims 1 to 12, wherein, Also includes: A shielding conductor, wherein the gate conductor is located above the shielding conductor; A shielding dielectric layer covers the bottom of the trench and the lower sidewalls of the trench; The shielding conductor is located within the cavity formed by the shielding dielectric layer surrounding the trench; The gate dielectric layer is located on the sidewall of the upper part of the trench, the surface of the shielding dielectric layer, and the surface of the shielding conductor.

14. A method for fabricating a trench field-effect transistor, comprising: Provide substrate; An epitaxial layer is formed on the substrate; A trench is formed in the epitaxial layer, extending from the surface of the epitaxial layer into the interior of the epitaxial layer; A grid dielectric layer is formed on the sidewall of the trench; A gate conductor is formed in the trench, and the gate conductor and the epitaxial layer are separated from each other by the gate dielectric layer; A first dielectric layer is formed above the gate conductor, and the first dielectric layer is aligned with the gate conductor; Sidewalls are formed on both sides of the first dielectric layer. The sidewalls include a first sidewall, which includes a first portion covering the sidewall of the first dielectric layer and a second portion located above the epitaxial layer. The first portion and the second portion constitute an L-shaped first sidewall. as well as A conductive channel is formed within the location defined by the sidewall; Also includes: Forming a source region located between the trenches, extending from the surface of the epitaxial layer into the interior of the epitaxial layer; and A second dielectric layer is formed, which covers the surface of the first dielectric layer and the surface of the first portion of the first sidewall; The cross-sectional shape of the conductive channel extending through the second dielectric layer and the gate dielectric layer into the source region includes: The upper trapezoid extends from the surface of the second dielectric layer toward the substrate, with its bottom located on the surface of the second portion of the first sidewall; The lower trapezoid extends from the surface of the second portion of the first sidewall into the source region inside the epitaxial layer, and is smaller in size than the upper trapezoid.

15. The preparation method according to claim 14, wherein, Before forming the gate conductor, the method further includes: forming an isolation layer, the isolation layer being located between the gate dielectric layer and the gate conductor, to isolate the gate dielectric layer and the gate conductor; The isolation layer includes a first isolation layer and a second isolation layer stacked together, wherein the first isolation layer covers the gate dielectric layer and the second isolation layer covers the first isolation layer.

16. The preparation method according to claim 15, wherein, The first isolation layer is a silicon nitride layer, and the second isolation layer is a silicon oxide layer.

17. The preparation method according to claim 14, wherein, The first dielectric layer is formed by oxidizing the gate conductor.

18. The preparation method according to claim 15, wherein, The upper surface of the gate conductor is lower than the upper surface of the isolation layer, and the upper surface of the first dielectric layer is higher than the upper surface of the isolation layer.

19. The preparation method according to claim 15, wherein, The gate dielectric layer and the isolation layer also extend to cover the surface of the epitaxial layer between the trenches.

20. The preparation method according to claim 19, wherein, The method of forming the sidewall includes: An etch stop layer is formed, which covers the surface of the isolation layer, the surface of the first dielectric layer, and the sidewalls; A mask layer is formed on the surface of the etching stop layer; The mask layer is etched using the etching stop layer as a barrier layer to form a second sidewall; The second sidewall covers the etching barrier layer on the side of the first dielectric layer and part of the etching barrier layer above the epitaxial layer; The etching stop layer is etched through the second sidewall to form the first sidewall, and the first sidewall and the second sidewall constitute a sidewall. The second sidewall is located above the second portion of the first sidewall.

21. The preparation method according to claim 20, wherein, The first sidewall is a silicon nitride layer with a thickness of 10 nanometers to 50 nanometers.

22. The preparation method according to claim 20, wherein, The second sidewall is a silicon oxide layer with a thickness of 20 nanometers to 100 nanometers.

23. The preparation method according to claim 20, wherein, Also includes: A portion of the isolation layer above the epitaxial layer is etched through the sidewall to form an opening in the isolation layer that penetrates the isolation layer and exposes the surface of the gate dielectric layer; the sidewall is located on the remaining isolation layer above the epitaxial layer and exposes the opening in the isolation layer.

24. The preparation method according to claim 23, wherein, The method of forming an opening within the isolation layer includes: Using the first isolation layer as the etch stop layer, the second isolation layer is etched through the second sidewall to form a first opening penetrating the second isolation layer; Using the gate dielectric layer as the etch stop layer, the first isolation layer is etched through the second sidewall to form a second opening penetrating the first isolation layer. The first opening and the second opening are connected to form an opening penetrating the isolation layer.

25. The preparation method according to claim 23, wherein, A source region is formed before or after the formation of the trench; and After the opening is formed, a second dielectric layer is formed, which covers the surface of the first dielectric layer, the surface of the first portion of the first sidewall, the surface of the second sidewall, and the gate dielectric layer exposed by the opening of the isolation layer. A portion of the conductive channel extends through the second dielectric layer into the gate conductor, and a portion of the conductive channel extends through the second dielectric layer and the gate dielectric layer into the source region.

26. The preparation method according to claim 14, wherein, It also includes forming a drain electrode on the surface of the substrate away from the epitaxial layer, the drain electrode being electrically connected to the substrate.

27. The preparation method according to any one of claims 14 to 26, wherein, Before forming the gate conductor, the method further includes: A shielding medium layer is formed, which covers the bottom of the trench and the lower sidewalls of the trench; A shielding conductor is formed, wherein the gate conductor is located above the shielding conductor, and the shielding conductor is located within the cavity formed by the shielding dielectric layer surrounding the trench; The gate dielectric layer is located on the sidewall of the upper part of the trench, the surface of the shielding dielectric layer, and the surface of the shielding conductor.

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