Sequential read optimization in sequentially programmed memory subsystems

Abstract

A system includes a volatile memory having a buffer, and a processing device. A command generation processor receives a read request having a logical block address (LBA) from a host, and creates a first logical transfer unit (LTU) including the first LBA to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space that includes sequential LBAs mapped sequentially to sequential physical addresses. The command generation processor generates a command tag that will direct the processing device to retrieve the data from the memory device and store the data in a set of buffers, where the command tag includes a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to sequential read optimization in sequentially programmed memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0004] Figure 1A This describes an example computing system including a memory subsystem according to an embodiment.

[0005] Figure 1B Description according to the embodiments Figure 1A Additional details about the memory subsystem.

[0006] Figure 2 This is a block diagram illustrating instances of data structures configured to support region-based mappings, based on various embodiments.

[0007] Figure 3 According to the embodiments Figure 1A-1B A block diagram showing the interrelationships between the command generation processor, translation processor, and command execution processor of the memory subsystem controller.

[0008] Figure 4 This is a flowchart of a method for sequential reading optimization according to an embodiment.

[0009] Figure 5 This is a flowchart of a method for sequential reading optimization according to a relevant embodiment.

[0010] Figure 6 This is a block diagram of an example computer system operable according to an embodiment of the present disclosure. Detailed Implementation

[0011] This disclosure relates to sequential read optimization in a sequentially programmed memory subsystem. The memory subsystem can be a storage device, a memory module, or a hybrid of both. The following is combined with… Figure 1ADescribe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0012] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1A Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. The dies in the package may be assigned to one or more channels for communication with a memory subsystem controller. Each die may consist of one or more planes. Planes may be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. In the following, a block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells.

[0013] Data operations can be performed by the memory subsystem. These data operations can be initiated by the host system. For example, the host system can initiate data operations on the memory subsystem (e.g., write, read, erase, etc.). The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data in and read data from the memory devices located in the memory subsystem.

[0014] The data to be read or written, as specified in a host request, is referred to hereinafter as "host data". A host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated with the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check), data version (e.g., age to distinguish the data being written), a validity bitmap (whose LBA or logical transfer unit contains valid data), and the like. For simplicity, when "data" is used hereinafter, it is understood to refer at least to host data, but may also refer to other data such as media management data and / or system data.

[0015] The cells (or simply "media") of a memory device can be organized hierarchically, from die (upper level) to plane, to block, to page (lower level). A block set (also called a block stripe) can be a set of blocks arranged in a plane across different dies so that the blocks are grouped together for data storage. Writing to a block stripe allows more data to be written and read simultaneously and in parallel across multiple dies. Multiple blocks from one or more block sets can be identified as data groups.

[0016] In various embodiments, the host file system can group host data using locality and write the host data sequentially to the memory subsystem. The file system can then write data with different localities as parallel sequential streams to the memory subsystem, each stream having its own locality, for example, where different host applications can each write to their own stream. "Locality" can refer to temporal locality or spatial locality. Data grouped by temporal locality is host data that the processor tends to access repeatedly at the same memory device location within short time periods; for example, data that is written, overwritten, and trimmed approximately simultaneously. Trimming involves the operating system using trimming commands to inform the memory device of data blocks that are no longer in use and can be internally erased, for example, via garbage collection. Data grouped by spatial locality contains data retrieval patterns when referencing a specific memory location at a particular time, and subsequently, references to nearby memory locations (on the memory device) may be made in the near future. In this case, the processor may attempt to determine the size and shape of an area around the currently referenced memory location that is worth preparing for faster access to subsequent referenced locations. The reference to sequential locality is a special case of spatial locality that occurs when data elements are arranged and accessed linearly (e.g., when traversing elements in a one-dimensional array).

[0017] Memory subsystem controllers (e.g., including processing devices) typically write to the media randomly in portions of host data (e.g., 4 KB) and then use metadata to map the LBA space to the media's physical address space. However, when writing large groups of host data (e.g., 100 MB or more) in data locality groups, "data groups" can be written sequentially as larger chunks to one or more block sets across multiple dies. To simplify the mapping of such data groups, LBAs (e.g., logical address spaces associated with the data group) of regions can be sequentially ordered within the LBA space and mapped to sequentially ordered physical addresses within the physical address space. In other words, a data group can be associated with an LBA space region having multiple sequential LBAs sequentially mapped to multiple sequential physical addresses. Memory subsystems that can write (e.g., program) data regions at once and map said regions accordingly operate in a Zone Name Space (ZNS), where logical address regions are named / identified as groups. Advantageously, using a ZNS for logical-to-physical (LTP) address mapping greatly reduces the amount of metadata used to track LTP mappings.

[0018] In the memory subsystem, read requests (or read operations) are typically issued to the memory subsystem controller's translation processor (e.g., translating logical addresses to physical addresses) one command tag at a time, resulting in random reads at the granularity specified by the command tag. The command tag, also known as a system tag (e.g., systag), contains the number of logical transfer units (LTUs) and the address of a buffer that identifies the contents corresponding to the transfer unit as stored in a cache (e.g., a slot or entry in volatile memory). In one embodiment, an LTU corresponding to a 4 KB data portion is a subset of multiple sequential LBAs that can be mapped to physical addresses via a set of mapped data structures. Therefore, to create an LTU, the memory subsystem controller's command generation processor can combine the LBAs of the read request with additional LBAs sequentially following those LBAs (which may also be received in the read request). Each LTU can be translated into a logical block or a logical page, depending on the LTU type.

[0019] Because read requests are routinely executed one command tag at a time, each read request generates a command message (e.g., a mailbox message in one instance) that enters the command generation processor of the memory subsystem controller (regardless of whether the read is sequential), generating multiple (e.g., four) data structure lookups to map the LBA of the read request to a physical location in the memory device, as will be explained in detail. The command message can be used after the non-volatile memory command is fetched, where the command generation processor notifies the translation processor that the command has been received. These data structures (e.g., tables) can be stored in tightly coupled memory (TCM), static read-only memory (SRAM), or other volatile memories. This method of handling read requests increases overhead and degrades overall performance due to increased latency, especially when some read requests are issued sequentially to (e.g., ZNS) sequentially written physical address spaces. Therefore, the sequential data layout from sequential writes is not used to limit the number of lookups that the memory subsystem controller (e.g., the translation processor of the memory subsystem controller) must perform to determine the physical address from which data will be retrieved to satisfy the read request.

[0020] This disclosure addresses the above and other drawbacks by employing shared volatile memory (e.g., at least one volatile memory device). With shared volatile memory, the translation processor of the processing device can transmit a first physical address (to which a first LTU, specified by a first command tag, is mapped) to the command execution processor of the processing device, and set a flag (e.g., a bit flag) indicating that the first physical address is a portion of data to be sequentially written. The command generation processor of the processing device can then access the physical address and flag in the volatile memory to determine how to generate a set of command tags, which will contain the first command tag, to be issued as a group. The command generation processor can further send the set of commands containing the command tags directly to the command execution processor of the processing device, bypassing any further lookups in the mapped data structure by the translation processor. The command execution processor can read data from the physical address specified by the command tag into a set of buffers (e.g., slots within the volatile memory) allocated for this purpose.

[0021] In various embodiments, more specifically, this command tag set may contain not only a first command tag associated with a physical address, but also additional command tags associated with subsequent physical addresses sequentially numbered within a read window size (e.g., an offset value) starting at the first physical address. In this way, sequential data is read in a preview manner and stored in a set of buffers allocated to dispose of the data stored at the first physical address and subsequent physical addresses, e.g., a read preview of the offset value. Data requested by the host system from a physical address is returned to the host system. In the event that the host system requests data from a second or subsequent physical address within an offset value of the physical address, the command generation processor can quickly retrieve the data from the buffer set and send the data to the host system without any further lookup or translation.

[0022] The advantages of this disclosure include, but are not limited to, improved read performance and the significant cost of avoiding interrupted write operations to serve too many read requests (which occur more frequently than write operations), for example, by allowing many read requests to hit the buffer through read preview operations. Furthermore, this disclosure illustrates methods for performing sequential read performance optimizations to reduce latency of sequential read requests from the host system (even if those read requests are scattered with write operations and / or read requests to other areas). These advantages synergistically leverage sequential writes performed by a memory device with ZNS functionality. Those skilled in the art will appreciate other advantages of memory allocation and error optimization within the memory subsystem discussed below.

[0023] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as volatile memory (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof. Each memory device 130 or 140 may be one or more memory components.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components or devices, which can be an indirect or direct communication connection (e.g., without intermediate components or devices), whether wired or wireless, including connections such as electrical, optical, magnetic and the like.

[0027] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface that can communicate on a system bus. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] While non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1A The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into instructions for accessing the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for memory management within the same memory device package or memory die. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] In some embodiments, controller 115 includes an error correction code (ECC) encoder / decoder 111. The ECC encoder / decoder 111 can perform ECC encoding on data written to memory device 130 and ECC decoding on data read from memory device 130. ECC decoding can be performed to decode ECC codewords to correct errors in the original read data, and in many cases, it also reports the number of bit errors in the original read data.

[0040] Figure 1B Description according to the embodiments Figure 1AAdditional details of the memory subsystem 110. In an embodiment, the memory subsystem controller 115 (e.g., a processing device, referred to as controller 115 for simplicity) includes one or more registers 112, a command generation processor 122 including a buffer manager 113, a translation processor 123, a command execution processor 124, and local memory 119. For example, processor 117 ( Figure 1A The local memory 119 may include a command generation processor 123, a translation processor 123, and a command execution processor 124. In addition to other ZNS-mapped data structures, the local memory 119 may also store area-mapped data structures 101 and block set-mapped data structures 107, such as... Figure 2 As illustrated in the figure. In one embodiment, the block mapping data structure 101 contains multiple entries, such that each entry has a block set entry identifier that links to entries within the block set mapping data structure 107, which in turn may link to entries in a page mapping data structure that locates pages in memory, as shown in the reference... Figure 2 Detailed explanation.

[0041] Furthermore, as previously discussed with reference to one or more memory devices 130, 140, the physical address spaces of multiple dies (e.g., die A and die B) can be organized hierarchically by planes, blocks, and pages. Thus, for example, each of die A and die B may contain plane A and plane B, and each of plane A and plane B may contain block A and block B. A block set (or block stripe) may be defined as a group of blocks arranged in a plane across multiple dies of the memory device. As illustrated, block set 144 is arranged to include block A of plane A of die A, block A of plane B of die B, and so on, for example, blocks of plane C of die C and on other dies (if present and online).

[0042] In various embodiments, the translation processor 123 (and / or a dynamic data placer coupled to the controller 115 of the translation processor 123) dynamically determines the media layout to place data associated with logical addresses in the media cells or memory components (also referred to as "IC dies" or "media") of the memory devices 130, 140. The media layout specifies the mapping between logical addresses used in commands received in the memory subsystem 110 (e.g., from the host system 120) and physical memory locations in the media of the memory subsystem 110.

[0043] Translation processor 123 may, for example, determine a media layout for a portion of the logical address space used for writing, programming, storing, and committing data during input / output scheduling in memory subsystem 110, to place data at logical addresses associated with the physical addresses of the media in memory devices 130 or 140. When the IC die (containing media cells within the IC die) is available for committing / programming data, a write command is scheduled for execution in memory subsystem 110; and translation processor 123 generates a portion of the media layout for the write command and maps the logical addresses used in the write command to memory locations within the IC die. Execution of the write command causes memory subsystem 110 to commit / program the data associated with the write command to the IC die.

[0044] Depending on the availability of IC dies for the media and / or application across the sequential mapping scheme, controller 115 may sequentially write data groups (e.g., provided in sequential data stream locality) to fill one IC die at a time, or may sequentially write to multiple IC dies in parallel at once, such as to fill IC dies for the media simultaneously. Mapping within regions of the LBA space can also be performed sequentially to simplify the calculations used to perform the mapping, as will be discussed in more detail with reference to the ZNS mapping data structure. When multiple IC dies are available, logical addresses (e.g., LBAs) used in commands from multiple write streams can be mapped to the multiple IC dies respectively through dynamically generated portions of the media layout, ensuring no media access conflicts occur during the execution of commands from multiple write streams.

[0045] In various embodiments, translation processor 123 accesses certain ZNS mapping data structures (e.g., region mapping data structure 101 and block set mapping data structure 107) to translate LBAs into physical block addresses (PBAs) in the physical address space. Translation processor 123 in the context of flash media (e.g., NOR or NAND flash memory) may be referred to as a flash translation layer (FTL). The mapping employed by translation processor 123 can generally be considered to involve a type of block mapping, such as block-level mapping or logical block mapping. In cases where data locality is detected or in a ZNS memory device, translation processor 123 may, for example, map groups of blocks forming regions within a ZNS data structure, which may involve mapping sequentially numbered LBAs to sequentially numbered PAs, as previously discussed. Reference Figure 2 The use of the ZNS data structure and its interrelationships for mapping the LBA space of a region to the physical address space of the media is discussed in more detail.

[0046] In some embodiments, the memory subsystem 110 further includes volatile memory devices 140A (e.g., shared volatile memory, such as TCM, SRAM, DRAM, or combinations thereof), with buffers allocated for storing (e.g., caching) data to satisfy read requests. For example, each buffer may be an addressed slot or entry of the volatile memory device 140A. Buffers may include a first buffer 142A, a second buffer 142B, a third buffer 142C, and so on, up to an Nth buffer 142N. Each buffer may store page-sized data. In alternative embodiments, although shown separately, the volatile memory device 140A is actually part of the local memory 119 of the controller 115.

[0047] In various embodiments, the command generation processor 122 performs command processing, such as generating read commands and write commands, based on read and write requests received respectively from the host system 120 or another request agent. As part of executing the read request, the buffer manager 113 of the command generation processor 122 may allocate a number (e.g., a “set”) of buffers having a capacity matching the amount of data stored at a first physical address (via an LTU mapping created to contain the LBA of the read request) and subsequent physical addresses sequentially numbered after the first physical address, for example, within an offset value that defines the read window size of the memory device. In one embodiment, the offset value is 128 KB, thereby allowing read previewing of an additional 124 KB of data beyond the first read request. Various other offset values ​​or read window sizes are contemplated. For example, each subsequent physical address could be incremented by the number of pages of the read window across the sequential physical address space defined by the offset value to determine the subsequent physical address. The allocation and tracking of buffers by the buffer manager 113 facilitates the read previewing operation.

[0048] In these embodiments, the command generation processor 122 may further generate a set of command tags to guide the command execution processor 124 of the processing device to retrieve data from a first address and subsequent addresses of the memory device 130 or 140, and to store the data in a set of buffers. The command generation processor 122 may further transmit a group of commands containing the set of command tags to the command execution processor 124. In this manner, each command tag in the set of command tags contains an LTU number that identifies the LTU of a physical address mapped to one of the corresponding sequential physical addresses.

[0049] In related embodiments, buffer manager 113 can track buffer usage and is responsible for locking or releasing buffers using any number of buffer management algorithms when a host command hits these buffers to track data cached by a number of possible applications in various buffers. Buffer management algorithms may include, for example, a two-to-three tree algorithm (also known as a 2-3 tree algorithm), where buffers are sorted by LTU number (or LBA number), linked list algorithm, or N-way cache employing a hash algorithm. For example, buffer manager 113 may employ a buffer index table, where sequentially read data cached in buffers is indexed by the number of non-contiguous buffers, as shown in Table 1.

[0050] 0 0 1 3 2 4 … … … … 63 230

[0051] Table 1

[0052] Metadata that can be used by such buffer management algorithms (e.g., for tracking buffer allocation and usage) includes LTU / LBA (on which data is sorted), a buffer address indicating which buffer slot the data resides in (or other buffer identifiers for indexing), and buffer usage counts that allow joint tracking of multiple users (e.g., host applications) in separate read or write paths. In this way, buffer manager 113 can manage multiple applications writing to and reading from multiple zones, where any set of commands can be for writing to or reading from sequentially stored data, but the allocated buffers may not be sequentially numbered, as shown in Table 1. If tracking data in buffers is required, hardware acceleration can be used to facilitate tracking and management of the data in the buffers.

[0053] Buffer manager 113 may further use flags (e.g., bit flags) or counters to track whether any given buffer is being used in a read or write path. This allows for fast buffer search times to satisfy in-progress commands (e.g., already being processed) and short search times to find a specific LBA, and thus whether a buffer is available for a cache hit and directly delivered to host system 120, without having to return to translation processor 123 for mapping. Since the coherence resulting from retrieving data from buffers that behave like caches is not an issue, as long as the area mapping data structure 101 is checked first, this is the operation that command generation processor 122 will continue to perform within the disclosed sequential read optimization. In some embodiments, controller 115 includes at least a portion of buffer manager 113. In other embodiments, or in combination, the controller and / or processing apparatus of host system 120 includes at least a portion of buffer manager 113. For example, controller 115 or processing apparatus of host system 120 may be configured to execute instructions stored in memory for performing the operations of buffer manager 113 described herein. In some embodiments, a buffer manager 113 is implemented in an integrated circuit chip housed in the memory subsystem 110. In other embodiments, the buffer manager 113 is part of the operating system, device driver, or application of the host system 120.

[0054] In these embodiments, command execution processor 124 serializes write and read commands within the data bus channel to memory devices 130, 140. Command execution processor 124 may further retrieve data from a first physical address and subsequent physical addresses of memory devices 130, 140 pointed to by a set of command tags in response to receiving a read command. Each command tag contains an LTU mapped to a physical address, and a buffer address is identified within a buffer cached in volatile memory device 140A. Command execution processor 124 may further store (e.g., cache) data satisfying a read command into an allocated buffer based on the corresponding buffer address of the command tag set, the corresponding buffer address being generated by command generation processor 122 and included in the command group sent to command execution processor 124. Command execution processor 124 may further perform error handling in the physical layer, for example, corresponding to the physical address space.

[0055] Translation processor 123 translates the LTU into a physical address in the physical address space to facilitate command generation processor 122 in generating commands for command execution processor 124. Therefore, translation processor 123 can act as an intermediary between command generation processor 124 (which receives memory requests about LBAs and creates LTUs containing LBAs) and command execution processor 124, which needs to know the physical address of the physical layer to satisfy the command. In this disclosure, the conventional use of translation processor 123 for indexing various ZNS-mapped data structures is avoided in sequential read-optimized read preview operations.

[0056] Figure 2 This is a block diagram illustrating instances of data structures configured to support region-based mappings according to various embodiments. Controller 115 may be stored in local memory 119, such as in SRAM, or in a memory component of memory device 140, such as in DRAM. Figure 2 The data structure shown. Controller 115 can also use... Figure 2 The data structure configuration or implementation of media layout (e.g., the layout in which data groups of a region will reside within the physical address space). In Figure 2 In this context, the zone mapping data structure 201 is configured to provide media layout information for zones within a namespace, such as an LBA space used for ZNS operations. The zone mapping data structure 201 may be the same as or similar to... Figure 1B The area mapping data structure 101. The area mapping data structure 201 may have multiple entries. Each area mapping entry in the area mapping data structure 201 identifies information about the area, such as the area's starting LBA identifier 211, the area's block set identifier 213, the area's area cursor value 215, the area's state 217, etc.

[0057] Host system 120 begins writing data into the region at the LBA of the region start LBA identifier 211. Host system 120 sequentially writes data into the region within the LBA space. After a certain amount of data has been written into the region, the region cursor value 215 identifies the current starting LBA address for writing subsequent data. For each write command to the region, the region cursor value 215 is moved to a new starting LBA address for the next write command to the region. State 217 may have values ​​indicating whether the region is empty, full, implicitly open, explicitly open, closed, etc., to track the progress of writing to the region.

[0058] exist Figure 2In this context, the logical-to-physical block mapping data structure 203 is configured to facilitate the translation of LBA addresses to physical addresses in the media. The logical-to-physical block mapping data structure 203 may have multiple entries. LBAs can be used as or converted into indexes (e.g., LTU numbers) for entries in the logical-to-physical block mapping data structure 203. The indexes can be used to look up entries for the LBAs. Each entry in the logical-to-physical block mapping data structure 203 identifies the physical address of a memory block in the media for the LBA. For example, the physical address of a memory block in the media may include a die identifier 233, a block identifier 235, a page mapping entry identifier 237, and the like. The die identifier 233 identifies a specific IC die (e.g., die A or die B) of the memory devices 130, 140 of the memory subsystem 110. The block identifier 235 identifies a specific memory block (e.g., NAND flash memory) within the IC die identified using the die identifier 233. The page mapping entry identifier 237 identifies entries in the page mapping data structure 205.

[0059] Page mapping data structure 205 may have multiple entries. Each entry in page mapping data structure 205 may contain a page identifier 251 that identifies a memory cell page within a memory cell block (e.g., a NAND memory cell). For example, page identifier 251 may contain the word line number of the page and the sub-block number of the page within the NAND memory cell block. Furthermore, the page entry may contain the page's programming mode 253. For example, the page may be programmed in SLC mode, MLC mode, TLC mode, or QLC mode. When configured in SLC mode, each memory cell in the page stores one data bit. When configured in MLC mode, each memory cell in the page stores two data bits. When configured in TLC mode, each memory cell in the page stores three data bits. When configured in QLC mode, each memory cell in the page stores four data bits. Different pages in an integrated circuit die may have different modes for data programming.

[0060] exist Figure 2 In this context, the data control aspect of the dynamic media layout of the block set data structure 207 storage area is discussed. The block set data structure 207 may be identical or similar to... Figure 1B The block set mapping data structure 207. In one embodiment, the block set data structure 207, which may be a table, may have multiple entries. Each block set entry in the block set data structure 207 identifies the number / count 271 of the integrated circuit dies (e.g., die A and die B) in which the data of the region is stored. For each of the integrated circuit dies in the region, the block set entry of the block set data structure 207 has a die identifier 273, a block identifier 275, a page mapping entry identifier 277, a page mapping offset value, and the like.

[0061] Die identifier 273 identifies a specific IC die (e.g., die A or die B) in the media of memory subsystem 110, on which subsequent data of the IC die area can be stored. Block identifier 275 identifies a specific memory block (e.g., NAND flash memory or other media) within the IC die identified using die identifier 273, in which subsequent data of the area can be stored. Page mapping entry identifier 237 identifies page mapping entries in page mapping data structure 205, which identify pages that can be used to store subsequent data of the area.

[0062] For example, memory subsystem 110 receives multiple write command streams. In one embodiment, each corresponding stream of the multiple streams is configured to sequentially write data in a logical address space; and in another embodiment, the streams of the multiple streams are configured to pseudo-sequentially or randomly write data in a logical address space. Each write stream contains a set of commands marked to group data sets together for writing, trimming, or rewriting. Within the group, data may be written sequentially, randomly, or pseudo-sequentially in the logical space. Preferably, data in the group is written to an erase block set, wherein memory cells in the erase block set store data for the stream but not data from other streams. The erase block set can be erased to remove data from the stream without erasing data from other streams.

[0063] For example, each element in the write stream is permitted to write sequentially to an LBA in a region of the namespace allocated in the media of the memory devices 130, 140 of the memory subsystem 110, but writing data out of order in the LBA (or logical address) space is prohibited. The translation processor 123 of the memory subsystem 110 identifies multiple media units in the memory subsystem 110 that can be used to write data simultaneously.

[0064] Translation processor 123 can select a first command from multiple streams for simultaneous execution in multiple media units available for writing data. Translation processor 123 can dynamically generate and store a portion of a media layout in response to the selection of the first command for simultaneous execution in multiple media units, which maps a logical address identified by the first command in the logical address space to the physical address of a memory unit in the multiple memory units.

[0065] The command execution processor 124 can simultaneously execute the first command by storing data into memory cells according to physical addresses. For example, while scheduling the execution of the first command, execution of the second command may be in progress in a subset of the memory cells of the media in the memory subsystem 110. Therefore, the subset of memory cells used to execute the second command is unavailable for the first command. After scheduling the first command and determining the portion of the media layout containing the logical addresses used in the first command, the first command can be executed simultaneously in multiple media cells and / or concurrently with the execution of the second command in the remaining media cells of the memory subsystem 110.

[0066] For example, after identifying multiple memory cells (e.g., IC dies) that can be used to execute the next command, the translation processor 123 can identify the physical address from the block set data structure 207 that can be used to store the data for the next command. The physical address can be used to update the corresponding entry in the logical-to-physical block mapping data structure 203 for the LBA address used in the next command.

[0067] For example, when the IC die is available for writing data, the translation processor 123 can determine the command for a region that can be written to / programmed into the memory cell of the IC die. From the block set data structure 207, the translation processor 123 locates the entry for the region, locates the block identifier 275 and page map entry identifier 277 associated with the IC die identifier 273, and uses the die identifier 273, block identifier 275, and page map entry identifier 277 to update the corresponding fields of the LBA entries used in the region-specific commands in the logic-to-physical block mapping data structure 203.

[0068] Figure 3 According to the embodiments Figure 1A-1B A block diagram illustrating the interrelationships of the command generation processor 122, translation processor 123, and command execution processor 124 of the subsystem memory controller 115. In various embodiments, controller 115 includes shared volatile memory 140B and a command buffer 140C within shared volatile memory 140B. In one embodiment, shared volatile memory 140B is a reference... Figure 1B This relates to local memory 119 or volatile memory device 140A. In various embodiments, command generation processor 122 may receive a first read request from host system 120 (or other request agent). The first read request may include a first LBA, which corresponds to a first physical address of memory device 130 or 140 to which the read operation is targeted. In servicing the first read request, command generation processor 122 may create a first logical transfer unit (LTU) to include the first LBA, the first LTU being mapped to the first physical address of the memory device.

[0069] In some embodiments, the translation processor 123 may be configured to automatically store (or buffer) the LTU-to-Physical Address (PA) mapping 301 into shared volatile memory 140B when the data is programmed into memory devices 130, 140. For example, the LTU-to-PA mapping 301 may be part of a logical-to-physical block mapping data structure 203 and a page mapping data structure 205, which are written when the corresponding physical addresses are programmed into memory devices 130 or 140. This provides a fast-accessible data structure that offers only LTU-to-PA mappings at the command tag level. In some embodiments, the LTU-to-PA mapping 301 in shared volatile memory 140B may be processed as a cache to keep the size of this data structure limited.

[0070] Continue to refer to Figure 3 The translation processor 123 may further selectively set flags 303 (e.g., bit flags or the like) in shared volatile memory 140B. Each entry in the LTU-PA mapping 301 may therefore contain a physical address mapped to an LTU number and a flag. In an alternative embodiment, the flag stored in register 112 may be set. Figure 1B The bit values ​​in the bitmap. One of the bit values ​​in the bitmap may correspond to a specific LTU and thus act as a flag 303 for the shared volatile memory 140B. The bitmap may be associated with a physical address space known, for example, to be sequentially written to per ZNS operation. Flag 303 (or a bit value within the bitmap) may indicate whether an LTU-to-PA mapping entry is associated with a region in the LBA address space, which maps to data sequentially written to memory devices 130 or 140. The translation processor 123 may further selectively set a die availability flag 305 to indicate that a die in which a physical address is located is available to serve commands.

[0071] In various embodiments, if flag 303 is set and die availability flag 305 is also set, then command generation processor 122 performs the read preview optimization disclosed herein. The read optimization may include, for example, automatically incrementing a first physical address retrieved from the LTU-PA mapping 301 for the first read request to determine subsequent physical addresses within an offset of the first physical address (e.g., the read window size). In one embodiment, automatic incrementing is performed to increment the first physical address by a number of pages until the end of the read window size from the first physical address is reached.

[0072] Command generation processor 122 may subsequently generate (or update) a set of command tags within command buffer 140C, which is used to guide command execution processor 124 to retrieve data from memory device 130 or 140 and in reference Figure 1BData is stored in a set of buffers. The command generation processor 122 may then further transmit command groups, each containing one of the command tag sets, to the command execution processor 124 of the processing device. The command sets may be buffered in command buffers 140C, such as Cmd[0], Cmd[1], Cmd[2], etc., up to Cmd[n]. In one embodiment, the command generation processor 122 may interconnect the command tag sets to a command chain (e.g., a chain of corresponding commands) and transmit the command chain to the command execution processor 124 in a single command message.

[0073] After the command execution processor 124 has stored the data in the appropriate buffer allocated for the read preview of the first (or original) read command, the command generation processor 122 may transfer the data stored at the first physical address back to the host system 120 or other request broker. However, the command generation processor 122 may also further serve subsequent read commands for subsequent physical addresses directly outside the buffer. For example, in response to a second read request, the command generation processor 122 may determine that the second LBA of the second read request corresponds to a second physical address in the subsequent physical addresses. The command generation processor 122 may then retrieve a second subset of data from a second buffer in the buffer set having a buffer address associated with a second command tag in the command tag set, and transfer the second subset of data to the host system 120 in response to the first of the subsequent read commands.

[0074] As an example of the sequential read optimization described above, which includes read preview operations, assume each region is 100 MB and the host system 120 attempts to read access sequential read locations. The host system 120 may issue multiple read requests falling within the instance LBAs of the regions described in Table 2.

[0075] 300-399 3 200-299 2 100-199 1 0-99 0

[0076] Table 2

[0077] Assuming each block set (e.g., a block stripe) has 200 pages, these region IDs can be translated via region mapping data structure 201 into the following block set identifiers and write pointers as shown in Table 3. Each block set identifier identifies the block set (or block stripe) in which data is written, and the write pointer tracks the position where new data should be written next in a given region. For each region, data can be read from the starting position described in Table 2 up to the write pointer.

[0078] 3 0xA, 99 2 0xF, 200 1 0x7, 178 0 0x2, 0

[0079] Table 3

[0080] Therefore, assuming the first read request is for LBA 200, the command generation processor 122 determines the region ID to be 2. In response, the command generation processor 122 can execute multiple commands of the read preview operation disclosed herein, which instruct the command execution processor 124 to store data associated with LBA values ​​200-208 in an allocated set of buffers, for example, the base LBA value plus, for example, an offset of eight. The offset value can be determined as a predetermined amount of data to be written sequentially at once or as some other predetermined number of pages of data that the buffer can cache. Assuming the host system 120 can then issue a second read request with an LBA value of 201, the next sequential LBA after LBA 200. This second subset of data for the LBA value 201 is now stored in the buffer, and the command generation processor 122 can return the second subset of data to the host system 120 in response to the second read request.

[0081] Figure 4 This is a flowchart of a method 400 for sequential read optimization according to an embodiment. Method 400 may be performed by processing logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on a processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1A-1B The controller 115 (e.g., command generation processor 122) executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0082] refer to Figure 4 At operation 410, the processing logic receives a read request containing a first LBA of the logical block address (LBA) address space for the memory device. At operation 415, the processing logic creates a first logical transfer unit (LTU) to contain the first LBA, the first LTU being mapped to a first physical address of the memory device. The first LTU does not need to be sent to the translation processor 123, as long as the translation processor 123 already has it in the shared volatile memory 140B. Figure 3 An LTU-to-PA entry is created in LTU-to-PA mapping 301. The processing logic can then access shared memory 140B ( Figure 3 The first physical address indexed by the first LTU within )

[0083] Continue to refer to Figure 4At operation 420, the processing logic determines whether a fast lookup flag is set. This fast lookup flag may be a flag 303 set in shared volatile memory 140B and associated with a first physical address; or the fast lookup flag may be a bit value in one of the registers 112 storing a bitmap associated with the ZNS-related physical address space of memory devices 130 or 140. In either case, the fast lookup flag may indicate that the first LTU is associated with a region of multiple sequential LBAs sequentially mapped to multiple sequential physical addresses. At operation 440, the processing logic determines a reference Figure 3 The discussion can be conducted using whether flag 305 has been set.

[0084] At operation 430, if the fast lookup flag or die availability flag is not set, the processing logic submits a read request via the normal read path. This includes sending a first LTU to the translation processor 123 so that the translation processor 123 performs a lookup within the ZNS data structure to map the first LTU to a first physical address.

[0085] At operation 450, assuming the fast lookup flag and the die availability flag are set with respect to the first LTU, the processing logic retrieves data from volatile memory (e.g., ...). Figure 3 The shared volatile memory 140B retrieves the first physical address stored (or buffered) there by the translation processor 123. The first physical address can be indexed within the entry of the LTU-PA mapping 301 in the shared volatile memory 140B.

[0086] At operation 460, the processing logic allocates a set of buffers in volatile memory, the capacity of which matches the amount of data stored at a first physical address and subsequent physical addresses sequentially numbered within a read window size starting from the first physical address. The volatile memory storing the buffers may be local memory 119, volatile memory device 140A, and / or shared volatile memory 140B. In various embodiments, the processing logic determines each subsequent physical address by incrementing the first physical address by the number of pages until the end of the read window size (e.g., an offset value) is reached.

[0087] At operation 470, the processing logic generates a set of command tags that will guide the command execution processor 124 of the processing device to retrieve data from the memory device and store the data in a set of buffers. The set of command tags may include a first command tag associated with a first physical address and additional command tags associated with subsequent physical addresses.

[0088] At operation 480, the processing logic transmits command groups, each containing a set of command tags, to command execution processor 124. In one embodiment, command generation processor 122 may interconnect the sets of command tags into a command chain (e.g., a chain of corresponding commands) and transmit the command chain to command execution processor 124 in a single command message.

[0089] Figure 5 This is a flowchart of a method 500 for sequential read optimization according to a relevant embodiment. Method 500 may be performed by processing logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on a processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1A-1B The controller 115 (e.g., command generation processor 122) executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0090] refer to Figure 5 At operation 510, the processing logic receives a read request containing a first LBA for the logical block address (LBA) address space of the memory device. At operation 520, the processing logic creates a first logical transfer unit (LTU) containing the first LBA and mapped to a first physical address of the memory device.

[0091] At operation 530, the processing logic reads a flag to determine which region of the LBA address space a first LTU is associated with, wherein the region contains multiple sequential LBAs that are sequentially mapped to multiple sequential physical addresses. As discussed, the flag may be a flag 303 stored in shared volatile memory 140B or a bit value of a bitmap stored in register 112. In either case, the flag or the bit value may indicate that the LTU is associated with a region mapped to data sequentially written in the memory device.

[0092] At operation 540, the processing logic allocates a set of buffers in volatile memory, the capacity of which matches the amount of data stored at a first physical address and subsequent physical addresses sequentially numbered within a read window size starting from the first physical address. The volatile memory storing the buffers may be local memory 119, volatile memory device 140A, or other shared volatile memory 140B. In various embodiments, the processing logic determines each subsequent physical address by incrementing the first physical address by the number of pages until the end of the read window size is reached.

[0093] At operation 550, the processing logic generates a set of command tags that guides the command execution processor of the processing device to retrieve data from the memory device and store the data in a set of buffers. In this embodiment, the set of command tags includes at least a first command tag associated with a first physical address and a second command tag associated with a second physical address that follows the first physical address in subsequent physical addresses.

[0094] Figure 6 An example machine illustrating computer system 600 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A (Memory subsystem 110). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0095] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0096] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0097] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0098] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more instruction sets 626 or software embodying any or more of the methods or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1A-1B The memory subsystem 110.

[0099] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1B The buffer manager 113 provides functional instructions. Although machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "non-transitory machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0100] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0101] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0102] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0103] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0104] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0105] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; Volatile memory, including buffers; as well as A processing device coupled to the memory device and the volatile memory, wherein the command generation processor of the processing device performs the following operations: Receive a read request from the host system, including a first logical block address for the logical block address (LBA) space of the memory device; A first logical transfer unit (LTU) is created to contain the address of the first logical block, the first logical transfer unit being mapped to a first physical address of the memory device; A flag is read from the volatile memory to determine that the first logical transfer unit is associated with a region of the logical block address space, wherein the region includes a plurality of sequential logical block addresses that are sequentially mapped to a plurality of sequential physical addresses; as well as A set of command tags is generated, which will guide the command execution processor of the processing device to retrieve data from the memory device and store the data in a set of buffers, wherein the set of command tags includes a first command tag associated with the first physical address and a second command tag associated with a second physical address that follows the first physical address sequentially.

2. The system according to claim 1, wherein each command tag in the command tag set comprises: A logical transfer unit number, which identifies the logical transfer unit whose physical address is mapped to the physical address space of the memory device; as well as The buffer address of the location within the set of buffers.

3. The system of claim 1, wherein the set of command tags further includes additional command tags associated with subsequent physical addresses sequentially numbered after the second physical address, and wherein the number of pages is incremented for each subsequent physical address until the end of the read window size from the first physical address is reached.

4. The system of claim 1, wherein the command generation processor of the processing device further performs the following operations: Retrieve the first physical address from the volatile memory; and A first subset of the data retrieved from the first physical address and stored in the first buffer of the set of buffers is returned to the host system.

5. The system of claim 4, wherein in response to the second read request, the command generation processor performs the following operations: It is determined that the second logical block address of the second read request corresponds to the second physical address; Retrieve a second subset of the data from a second buffer in the set of buffers, the second buffer having a buffer address associated with the second command tag; and The second subset of the data is transmitted to the host system.

6. The system of claim 1, wherein the translation processor of the processing device sets the flag in the volatile memory based on the data being sequentially written to the memory device.

7. The system of claim 1, wherein the command generation processor further transmits a group of commands, each including one of the command tag sets, to the command execution processor of the processing device, and in response to receiving the command tag sets, the command execution processor retrieves the data from the memory device according to the corresponding buffer address of the command tag sets and stores the data in the set of buffers.

8. The system of claim 1, wherein the command generation processor further performs the following operations: Interconnect the command tag set to the command chain; and The command chain is transmitted to the command execution processor in a single command message.

9. The system of claim 1, wherein the command generation processor further uses one of the following to allocate and track the buffer within the volatile memory: A two-to-three-tree algorithm, wherein the buffers are sorted by logical transmission unit numbers; or The N-way cache uses a hashing algorithm.

10. A method comprising: The processor, which generates commands from the processing device, receives a read request that includes the address of a first logical block address for the logical block address (LBA) space of the memory device; The command-generating processor creates a first logical transfer unit to contain the first logical block address, the first logical transfer unit being mapped to a first physical address of the memory device; The command-generating processor reads bit values ​​from a bitmap from volatile memory to determine the association of the first logical transfer unit with a region of the logical block address space, wherein the region includes multiple sequential logical block addresses that are sequentially mapped to multiple sequential physical addresses; The command-generating processor allocates a set of buffers in the volatile memory, wherein the capacity of the set of buffers is matched to the amount of data stored at the first physical address and subsequent physical addresses sequentially numbered within a read window size starting at the first physical address; as well as The command generation processor generates a set of command tags, which instructs the command execution processor of the processing device to retrieve the data from the memory device and store the data in the set of buffers. The set of command tags includes at least a first command tag associated with the first physical address and a second command tag associated with a second physical address that follows the first physical address in the subsequent physical addresses.

11. The method of claim 10, further comprising a processor generated by the command: Retrieve the first physical address from the volatile memory; The available flag for the die associated with the first physical address has been set; and The request agent returns a first subset of the data retrieved from the first physical address and cached in a first buffer of the buffer set.

12. The method of claim 11, further comprising: Receive the second read request; The second logical block address of the second read request is determined to correspond to the second physical address within the read window size starting from the first physical address; A second subset of the data is retrieved from a second buffer in the buffer set, the second buffer having a buffer address associated with the second command tag; as well as The second subset of the data is transmitted to the request broker.

13. The method of claim 10, further comprising tracking the use of the buffer set via the use of one of a flag or counter for each buffer, wherein the tracking implements the use of the buffer set by multiple host applications corresponding to multiple zones.

14. The method of claim 10, wherein the command tag set further includes additional command tags associated with a subsequent physical address, including the second command tag, and the method further includes determining the subsequent physical address by incrementing the first physical address by a number of pages until the end of the read window size from the first physical address is reached.

15. The method of claim 10, wherein generating the command tag set further comprises performing the following update within the command buffer of the volatile memory: Update the first command tag with the first logical transmission unit number of the first logical transmission unit and the first buffer address of the buffer set; and The second command tag is updated with the second logical transfer unit number corresponding to the second logical block address of the second logical transfer unit and the second buffer address of the buffer set.

16. The method of claim 10, further comprising a translation processor of the processing device: Determine that the address of the first logical block is associated with the region; and The bit value associated with the first physical address is set in the volatile memory based on the data being sequentially written to the memory device.

17. The method of claim 10, wherein the command tag set further includes additional command tags associated with the subsequent physical address, including the second command tag, the method further comprising: The command generation processor transmits command groups, each including the set of command tags, to the command execution processor; The command execution processor retrieves the data from the first physical address and from the subsequent physical address of the memory device; and The data is stored in the buffer set according to the corresponding buffer address of the command label set.

18. The method of claim 10, further comprising: Interconnect the command tag set to the command chain; as well as The command chain is transmitted to the command execution processor in a single command message.

19. The method of claim 10, further comprising tracking the allocation of the set of buffers within the volatile memory via one of the following: A two-to-three-tree algorithm, wherein the buffer set is sorted by a logical transfer unit; or The N-way cache uses a hashing algorithm.

20. A non-transitory computer-readable medium storing instructions, said instructions causing the processing apparatus to perform a plurality of operations when executed by a command-generating processor of a subsystem memory controller, said plurality of operations including: Receive a read request including a first logical block address for the logical block address (LBA) space of the memory device; The command generating processor creates a first logical transfer unit (LTU) to contain the first logical block address, the first logical transfer unit to be mapped to a first physical address of the memory device; A flag is read from volatile memory to determine that the first logical transfer unit is associated with a region of the logical block address space, wherein the region includes a plurality of sequential logical block addresses that are sequentially mapped to a plurality of sequential physical addresses; A set of buffers is allocated in the volatile memory, wherein the capacity of the set of buffers is matched to the amount of data stored at the first physical address and subsequent physical addresses that are sequentially numbered within the read window size starting at the first physical address; as well as A set of command tags is generated, which will guide the command execution processor of the processing device to retrieve the data from the memory device and store the data in the set of buffers, wherein the set of command tags includes at least a first command tag associated with the first physical address and a second command tag associated with a second physical address that follows the first physical address in the subsequent physical addresses.

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