A multi-bit in-memory computation (CIM) array employing bitcell circuits optimized for accuracy and power efficiency

Abstract

A bitcell circuit of a most significant bit (MSB) of a multi-bit product generated in a bitcell array in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to another bitcell circuit of another bitcell corresponding to another bit of the multi-bit product. The bitcell circuit receiving the higher supply voltage increases a voltage difference between increments of an accumulation voltage, which can improve accuracy of a digital-to-analog converter determining a population count. The bitcell circuit of the MSB in the CIM array circuit receives the higher supply voltage to improve accuracy of the MSB, which improves accuracy of an output of the CIM array circuit. A capacitor in the bitcell circuit of the MSB has a lower capacitance to avoid increasing energy consumption due to the higher voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 868,202, filed May 6, 2020, entitled “MULTI-BIT COMPUTE-IN-MEMORY(CIM)ARRAYS EMPLOYING BIT CELL CIRCUITS OPTIMIZED FOR ACCURACY AND POWEREFFICIENCY”, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The technology disclosed herein generally relates to high-performance computing memory, and more specifically, to in-memory computing (CIM) arrays. Background Technology

[0004] Facial recognition is an example of a task that can be performed by a machine executing machine learning software. During the learning phase, a computer evaluates a set of facial images and provides feedback indicating whether the evaluation is correct. To evaluate an image, an algorithm is used to analyze the image as a group of pixels looking for specific facial features. Initially, the algorithm has no historical information to provide reference points. As more feedback is received, the algorithm becomes more accurate. Thousands of computations are performed during the evaluation of a single image. These computations can be implemented using a neural network framework, which consists of an array of nodes organized in a structure similar to synapses in the brain. In a computer, each of these nodes performs a multiplication-accumulation (MAC) operation. In this respect, Figure 1 This is a diagram of node 100 in a neural network. Node 100 receives a set of inputs X0-X... M These inputs are based on historical data and their corresponding weight values ​​W0-W0. M Multiply them to obtain the corresponding product P0-P M Product P0-P M The sums are calculated as SUM, and node 100 generates an output OUTPUT, which is a function of the sum SUM.

[0005] To implement neural networks in computer hardware, multiplication and accumulation functions are performed in dedicated processing circuitry. Data transfer bottlenecks arise because the large amounts of input, weight, and output data required for thousands of calculations must be rapidly transferred between the processing circuitry and memory. These bottlenecks cause the processing circuitry to become idle due to the urgent need for data, thus prolonging execution time, wasting power, and increasing the time the user must wait for the results.

[0006] In-memory computation (CIM) arrays were developed to implement nodes in neural network frameworks without data transfer bottlenecks. By storing weight data in each bit of the CIM array and performing multiplication operations in each bit, data transfer bottlenecks are avoided. Neural networks are a form of artificial intelligence that relies on high accuracy, so it is crucial that the CIM array generates accurate results. Since many bits of the CIM array perform thousands of computations simultaneously, speed and power efficiency are also critical. Summary of the Invention

[0007] The aspects disclosed herein include the use of a multi-bit computational memory (CIM) array with bit cell circuitry optimized for accuracy and power efficiency. The multi-bit product of input bits and digital weighted data is summed bit-by-bit by accumulating the voltages from bit cells at the same bit positions across all products. The accumulated voltage at each bit position is converted to a digital pop-count by an analog-to-digital converter (ADC). The pop-count in the most significant bit (MSB) is most critical to the accuracy of the sum, much like the leftmost digit in a decimal number. In one exemplary aspect, the bit cell circuitry for the MSB of the multi-bit product generated in the bit cell array of the CIM array circuitry is configured to receive a higher supply voltage than the supply voltage provided to the bit cell circuitry of the corresponding bit cell in the other multi-bit product. The bit cell circuitry receiving the higher supply voltage increases the voltage difference between the increments of the accumulated voltage, which can improve the accuracy of the ADC in determining the pop-count. The bit cell circuitry for the MSB in the CIM array circuitry is configured to receive a higher supply voltage to improve the accuracy of the MSB, which in turn improves the accuracy of the CIM array circuitry output. In another exemplary aspect, the capacitance of the capacitor in the bit cell circuit of the MSB is smaller than the capacitance in the bit cell circuit of other bit cells corresponding to the bits of the multi-bit product, in order to avoid increased power consumption due to higher voltage.

[0008] In one aspect, a CIM array circuit is disclosed. The CIM array circuit includes a first-bit cell array configured to generate a first multi-bit product. The first-bit cell array includes a first MSB bit cell corresponding to the MSB of the first multi-bit product and a first less significant bit cell corresponding to a less significant bit lower than the MSB in the first multi-bit product. Each bit cell of the first-bit cell array includes a bit cell circuit. Each bit cell circuit includes multiple inputs, each configured to receive a binary input signal, and a capacitor configured to indicate a voltage of a binary output. Each bit cell circuit is configured to store bits of a weight array and generate a binary output based on the multiple inputs and the bits of the weight array. The bit cell circuit of the first MSB bit cell is configured to receive a first voltage higher than a second voltage received in the bit cell circuit of the first less significant bit cell.

[0009] In another aspect, a CIM array circuit is disclosed. The CIM array circuit includes an array of bit cells configured to generate a multi-bit product. Each bit cell includes bit cell circuitry. Each bit cell circuit includes multiple inputs based on a binary input signal and a capacitor configured to indicate a voltage for a binary output. Each bit cell circuit is configured to store bits of a weight array and generate a binary output based on the multiple inputs and the bits of the weight array. The capacitance of the capacitor in the first bit cell circuit is less than the capacitance of the capacitor in another bit cell circuit. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a node configured to perform multiply-accumulate (MAC) operations in a neural network;

[0011] Figure 2A This is a schematic diagram of an in-memory computing (CIM) array circuit, which includes two functionally different CIM array circuits. Each CIM array circuit includes rows of multi-bit arrays, and each multi-bit array is configured to store multi-bit weight data and row input bits and generate multi-bit products.

[0012] Figure 2B Is Figure 2A A schematic diagram of the bit cell circuit used in each bit cell of the CIM array circuit;

[0013] Figure 3A This is a schematic diagram of a CIM array circuit, which includes multiple bit cells, each bit cell including a bit cell circuit configured to store multi-bit weight data and generate a multi-bit product, and the bit cell circuit corresponding to the most significant bit (MSB) of the multi-bit product is configured to receive a higher power supply voltage than the bit cell circuits corresponding to the bits in the multi-bit product other than the MSB.

[0014] Figure 3B In the context of Figure 3A A schematic diagram of the bit cell circuit used in the bit cell corresponding to other bits of the CIM array circuit;

[0015] Figure 3C In the context of Figure 3A A schematic diagram of the bit cell circuit used in the bit cell corresponding to the MSB of the multi-bit product in the CIM array circuit, including a transistor configured to receive a higher voltage and a capacitor having a smaller capacitance than the bit cell circuit corresponding to other bits.

[0016] Figure 4A This is a schematic diagram of another exemplary CIM array circuit, which is related to... Figure 3AThe CIM array circuit is similar, but includes a bit cell circuit corresponding to the MSB of the multi-bit product and also to the second most significant bit (second MSB), which is configured to receive a higher supply voltage than the bit cell circuit corresponding to the other bits in the multi-bit product except the MSB.

[0017] Figure 4B In the context of Figure 4A A schematic diagram of the bit cell circuit used in the bit cell corresponding to other bits in the CIM array circuit;

[0018] Figure 4C In the context of Figure 4A A schematic diagram of the bit cell circuit used in the bit cell corresponding to the MSB and the next MSB of the multi-bit product in the CIM array circuit. The bit cell circuit includes a transistor with a higher voltage and a smaller capacitor than the bit cell circuit in the bit cell corresponding to other bits.

[0019] Figure 5A Is with Figure 3A A schematic diagram of a CIM array circuit similar to the CIM array circuit in the diagram, wherein the bit cell circuits in the bit cells corresponding to the MSB and the next MSB of the multi-bit product are configured to receive a higher power supply voltage than the bit cell circuits in the bit cells corresponding to the other bits in the multi-bit product except the MSB, and each bit cell circuit in the bit cell corresponding to the MSB includes a capacitor with a smaller capacitance than the bit cell circuits in the bit cells corresponding to the other bits.

[0020] Figure 5B In the context of Figure 5A A schematic diagram of the bit cell circuit used in the bit cell corresponding to other bits in the CIM array circuit;

[0021] Figure 5C In the context of Figure 5A A schematic diagram of the bit cell circuit used in the bit cell corresponding to the next MSB of the multi-bit product in the CIM array circuit, the bit cell circuit including a transistor configured to receive a higher power supply voltage and a capacitor having the same capacitance as the bit cell circuit in the bit cell corresponding to other bits.

[0022] Figure 5D In the context of Figure 5A A schematic diagram of the bit cell circuit used in the bit cell corresponding to the MSB of the multi-bit product in the CIM array circuit, the bit cell circuit including a transistor configured to receive a higher power supply voltage and a capacitor having a smaller capacitance than the bit cell circuit in the bit cell corresponding to other bits.

[0023] Figure 6A Is with Figure 3AThe schematic diagram of a CIM array circuit is similar to that in the CIM array circuit, where the area of ​​the bit cell circuit in the bit cell corresponding to the MSB of the multi-bit product is larger to receive a higher power supply voltage than the bit cell circuit corresponding to the other bits in the multi-bit product excluding the MSB.

[0024] Figure 6B In the context of Figure 6A A schematic diagram of the bit cell circuit used in the bit cell corresponding to other bits in the CIM array circuit;

[0025] Figure 6C In the context of Figure 6A A schematic diagram of the bit cell circuit used in the bit cell corresponding to the MSB of the multi-bit product in the CIM array circuit, which uses a transistor configured to receive a higher voltage and a capacitor with a smaller capacitance than the bit cell circuit used in the bit cell corresponding to other bits.

[0026] Figure 7 This is a block diagram of an exemplary processor-based system that may include an integrated circuit (IC) of a CIM array circuit, wherein, as Figure 3A , Figure 4A , Figure 5A and Figure 6A In any of the illustrations, the bit cell circuitry used in the bit cell corresponding to the MSB of the multi-bit product generated by the bit cell array is configured to receive a higher supply voltage and / or a capacitor having a smaller capacitance than the bit cell circuitry corresponding to the other bits in the multi-bit product excluding the MSB; and

[0027] Figure 8 This is a block diagram of an exemplary wireless communication device including radio frequency (RF) components formed by an IC, wherein the IC may include a CIM array circuit, wherein, as Figure 3A , Figure 4A , Figure 5A and Figure 6A In any of the illustrations, the bit cell circuitry used in the bit cell corresponding to the MSB of the multi-bit product generated by the bit cell array is configured to receive a higher supply voltage and / or a capacitor having a smaller capacitance than the bit cell circuitry corresponding to the other bits in the multi-bit product excluding the MSB. Detailed Implementation

[0028] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. As used herein, the word “exemplary” means “as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0029] The aspects disclosed herein include the use of a multi-bit in-memory computation (CIM) array with bit cell circuitry optimized for accuracy and power efficiency. A bit-by-bit summation of the input bits and digital weighted data is performed by accumulating the voltages from bit cells at the same bit positions in all products. The accumulated voltage at each bit position is converted into a digital population count by an analog-to-digital converter (ADC). The population count in the most significant bit (MSB) is most important for the accuracy of the sum, much like the leftmost digit in a decimal. In one exemplary aspect, the bit cell circuitry for the MSB of the multi-bit product generated in the bit cell array of the CIM array circuitry is configured to receive a higher supply voltage than the supply voltage provided to the bit cell circuitry of the corresponding bit cell in the multi-bit product. The bit cell circuitry receiving the higher supply voltage increases the voltage difference between the increments of the accumulated voltage, which can improve the accuracy of the ADC in determining the population count. The bit cell circuitry for the MSB in the CIM array circuitry is configured to receive a higher supply voltage to improve the accuracy of the MSB, which in turn improves the accuracy of the CIM array circuitry output. In another exemplary aspect, the capacitance of the capacitor in the bit cell circuit of the MSB is smaller than the capacitance in the other bit cell circuits corresponding to the bits of the multi-bit product, in order to avoid increased power consumption due to higher voltage.

[0030] The exemplary aspects disclosed herein include multi-bit CIM arrays employing bit cell circuitry optimized for accuracy and power efficiency. From Figure 3A Before discussing in detail the aspects of using multi-bit CIM arrays with bit cell circuitry optimized for accuracy and power efficiency, Figure 2A Figure 2C illustrates and discusses the CIM array circuit 200, which does not include bit cell circuitry optimized for accuracy and power efficiency.

[0031] like Figure 2A As illustrated, the CIM array circuit 200 functions as two (2) independent CIM array circuits 200A and 200B. Each CIM array circuit 200A and 200B includes sixteen (16) bit cell rows 202, and each row 202 includes a bit cell array 204 of eight (8) bit cells 206. In the corresponding bit cell array 204, the bit cells 206 at the same bit position form a column 208. In this example, each of the CIM array circuits 200A and 200B can be implemented identically. Figure 1 The multiplication and accumulation component (MAC) operations described by neural network node 100 are used here, so only CIM array circuit 200A is described. The description of CIM array circuit 200A also applies to CIM array circuit 200B.

[0032] The bit cell array 204 included in each row 202 of the CIM array circuit 200A is a one-dimensional 8-bit array of bit cells 206. The bit cell array 204 is configured to store an 8-bit weight array W. Each bit cell 206 of the bit cell array 204 receives the same input bit 210 of a multi-bit (e.g., 16-bit) input signal 212. The bit cell 206 multiplies the received input bit 210 by the corresponding bit of the weight array W stored in the bit cell 206 and generates a 1-bit product. Storing the weight array W in the bit cell array 204 reduces the data transmission bottleneck that could be caused by the transmission of the weight array W for each multiplication occurring in the bit cell array 204 of the CIM array circuit 200.

[0033] The CIM array circuit 200 can be used to perform... Figure 1 The MAC function of neural network node 100. Figure 1 Node 100 is compared with CIM array circuit 200, and the inputs X0-X of node 100 are... M Corresponding to the multi-bit input signal 212, one input bit 210 of the multi-bit input signal 212 is received in each corresponding row 202. Figure 1 Each weight W0-W M This corresponds to the weight array W stored in the bit cell array 204 in each row 202. The bit cell array 204 in each row 202 implements the multiplication function of the MAC operation to generate the product P0-P. M One of the corresponding results.

[0034] The result of the multiplication function in each bit cell array 204 is a multi-bit binary value. In this example, the multi-bit value is an 8-bit value, generating one (1) bit in each bit cell 206. The accumulation function of the MAC operation performed in the CIM array circuit 200A is a column-by-column accumulation of the 1-bit result from all bit cells 206 in column 208. For example, the leftmost bit cell 206 in the bit cell array 204 in each row 202 is accumulated on the output read bit line (“output RBL”) of the leftmost column 208. The next bit cell 206 in the bit cell array 204 in each row 202 is accumulated by the ADC 214 on the output RBL of the next column, and so on, with one output RBL for each column 208. The output RBLs of each column in the eight (8) columns 208 are evaluated, and an 8-bit output SOP including the output RBLs for column 208 is generated as the output of the CIM array circuit 200A. The output SOP corresponds to Figure 1 The output SUM in the file.

[0035] As noted above, each bit cell 206 of the bit cell array 204 multiplies one bit of the weight array W with the input bit 210 of the corresponding row 202. The binary multiplication of two 1-bit values ​​can be implemented as a binary XOR (NOR) operation. To store a bit of the weight array W and perform an XNOR operation on that bit and the input bit 210, each bit cell 206 includes a bit cell circuit 216, such as... Figure 2B As illustrated in the figure. The bit cell circuit 216 can be provided as a static random access memory (RAM) (SRAM) circuit, comprising cross-coupled complementary metal-oxide-semiconductor (CMOS) inverters 218T and 218C for storing bits of the weight array W, and CMOS pass-through gates 220T and 220C for storing and controlling access to the storage bits of the weight array W. The pass-through gates 220T and 220C are controlled by input signals IN1-IN4. The input signals IN1-IN4 are generated by the input bit 210 received in row 202. The bit cell circuit 216 also includes a product node 222 coupled to each of the pass-through gates 220T and 220C. The product node 222 is configured with a voltage V corresponding to a 1-bit result of the XNOR operation of the input bit 210 and the storage bits of the weight array W. PROD The XNOR operation is performed by input signals IN1-IN4 and through gates 220T and 220C in a manner unrelated to this disclosure and therefore not described in detail herein, but should be understood by those skilled in the art. The bit cell circuit 216 also includes a switch 224 controlled by the input read word line (RWL) to set the bit values ​​of the weight array W to be stored in the bit cell circuit 216.

[0036] The result of the XNOR operation is indicated as voltage V at product node 222. PROD It represents a 1-bit binary value. For example, a binary "0" can be indicated as 0 volts (V) at the product node 222, while a binary "1" can be indicated as the supply voltage V. SUP Power supply voltage V SUP This is the voltage supplied to the bit cell circuit 216. Voltage V PROD (i.e., 0V or V) SUP The voltage V is stored in capacitor 226, which will store the voltage V. PROD The product node 222 of the bit cell circuit 216 is coupled to the output RBL. The CIM array circuit 200A includes a corresponding output RBL for each column 208, and the output RBL for a given column 208 is coupled to all bit cells 206 of that column 208 in this way. Therefore, the voltage V on the output RBL is... RBL The voltage V is provided by each bit cell circuit 216 in column 208. PROD The accumulation of.

[0037] Each column 208 has sixteen (16) bit cells 206 (one per row 202), and each bit cell 206 corresponds to the voltage V. RBL Contribute 0V or power supply voltage V SUP Therefore, the voltage V RBL The range can be from 0V (when all sixteen (16) bit cells 206 in column 208 have a binary “0” (0V) on their product node 222) to voltage V. MAX (When all sixteen (16) bit units 206 in column 208 have a binary "1" at their product node 222 (i.e., the power supply voltage V) SUP (When). The number of binary "1"s in column 208 (e.g., contributing supply voltage V to output RBL). SUP The number of bit cell circuits 216 is called the pop-count. In the example of CIM array circuit 200A, the pop-count of column 208 can range from 0 to 16, and the analog voltage V RBL Based on population counting, it is assumed to be related to the maximum voltage V. MAX A proportional voltage. Theoretically, voltage V RBL =(V MAX *Population count) / 16, although the actual voltage V RBL It may vary due to factors such as thermal noise.

[0038] In one example, when the population count in a column 208 is 8, the voltage V on the output RBL for that column 208 is... RBL It should be (V) MAX *8) / 16 or V MAX / 2. The ADC 214 in each column 208 is used to evaluate the voltage V on the output RBL. RBL This generates a numerical value indicating the population count for column 208. In the example above, the voltage V RBL Having value V MAX / 2 indicates population count = 8. The accuracy of the CIM array circuit 200A depends on the ADC 214 in each column 208 correctly distinguishing the analog voltage V accumulated on the output RBL for the corresponding column 208. RBL The ability to count populations.

[0039] The output SOP of the CIM array circuit 200A is a one-dimensional array of eight (8) population counts from column 208 of the CIM array circuit 200A. The least significant bit (LSB) of the output is generated in the rightmost column 208 of the CIM array circuit 200A, and the MSB of the output SOP is generated in the leftmost column 208. The leftmost bit cell column 208 may also be referred to herein as the MSB column 208. The population count of column 208 corresponding to the MSB column 208 of the bit cell array 204 in each row 202 is the most significant data in the output SOP. In other words, the population count in the MSB column 208 of the output SOP is the most important for the accuracy of the neural network node implemented by the CIM array circuit 200A, just like the leftmost digit of a decimal. Therefore, the accuracy of the population count in the MSB column 208 is more important than the accuracy of the population count in the other columns 208. This means that the ADC 214 correctly determines the value of the analog voltage V. RBL The ability to represent population counts is more important in MSB column 208 than in any other column 208 of CIM array circuit 200A.

[0040] Such as about Figure 2A and Figure 2B As noted, the accuracy of the CIM array circuit 200 depends on the ADC 214 correctly distinguishing the analog voltage V accumulated on the output RBL. RBL The population counting capability is represented by the analog voltage level and voltage V corresponding to the population count. MAX Proportional. As an example, if V MAX =16V, then in a CIM array circuit with 16 bit cells 206 in each column 208, the voltage difference between the corresponding population counts will be V. MAX / 16 or 1V. However, the maximum operating voltage of transistors in integrated circuits (ICs) is much less than 16V, and can range from 0.7 to 1.8V. As the incremental difference between the voltages corresponding to adjacent population counts becomes smaller, distinguishing between population counts becomes more difficult. In the presence of interference in the IC, this can lead to voltage V RBL The change in voltage V, for the ADC 214, may affect the detected voltage. RBL It becomes more difficult to accurately distinguish between the two population counts on opposite sides of the population.

[0041] In the exemplary aspects disclosed herein, the bit cell circuit configured to receive a higher supply voltage increases the voltage difference between the increments of the accumulated voltage. The increased supply voltage in the bit cell circuit of the bit cell at the same bit position in all bit cell arrays can improve the accuracy of the ADC in determining the population count at that bit position. In this regard, the bit cell circuit used in the bit cell corresponding to the MSB of the multi-bit product generated by the bit cell array in the CIM array circuit can be configured to receive a higher supply voltage than the supply voltage received in the bit cell circuit used in the lower significant bit cell corresponding to the lower significant bit excluding the MSB in the multi-bit product.

[0042] In the CIM array circuit 300, as referred to in this article Figures 3A-3C As disclosed, bit cell 302 includes bit cell circuit 304 or bit cell circuit 306. Both bit cell circuit 304 and bit cell circuit 306 are similar in structure and function. Figure 2A The bit cell circuit 216 is used, but the bit cell circuit 306 is optimized to improve accuracy and reduce power consumption. For example, the bit cell circuit 306 is configured to receive a higher voltage V. SUPH Higher voltage V SUPH Higher than the lower voltage V received in the in-situ unit circuit 304 SUPL Bit cell circuit 306 is employed in bit cell 302 corresponding to the MSB of the multi-bit product PROD generated in bit cell array 308. Bit cell circuit 304 is employed in other bit cells 302 corresponding to bits in the multi-bit product PROD other than the MSB, which are the less significant bits in the multi-bit product PROD other than the MSB. The LSB of the multi-bit product PROD is an example of the less significant bits other than the MSB, and LSB can be used herein to refer to bits other than the MSB, but the reference to less significant bits or bits other than the MSB herein does not exclusively refer to LSB.

[0043] In bit cell 302, which includes bit cell circuit 306, the transistor (not shown) of bit cell circuit 306 is configured to receive a higher voltage V. SUPH Furthermore, in bit cell 302, which includes bit cell circuit 304, the transistor of bit cell circuit 304 is configured to receive a lower voltage V. SUPL The transistor in bit cell circuit 306 is configured to receive a higher voltage V by having one or more of a thicker gate oxide and a longer gate length than the transistor used in bit cell circuit 306. SUPH Receives a higher voltage V SUPH The transistor can generate a higher maximum accumulated voltage V. MAXHThis increases the voltage difference between the increments indicating the corresponding population counts. Increasing the voltage difference between the increments of the accumulated voltage of bit cell 302 corresponding to the MSB of the multi-bit product PROD improves the accuracy of the ADC 310 for evaluating the population count of bit cell 302 corresponding to other bits (such as LSB) of the multi-bit product PROD.

[0044] Each row 312 of the CIM array circuit 300 includes a bit cell array 308 of bit cells 302. The bit cell array 308 is configured to generate a multi-bit product PROD, including at least one MSB and one LSB. The individual bits of the multi-bit product PROD are determined by the corresponding voltage V on the product node 314 of the bit cell circuits 304 and 306 in the bit cells 302 of the bit cell array 308. PROD To indicate (e.g., V) PROD The low and high voltage levels indicate binary "0" and "1". Each bit cell circuit 304, 306 includes: multiple inputs IN1-IN4, each receiving a binary input signal ARY_IN; and capacitors 316, 318, which store the binary output as a voltage V. PROD Each bit cell circuit 304, 306 is configured to store a bit of the weight array W and generate a binary output voltage V based on multiple inputs IN1-IN4 and the bits of the weight array W. PROD .

[0045] The power supply voltage V received in the bit cell circuit 306 of the bit cell 302 corresponding to the MSB of the bit cell array 308 is... SUPH The power supply voltage V of the bit cell circuit 304 of the bit cell 302 corresponding to the LSB of the bit cell array 308 is higher than that of the bit cell 308. SUPL In this regard, the binary output voltage V for column 320 (also referred to herein as "MSB column 320") corresponding to the MSB of bit cell array 308 is... PROD The ADC 310, which performs the accumulation, can determine the population count with higher accuracy than the ADC 310 in column 320 (“LSB column 320”) corresponding to the LSB. This is due to the power supply voltage V of the bit cell circuit 306 of the MSB. SUPH The power supply voltage V in the bit cell circuit 304 above LSB SUPL Therefore, the maximum voltage V on the read bit line (“output RBL”) corresponding to column 320 of MSB column 320 is... MAXH The accumulated voltage V on the output RBL of LSB column 320 is higher than that of LSB column 320. RBL Maximum voltage V MAX Due to the higher voltage V MAXHThe incremental differences between the corresponding population counting voltages are larger, and therefore this incremental difference can be determined with greater accuracy. For example, the power supply voltage V for the bit cell circuit 306 in column 320 of the MSB. SUPH It is the power supply voltage V of bit cell circuit 304 in column 320 of LSB. SUPL Twice that can make the voltage V MAX Doubling this can increase the voltage V between the corresponding group counts. RBL The difference is doubled, and the accuracy of the ADC 310 in column 320 of MSB is doubled.

[0046] Details of bit cell circuits 304 and 306 will be referred to Figure 3B and Figure 3C The description is as follows. As indicated above, the binary output voltage V... PROD The signal can be generated in bit cell circuits 304 and 306 by performing an XNOR operation on the binary input signal ARY_IN received at inputs IN1-IN4 and the bits of the weighted array W stored in the SRAM circuit 322 in bit cell circuits 304 and 306. The SRAM circuit 322 includes cross-coupled inverters 324T and 324C controlled by gates 326T and 326C. Each input IN1-IN4 receives the binary true or complement version of the binary input signal ARY_IN received in bit cell array 308. The cross-coupled inverters 324T and 324C, gates 326T and 326C, and switch 328 in bit cell circuits 304 and 306 are implemented as CMOS transistors.

[0047] In column 320 corresponding to the LSB of bit cell array 308, Figure 3B The bit cell circuit 304 is used in the column 320 corresponding to the MSB of the bit cell array 308. Figure 3C The bit cell circuit 306 in the middle. The cross-coupled inverters 324T and 324C, the gates 326T and 326C, and the switch 328 in the bit cell circuits 304 and 306 are implemented by transistors. The difference between the transistors in the bit cell circuits 304 and 306 is that the transistors in the bit cell circuit 306 can receive higher voltages than the transistors in the bit cell circuit 304. Specifically, Figure 3C The transistor in the bit cell circuit 306 can receive a higher power supply voltage V. SUPH Higher power supply voltage V SUPH The power supply voltage V of the transistor in the bit cell circuit 304 is higher than the power supply voltage V. SUPL Higher power supply voltage V SUPHThis is possible because the transistors in bit cell circuit 306 are manufactured for higher voltage operation. In one example, the thickness of the gate oxide in the transistor in bit cell circuit 306 is greater than the thickness of the gate oxide in the transistor in bit cell circuit 304. In another example, the gate length of the transistor in bit cell circuit 306 is longer than the gate length in bit cell circuit 304. One or both of the thicker gate oxide and the longer gate length allow the transistor in bit cell circuit 306 to receive a higher voltage than bit cell circuit 304. If the bit cell circuit 306 used in each bit cell 302 in MSB column 320 receives a supply voltage V SUPH It is the power supply voltage V in bit cell circuit 304 of bit cell 302 in LSB column 320. SUPL If the accuracy of MSB column 320 is twice that of LSB column 320, then the accuracy of MSB column 320 can be twice that of LSB column 320.

[0048] However, in Figure 3B and Figure 3C In bit cell circuits 304 and 306, energy is consumed each time capacitors 316 and 318 are charged and discharged. The energy consumed in bit cell circuit 304 is related to C*V. SUPL 2 Proportional, where C is the effective storage capacitor, and the supply voltage V SUPL This is the voltage to which capacitor 316 is charged. Figure 3C In the bit unit circuit 306, the power supply voltage V SUPH If compared to the power supply voltage V SUPL Increasing by 2X (i.e., doubling) will increase dynamic energy consumption by 4X (four times). To compensate for the difference in power supply voltage V... SUPH To minimize the increase in energy consumption caused by the increase, C can be reduced to Cmin, defined by the acceptable upper limit of thermal noise KT / C, or even slightly lower, where C is capacitance, T is temperature, and K is the Boltzmann constant. In one example, this is used in MSB column 320. Figure 3C The capacitance of capacitor 318 in bit cell circuit 306 is smaller than the capacitance of capacitor 316 in bit cell circuit 304 used in LSB column 320. Because... Figure 3C Capacitor 318 and Figure 3B The capacitor 316 in the middle has a smaller physical size (especially area) compared to the capacitor 316, so the capacitance of the capacitor 318 can be reduced or is smaller than the capacitance of the capacitor 316.

[0049] In each row 312 of the CIM array circuit 300, the capacitor 318 of the bit cell circuit 306 in the bit cell 302 of the MSB column 320 of the bit cell array 308 is coupled to the same output RBL. The bit cell circuit 306 couples a higher supply voltage V to the output RBL compared to the bit cell circuits 304 in other columns 320. SUPH Coupled to the output RBL for MSB column 320, but by a higher supply voltage V SUPH The resulting power consumption is Figure 3C The reduced capacitance in the smaller capacitor 318 is mitigated.

[0050] The higher power supply voltage V on each bit cell circuit 306 SUPH Voltage V RBL The maximum voltage increases to voltage V MAXH This increases the voltage difference between the voltage and the corresponding population count. In this respect, the accuracy of the ADC 310 in MSB column 320 is improved. The accuracy of MSB column 320 is the most important compared to any other column 320 in the CIM array circuit 300. Although due to the higher supply voltage V SUPH The additional power consumption in MSB column 320 is mitigated by the reduced capacitance of capacitor 318, but it receives a higher supply voltage V. OPH The transistors in the CIM array circuit 300 may be larger and occupy more area than those in the bit cell circuit 304. For the improved accuracy of the MSB column 320, the increased area is an acceptable trade-off in the CIM array circuit 300, but the accuracy of the other columns 320 is less important, and therefore no such trade-off is made in the other columns 320 of the CIM array circuit 300.

[0051] exist Figures 4A-4C The figure also illustrates another exemplary CIM array circuit 400, which includes functional CIM array circuits 400A and 400B. Figure 4B and Figure 4C The bit cell circuits 402 and 404 in the text correspond to the above-mentioned... Figures 3A-3C The CIM array circuit 300 describes bit cell circuits 304 and 306. The LSB column 406 of the CIM array circuits 400A and 400B includes bit cell circuit 402. The MSB column 406 of the CIM array circuits 400A and 400B includes bit cell circuit 404, which employs transistors with a higher supply voltage than the bit cell circuit 402 in the LSB column 406, and... Figure 4BThe capacitor 408 in the bit cell circuit 402 has a smaller capacitance than the capacitor 410. Therefore, the CIM array circuits 400A and 400B employ a bit cell circuit 404 optimized for accuracy and power in the MSB column 406, as discussed above regarding the MSB column 320 in the CIM array circuits 300A and 300B.

[0052] CIM array circuits 400A and 400B differ from CIM array circuits 300A and 300B in the second most significant bit (second MSB) column 406. In CIM array circuit 400, Figure 4C Receives a higher power supply voltage V SUPH The bit cell circuit 404 is also used in the sub-MSB column 406 and in bit cell 412 within the MSB column 406. Higher supply voltage V SUPH The accuracy of ADC 414 in determining population counts in the second MSB has been improved. The higher accuracy in MSB column 404 and second MSB column 404 compared to the accuracy of CIM array circuits 300A and 300B improves the accuracy of CIM array circuits 400A and 400B. This is due to the higher supply voltage V in the bit cell circuit 404. SUPH The power consumption in sub-MSB column 406 increases to the same extent as in MSB column 406. The accuracy of the ADC 414 in sub-MSB column 406 is not as critical to the accurate output SOP of CIM array circuits 400A and 400B as the accuracy of MSB column 406. Therefore, the incentive to trade increased power consumption for improved accuracy is lower in sub-MSB column 406 than in MSB column 406. However, when the focus on higher accuracy outweighs the focus on power consumption, CIM array circuits 400A and 400B offer benefits exceeding those of CIM array circuits 300A and 300B.

[0053] exist Figures 5A-5D The figure shows another exemplary CIM array circuit 500, which includes functional CIM array circuits 500A and 500B. Figure 5B and Figure 5C The bit cell circuits 502 and 504 in the text correspond to the above-mentioned... Figures 3A-3C The CIM array circuit 300 describes bit cell circuits 302 and 304. The LSB column 506 of the CIM array circuits 500A and 500B includes bit cell circuit 502. The MSB column 506 of the CIM array circuits 500A and 500B includes bit cell circuit 504, which employs transistors with a higher supply voltage than the bit cell circuit 502 in the LSB column 504, and... Figure 5BThe capacitor 508 in the bit cell circuit 502 has a smaller capacitance than the capacitor 510. Therefore, the CIM array circuits 500A and 500B employ a bit cell circuit 504 in MSB column 506 optimized to improve the accuracy of the ADC 512 in determining population counts. MSB column 506 is also optimized to reduce power consumption, as discussed above regarding MSB column 320 in CIM array circuits 300A and 300B.

[0054] like Figure 5D As illustrated in the diagram, bit cell circuit 514 is used in the sub-MSB column 506 of CIM array circuits 500A and 500B. Bit cell circuit 504 differs from bit cell circuit 502 in two aspects; the only difference between bit cell circuit 514 and bit cell circuit 502 is the increased received power supply voltage V. SUPH Or reduce the capacitance of capacitor 516. For example, bit cell circuit 514 can only receive the increased power supply voltage V. SUPH (For example, by increasing the gate oxide thickness of the transistor in bit cell circuit 514 and / or increasing the gate length of the transistor), without reducing the capacitance of capacitor 516. In cases where higher accuracy is required but it is necessary to maintain a level well below the thermal noise limit determined by KT / C, a higher supply voltage V is used. SUPH The additional power consumption incurred might be acceptable without the smaller capacitor 516. Alternatively, the bit cell circuit 514 could employ a capacitor 516 with a smaller capacitance, in which case the need to reduce power consumption takes precedence over avoiding thermal noise limits, and the accuracy level is already acceptable. Therefore, Figure 5D The bit cell circuit 514 in the middle has a high power supply voltage V SUPH And one of the smaller capacitors 516. This is achieved by employing bit cell circuit 514 in the secondary MSB column 506. Figure 5A The CIM array circuit 500 in the middle can provide more than in some aspects Figures 3A-3C and Figures 4A-4C The flexibility of the CIM array circuits 300 and 400.

[0055] exist Figures 6A-6C The diagram illustrates yet another exemplary CIM array circuit 600. Figure 6B The bit cell circuit 602 in the middle corresponds to the above about Figures 3A-3C The bit cell circuit 302 described in the CIM array circuit 300. Furthermore, the bit cell circuit 604 corresponds to... Figure 3C The bit cell circuit 306 in the middle uses a higher power supply voltage V than the bit cell circuit 602. SUPH The transistor is used to increase the analog voltage V from the output RBL of the ADC 606. RBLTo determine the accuracy of population counting. However, in order to achieve a higher power supply voltage V SUPH The area of ​​bit cell circuit 604 is larger than that of bit cell circuit 602. A larger area may be needed to account for the larger gate length and / or gate oxide thickness of the transistor in bit cell circuit 604. LSB column 608 of CIM array circuits 600A and 600B includes bit cell circuit 602. MSB column 608 of CIM array circuits 600A and 600B includes bit cell circuit 604, which receives a higher supply voltage V than the bit cell circuit 602 in LSB column 608. SUPH transistors and have a higher Figure 6B The capacitor 610 in the bit unit circuit 602 has a smaller capacitance than the capacitor 612.

[0056] like Figure 6A As shown, the area of ​​bit cell circuit 604 in MSB column 608 is larger than that of bit cell circuit 602 in LSB column 608. Due to this size difference, bit cell circuit 604 in MSB column 608 cannot be like... Figure 3A , Figure 4A and Figure 5A They are physically organized into rows 614 and columns 608, as in the example. Therefore, the orientation of the bit cell circuits 604 in MSB column 608 can be modified to accommodate larger bit cell circuits 604, while logically still being organized into rows, like... Figure 2A The bit cell array 204 is the same. Figure 6A In the example, the bit cell circuits 604 for the MSB can be placed adjacent to each other in pairs in the row direction to improve space efficiency, while still being functionally organized as a single column.

[0057] like Figure 3A , Figure 4A , Figure 5A and Figure 6AAs illustrated in any of the diagrams herein, and according to any aspect disclosed herein, the CIM array circuitry disclosed herein includes bit cell circuitry employed in the bit cells corresponding to the MSB of the multi-bit product generated by the bit cell array, the bit cell circuitry being configured to receive a higher supply voltage to improve accuracy, and having a capacitor with a smaller capacitance than the bit cell circuitry corresponding to the other bits of the multi-bit product to mitigate the increase in power consumption. Examples, and not limitations, include set-top boxes; entertainment units; navigation units; communication devices; fixed location data units; mobile location data units; Global Positioning System (GPS) devices; mobile phones; cellular phones; smartphones; Session Initiation Protocol (SIP) phones; tablets; mobile phones; servers; computers; portable computers; mobile computing devices; wearable computing devices (such as smartwatches, health or fitness trackers, glasses, etc.); desktop computers; personal digital assistants (PDAs); displays; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; motor vehicles; vehicle components; avionics systems; drones; and multirotor aircraft.

[0058] in this regard, Figure 7 The illustration shows an example of a processor-based system 700 that includes CIM array circuitry, such as... Figure 3A , Figure 4A , Figure 5A and Figure 6A As illustrated in any of the diagrams herein, and according to any aspect disclosed herein, the CIM array circuitry includes bit cell circuitry employed in the bit cells corresponding to the MSB of the multi-bit product generated by the bit cell array. This bit cell circuitry is configured to receive a higher supply voltage to improve accuracy and has capacitors smaller than those corresponding to the bit cell circuitry of other bits of the multi-bit product to mitigate increased power consumption. In this example, the processor-based system 700 includes one or more central processing unit (CPU) units 702, which may also be referred to as CPUs or processor cores, each including one or more processors 704. The CPU(s) 702(s) may have cache memory 706 coupled to the processor(s) 704(s) for fast access to temporarily stored data. As an example, such as Figure 3A , Figure 4A , Figure 5A and Figure 6AAs illustrated in any of the diagrams herein, and according to any aspect disclosed herein, processor(s) 704 may include CIM array circuitry including bit cell circuitry employed in bit cells corresponding to the MSB of a multi-bit product generated by the bit cell array, the bit cell circuitry being configured to receive higher supply voltages for improved accuracy and having capacitors smaller than those of the bit cell circuitry corresponding to other bits of the multi-bit product to mitigate increased power consumption. CPU(s) 702 is coupled to system bus 708 and may couple master and slave devices included in processor-based system 700 to each other. It is known that CPU(s) 702 communicate with these other devices by exchanging address, control, and data information via system bus 708. For example, CPU(s) 702 may communicate bus transaction requests to memory controller 710, which is an example of a slave device. Although in Figure 7 Not shown in the figure, but multiple system buses 708 can be provided, each of which constitutes a different fabric.

[0059] Other master and slave devices can be connected to system bus 708. For example... Figure 7 As illustrated in the diagram, these devices may, as an example, include a memory system 712 (which includes a memory controller 710 and one or more memory arrays 714), one or more input devices 716, one or more output devices 718, one or more network interface devices 720, and one or more display controllers 722. Each of the memory system 712, one or more input devices 716, one or more output devices 718, one or more network interface devices 720, and one or more display controllers 722 may include CIM array circuitry including bit cell circuitry employed in the bit cells corresponding to the MSB of the multi-bit product generated by the bit cell array. This bit cell circuitry is configured to receive higher supply voltages to improve accuracy and has capacitors smaller than those in the bit cell circuitry corresponding to other bits of the multi-bit product to mitigate increased power consumption. Figure 3A , Figure 4A , Figure 5A and Figure 6AAny of the following are illustrated herein and are subject to any aspect disclosed herein. One or more input devices 716 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. One or more output devices 718 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. One or more network interface devices 720 may be any device configured to allow data exchange with network 724. Network 724 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. One or more network interface devices 720 may be configured to support any type of desired communication protocol.

[0060] One or more CPUs 702 may also be configured to access one or more display controllers 722 via system bus 708 to control information sent to one or more displays 726. The one or more display controllers 722 send information to one or more displays 726 for display via one or more video processors 728, which process the information to be displayed into a format suitable for one or more displays 726. The one or more displays 726 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. The one or more display controllers 722, one or more displays 726, and / or one or more video processors 728 may include CIM array circuitry including bit cell circuitry employed in bit cells corresponding to the MSB of a multi-bit product generated by the bit cell array. This bit cell is configured to receive a higher supply voltage to improve accuracy and has a capacitor smaller than the capacitance of the bit cell circuitry corresponding to other bits of the multi-bit product to mitigate increased power consumption. Figure 3A , Figure 4A , Figure 5A and Figure 6A Any of the illustrations in any of them, and in accordance with any aspect disclosed herein.

[0061] Figure 8An exemplary wireless communication device 800 is illustrated. The exemplary wireless communication device 800 includes a radio frequency (RF) component formed by an IC 802. Any component in the exemplary wireless communication device 800 may include a CIM array circuitry. This CIM array circuitry includes bit cell circuitry employed in bit cells corresponding to the MSB of a multi-bit product generated by a bit cell array. The bit cells are configured to receive higher supply voltages to improve accuracy and have capacitors smaller than those in the bit cell circuitry corresponding to other bits of the multi-bit product to mitigate increased power consumption. Figure 3A , Figure 4A , Figure 5A and Figure 6A Any of the devices illustrated herein, and in accordance with any aspect disclosed herein. As an example, wireless communication device 800 may include or be provided therein any of the devices mentioned above. Figure 8 As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. Generally, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0062] Transmitter 808 or receiver 810 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, for receiver 810, it might be from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800, the transmitter 808 and receiver 810 are implemented using a direct conversion architecture.

[0063] In the transmission path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1) and 812(2) for converting digital signals generated by the data processor 806 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0064] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 upconverts the I and Q baseband signals using I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 822 via mixers 820(1) and 820(2) to provide upconverted signal 824. Filter 826 filters upconverted signal 824 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 828 amplifies upconverted signal 824 from filter 826 to obtain the desired output power level and provides the transmit RF signal. The RF signal is routed via a duplexer or switch 830 and transmitted via antenna 832.

[0065] In the receiving path, antenna 832 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 830 and provided to low-noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate with a specific receive (RX) to TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Downconversion mixers 838(1) and 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 842(1) and 842(2) and further filtered by low-pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, the data processor 806 includes ADCs 846(1) and 846(2) for converting analog input signals into digital signals for further processing by the data processor 806.

[0066] exist Figure 8In the wireless communication device 800, a TX LO signal generator 822 generates I and Q TX LO signals for frequency up-conversion, while an RX LO signal generator 840 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from a data processor 806 and generates control signals used to adjust the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. Similarly, an RX PLL circuit 850 receives timing information from a data processor 806 and generates control signals used to adjust the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0067] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0068] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0069] The aspects disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0070] It should also be noted that the operational steps described in any exemplary aspect of this document are described as being for the purpose of example and discussion. The described operations can be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps illustrated in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0071] The foregoing description provided in this disclosure is intended to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An in-memory computing (CIM) array circuit, comprising: The first bit cell array is configured to generate a first multi-bit product. The first bit cell array includes a first most significant bit (MSB) bit cell and a first least significant bit cell. The first MSB bit cell corresponds to the MSB of the first multi-bit product, and the first least significant bit cell corresponds to the least significant bits in the first multi-bit product excluding the MSB. Each bit cell of the first bit cell array includes a bit cell circuit, wherein: Each bit cell circuit includes: Multiple inputs, each configured to receive binary input signals; and A capacitor is configured to be set to indicate the voltage of a binary output; Each bit cell circuit is configured as follows: The bits of the storage weight array; and The binary output is generated based on the plurality of inputs and the bits of the weight array; The bit cell circuit of the first MSB bit cell is configured to receive a first voltage, which is higher than a second voltage received in the bit cell circuit of the first less significant bit cell; and The first multi-bit product includes a voltage indicating the binary output of each bit cell circuit in the first bit cell array.

2. The CIM array circuit according to claim 1, wherein a first transistor among a plurality of transistors in the bit cell circuit of the first MSB bit cell is configured to receive the first voltage, and a second transistor among a plurality of transistors in the bit cell circuit of the first lower active bit cell is configured to receive the second voltage.

3. The CIM array circuit of claim 2, wherein the first transistor comprises a thicker gate oxide than the second transistor.

4. The CIM array circuit of claim 2, wherein the first transistor has a longer gate length than the second transistor.

5. The CIM array circuit of claim 2, wherein each of the plurality of transistors in the bit cell circuit of the first lower effective bit cell is configured to receive the second voltage.

6. The CIM array circuit of claim 1, further comprising a second bit cell array configured to generate a second multi-bit product, the second multi-bit product including a second MSB and a second less significant bit excluding the second MSB, wherein: The bit cell circuit of the second MSB bit cell corresponding to the second MSB of the second multi-bit product is configured to receive the first voltage; and The bit cell circuit of the second least significant bit bit cell corresponding to the second least significant bit of the second multi-bit product is configured to receive the second voltage.

7. The CIM array circuit according to claim 6, wherein: The plurality of inputs of each bit cell circuit in the first bit cell array are coupled to the binary input signal; Multiple inputs of each bit cell circuit in the second bit cell array are coupled to the binary input signal; as well as The first bit cell array and the second bit cell array are in the first row of the CIM array circuit.

8. The CIM array circuit according to claim 6, wherein: The plurality of inputs of each bit cell circuit in the first bit cell array are coupled to the binary input signal; Multiple inputs of each bit cell circuit in the second bit cell array are coupled to a second binary input signal; as well as The capacitors of the bit cell circuit of the first MSB bit cell and the bit cell circuit of the second MSB bit cell are coupled to the first read bit line.

9. The CIM array circuit according to claim 1, wherein: The bit cell circuit of the first MSB bit cell corresponding to the second MSB of the first multi-bit product is configured to receive the first voltage; and The first transistor in the bit cell circuit of the first MSB bit cell is configured to receive the first voltage.

10. The CIM array circuit according to claim 1, wherein the capacitance of the capacitor in the bit cell circuit of the first MSB bit cell is less than the capacitance of the capacitor in the bit cell circuit of the first lower effective bit cell.

11. The CIM array circuit of claim 1, further comprising a second bit cell array configured to generate a second multi-bit product, the second multi-bit product comprising an MSB, a second MSB, and lower significant bits excluding the MSB and the second MSB, wherein: The bit cell circuit of the second MSB bit cell corresponding to the MSB of the second multi-bit product is configured to receive the first voltage; The bit cell circuit of the second MSB bit cell corresponding to the second MSB of the second multi-bit product is configured to receive the first voltage; and The bit cell circuit of the second least significant bit bit cell corresponding to the less significant bit of the second multi-bit product is configured to receive the second voltage.

12. The CIM array circuit according to claim 1, wherein the first lower significant bit unit further includes the least significant bit (LSB) of the first multi-bit product.

13. The CIM array circuit according to claim 9, wherein the capacitance of the capacitor in the bit cell circuit of the first MSB bit cell is less than the capacitance of the capacitor in the bit cell circuit of the first lower effective bit cell.

14. The CIM array circuit according to claim 1, wherein: The bit cell circuit of the first lower effective bit cell occupies at least the first region; The bit cell circuit of the first MSB bit cell occupies at least the second region; and The second region is larger than the first region.

15. The CIM array circuit of claim 1, wherein each bit cell circuit is configured to generate the binary input signal and the bit of the weight array XNOR.

16. The CIM array circuit of claim 2, wherein the first transistor of the plurality of transistors in the bit cell circuit of the first MSB bit cell is a transistor in a static random access memory (RAM) SRAM circuit, or a transistor in a switch configured to provide access to the SRAM circuit.

17. The CIM array circuit according to claim 1, comprising an integrated circuit IC.

18. The CIM array circuit of claim 1, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation units; communication devices; fixed location data units; mobile location data units; Global Positioning System (GPS) devices; mobile phones; cellular phones; smartphones; Session Initiation Protocol (SIP) phones; tablet computers; mobile phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); displays; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; motor vehicles; vehicle components; avionics systems; unmanned aerial vehicles (UAVs); and multirotor aircraft.

19. An in-memory computing (CIM) array circuit, comprising: A bit cell array is configured to generate multi-bit products, each bit cell including bit cell circuitry, wherein: Each bit cell circuit includes: Multiple inputs, based on binary input signals; and A capacitor is configured to be set to indicate the voltage of a binary output; Each bit cell circuit is configured as follows: The bits of the storage weight array; and The binary output is generated based on the plurality of inputs and the bits of the weight array; and The capacitance of the capacitor in the first unit circuit is less than the capacitance of the capacitor in the other unit circuit.

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