Systems, methods, and apparatus for page migration in memory systems

Abstract

A method for managing a memory system may include monitoring pages of a first type of first memory, determining page usage based on the monitoring, and migrating pages to a second type of second memory based on the page usage. Monitoring pages may include a mapping of monitored pages. The mapping of monitored pages may include a mapping of monitored pages from logical addresses to physical addresses. Determining page usage may include determining the page update frequency. Determining page usage may include comparing the page update frequency to a threshold. Migrating pages may include sending an interrupt to a device driver. Migrating pages may include setting a write-protected state for the page.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 195,708, filed June 1, 2021, entitled "Systems, Methods, and Devices for Page Migration in Memory Systems," which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to memory systems, and more specifically to systems, methods and apparatus for page migration in memory systems. Background Technology

[0004] In some embodiments, a heterogeneous memory system may use two or more types of memory, each suitable for a particular purpose. For example, a heterogeneous memory system may include non-volatile memory that can retain data across power cycles. As another example, a heterogeneous memory system may include volatile memory that can be frequently updated without lifetime degradation.

[0005] The information disclosed in the background section is only for enhancing the understanding of the background of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] A method for managing a memory system may include monitoring pages of a first type of first memory, determining page usage based on the monitoring, and migrating pages to a second type of second memory based on page usage. Monitoring pages may include a mapping of monitored pages. The mapping of monitored pages may include a mapping of monitored pages from logical addresses to physical addresses. Determining page usage may include determining the page update frequency. Determining page usage may include comparing the page update frequency to a threshold. Migrating pages may include sending an interrupt to a device driver. Migrating pages may include setting a write-protected state for the page. Migrating pages may also include migrating pages by a page fault handler based on the write-protected state. Migrating pages by the page fault handler may be based on writes to the page. The first memory may include device-attached memory. Device-attached memory may be exposed via a memory protocol. The memory protocol may include a consistent memory protocol. The method may also include storing page usage information in the device-attached memory. The page may be migrated by a host, and the method may further include updating the page usage information by the host based on the migrated page. The first memory may include non-volatile memory, and the second memory may include volatile memory.

[0007] An apparatus may include a memory and a device controller configured to monitor pages in the memory, determine page usage based on the monitoring, and send indications based on page usage. The device controller may be configured to monitor pages by monitoring page mappings. The device controller may be configured to monitor page mappings by monitoring logical address-to-physical address mappings. The device controller may be configured to determine page usage by determining the page update frequency. The device controller may be configured to determine page usage by comparing the page update frequency to a threshold. The device controller may be configured to send interrupts based on page usage. The apparatus may include a storage device, and the memory may include non-volatile memory. The memory may be exposed via a memory protocol. The memory protocol may include a consistent memory protocol. The device controller may be configured to store page usage information in the memory. The device controller may be configured to receive update messages and update the usage information based on the update messages.

[0008] A system may include a host processor, a first type of memory arranged for access by the host processor, a device interface configured to expose a second type of memory to the host processor, and migration logic configured to receive migration messages and migrate pages from the second memory to the first memory based on the migration messages. The migration logic may include a device driver configured to receive migration messages. The device driver may be configured to set a write-protected state for a page based on the migration message. The device driver may be configured to set the write-protected state in a page table entry for the page. The migration logic may include a page fault handler configured to migrate pages from the second memory to the first memory. The migration logic may be configured to send an update message through the device interface based on the migration of pages from the second memory to the first memory. Attached Figure Description

[0009] The accompanying drawings are not necessarily drawn to scale. In all the drawings, for illustrative purposes, elements with similar structures or functions are often indicated by similar reference numerals or portions thereof. The drawings are merely for the purpose of facilitating the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the drawings from becoming obscure, not all components, connections, etc., are shown, and not all components have reference numerals. However, the pattern of component configuration can be readily discerned from the drawings. The drawings, together with the description, illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] Figure 1 An example embodiment of a system according to an example embodiment of the present disclosure is shown, in which a host can access a device-attached memory.

[0011] Figure 2 An example embodiment of a heterogeneous memory scheme according to an example embodiment of the present disclosure is shown.

[0012] Figure 3 An example embodiment of a heterogeneous memory scheme with page migration according to an example embodiment of the present disclosure is shown.

[0013] Figure 4 Another example embodiment of a heterogeneous memory scheme with page migration according to an example embodiment of the present disclosure is shown.

[0014] Figure 5 Another example embodiment of a heterogeneous memory scheme is shown, illustrating some possible implementation details of a page migration scheme according to an example embodiment of this disclosure.

[0015] Figure 6 An embodiment of a system for storing information that determines the usage patterns of one or more memory pages, according to an example embodiment of the present disclosure, is shown.

[0016] Figure 7 An example embodiment of a host device that can be used to implement a page migration scheme according to an example embodiment of the present disclosure is shown.

[0017] Figure 8 An example embodiment of a device that can be used to implement a page migration scheme according to an example embodiment of the present disclosure is shown.

[0018] Figure 9 An embodiment of a method for managing a memory system according to an example embodiment of the present disclosure is shown. Detailed Implementation

[0019] In a heterogeneous memory system according to an example embodiment of this disclosure, memory pages can be migrated from a first type of memory (e.g., non-volatile memory) to a second type of memory (e.g., volatile memory) based on determined memory page usage patterns. For example, usage patterns of one or more pages in non-volatile memory can be monitored to identify pages that are likely to be accessed more frequently than others. Pages identified as frequently accessed (which may be referred to as hot pages) can be migrated from non-volatile memory to volatile memory, for example, to reduce page writes (which can increase the lifetime of non-volatile memory), to improve system performance (e.g., by load balancing), and so on.

[0020] In some embodiments, the first type of memory (e.g., non-volatile memory) can be implemented as device-attached memory at a storage device such as a solid-state drive (SSD). Usage patterns of one or more pages of the device-attached memory can be monitored at the SSD, for example, by monitoring changes in the logical-to-physical (L2P) mapping of memory pages. For example, if the L2P mapping of a particular page is updated more frequently than a threshold level, which can be determined, for example, based on the average of some or all pages of the SSD, that particular page can be identified as a hot page. The SSD can initiate the migration of one or more hot pages, for example, by issuing an interrupt to the device driver at the host.

[0021] In some embodiments, a page fault handler can be used to migrate hot pages from a first type of memory to a second type of memory. For example, a device driver for a storage device with device-attached memory can set a write-protected state for one or more pages of the first type of memory that have been identified as hot pages. Subsequent writes to one of the write-protected pages can cause the page fault handler to migrate the accessed page from the first type of memory to the second type of memory. In some embodiments, a write-protected state for a hot page can be set, for example, by setting a write-protected bit in a page table entry pointing to the hot page.

[0022] In some embodiments, information for monitoring the usage patterns of one or more pages of the device-attached memory (MAP) may be stored in the MAP. For example, a portion of the MAP may be reserved for write counts or other metrics that may be used to determine usage patterns. The reserved portion may be accessible to the device and / or the host. For example, the device may update the write count for each page when the page's L2P mapping changes. The host may reset the page's write count when the page is deallocated and therefore no longer used by applications and / or processes at the host.

[0023] Figure 1 An example embodiment of a system according to an example embodiment of the present disclosure is shown, in which a host can access a device-attached memory. Figure 1 The system shown may include a host 102 and a device 104. The host 102 may include a central processing unit (CPU) 105 with a memory controller 106 and system memory 110. In some embodiments, the CPU 105 may execute software such as a device driver, a page fault processor, and / or other system software as described below. The system memory 110 may be implemented using any type of memory, such as volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc. However, in other embodiments, any other type of memory may be used.

[0024] Device 104 may include device memory 108. Device 104 may be implemented as a storage device such as a solid-state drive (SSD), wherein device memory 108 may be implemented using non-volatile memory (NVM) such as NAND flash memory. However, in other embodiments, any other type of device 104 and / or device memory 108 may be used.

[0025] Host 102 and device 104 can communicate via any type of interconnect 112 (such as a ComputeExpress Link (CXL)). Host 102 can access device memory 108 via interconnect 112 using any type of protocol. Figure 1 In the illustrated embodiment, host 102 may use the CXL.mem protocol 114, which is operable on CXL interconnect 112, to access device memory 108. The CXL.mem protocol may expose device memory 108 to host 102 in a manner that allows host 102 to access device memory 108 as if device memory 108 were part of system memory 110.

[0026] Figure 1 The configuration of the components shown is merely exemplary, and they may be arranged differently in other embodiments. For example, in other embodiments, the illustrated memory controller 106 and / or system memory 110 may be implemented separately from the host 102.

[0027] Figure 2 An example embodiment of a heterogeneous memory scheme according to an example embodiment of this disclosure is shown. For example, a heterogeneous memory scheme can be used... Figure 1 The system shown implements Figure 2 The memory scheme shown, but Figure 2 The memory scheme shown can also be implemented using other systems.

[0028] Figure 2 The illustrated memory scheme may include a first type of memory 208, a second type of memory 210, and a host 202 that can use the first type of memory 208 and the second type of memory 210. The first type of memory 208 may be implemented as, for example, volatile memory, such as NAND flash memory. The second type of memory 210 may be implemented as, for example, non-volatile memory, such as dynamic random access memory (DRAM).

[0029] In some embodiments, some or all of the first type of memory 208 may be implemented as device-attached memory, while some or all of the second type of memory 210 may be implemented as system memory. The device-attached memory may be exposed to the host 202 via an interconnect and / or a protocol such as CXL and / or CXL.mem. In some embodiments, the use of a consistent memory protocol such as CXL.mem may make the device-attached memory appear as system memory to the host 202. The first type of memory 208 and the second type of memory 210 may be mapped to one or more processes 216 running on the host 202 via a mapping scheme 218.

[0030] exist Figure 2 In the illustrated configuration, one or more processes 216 running on host 202 may utilize the first type of memory 208 in a manner that could reduce the lifespan of the first type of memory 208 and / or cause load imbalances that could degrade system performance. For example, in some embodiments, one or more pages of the first type of memory 208 may be frequently written to by process 216. However, because the first type of memory 208 may wear out after a finite number of writes, frequent updates may reduce the lifespan of the first type of memory 208.

[0031] Furthermore, because the first type of memory 208 can be implemented as device-attached memory rather than system memory, the host 202 may not be able to access information that could affect the lifespan and / or performance of the first type of memory 208. For example, if the device-attached memory 208 is implemented using non-volatile memory in a solid-state drive (SSD), frequent page updates may increase the number of invalid pages, which could trigger frequent garbage collection. This, in turn, reduces the lifespan of the non-volatile memory. Additionally, frequent page updates may degrade system performance, for example, by increasing tail latency, which may occur when an application waits for the longest-latency request to complete after issuing multiple access requests to the device-attached memory 208.

[0032] Figure 3 An example embodiment of a heterogeneous memory scheme with page migration according to an example embodiment of the present disclosure is shown. Figure 3 The illustrated embodiments may include those similar to Figure 2 The configuration shown includes a first-type memory 308, a second-type memory 310, and a host 302. However, Figure 3The illustrated embodiment may further include a monitoring process 320 that can monitor one or more pages 322 of the first type of memory 308 to determine one or more usage patterns of the one or more pages 322. For example, the monitoring process 320 may determine that one or more of the pages 322 may be hot pages that can be frequently accessed by a process 316 running on the host 302. The monitoring process 320 may send a migration signal 324 to migration logic 326 at the host 302 to identify one or more pages 322 that may be hot pages. The migration logic 326 may then control a mapping scheme 318 to migrate one or more hot pages 322 from the first type of memory 308 to the second type of memory 310 by remapping the one or more hot pages to one or more locations 328 in the second type of memory 310, as indicated by arrow 330.

[0033] Depending on the implementation details, Figure 3 The illustrated memory scheme can extend the lifespan of the first type of memory 308 and / or improve system performance. For example, if the first type of memory 308 is implemented as flash memory and the second type of memory 310 is implemented as DRAM, one or more hot pages that have been migrated to DRAM can be frequently rewritten without reducing the lifespan of the flash memory and / or introducing additional latency.

[0034] For illustrative purposes, some embodiments may be described in the context of device-attached memory. However, the principles associated with hot page migration can be applied to any memory context in which hot pages can be migrated from a first type of memory to a second type of memory. For example, these principles can be applied to embodiments in which the second type of memory can be implemented as system memory rather than device-attached memory. Furthermore, these principles can be applied to any type of memory with different characteristics that can benefit from migrating one or more pages from one type of memory to another based on monitoring and determining memory usage patterns.

[0035] For illustrative purposes, some embodiments may be described in the context of CXL interfaces and / or protocols. However, embodiments may also be implemented using any other interfaces and / or protocols, including cache-coherent and / or memory semantic interfaces and / or protocols such as Gen-Z, Coherent Accelerator Processor Interface (CAPI), Cache Coherent Interconnect for Accelerator (CCIX), etc. Other examples of suitable interfaces and / or protocols may include Fast Peripheral Component Interconnect (PCIe), Fast Non-Volatile Memory (NVMe), NVMe-over-fabric (NVMe-oF), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, and / or combinations thereof.

[0036] Figure 4 Another example embodiment of a heterogeneous memory scheme with page migration according to an example embodiment of the present disclosure is shown. Figure 4 The illustrated memory scheme may include device-attached memory 408 and system memory 410. In this example, device-attached memory 408 may be implemented using flash memory in an SSD 432, which may be exposed via a memory protocol such as CXL.mem. In this example, system memory 410 may be implemented using volatile memory such as DRAM.

[0037] A paging scheme 436 with one or more page tables 438a-d can be used to map device-attached memory 408 and system memory 410 to process virtual memory 434, where page tables 438a-d can provide the mapping to device-attached memory 408 and system memory 410. Figure 4In the example shown, four levels of paging can be used (e.g., page global directory (PGD) 438a, page upper directory (PUD) 438b, page middle directory (PMD) 438c, and page table entry (PTE) 438d), but other paging schemes can also be used. The process virtual memory 434 can be provided, for example, by a host (such as...) Figure 1 , Figure 2 and / or Figure 3 Used by one or more processes running on any of the hosts shown.

[0038] Refer again Figure 4 The SSD 432 may include monitoring logic 420, which can monitor the mapping 442 of logical block addresses (LBAs) 431 to physical block addresses (PBAs) 433 of the flash memory in the SSD 432. This LBA-to-PBA mapping can also be referred to as the L2P mapping 442. As shown by arrow 437, LBAs 431 can be exposed in the flash memory of the SSD 432 via CXL.mem.

[0039] Based on monitoring of the L2P mapping 442, monitoring logic 420 can determine that one or more pages 422 of the device-attached memory 408 are hot pages that can be accessed relatively frequently by one or more processes using the process virtual memory 434. Based on this determination, monitoring logic 420 can send a migration signal 424 to the paging scheme 436, which can trigger the migration of one or more hot pages 422 from the device-attached memory 408 to the system memory 410.

[0040] One or more hot pages 422 can initially be mapped using the original mapping 444 before migration. Based on the received migration signal 424, the paging scheme 436 can modify the mapping 440 to use the new mapping 446 after migration to migrate one or more hot pages 422 to a new location 428 in system memory 410 (as shown by arrow 430).

[0041] Figure 5 Another example embodiment of a heterogeneous memory scheme is shown, illustrating some possible implementation details of a page migration scheme according to an example embodiment of this disclosure. Figure 5The illustrated memory scheme may include device-attached memory 508 and system memory 510. Device-attached memory 508 may be implemented using one or more flash memory devices 554 in a CXL-enabled SSD 532, which may be exposed via a memory protocol such as CXL.mem. System memory 510 may be implemented using volatile memory such as DRAM.

[0042] A paging scheme 536 with page tables 538 and 539 can be used to map device-attached memory 508 and system memory 510 to process A virtual memory 534 and process B virtual memory 535. Page tables 538 and 539 can provide the mapping to device-attached memory 508 and system memory 510. Process virtual memories 534 and 535 can be respectively provided by, for example, in the host (e.g., Figure 1 , Figure 2 and / or Figure 3 The first process (process A) and the second process (process B) running on any host shown are used.

[0043] Refer again Figure 5 Device-attached memory may include one or more pages 522 that can be initially mapped to process virtual memory 534 and 535 using the initial mapping shown by solid line 544.

[0044] SSD 532 may include a flash translation layer (FTL) 548 that can map LBA 550 to PBA 552 of one or more flash devices 554. FTL 548 may include monitoring logic 520 that can monitor LBA-to-PBA mapping 556 to determine one or more usage patterns of one or more pages 522 of device-attached memory 508. For example, when a page 522 associated with a particular LBA 550C is first written to by a process using one of process virtual memories 534 and 535, the FTL can map LBA 550C to a first PBA 552B. The next time page 522 is written, the FTL can change the mapping, so LBA 550C is mapped to a second PBA 552C. The next time page 522 is written, the FTL can change the mapping again, so LBA 550C is mapped to a third PBA 552n.

[0045] Therefore, monitoring logic 520 can determine that one or more pages 522 of the device attached memory 508 may be frequently accessed hot pages. In some embodiments, monitoring logic 520 may monitor some or all of the LBA-to-PBA mappings 556 to establish an average number of mapping updates per page or other metrics for determining the usage patterns of pages in the device attached memory 508. Monitoring logic 520 may use an average or other metric as a threshold to which it can compare individual monitored pages. If the number of LBA-to-PBA mappings 556 for a particular page (e.g., on a total cumulative basis, during a rolling time window, and / or similar) exceeds the threshold, monitoring logic 520 may determine that the particular page is a hot page.

[0046] When monitoring logic 520 determines that one or more pages 522 of device-attached memory 508 are hot pages, monitoring logic 520 can trigger a migration by sending a migration message 524 to the device driver 558 of SSD 532, for example, on a host where process A and / or process B may be running. Figure 5 In the example shown, migration message 524 can be implemented as an interrupt (e.g., a hardware interrupt).

[0047] Based on the received interrupt 524, the device driver 558 can initiate the process of migrating one or more hot pages 522 from device-attached memory 508 to system memory 510 using the page fault processor 560. In some embodiments, the page fault processor 560 can be implemented as system software (e.g., as a component of the operating system kernel) that can be invoked when a page fault occurs. Page faults can occur for various reasons. Therefore, based on the received interrupt 524, the driver 558 can set protection bits for the hot page to cause a page fault when an application attempts to access the page.

[0048] In some embodiments, the page fault processor 560 can be used to swap pages between system memory 510 and a storage device. For example, if one of processes A or B attempts to access a requested page in system memory 510 that has been moved to a storage device, it may generate a page fault. Based on the page fault, the page fault processor 560 can retrieve the requested page from the storage device and swap it into system memory 510 so that it becomes available to the requesting process.

[0049] According to exemplary embodiments of this disclosure, Figure 5 The illustrated embodiment utilizes the page fault processor 560 (which may already exist in the system) by adapting the page fault processor 560 to perform hot page migration.

[0050] In this example, device driver 558 can set a write protection state (e.g., using write protection bits) for each hot page 522 in device-attached memory 508 detected by monitoring logic 520. The write protection state can be set in each of page tables 538 and 539, as shown by arrow 559. This can set a software trap that can be activated when a process attempts to write to one or more of the hot pages 522 that are already write-protected. Based on a write attempt to one of the write-protected pages 522, a page fault handler can migrate one or more hot pages 522 from the attached device's memory 508 to one or more new locations 528 in system memory 510, for example, by moving page data from device-attached memory 508 to system memory 510 as shown by arrow 530 and replacing the original mapping 544 with a new mapping as shown by dashed line 546.

[0051] In some embodiments, Figure 5 The memory scheme shown can implement a passive (e.g., efficient passive) page migration scheme, in which page 522, which has been identified as a hot page, is marked for migration (e.g., by marking it as write-protected). However, hot page 522 may not actually be migrated until it may be needed by a process such as, for example, indicated by an attempt to write to the hot page.

[0052] Figure 6 An embodiment of a system for storing information for determining the usage patterns of one or more memory pages, according to an example embodiment of the present disclosure, is shown. Figure 6 In the illustrated system, device 604 may include device-attached memory 608, which may be exposed, for example, via a memory protocol such as CXL.mem. A reserved portion 621 of the device-attached memory 608 may be reserved for information such as write counts, which may be used to determine the usage patterns of one or more pages of the first type of memory. In some embodiments, device 604 may be implemented as an SSD with an FTL 648 and monitoring logic 620. Monitoring logic 620 may increment the page write count each time a changed L2P mapping of a page is detected, as indicated by arrow 662. Monitoring logic 620 may also check the page write count each time a changed L2P mapping of a page is detected, as indicated by arrow 664, for example, to determine whether the page write count has reached a threshold indicating that the page can be considered a hot page. The monitoring logic may then send a migration message based on the detection of a hot page.

[0053] When a page is deallocated and is therefore no longer used by applications and / or processes on the host, a memory allocator 666, which may be located on, for example, the host, may reset the page write count, for example, by sending an update message, as shown by arrow 668.

[0054] Figure 7 An example embodiment of a host device that can be used to implement a page migration scheme according to an example embodiment of the present disclosure is shown. Figure 7 The host device 702 shown may include a processor 770, a memory controller 772, a page fault processor 760, a system memory 710, and an interconnect interface 774, which may be implemented, for example, using a CXL. Figure 7 Any or all of the components shown can communicate via system bus 776. In some embodiments, Figure 7 The host device 702 shown can be used to implement any of the host functions disclosed herein, including Figures 1 to 6 Any of the processing, mapping, paging, page fault handling, interrupt handling, and / or memory allocation functions disclosed in the illustrated embodiments.

[0055] Figure 8 An example embodiment of a device that can be used to implement a page migration scheme according to an example embodiment of the present disclosure is shown. Figure 8 The device 804 shown may include a device controller 880, a device function circuit 882, and an interconnection interface 884. Figure 8 Any or all of the components shown can communicate via system bus 886. Device functional circuitry 882 may include any hardware that implements the functionality of device 802. For example, if device 802 is implemented as a storage device, device functional circuitry 882 may include storage media such as one or more flash memory devices, FTL, etc. As another example, if device 804 is implemented as a network interface card (NIC), device functional circuitry 882 may include one or more modems, network interfaces, physical layer (PHY), media access control layer (MAC), etc. As another example, if device 804 is implemented as an accelerator, device functional circuitry 882 may include one or more accelerator circuits, memory circuits, etc. In some embodiments, Figure 8 The device 804 shown can be used to implement any function related to the devices and / or device-attached memory disclosed herein, including Figure 1-6 Any such function disclosed in the document.

[0056] In embodiments where device 804 can be implemented as a storage device, the storage device can be based on any type of storage medium, including magnetic media, solid-state media, optical media, etc. For example, in some embodiments, device 804 can be implemented as a NAND flash-based SSD, permanent memory such as cross-grid non-volatile memory, memory with varying bulk resistance, phase-change memory (PCM), etc., and / or any combination thereof. Such a storage device can be configured using any connector such as Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), U.2, etc., and implemented with any form factor such as 3.5-inch, 2.5-inch, 1.8-inch, M.2, Enterprise and Data Center SSD Form Factor (EDSFF), NF1, etc. Such a storage device can be implemented and / or used in conjunction with server chassis, server racks, data rooms, data centers, edge data centers, mobile edge data centers, and / or any combination thereof, wholly or partially.

[0057] Any features described in this article, including Figures 1-8 Any of the host functions, device functions, etc. described herein may be implemented in hardware, software, or any combination thereof, including combinational logic, sequential logic, one or more timers, counters, registers, state machines, volatile memory such as dynamic random access memory (DRAM) and / or static random access memory (SRAM), non-volatile memory such as flash memory including NAND flash memory, permanent memory such as cross-grid non-volatile memory, memory with varying volume resistance, and / or any combination thereof, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), central processing units (CPUs) such as complex instruction set computer (CISC) processors (such as x86 processors) and / or reduced instruction set computer (RISC) processors (such as ARM processors), graphics processing units (GPUs), neural processing units (NPUs), etc. In some embodiments, one or more components may be implemented as a system-on-a-chip (SOC).

[0058] Figure 9An embodiment of a method for managing a memory system according to an example embodiment of the present disclosure is shown. The method may begin at operation 902. At operation 904, the method may monitor pages of a first type of first memory. For example, in some embodiments, the method may monitor write counts of pages of device-attached non-volatile memory. At operation 906, the method may determine page usage based on the monitoring. For example, in some embodiments, the method may determine that a page may be a frequently accessed hot page based on changes in the page's logical-to-physical mapping. At operation 908, the method may migrate pages to a second type of second memory based on page usage. For example, in some embodiments, the method may migrate hot pages from non-volatile memory to volatile memory. The method may end at operation 910.

[0059] Figure 9 The embodiments shown, as well as all other embodiments described herein, are example operations and / or components. In some embodiments, some operations and / or components may be omitted, and / or other operations and / or components may be included. Furthermore, in some embodiments, the temporal and / or spatial order of operations and / or components may vary. Although some components and / or operations may be shown as separate components, in some embodiments, some components and / or operations shown separately may be integrated into a single component and / or operation, and / or some components and / or operations shown as single components and / or operations may be implemented using multiple components and / or operations.

[0060] Some embodiments disclosed above have been described in the context of various implementation details, but the principles of this disclosure are not limited to these or any other specific details. For example, some functions have been described as being implemented by certain components, but in other embodiments, the functions may be distributed among different systems and components in different locations and with various user interfaces. Some embodiments are described as having specific processes, operations, etc., but these terms also include embodiments in which a particular process, operation, etc. may be implemented by multiple processes, operations, etc., or in which multiple processes, operations, etc. may be integrated into a single process, step, etc. References to a component or element may refer only to a portion of that component or element. For example, a reference to an integrated circuit may refer to all or only a portion of the integrated circuit, and a reference to a block may refer to the entire block or one or more sub-blocks. The use of terms such as “first” and “second” in this disclosure and claims may be merely for distinguishing what they modify and may not indicate any spatial or temporal order unless otherwise apparent from the context. In some embodiments, a reference to something may refer to at least a portion of that thing; for example, “based on” may mean “at least partially based on”, etc. A reference to a first element does not imply the presence of a second element. The principles disclosed herein have independent utility and can be implemented individually, and not every embodiment can utilize every principle. However, these principles can also be embodied in various combinations, some of which can synergistically amplify the benefits of individual principles.

[0061] Based on the inventive principles of this disclosure, the various details and embodiments described above can be combined to produce other embodiments. Since modifications can be made to the arrangement and details of the inventive principles of this disclosure without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A method for managing a memory system, the method comprising: Monitor the frequency of changes in the logical-to-physical L2P mapping of pages in the first memory of the first type; Page usage is determined based on monitoring, wherein the usage is represented by the update frequency, which is the frequency of changes in the L2P mapping; and Based on page usage, the page is migrated to the second type of second memory. The determination of page usage includes comparing the update frequency of the page, represented by the frequency of changes in L2P mapping, with a threshold, wherein the threshold includes the average of the update frequencies of multiple pages of the first memory, represented by the frequency of changes in L2P mapping.

2. The method according to claim 1, wherein, The migration page includes sending an interrupt to the device driver.

3. The method according to claim 1, wherein, The migration page includes: Set the page to write-protected; and Pages are migrated by the page fault handler based on writes to the page.

4. The method according to claim 1, wherein, The first memory includes a device-attached memory.

5. The method according to claim 4, wherein, The device-attached memory is exposed via a memory protocol.

6. The method according to claim 5, wherein, The memory protocol includes a consistent memory protocol.

7. The method according to claim 1, wherein: The first memory includes non-volatile memory; and The second memory includes volatile memory.

8. An apparatus comprising: Memory; as well as The device controller is configured as follows: Monitor the frequency of changes in the logical-to-physical L2P mapping of memory pages; Page usage is determined based on monitoring, wherein the usage is represented by the update frequency, which is the frequency of changes in the L2P mapping; and Send instructions based on page usage. The determination of page usage includes comparing the update frequency of the page, represented by the frequency of changes in L2P mapping, with a threshold, wherein the threshold includes the average of the update frequencies of multiple pages of the first memory, represented by the frequency of changes in L2P mapping.

9. The device according to claim 8, wherein: The device includes a storage device; and The memory is exposed via a consistent memory protocol.

10. The device according to claim 8, wherein, The device controller is configured to store page usage information in the memory.

11. The device according to claim 10, wherein, The device controller is configured to: Receive update messages; and The usage information is updated based on the update message.

12. A system comprising: Host processor; The first type of first memory is arranged to be accessed by the host processor; The device interface is configured to expose a second type of second memory to the host processor; The monitoring logic is configured as follows: Monitor the frequency of changes in the logical-to-physical L2P mapping of pages in the second memory; Page usage is determined based on monitoring, wherein the usage is represented by the update frequency, which is the frequency of changes in the L2P map; as well as Send migration messages based on page usage; as well as The migration logic is configured as follows: Receive migration message; as well as Based on the migration message, the page is migrated to the first memory. The determination of page usage includes comparing the update frequency of the page, represented by the frequency of changes in L2P mapping, with a threshold, wherein the threshold includes the average of the update frequencies of multiple pages of the first memory, represented by the frequency of changes in L2P mapping.

13. The system according to claim 12, wherein, The migration logic includes a device driver configured to receive migration messages.

14. The system according to claim 12, wherein, The migration logic is configured to send an update message via the device interface based on migrating a page from the second memory to the first memory.

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