Memory devices, semiconductor systems, and data processing systems

Abstract

The present disclosure relates to a memory device including a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing a burst operation supporting a variable burst address gap based on an address, a burst length, and a burst address gap provided from a memory controller. The burst address gap is a numerical difference between adjacent column addresses for which the burst operation is to be performed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0071108, filed on June 1, 2021, which is incorporated herein by reference in its entirety as described herein. Technical Field

[0003] The various embodiments of this disclosure relate to an integrated circuit technology, and more particularly, to a memory device, a semiconductor system, and a data processing system using the latter. Background Technology

[0004] Electronic devices can include many electronic components. Furthermore, a computer system, as an electronic device, includes many electronic components, each made of semiconductors. Within the semiconductor devices constituting a computer system, a host, such as a processor or memory controller, can perform data communication with the memory devices. A memory device includes multiple memory cells, each identified by word lines and bit lines. The memory device is configured to store data therein. Data to be stored in the memory device includes matrices. During artificial intelligence (AI) training operations, matrices can be read from the memory device to be used as either the original matrix or its transpose. Summary of the Invention

[0005] In embodiments of this disclosure, a memory device may include a memory cell array and peripheral circuitry. The memory cell array may include multiple memory regions, each identified by a corresponding row address and a corresponding column address. The peripheral circuitry can access the memory cell array by performing burst operations supporting variable burst address gaps based on addresses, burst lengths, and burst address gaps provided from a memory controller. The burst address gap is the numerical difference between adjacent column addresses to which a burst operation is to be performed.

[0006] In one embodiment, a semiconductor system may include a memory device and a memory controller. The memory device may include a memory cell array and peripheral circuitry. The memory cell array may include multiple memory regions. The peripheral circuitry can access the memory cell array by performing a burst operation supporting a variable burst address gap. The memory controller can provide the memory device with an address, a burst length, and a burst address gap to control the burst operation. The burst address gap is the numerical difference between adjacent column addresses for which a burst operation is to be performed.

[0007] In embodiments of this disclosure, a semiconductor system may include a plurality of memory devices and a memory controller. The memory controller may be connected to the plurality of memory devices via a plurality of device line groups and to a host device via system lines. The memory controller may include a write data processing component. The write data processing component may receive from the host device basic device information indicating the underlying devices among the plurality of memory devices, a mapping based on the basic device information, the plurality of device line groups, and a plurality of system line groups partitioned from the system lines, and transmits data provided from the host device via the plurality of system line groups to the plurality of device line groups mapped to the plurality of system line groups.

[0008] In embodiments of this disclosure, a data processing system may include a semiconductor system and a host device. The semiconductor system may include multiple memory devices and a memory controller. The memory controller may be connected to the multiple memory devices via multiple device line groups. The host device may be connected to the memory controller via system lines and may provide the memory controller with basic device information indicating the underlying devices among the multiple memory devices. To store a matrix in the semiconductor system, the host device may transmit multiple elements of the matrix in parallel to multiple system line groups partitioned from the system lines. The memory controller may map the multiple system line groups to multiple device line groups based on the basic device information to store the matrix in the multiple memory devices. The precision of the matrix may be the same as the bit width of each of the multiple device line groups.

[0009] In embodiments of this disclosure, a method of operating a data processing system includes a host and a memory system. The method may include: the host repeatedly providing the memory system with a first row address, a first starting column address, and a second number of elements belonging to a row of a matrix; and the memory system, in response to the first provision, performing a write operation to sequentially store the provided elements into memory regions indicated by the first row address and the second number of column addresses, the second number of column addresses starting from the first starting column address and having a second number of numerical differences between adjacent column addresses. The first number can be obtained by dividing the number of elements constituting a row by the second number. The first provision may include, in each repetition, changing the first row address to a row address that continuously increases from the row address of the initial element of the row to be stored in the memory region. The first starting column address may be the column address of the initial element of the row to be stored in the memory region.

[0010] In embodiments of this disclosure, the operation method of the data processing system may further include: the host performing a first number of repetitions to provide a first row address and a first starting column address to the memory system a second time; and the memory system, in response to the second provision, performing a read operation to sequentially and separately read a second number of elements belonging to the row from the memory region indicated by the first row address and the second number of column addresses. The second provision may include changing the first row address to a continuously increasing row address in each repetition.

[0011] In embodiments of this disclosure, the operation method of the data processing system may further include: the host performing a third repetition of providing a second row address and a second starting column address to the memory system for a second time; and the memory system, in response to the second provision, performing a read operation to sequentially and separately read a second number of elements belonging to a matrix column from a memory region indicated by a second number of consecutive column addresses starting from the second row address and the second starting column address. The third number can be obtained by dividing the number of elements constituting the column by the second number. The second provision may include, in each repetition, changing the second row address by adding a plurality of second number of row addresses from the row address of the memory region where the initial element of the column is stored. The second starting column address may be the column address of the memory region where the initial element of the column is stored. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a semiconductor system including a memory device supporting variable burst address gap (BAG) according to an embodiment of the present disclosure.

[0013] Figure 2A and Figure 2B This illustrates an embodiment according to the present disclosure. Figure 1 A diagram illustrating the process by which a memory device performs burst operations that support burst address gaps.

[0014] Figure 3 This is a diagram illustrating the process of storing a 16×16 matrix into a memory device according to an embodiment of the present disclosure.

[0015] Figure 4 This is a diagram illustrating the process of obtaining the original matrix from the memory device via a burst read operation when the matrix is ​​stored in the memory device according to a row-major scheme, according to an embodiment of the present disclosure.

[0016] Figure 5 This is a diagram illustrating the process of obtaining a transposed matrix from a memory device via a burst read operation when the matrix is ​​stored in the memory device according to a row-major scheme, according to an embodiment of the present disclosure.

[0017] Figure 6This is a diagram illustrating the process of storing a 16×16 matrix into a memory device supporting variable burst address gaps according to an embodiment of the present disclosure.

[0018] Figure 7 This is a diagram illustrating the process of obtaining the original matrix from a memory device via a burst read operation according to an embodiment of the present disclosure.

[0019] Figure 8 This is a diagram illustrating the process of obtaining a transpose matrix from a memory device via a burst read operation according to an embodiment of the present disclosure.

[0020] Figure 9 This is a block diagram illustrating a data processing system including a semiconductor system according to an embodiment of the present disclosure.

[0021] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 A block diagram of the write data processing component.

[0022] Figure 11 and Figure 12 This illustrates an embodiment according to the present disclosure. Figure 10 A diagram illustrating the line mapping operation of the write data processing component.

[0023] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 9 A block diagram of the data reading and processing component.

[0024] Figure 14 and Figure 15 This illustrates an embodiment according to the present disclosure. Figure 13 A diagram illustrating the line mapping operation of the data reading and processing component.

[0025] Figure 16 This illustrates an embodiment according to the present disclosure. Figure 9 A block diagram of the address translation component.

[0026] Figure 17 This illustrates storing a 16×16 matrix according to an embodiment of the present disclosure. Figure 9 A diagram illustrating the process in a semiconductor system.

[0027] Figure 18 and Figure 19 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which a semiconductor system obtains rows of a matrix.

[0028] Figure 20 and Figure 21 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which a semiconductor system obtains the columns of a matrix.

[0029] Figure 22 This illustrates storing a 16×16 matrix according to an embodiment of the present disclosure. Figure 9 A diagram illustrating the process in a semiconductor system.

[0030] Figure 23 and Figure 24 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which a semiconductor system obtains rows of a matrix.

[0031] Figure 25 and Figure 26 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which a semiconductor system obtains the columns of a matrix. Detailed Implementation

[0032] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0033] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. The terminology used herein is for describing particular embodiments only and is not intended to limit this disclosure.

[0034] As used herein, the term “and / or” includes at least one of the associated items listed. It will be understood that when an element is referred to as “connected to” or “linked to” another element, the element may be directly on, directly connected to, or linked to the other element, or one or more intermediate elements may be present. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form, and vice versa. It will be further understood that when the terms “comprising,” “including,” “including,” and “comprise” are used in this specification, the term specifies the presence of the stated element and does not exclude the presence or addition of one or more other elements.

[0035] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0036] According to embodiments, a memory device, semiconductor system, and data processing system may be provided that can efficiently store a matrix therein and can read the original matrix or transpose matrix at a low cost to use the read matrix.

[0037] Figure 1This is a block diagram illustrating a semiconductor system 100 including a memory device 120 supporting variable burst address gap (BAG) according to an embodiment of the present disclosure.

[0038] Reference Figure 1 The semiconductor system 100 may include a memory controller 110 and a memory device 120.

[0039] The memory controller 110 can provide various control signals required for the operation of the memory device 120. The memory controller 110 can be embedded in various types of host devices. Host devices may include central processing units (CPUs), graphics processing units (GPUs), multimedia processors (MMPs), digital signal processors, application processors (APs), etc. In embodiments, the memory controller 110 may be stacked together with the memory device 120 on a single substrate to be packaged into a single package. The memory device 120 may include dynamic random access memory (DRAM).

[0040] The memory controller 110 can control the memory device 120 to store data DATA in the memory device 120 and to read data DATA from the memory device 120. The memory controller 110 can provide the memory device 120 with an address AD for write or read operations.

[0041] The memory device 120 may include a mode register group 121, peripheral circuitry 122, and a memory cell array 123.

[0042] The mode register group 121 can store parameter values ​​for the operation of the memory device 120. For example, the mode register group 121 can store the burst length BL and burst address gap BAG set by the memory controller 110.

[0043] When the memory controller 110 commands a burst operation, the peripheral circuit 122 can access the memory cell array 123 by performing a burst operation that supports variable burst address gaps, based on the address AD provided by the memory controller 110 and the burst length BL and burst address gap BAG stored in the mode register group 121. The peripheral circuit 122 can access the memory cell array 123 to store data DATA provided by the memory controller 110 into the memory cell array 123, and to provide the memory controller 110 with data DATA read from the memory cell array 123.

[0044] The memory cell array 123 may include a plurality of memory cells configured to store data DATA. Under the control of the peripheral circuitry 122, the memory cell array 123 may store the data DATA provided from the memory controller 110 in the memory cell array 123, and may provide the data DATA stored in the memory cell array 123 to the peripheral circuitry 122.

[0045] In this disclosure, a dataset DQ can be a group or unit of data DATA that is input to or output from memory device 120 at a time via a DQ pin connected to memory device 120. For example, when memory device 120 is connected to memory controller 110 via eight DQ pins, each dataset DQ can be configured to be 8 bits.

[0046] In this disclosure, a burst write operation can be performed by memory device 120 and can be an operation of continuously receiving a number of datasets DQ corresponding to a burst length BL and sequentially storing the datasets DQ into memory cell array 123 in response to a single write command (e.g., a burst write command) provided from memory controller 110. In this disclosure, a burst read operation can be performed by memory device 120 and can be an operation of continuously reading a number of datasets DQ corresponding to a burst length BL from memory cell array 123 and sequentially providing the read datasets DQ to memory controller 110 in response to a single read command (e.g., a burst read command) provided from memory controller 110. The burst length BL can represent the number of datasets DQ to be written to or read from memory cell array 123 by a burst write operation or burst read operation of memory device 120. The burst length BL can be selected by memory controller 110.

[0047] In this embodiment, burst operations may support a variable burst address gap (BAG). The burst address gap (BAG) may represent the numerical difference between adjacent column addresses performing a burst write or burst read operation. The burst address gap (BAG) may represent the numerical difference between adjacent column addresses, which corresponds to the number of memory regions to be written to or data sets (DQ) to be read from the memory region, as indicated by the burst length (BL). The column address serving as the target address for a burst write / read operation may start from a starting column address, and the numerical difference between adjacent column addresses may be the amount of the burst address gap (BAG). The number of column addresses serving as the target address for a burst write / read operation may correspond to the burst length (BL). The burst address gap (BAG) may be a positive number greater than one (1). The burst address gap (BAG) may be selected by the memory controller 110.

[0048] Figure 2A and Figure 2BThis illustrates an embodiment according to the present disclosure. Figure 1 A diagram illustrating the process by which the memory device 120 performs a burst operation supporting burst address gap (BAG).

[0049] Reference Figure 2A , Figure 1 The memory cell array 123 may include memory regions M1 to M16 that collectively correspond to the first row address RAD1 and respectively correspond to consecutive first column addresses CAD1 to sixteenth column addresses CAD16. Each of the memory regions M1 to M16 may store a single dataset DQ. The memory regions M1 to M16 may be contained within the same page. In an embodiment, the number of consecutive column addresses corresponding to the page may be greater than or less than sixteen (16).

[0050] The memory controller 110 can command the memory device 120 a burst write operation with a burst length BL of four (4) and a burst address gap BAG of one (1). A burst address gap BAG of one (1) indicates that the numerical difference between adjacent column addresses to be used in the burst write operation is one (1). For the burst write operation, the memory controller 110 can provide the memory device 120 with a first row address RAD1, a first column address CAD1, and datasets DQ1 to DQ4. The first column address CAD1 can be the starting column address of the burst write operation to be performed. The first row address RAD1 and the first column address CAD1 can be used as... Figure 1 The address AD is provided to memory device 120.

[0051] Therefore, the memory device 120 can store datasets DQ1 to DQ4 into memory regions M1 to M4 corresponding to the first row address RAD1 and the consecutive first column addresses CAD1 to fourth column addresses CAD4, respectively. Since the value of the burst address gap BAG is one (1), the numerical difference between adjacent column addresses in the column addresses CAD1 to CAD4 corresponding to the memory regions M1 to M4 storing each dataset DQ1 to DQ4 can be one (1).

[0052] Burst operations that support a burst address gap BAG value of one (1) can store data in essentially the same way as burst operations that do not support a burst address gap BAG.

[0053] Reference Figure 2BThe memory controller 110 can command the memory device 120 a burst write operation with a burst length BL of four (4) and a burst address gap BAG of four (4). A burst address gap BAG of four (4) indicates that the numerical difference between adjacent column addresses to be used in the burst write operation is four (4). For the burst write operation, the memory controller 110 can provide the memory device 120 with a first row address RAD1, a first column address CAD1, and datasets DQ1 to DQ4. The first column address CAD1 can be the starting column address for the burst write operation to be performed.

[0054] Therefore, the memory device 120 can store datasets DQ1 to DQ4 into memory regions M1, M5, M9, and M13, respectively, corresponding to the first row address RAD1 and the first column address CAD1, the fifth column address CAD5, the ninth column address CAD9, and the thirteenth column address CAD13. Since the burst address gap BAG has a value of four (4), the numerical difference between adjacent column addresses in the first column address CAD1, the fifth column address CAD5, the ninth column address CAD9, and the thirteenth column address CAD13, respectively, corresponding to the memory regions M1, M5, M9, and M13 storing each dataset DQ1 to DQ4, can be four (4).

[0055] Burst address gap (BAG) can be applied to burst read operations in a manner similar to burst write operations. For reading such... Figure 2A The memory controller 110 can command the memory device 120 to perform a burst read operation with the burst length BL set to four (4), the burst address gap BAG set to one (1), and the first column address CAD1 as the starting column address, for the stored datasets DQ1 to DQ4. Figure 2B The memory controller 110 can command the memory device 120 to perform a burst read operation with the burst length BL set to four (4), the burst address gap BAG set to four (4), and the first column address CAD1 as the starting column address, for the stored datasets DQ1 to DQ4.

[0056] Figure 3 This is a diagram illustrating the process of storing a 16×16 matrix into memory device 120. In this disclosure, the N×N matrix may be an N×N array of a dataset DQ. Elements within the matrix may be a single dataset DQ. N×N memory regions may be required to store the N×N matrix.

[0057] Reference Figure 3The memory device 120 may include pages P1 to P16, each corresponding to a consecutive first row address RAD1 to a sixteenth row address RAD16. Each of pages P1 to P16 may include a memory region corresponding to consecutive column addresses CAD1 to CAD16. Each memory region included in the memory device 120 may be identified by a single row address and a single column address. Each memory region may store each element of a matrix. Each element within the matrix may be represented by the matrix's row number and column number. Figure 3 As shown, between the two numbers marked in the element EM, the left sixteen (16) can represent the sixteenth row RAD16 corresponding to the element EM in the matrix, and the right one (1) can represent the first column CAD1 corresponding to the element EM in the matrix.

[0058] The number of bits or bit width of each element constituting the matrix, i.e., the bit size of the dataset DQ, can represent the precision of the matrix. When the precision of the matrix is ​​the same as the number of data pins or the device input / output bit width of the memory device 120, the elements of the matrix can be stored in various memory areas.

[0059] like Figure 3 As shown, the matrix can be stored in the memory device 120 according to a row-major scheme. That is, the rows of the matrix can be stored in separate pages. For example, the first row of the matrix can be stored in the first page P1 corresponding to the first row address RAD1, the second row of the matrix can be stored in the second page P2 corresponding to the second row address RAD2, and the sixteenth row of the matrix can be stored in the sixteenth page P16 corresponding to the sixteenth row address RAD16.

[0060] and Figure 3 Depending on the diagram, the matrix can be stored in memory device 120 according to a column-major scheme. The columns of the matrix can be stored in individual pages. For example, the first column of the matrix can be stored in the first page P1 corresponding to the first row address RAD1, the second column can be stored in the second page P2 corresponding to the second row address RAD2, and the sixteenth column can be stored in the sixteenth page P16 corresponding to the sixteenth row address RAD16. That is, given... Figure 3 The array of memory regions shown can store the matrix as the original matrix according to the row-major scheme, and can also store the matrix as the transpose matrix according to the column-major scheme.

[0061] In data processing operations such as deep learning training in artificial intelligence (AI) systems, both the original matrix and its transpose can be used. However, due to the limited storage capacity of memory device 120, it may be difficult to store both the original matrix and its transpose in memory device 120. Therefore, for example, the matrix can be stored in memory device 120 as the original matrix according to a row-major scheme, and can be stored by referring to... Figure 4 and Figure 5 The process described is to obtain the original matrix and the transpose matrix of the matrix.

[0062] Figure 4 This is a diagram illustrating the process of obtaining the original matrix from memory device 120 via a burst read operation when the matrix is ​​stored in memory device 120 according to a row-major scheme, according to an embodiment of the present disclosure. Figure 4 In one embodiment, memory device 120 does not use burst address gap (BAG).

[0063] Reference Figure 4 , as reference Figure 3 As described, the matrix can be stored in memory device 120 according to a row-first scheme. Memory controller 110 can obtain the first row of the matrix through first burst read operations BR1 to fourth burst read operations BR4 with a burst length BL of four (4).

[0064] Specifically, memory controller 110 can provide memory device 120 with a first row address RAD1 and a first column address CAD1 for the first burst read operation BR1. Memory device 120 can perform the first burst read operation BR1 with the first column address CAD1 as the starting column address. Therefore, memory controller 110 can obtain the elements of the first column to the fourth column of the first row from the matrix.

[0065] The memory controller 110 can provide the memory device 120 with the first row address RAD1 and the fifth column address CAD5 for the second burst read operation BR2. The memory device 120 can perform the second burst read operation BR2 with the fifth column address CAD5 as the starting column address. Therefore, the memory controller 110 can obtain the elements of the fifth to eighth columns of the first row from the matrix.

[0066] The memory controller 110 can provide the memory device 120 with the first row address RAD1 and the ninth column address CAD9 for the third burst read operation BR3. The memory device 120 can perform the third burst read operation BR3 with the ninth column address CAD9 as the starting column address. Therefore, the memory controller 110 can obtain the elements of the ninth to twelfth columns of the first row from the matrix.

[0067] The memory controller 110 can provide the memory device 120 with the first row address RAD1 and the thirteenth column address CAD13 for the fourth burst read operation BR4. The memory device 120 can perform the fourth burst read operation BR4 with the thirteenth column address CAD13 as the starting column address. Therefore, the memory controller 110 can obtain the elements of the first row, columns thirteen through sixteen, from the matrix.

[0068] Rows two through sixteen can be obtained from the matrix in a similar manner to row one above. That is, rows one through sixteen can be obtained sequentially using burst read operations from the addresses of row one through row sixteen. Therefore, the original matrix can be obtained relatively easily.

[0069] Figure 5 This is a diagram illustrating the process of obtaining a transposed matrix from memory device 120 via a burst read operation when the matrix is ​​stored in memory device 120 according to a row-major scheme, according to an embodiment of the present disclosure. Figure 5 In one embodiment, memory device 120 does not use burst address gap (BAG).

[0070] Reference Figure 5 , as reference Figure 3 As described, the matrix can be stored in memory device 120 according to a row-first scheme. Memory controller 110 can obtain the first column of the matrix through a first burst read operation BR1 to a sixteenth burst read operation BR16 with a burst length BL of four (4).

[0071] Specifically, the memory controller 110 can provide the memory device 120 with a first row address RAD1 and a first column address CAD1 for the first burst read operation BR1. Therefore, the memory controller 110 can obtain the elements of the first row and the first to fourth columns from the matrix.

[0072] The memory controller 110 can provide the memory device 120 with a second row address RAD2 and a first column address CAD1 for the second burst read operation BR2. Therefore, the memory controller 110 can obtain the elements of the first to fourth columns of the second row from the matrix.

[0073] In a similar manner, the elements of the first to fourth columns of each row from the third to the sixteenth row can be obtained from the matrix through the third burst read operation BR3 to the sixteenth burst read operation BR16.

[0074] Upon completion of all first burst read operations BR1 to sixteenth burst read operations BR16, columns one through four of the matrix can be read. Of the first through fourth columns read, the first column can be used as the first row of the transposed matrix, and the remaining second through fourth columns can be temporarily stored in a separate memory (e.g., SRAM) to be used as the second through fourth rows of the transposed matrix.

[0075] In summary, when the matrix is ​​stored in memory device 120 according to the row pre-planning scheme, obtaining the transposed matrix may take more time and resources than obtaining the original matrix. Without a separate memory such as SRAM, the number of read operations may increase significantly.

[0076] When the matrix is ​​stored in the memory device 120 according to a column-major scheme, the process of obtaining the original matrix and the transpose matrix can be performed in the same manner as described above. When the matrix is ​​stored in the memory device 120 according to a column-major scheme, it can be performed according to reference... Figure 4 The transpose matrix is ​​obtained in the manner described, and can be obtained according to the reference. Figure 5 The original matrix is ​​obtained by describing the method.

[0077] In this embodiment, the matrix can be efficiently stored in the memory device 120 through the variable burst address gap, and the original matrix and transpose matrix can be obtained from the memory device 120 with less time and less resources, as will be described below.

[0078] Figure 6 This is a diagram illustrating the process of storing a 16×16 matrix into a memory device 120 that supports variable burst address gaps according to an embodiment of the present disclosure.

[0079] Reference Figure 6 When the precision of the matrix is ​​the same as the number of data pins or the device input / output bit width of the memory device 120, the elements of the matrix can be stored in a memory area within the memory device 120, identified by a single row address and a single column address.

[0080] The memory controller 110 can store the matrix in the memory device 120 through a burst write operation with a burst length BL of four (4) and a burst address gap BAG of four (4). Figure 6 The diagram shows four elements, bl0, bl1, bl2, and bl3, continuously supplied to memory device 120 when the burst length BL is four (4). The memory controller 110 can use the same values ​​for both the burst address gap (BAG) and the burst length BL. In an embodiment, the memory controller 110 can use values ​​other than four (4) for both the burst length BL and the burst address gap (BAG).

[0081] Specifically, the memory controller 110 can store the first row of the matrix into the memory device 120 through the first burst write operation BW1 to the fourth burst write operation BW4.

[0082] For the first burst write operation BW1, the memory controller 110 may provide the memory device 120 with a first row address RAD1, a first column address CAD1, and the elements bl0, bl1, bl2, and bl3 of the first column to the fourth column of the first row of the matrix. The memory device 120 may execute the first burst write operation BW1 with a burst length BL of four (4) and a burst address gap BAG of four (4) starting from the first column address CAD1 of the first row address RAD1.

[0083] For the second burst write operation BW2, the memory controller 110 may provide the memory device 120 with the second row address RAD2, the first column address CAD1, and the elements bl0, bl1, bl2, and bl3 of the fifth to eighth columns of the first row of the matrix. The memory device 120 may execute the second burst write operation BW2, starting from the first column address CAD1 of the second row address RAD2, with a burst length BL of four (4) and a burst address gap BAG of four (4).

[0084] For the third burst write operation BW3, the memory controller 110 may provide the memory device 120 with the third row address RAD3, the first column address CAD1, and the elements bl0, bl1, bl2, and bl3 of the ninth to twelfth columns of the first row of the matrix. The memory device 120 may execute the third burst write operation BW3 starting from the first column address CAD1 of the third row address RAD3, with a burst length BL of four (4) and a burst address gap BAG of four (4).

[0085] For the fourth burst write operation BW4, the memory controller 110 may provide the memory device 120 with the fourth row address RAD4, the first column address CAD1, and the elements bl0, bl1, bl2, and bl3 of the thirteenth to sixteenth columns of the first row of the matrix. The memory device 120 may execute the fourth burst write operation BW4, starting from the first column address CAD1 of the fourth row address RAD4, with a burst length BL of four (4) and a burst address gap BAG of four (4).

[0086] The second row of the matrix can be stored in the memory device 120 via fifth burst write operations BW5 to eighth burst write operations BW8, similar to the method described above for the first row of the matrix, by using the second column address CAD2, after the first column address CAD1 used as the starting column address for storing the first row, as the starting column address for storing the second row. The third row of the matrix can be stored in the memory device 120 by using the third column address CAD3 as the starting column address for storing the third row. The fourth row of the matrix can be stored in the memory device 120 by using the fourth column address CAD4 as the starting column address for storing the fourth row.

[0087] In a similar manner, the remaining rows of the matrix can be stored in pages corresponding to the addresses of the four rows for every four rows.

[0088] In an embodiment, the address of the memory region of the (i,j)th element of the storage matrix within the memory device 120 supporting variable burst address gaps can be determined according to Equation 1 below.

[0089] Equation 1:

[0090] The address of the memory region of the (i,j)th element of the storage matrix = Baddr + (i – i % (bl+1)) * Mcol + i % (bl+1) – 1 + (j-1) * bl

[0091] In Equation 1, "Baddr" can represent the address of the memory region storing the (1,1)th element of the matrix. "Mcol" can represent the number of columns in the matrix. "%" can represent the modulo operation. "bl" can represent the burst length BL. The burst address gap BAG can be set to have the same value as the burst length BL.

[0092] In an embodiment, the burst write operations (e.g., first burst write operations BW1 to fourth burst write operations BW4) for storing each row (e.g., the first row) of the matrix can be performed as many times as the value obtained by dividing the number of elements (e.g., sixteen (16)) constituting each row by the burst length BL (e.g., four (4)). The row address of the burst write operations (e.g., first burst write operations BW1 to fourth burst write operations BW4) for storing each row (e.g., the first row) of the matrix can be a series of consecutive row addresses (e.g., first row address RAD1 to fourth row address RAD4) starting from the row address of the initial element of each row of the matrix determined by Equation 1 (e.g., first row address RAD1). Each of the starting column addresses of the burst write operations (e.g., first burst write operations BW1 to fourth burst write operations BW4) for storing each row (e.g., the first row) of the matrix can be the column address of the initial element of the row of the matrix determined by Equation 1 (e.g., first column address CAD1). The initial element of each row of a matrix can be the element of the first column of that row.

[0093] Figure 7 This is a diagram illustrating the process of obtaining the original matrix from the memory device 120 via a burst read operation according to an embodiment of the present disclosure.

[0094] Reference Figure 7 , as reference Figure 6 The matrix can be stored in memory device 120. When the original matrix is ​​needed, memory controller 110 can read the first row of the matrix through first burst read operations BR1 to fourth burst read operations BR4. The burst length BL can be four (4). That is, the burst length BL used when reading the matrix from memory device 120 can be the same as the burst length BL used when storing the matrix in memory device 120. The burst address gap BAG can be four (4). That is, the burst address gap BAG used when reading rows of the matrix from memory device 120 can be the same as the burst address gap BAG used when storing rows of the matrix in memory device 120. That is, the burst address gap BAG can be the same as the burst length BL.

[0095] For the first burst read operation BR1, the memory controller 110 can provide the memory device 120 with a first row address RAD1 and a first column address CAD1. The memory device 120 can execute the first burst read operation BR1 with a burst address gap BAG value of four (4) starting from the first column address CAD1 of the first row address RAD1. Therefore, the memory controller 110 can obtain the elements of the first column to the fourth column of the first row in the matrix.

[0096] For the second burst read operation BR2, the memory controller 110 can provide the memory device 120 with the second row address RAD2 and the first column address CAD1. The memory device 120 can execute the second burst read operation BR2 with a burst address gap BAG value of four (4) starting from the first column address CAD1 of the second row address RAD2. Therefore, the memory controller 110 can obtain the elements of the fifth to eighth columns of the first row in the matrix.

[0097] For the third burst read operation BR3, the memory controller 110 can provide the memory device 120 with the third row address RAD3 and the first column address CAD1. The memory device 120 can execute the third burst read operation BR3 with a burst address gap BAG value of four (4) starting from the first column address CAD1 of the third row address RAD3. Therefore, the memory controller 110 can obtain the elements of the ninth to twelfth columns of the first row in the matrix.

[0098] For the fourth burst read operation BR4, the memory controller 110 can provide the memory device 120 with the fourth row address RAD4 and the first column address CAD1. The memory device 120 can execute the fourth burst read operation BR4 with a burst address gap BAG value of four (4) starting from the first column address CAD1 of the fourth row address RAD4. Therefore, the memory controller 110 can obtain the elements of the thirteenth to sixteenth columns of the first row in the matrix.

[0099] The second row of the matrix can be obtained from the memory device 120 in a manner similar to that of the first row of the matrix described above, by using the second column address CAD2, which is used as the starting column address for reading the first row, after the first column address CAD1. That is, each row of the matrix can be obtained from the memory device 120 by a process that is the reverse of the process of storing that row in the memory device 120.

[0100] In an embodiment, burst read operations (e.g., first burst read operations BR1 to fourth burst read operations BR4) for reading each row (e.g., the first row) of the matrix can be performed as many times as the value obtained by dividing the number of elements (e.g., sixteen (16)) constituting each row by the burst length BL (e.g., four (4)). The row address of the burst read operations (e.g., first burst read operations BR1 to fourth burst read operations BR4) for reading each row (e.g., the first row) of the matrix can be a series of consecutive row addresses (e.g., first row address RAD1 to fourth row address RAD4) starting from the row address of the initial element of each row of the matrix as determined by Equation 1 (e.g., first row address RAD1). Each of the starting column addresses of the burst read operations (e.g., first burst read operations BR1 to fourth burst read operations BR4) for reading each row (e.g., the first row) of the matrix can be the column address of the initial element of the row of the matrix as determined by Equation 1 (e.g., first column address CAD1). The initial element of each row of the matrix can be the element of the first column of that row of the matrix.

[0101] Figure 8 This is a diagram illustrating the process of obtaining a transpose matrix from a memory device 120 via a burst read operation according to an embodiment of the present disclosure.

[0102] Reference Figure 8 , as reference Figure 6 The matrix can be stored in memory device 120. When the matrix needs to be transposed, memory controller 110 can read the first column of the matrix through first burst read operations BR1 to fourth burst read operations BR4. The burst length BL can be four (4). That is, the burst length BL used when reading the matrix from memory device 120 can be the same as the burst length BL used when storing the matrix in memory device 120. The burst address gap BAG can be one (1). That is, the burst address gap BAG used when reading columns of the matrix from memory device 120 can be different from the burst address gap BAG used when storing rows of the matrix in memory device 120.

[0103] For the first burst read operation BR1, the memory controller 110 can provide the memory device 120 with a first row address RAD1 and a first column address CAD1. The memory device 120 can execute the first burst read operation BR1 with a burst address gap BAG value of 1 (1) starting from the first column address CAD1 of the first row address RAD1. Therefore, the memory controller 110 can obtain the elements of the first column of the first row to the fourth row in the matrix.

[0104] For the second burst read operation BR2, the memory controller 110 can provide the memory device 120 with the fifth row address RAD5 and the first column address CAD1. The memory device 120 can execute the second burst read operation BR2 with the burst address gap BAG value of one (1) starting from the first column address CAD1 of the fifth row address RAD5. Therefore, the memory controller 110 can obtain the elements of the first column of the fifth row to the eighth row in the matrix.

[0105] For the third burst read operation BR3, the memory controller 110 can provide the memory device 120 with the ninth row address RAD9 and the first column address CAD1. The memory device 120 can execute the third burst read operation BR3 with the burst address gap BAG set to one (1) starting from the first column address CAD1 of the ninth row address RAD9. Therefore, the memory controller 110 can obtain the elements of the first column from the ninth row to the twelfth row in the matrix.

[0106] For the fourth burst read operation BR4, the memory controller 110 can provide the memory device 120 with the thirteenth row address RAD13 and the first column address CAD1. The memory device 120 can execute the fourth burst read operation BR4 with the burst address gap BAG value of one (1) starting from the first column address CAD1 of the thirteenth row address RAD13. Therefore, the memory controller 110 can obtain the elements of the first column from the thirteenth row to the sixteenth row in the matrix.

[0107] The second column of the matrix can be obtained from the memory device 120 in a manner similar to the first column of the matrix as described above, by using the fifth column address CAD5, which is a larger than the burst length BL of the first column address CAD1 used as the starting column address for reading the first column, as the starting column address for reading the second column.

[0108] In an embodiment, burst read operations (e.g., first burst read operation BR1 to fourth burst read operation BR4) for reading each column (e.g., the first column) of the matrix can be performed as many times as the value obtained by dividing the number of elements (e.g., sixteen (16)) constituting each column by the burst length BL (e.g., four (4)). The row address of the burst read operations (e.g., first burst read operation BR1 to fourth burst read operation BR4) for reading each column (e.g., the first column) of the matrix can be the row address (e.g., first row address RAD1) starting from the row address of the initial element of the column of the matrix determined by Equation 1 (e.g., first row address RAD1) and the row address (e.g., first row address RAD1, fifth row address RAD5, ninth row address RAD9 and thirteenth row address RAD13) with a numerical difference between adjacent row addresses equal to the burst length BL (e.g., four (4)). Each of the starting column addresses of a burst read operation (e.g., first burst read operation BR1 through fourth burst read operation BR4) used to read each column (e.g., the first column) of the matrix can be the column address of the initial element of the column of the matrix, as determined by Equation 1 (e.g., the first column address CAD1). The initial element of each column of the matrix can be the element of that column in the first row of the matrix.

[0109] When comparing to obtain the transpose matrix Figure 8 Burst read operations and Figure 5 During sudden read operations, such as Figure 8 The process of obtaining the transpose matrix shown can significantly reduce the number of burst read operations, thereby improving computational speed and reducing power consumption. Figure 8 The process of obtaining the transpose matrix shown requires four burst read operations to read only the first column of the matrix, unlike... Figure 5 The diagram shows that a separate memory is needed to temporarily store other columns, thus saving the cost of separate memory.

[0110] In the embodiments, references can be made. Figure 8 The described process reads any column of a matrix except for the transpose of the matrix.

[0111] Figure 9 This is a block diagram illustrating a data processing system 2 including a semiconductor system 200 according to an embodiment of the present disclosure.

[0112] Reference Figure 9 The data processing system 2 may include a host device 20 and a semiconductor system 200.

[0113] In order to store data in and retrieve data from the semiconductor system 200, the host device 20 can control the semiconductor system 200. The host device 20 can be connected to the semiconductor system 200 via multiple system lines SL and can exchange data with the semiconductor system 200 via multiple system lines SL.

[0114] The semiconductor system 200 may include a memory controller 210 and a first memory device MEM1 to a fourth memory device MEM4.

[0115] The memory controller 210 can control the write and read operations of the first memory device MEM1 to the fourth memory device MEM4 under the control of the host device 20.

[0116] The memory controller 210 can be connected to the host device 20 via multiple system lines SL. The host input / output bit width can be the number of bits that are transferred in parallel between the host device 20 and the memory controller 210 at one time via multiple system lines SL.

[0117] The memory controller 210 can be connected to the first memory device MEM1 to the fourth memory device MEM4 via the first device line group DLG1 to the fourth device line group DLG4, respectively. Each of the first device line groups DLG1 to the fourth device line group DLG4 can be configured with multiple device lines. The device input / output bit width can be the number of data bits transferred in parallel at one time between the memory controller 210 and any one of the first memory device MEM1 to the fourth memory device MEM4 via a corresponding group of the first device line groups DLG1 to the fourth device line groups DLG4. That is, the device input / output bit width can be a reference... Figure 3 The bit size of the dataset DQ under discussion. The device input / output bit width can represent the number of data pins or DQ pins for each of the first memory devices MEM1 through the fourth memory device MEM4.

[0118] Therefore, the host input / output bit width can be four (4) times the device input / output bit width, where four (4) is the number of the first memory devices MEM1 to the fourth memory devices MEM4 included in the semiconductor system 200. For example, when the device input / output bit width of each of the first memory devices MEM1 to the fourth memory devices MEM4 is 8, the host input / output bit width can be 32.

[0119] As described later, the memory controller 210 can divide multiple system lines SL into first system line groups SLG1 to fourth system line groups SLG4. The number of first system line groups SLG1 to fourth system line groups SLG4 can be the same as the number of first memory devices MEM1 to fourth memory devices MEM4. Each of the first system line groups SLG1 to fourth system line groups SLG4 can have the same bit width as each of the first device line groups DLG1 to fourth device line groups DLG4. The bit width can be the number of data bits transmitted at one time. For example, when multiple system lines SL transmit [31:0] bits, the first system line groups SLG1 to fourth system line groups SLG4 can transmit [7:0] bits, [15:8] bits, [23:16] bits, and [31:24] bits, respectively.

[0120] The memory controller 210 may include a write data processing component 211, a read data processing component 212, and an address translation component 213.

[0121] The write data processing component 211 can map the first system line group SLG1 to the fourth system line group SLG4 to the first device line group DLG1 to the fourth device line group DLG4, respectively, based on the basic device information provided from the host device 20. The write data processing component 211 can transfer data provided from the host device 20 through each system line group to the device line group mapped to the system line group. The basic device information can indicate one of the first memory devices MEM1 to the fourth memory device MEM4 as the basic device. The basic device can be selected by the host device 20.

[0122] The read data processing component 212 can map the first system line group SLG1 to the fourth system line group SLG4 to the first device line group DLG1 to the fourth device line group DLG4 respectively, based on the basic device information provided from the host device 20. The read data processing component 212 can transfer data provided from each memory device through the corresponding device line group to the system line group mapped to that device line group.

[0123] For each read operation of the first memory device MEM1 to the fourth memory device MEM4, the address translation component 213 can translate the base address into a first device address to a fourth device address based on the base device information provided from the host device 20, and provide them to the first memory device MEM1 to the fourth memory device MEM4 respectively. The base address can be an address provided along with the read command from the host device 20.

[0124] The first memory device MEM1 to the fourth memory device MEM4 can perform their respective write or read operations in parallel under the control of the memory controller 210. Although Figure 9 A semiconductor system 200 including four memory devices MEM1 to MEM4 is shown, but according to an embodiment, the number of memory devices included in the semiconductor system 200 is not limited to this.

[0125] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 A block diagram of the write data processing component 211.

[0126] In this disclosure, the device sequence can be a predetermined order of the first memory device MEM1 to the fourth memory device MEM4. For example, the device sequence can be the order from the first memory device MEM1 to the fourth memory device MEM4. The first memory device MEM1 to the fourth memory device MEM4 can be cyclical according to the device sequence. For example, according to the device sequence, the first memory device MEM1 can be after the fourth memory device MEM4. The order of the first device line group DLG1 to the fourth device line group DLG4 can be the same as the device sequence of the first memory device MEM1 to the fourth memory device MEM4.

[0127] Reference Figure 10 The write data processing component 211 can perform line mapping operations based on the basic device information BASEI, mapping the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4, which are divided from multiple system lines SL. The write data processing component 211 can transmit data provided from the first system line group SLG1 to the fourth system line group SLG4 to the device line groups mapped to the system line groups respectively.

[0128] The write data processing component 211 can perform line mapping operations based on the line mapping table LMT. According to the base device BASE determined by the base device information BASEI, the line mapping table LMT can represent the mapping relationship between the first device line groups DLG1 to the fourth device line groups DLG4 and the first system line groups SLG1 to the fourth system line groups SLG4. For example, the line mapping table LMT may include information about system line groups that are respectively mapped to the first device line groups DLG1 to the fourth device line groups DLG4 according to the base device BASE.

[0129] The write data processing component 211 can sequentially map the first system line group SLG1 to the fourth system line group SLG4 to the device line group according to the device sequence starting from the device line group corresponding to the base device BASE. For example... Figure 10As shown in the Line Mapping Table (LMT), when the base device (BASE) is the first memory device (MEM1), the first system line groups (SLG1) to the fourth system line groups (SLG4) are sequentially mapped to the first device line groups (DLG1) to the fourth device line groups (DLG4) according to the device order starting from the first device line group (DLG1). When the base device (BASE) is the second memory device (MEM2), the first system line groups (SLG1) to the fourth system line groups (SLG4) are sequentially mapped to the second device line group (DLG2), the third device line group (DLG3), the fourth device line group (DLG4), and the first device line group (DLG1) according to the device order starting from the second device line group (DLG2). When the base device (BASE) is the third memory device (MEM3), the first system line groups (SLG1) to the fourth system line groups (SLG4) are sequentially mapped to the third device line group (DLG3), the fourth device line group (DLG4), the first device line group (DLG1), and the second device line group (DLG2) according to the device order starting from the third device line group (DLG3). When the base device BASE is the fourth memory device MEM4, the first system line group SLG1 to the fourth system line group SLG4 can be sequentially mapped to the fourth device line group DLG4, the first device line group DLG1, the second device line group DLG2 and the third device line group DLG3 according to the device order starting from the fourth device line group DLG4.

[0130] The write data processing component 211 may include a write mapping signal generation component 221 and first write multiplexers WM1 to fourth write multiplexers WM4, which correspond to the first device line group DLG1 to the fourth device line group DLG4, respectively. The number of first write multiplexers WM1 to fourth write multiplexers WM4 may be the same as the number of first memory devices MEM1 to fourth memory devices MEM4.

[0131] The first system line group SLG1 to the fourth system line group SLG4 can be connected to the input node of each of the first write multiplexers WM1 to the fourth write multiplexers WM4. The output node of each of the first write multiplexers WM1 to the fourth write multiplexers WM4 can be connected to a corresponding group of the first device line groups DLG1 to the fourth device line groups DLG4. For example, the output nodes of the first write multiplexers WM1 to the fourth write multiplexers WM4 can be connected to the first device line groups DLG1 to the fourth device line groups DLG4 respectively. Each of the first write multiplexers WM1 to the fourth write multiplexers WM4 can select one group of the first system line groups SLG1 to the fourth system line groups SLG4 and can transmit data from the selected system line group to the device line group connected to that write multiplexer. The selected system line group can be mapped to the device line group connected to that write multiplexer. The first write multiplexer WM1 to the fourth write multiplexer WM4 can each respond to the first write mapping signal WMS1 to the fourth write mapping signal WMS4 to select one of the first system line groups SLG1 to the fourth system line groups SLG4. The selected system line group can be mapped to the device line groups connected to the first device line group DLG1 to the fourth device line group DLG4.

[0132] The write mapping signal generation component 221 can generate first write mapping signals WMS1 to fourth write mapping signals WMS4, respectively, corresponding to the first device line group DLG1 to the fourth device line group DLG4, based on the base device information BASEI. Based on the base device BASE determined by the base device information BASEI, the write mapping signal generation component 221 can generate the first write mapping signals WMS1 to the fourth write mapping signals WMS4 to respectively indicate the system line group mapped to the device line group corresponding to the base device BASE. For example, the write mapping signal generation component 221 can refer to the line mapping table LMT to generate the first write mapping signals WMS1 to the fourth write mapping signals WMS4.

[0133] For example, when the base device (BASE) is a first memory device (MEM1), the write mapping signal generation component 221 can generate first write mapping signals WMS1 to fourth write mapping signals WMS4 to indicate first system line groups SLG1 to fourth system line groups SLG4, respectively. When the base device (BASE) is a second memory device (MEM2), the write mapping signal generation component 221 can generate first write mapping signals WMS1 to fourth write mapping signals WMS4 to indicate fourth system line group SLG4, first system line group SLG1, second system line group SLG2, and third system line group SLG3, respectively. When the base device (BASE) is a third memory device (MEM3), the write mapping signal generation component 221 can generate first write mapping signals WMS1 to fourth write mapping signals WMS4 to indicate third system line group SLG3, fourth system line group SLG4, first system line group SLG1, and second system line group SLG2, respectively. When the base device BASE is the fourth memory device MEM4, the write mapping signal generation component 221 can generate the first write mapping signal WMS1 to the fourth write mapping signal WMS4 to indicate the second system line group SLG2, the third system line group SLG3, the fourth system line group SLG4 and the first system line group SLG1 respectively.

[0134] Figure 11 and Figure 12 This illustrates an embodiment according to the present disclosure. Figure 10 A diagram illustrating the line mapping operation of the write data processing component 211.

[0135] Reference Figure 11 The base device information BASEI can indicate the first memory device MEM1 as the base device BASE. In this case, the write data processing component 211 can perform the following operations.

[0136] The write mapping signal generation component 221 can generate first write mapping signals WMS1 to fourth write mapping signals WMS4 respectively, in response to the base device information BASEI.

[0137] In response to the first write mapping signal WMS1, the first write multiplexer WM1 can transmit data from the first system line group SLG1 (from the first system line group SLG1 to the fourth system line group SLG4) to the first device line group DLG1.

[0138] In response to the second write mapping signal WMS2, the second write multiplexer WM2 can transmit data from the second system line group SLG2, which is one of the first system line groups SLG1 to the fourth system line group SLG4, to the second device line group DLG2.

[0139] In response to the third write mapping signal WMS3, the third write multiplexer WM3 can transmit data from the third system line group SLG3 (from the first system line group SLG1 to the fourth system line group SLG4) to the third device line group DLG3.

[0140] In response to the fourth write mapping signal WMS4, the fourth write multiplexer WM4 can transmit data from the fourth system line group SLG4 among the first system line group SLG1 to the fourth system line group SLG4 to the fourth device line group DLG4.

[0141] Reference Figure 12 According to embodiments of this disclosure, the base device information BASEI can indicate the second memory device MEM2 as the base device BASE. In this case, the write data processing component 211 can perform the following operations.

[0142] The write mapping signal generation component 221 can generate first write mapping signals WMS1 to fourth write mapping signals WMS4 respectively, in response to the base device information BASEI.

[0143] In response to the first write mapping signal WMS1, the first write multiplexer WM1 can transmit data from the fourth system line group SLG4 among the first system line group SLG1 to the first device line group DLG1.

[0144] In response to the second write mapping signal WMS2, the second write multiplexer WM2 can transmit data from the first system line group SLG1 (from the first system line group SLG1 to the fourth system line group SLG4) to the second device line group DLG2.

[0145] In response to the third write mapping signal WMS3, the third write multiplexer WM3 can transmit data from the second system line group SLG2, which is one of the first system line groups SLG1 to the fourth system line group SLG4, to the third device line group DLG3.

[0146] In response to the fourth write mapping signal WMS4, the fourth write multiplexer WM4 can transmit data from the third system line group SLG3 among the first system line group SLG1 to the fourth system line group SLG4 to the fourth device line group DLG4.

[0147] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 9A block diagram of the data reading and processing component 212.

[0148] Reference Figure 13 The data processing component 212 can perform line mapping operations based on the basic device information BASEI, mapping the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4 respectively. The data reading processing component 212 can transmit the data provided from the first device line group DLG1 to the fourth device line group DLG4 to the system line group that has been mapped to the device line group respectively.

[0149] The data processing component 212 can perform line mapping operations based on the line mapping table LMT'. The line mapping table LMT' can represent the mapping relationship between the first device line group DLG1 to the fourth device line group DLG4 and the first system line group SLG1 to the fourth system line group SLG4, based on the base device BASE. For example, the line mapping table LMT' can include information on the device line groups that are respectively mapped to the first system line group SLG1 to the fourth system line group SLG4 according to the base device BASE.

[0150] The line mapping table LMT' may include information about mapping relationships that are substantially the same as those referenced by the line mapping table LMT of the write data processing component 211. Therefore, the result of the line mapping operation performed by the read data processing component 212 can be the same as the result of the line mapping operation performed by the write data processing component 211. The read data processing component 212 can sequentially map the first system line group SLG1 to the fourth system line group SLG4 to the device line group according to the device sequence starting from the device line group corresponding to the base device BASE.

[0151] The read data processing component 212 may include a read mapping signal generation component 222 and a first read multiplexer RM1 to a fourth read multiplexer RM4 corresponding to the first system line group SLG1 to the fourth system line group SLG4, respectively. The number of the first read multiplexer RM1 to the fourth read multiplexer RM4 may be the same as the number of the first memory device MEM1 to the fourth memory device MEM4.

[0152] The first device line group DLG1 to the fourth device line group DLG4 can be connected to the input node of each of the first read multiplexers RM1 to the fourth read multiplexer RM4. The output node of each of the first read multiplexers RM1 to the fourth read multiplexer RM4 can be connected to a corresponding group of the first system line groups SLG1 to the fourth system line groups SLG4. For example, the output nodes of the first read multiplexers RM1 to the fourth read multiplexer RM4 can be connected to the first system line groups SLG1 to the fourth system line groups SLG4 respectively. Each of the first read multiplexers RM1 to the fourth read multiplexer RM4 can select one group of the first device line groups DLG1 to the fourth device line groups DLG4 and can transmit data from the selected device line group to the system line group connected to that read multiplexer. The selected device line group can be mapped to the system line group connected to that read multiplexer. The first read multiplexer RM1 to the fourth read multiplexer RM4 can each respond to the first read mapping signal RMS1 to the fourth read mapping signal RMS4 to select one of the first device line groups DLG1 to the fourth device line groups DLG4. The selected device line group can be mapped to one of the first system line groups SLG1 to the fourth system line groups SLG4 and connected to one of the first read multiplexers RM1 to the fourth read multiplexer RM4.

[0153] The read mapping signal generation component 222 can generate first read mapping signals RMS1 to fourth read mapping signals RMS4, respectively, corresponding to the first system line group SLG1 to the fourth system line group SLG4, based on the base device information BASEI. Based on the base device BASE, the read mapping signal generation component 222 can generate the first read mapping signals RMS1 to the fourth read mapping signals RMS4 to indicate the device line group mapped to the system line group corresponding to the base device BASE. For example, the read mapping signal generation component 222 can refer to the line mapping table LMT' to generate the first read mapping signals RMS1 to the fourth read mapping signals RMS4.

[0154] For example, when the base device (BASE) is a first memory device (MEM1), the read mapping signal generation component 222 can generate first read mapping signals RMS1 to fourth read mapping signals RMS4 to indicate first device line groups DLG1 to fourth device line groups DLG4, respectively. When the base device (BASE) is a second memory device (MEM2), the read mapping signal generation component 222 can generate first read mapping signals RMS1 to fourth read mapping signals RMS4 to indicate second device line groups DLG2, third device line groups DLG3, fourth device line groups DLG4, and first device line groups DLG1, respectively. When the base device (BASE) is a third memory device (MEM3), the read mapping signal generation component 222 can generate first read mapping signals RMS1 to fourth read mapping signals RMS4 to indicate third device line groups DLG3, fourth device line groups DLG4, first device line groups DLG1, and second device line groups DLG2, respectively. When the base device BASE is the fourth memory device MEM4, the read mapping signal generation component 222 can generate the first read mapping signal RMS1 to the fourth read mapping signal RMS4 to indicate the fourth device line group DLG4, the first device line group DLG1, the second device line group DLG2 and the third device line group DLG3 respectively.

[0155] Figure 14 and Figure 15 This illustrates an embodiment according to the present disclosure. Figure 13 A diagram illustrating the line mapping operation of the data processing component 212.

[0156] Reference Figure 14 The base device information BASEI can indicate the first memory device MEM1 as the base device BASE. In this case, the read data processing component 212 can perform the following operations.

[0157] The read mapping signal generation component 222 can generate first read mapping signals RMS1 to fourth read mapping signals RMS4 respectively, in response to the basic device information BASEI.

[0158] In response to the first read mapping signal RMS1, the first read multiplexer RM1 can transmit data from the first device line group DLG1 (from the first device line group DLG1 to the fourth device line group DLG4) to the first system line group SLG1.

[0159] In response to the second read mapping signal RMS2, the second read multiplexer RM2 can transmit data from the second device line group DLG2, which is one of the first device line groups DLG1 to the fourth device line group DLG4, to the second system line group SLG2.

[0160] In response to the third read mapping signal RMS3, the third read multiplexer RM3 can transmit data from the third device line group DLG3 among the first device line group DLG1 to the fourth device line group DLG4 to the third system line group SLG3.

[0161] In response to the fourth read mapping signal RMS4, the fourth read multiplexer RM4 can transmit data from the fourth device line group DLG4 among the first device line group DLG1 to the fourth device line group DLG4 to the fourth system line group SLG4.

[0162] Reference Figure 15 The base device information BASEI can indicate the second memory device MEM2 as the base device BASE. In this case, the read data processing component 212 can perform the following operations.

[0163] The read mapping signal generation component 222 can respond to the basic device information BASEI to generate first read mapping signals RMS1 to fourth read mapping signals RMS4 that respectively indicate the second device line group DLG2, the third device line group DLG3, the fourth device line group DLG4 and the first device line group DLG1.

[0164] In response to the first read mapping signal RMS1, the first read multiplexer RM1 can transmit data from the second device line group DLG2, which is one of the first device line groups DLG1 to the fourth device line group DLG4, to the first system line group SLG1.

[0165] In response to the second read mapping signal RMS2, the second read multiplexer RM2 can transmit data from the third device line group DLG3 among the first device line group DLG1 to the fourth device line group DLG4 to the second system line group SLG2.

[0166] In response to the third read mapping signal RMS3, the third read multiplexer RM3 can transmit data from the fourth device line group DLG4 among the first device line group DLG1 to the fourth device line group DLG4 to the third system line group SLG3.

[0167] In response to the fourth read mapping signal RMS4, the fourth read multiplexer RM4 can transmit data from the first device line group DLG1 to the fourth system line group SLG4.

[0168] Figure 16 This illustrates an embodiment according to the present disclosure. Figure 9 Block diagram of address translation component 213.

[0169] For each read operation of the first memory device MEM1 to the fourth memory device MEM4, the address translation component 213 can translate the base address BAD into first device addresses DAD1 to fourth device addresses DAD4 based on the base device information BASEI provided from the host device 20, and provide them to the first memory device MEM1 to the fourth memory device MEM4 respectively. The base address BAD may include the row address RAD and column address CAD provided along with the read command from the host device 20.

[0170] For example, address translation component 213 can generate first device addresses DAD1 to fourth device addresses DAD4 based on address translation table ATT. Address translation table ATT may include first device addresses DAD1 to fourth device addresses DAD4 generated according to base device BASE. Figure 16 As shown in the Address Translation Table (ATT), the device address of the base device (BASE) can be the base address (BAD). Furthermore, the remaining device addresses from the first device address (DAD1) to the fourth device address (DAD4) can each include row addresses incremented by 1, 2, and 3 from the row address (RAD) of the base address (BAD), and each of the remaining device addresses from the first device address (DAD1) to the fourth device address (DAD4) can each include the column address (CAD) of the base address (BAD).

[0171] More specifically, when the base device BASE is the first memory device MEM1, the address translation component 213 can generate a first device address DAD1, which is the base address BAD. Furthermore, the address translation component 213 can generate row addresses that are incremented by the row address RAD of the base address BAD by corresponding amounts 1, 2, and 3, serving as the row addresses of the second device address DAD2, the third device address DAD3, and the fourth device address DAD4, respectively. When the base device BASE is the second memory device MEM2, the address translation component 213 can generate a second device address DAD2, which is the base address BAD. Furthermore, the address translation component 213 can generate row addresses that are incremented by the row address RAD of the base address BAD by corresponding amounts 1, 2, and 3, serving as the row addresses of the third device address DAD3, the fourth device address DAD4, and the first device address DAD1, respectively. When the base device BASE is the third memory device MEM3, the address translation component 213 can generate a third device address DAD3, which is the base address BAD. Furthermore, the address translation component 213 can generate row addresses that are incremented by the corresponding amounts 1, 2, and 3 from the row address RAD of the base address BAD, serving as the row addresses of the fourth device address DAD4, the first device address DAD1, and the second device address DAD2, respectively. When the base device BASE is the fourth memory device MEM4, the address translation component 213 can generate the fourth device address DAD4, which is the base address BAD. Moreover, the address translation component 213 can generate row addresses that are incremented by the corresponding amounts 1, 2, and 3 from the row address RAD of the base address BAD, serving as the row addresses of the first device address DAD1, the second device address DAD2, and the third device address DAD3, respectively.

[0172] In this embodiment, the address translation component 213 may operate selectively under the control of the host device 20. For example, as described later, the address translation component 213 may operate when the host device 20 requests a column read operation on the matrix.

[0173] Figure 17 This illustrates storing a 16×16 matrix according to an embodiment of the present disclosure. Figure 9 A diagram illustrating the process in semiconductor system 200. Figure 17 In the process, the first memory device MEM1 to the fourth memory device MEM4 do not operate according to the burst address gap BAG or according to the burst address gap BAG with a value of one (1), which is consistent with Figure 1 The memory device 120 is different.

[0174] The precision of the matrix can be the same as the device input / output bit width of each memory device included in the semiconductor system 200. The precision of the matrix can be the same as the bit width of each of the first device line groups DLG1 to the fourth device line group DLG4 and the first system line groups SLG1 to the fourth system line groups SLG4. Therefore, the host device 20 can provide four elements of the matrix to each of the first system line groups SLG1 to the fourth system line groups SLG4 at one time. The host device 20 can simultaneously provide four data groups, each having four elements of the matrix, to the first system line groups SLG1 to the fourth system line groups SLG4. The four data groups can correspond to the number of system line groups SLG1 to SLG4 and each of the four elements (i.e., four data sets DQ) can correspond to the bit width of each of the device line groups DLG1 to DLG4. Moreover, the host device 20 can control the semiconductor system 200 to perform burst write operations with a burst length BL of, for example, four (4). When four elements are transmitted simultaneously through system line SL and the burst length BL is four (4), host device 20 can store a single row of the matrix into semiconductor system 200 by a single burst write command. Figure 17 It is shown that when the burst length BL is four (4), each of the four elements bl0, bl1, bl2 and bl3 is transmitted to the four data groups of the first system line group SLG1 to the fourth system line group SLG4 respectively.

[0175] The host device 20 can provide matrix elements to the first system line group SLG1 to the fourth system line group SLG4 according to a row-first scheme. More specifically, for the first burst write operation BW1, the host device 20 can simultaneously provide the first system line group SLG1 to the fourth system line group SLG4 with the corresponding four data groups: the elements of the first row and the first to the fourth columns, the elements of the first row and the fifth to the eighth columns, the elements of the first row and the ninth to the twelfth columns, and the elements of the first row and the thirteenth to the sixteenth columns. For example... Figure 17 As shown, for the second burst write operation BW2 to the fifth burst write operation BW5, the host device 20 can provide the elements of the second to fifth rows of the matrix to the first system line group SLG1 to the fourth system line group SLG4 in a similar manner. The host device 20 can also provide the elements of the remaining rows of the matrix to the first system line group SLG1 to the fourth system line group SLG4 in a similar manner.

[0176] The host device 20 can provide the base address BAD to the memory controller 210. Specifically, when providing the memory controller 210 with the corresponding first row to the sixteenth row of the matrix, the host device 20 can provide the memory controller 210 with the corresponding first row address RAD1 to the sixteenth row address RAD16. For example, the host device 20 can provide the memory controller 210 with the first row address RAD1 when providing the first row of the matrix, and can provide the memory controller 210 with the second row address RAD2 when providing the second row of the matrix. When providing the memory controller 210 with the corresponding first row to the sixteenth row of the matrix, the host device 20 can provide the memory controller 210 with the starting column address CAD.

[0177] Each time a row of the matrix is ​​provided to the semiconductor system 200, the host device 20 can determine the base device (BASE) and provide the base device information (BASEI) to the memory controller 210. Each time rows starting from the first row of the matrix are sequentially provided to the semiconductor system 200, the host device 20 can sequentially determine the base devices (BASE) from the first memory device MEM1 to the fourth memory device MEM4 according to the device order. For example, the base device (BASE) may be the first memory device MEM1 when the first row is provided to the memory controller 210, the second memory device MEM2 when the second row is provided to the memory controller 210, the third memory device MEM3 when the third row is provided to the memory controller 210, and the fourth memory device MEM4 when the fourth row is provided to the memory controller 210. In this case, when the fifth row is provided to the memory controller 210, the base device (BASE) may again be the first memory device MEM1.

[0178] Based on the base address BAD and base device information BASEI provided from the host device 20, the memory controller 210 can control the first memory device MEM1 to the fourth memory device MEM4 to perform burst write operations with a burst length BL of four (4).

[0179] Specifically, when the first row of the matrix is ​​provided from the host device 20, the base device BASE can be the first memory device MEM1, and the write data processing component 211 can transfer elements from the first system line group SLG1 to the fourth system line group SLG4 to the first device line group DLG1 to the fourth device line group DLG4 respectively through line mapping operations. Therefore, the first memory device MEM1 to the fourth memory device MEM4 can store the elements transferred from the first system line group SLG1 to the fourth system line group SLG4 into the pages corresponding to the first row address RAD1 respectively through the first burst write operation BW1.

[0180] When the second row of the matrix is ​​provided from the host device 20, the base device BASE can be the second memory device MEM2, and the write data processing component 211 can transfer elements from the first system line group SLG1 to the fourth system line group SLG4 to the second device line group DLG2, the third device line group DLG3, the fourth device line group DLG4, and the first device line group DLG1, respectively, through line mapping operations. Therefore, the second memory device MEM2, the third memory device MEM3, the fourth memory device MEM4, and the first memory device MEM1 can store the elements transferred from the first system line group SLG1 to the fourth system line group SLG4 into the pages corresponding to the second row address RAD2, respectively, through the second burst write operation BW2.

[0181] When the third row of the matrix is ​​provided from the host device 20, the base device BASE can be the third memory device MEM3, and the write data processing component 211 can transfer elements from the first system line group SLG1 to the fourth system line group SLG4 to the third device line group DLG3, the fourth device line group DLG4, the first device line group DLG1, and the second device line group DLG2 respectively through line mapping operations. Therefore, the third memory device MEM3, the fourth memory device MEM4, the first memory device MEM1, and the second memory device MEM2 can store the elements transferred from the first system line group SLG1 to the fourth system line group SLG4 into the page corresponding to the third row address RAD3 through the third burst write operation BW3.

[0182] When the fourth row of the matrix is ​​provided from the host device 20, the base device BASE can be the fourth memory device MEM4, and the write data processing component 211 can transfer elements from the first system line group SLG1 to the fourth system line group SLG4 to the fourth device line group DLG4, the first device line group DLG1, the second device line group DLG2, and the third device line group DLG3 respectively via line mapping operations. Therefore, the fourth memory device MEM4, the first memory device MEM1, the second memory device MEM2, and the third memory device MEM3 can store the elements transferred from the first system line group SLG1 to the fourth system line group SLG4 into the pages corresponding to the fourth row address RAD4 via the fourth burst write operation BW4.

[0183] Similar to the first row of a matrix, the fifth row of the matrix can be stored in the semiconductor system 200 via a fifth burst write operation (BW5). The remaining rows of the matrix can be stored in the semiconductor system 200 in a similar manner.

[0184] In an embodiment, the number of the memory device indicating the (i,j)th element of the storage matrix can be determined according to Equation 2 below, and the address of the memory region in the memory device where the (i,j)th element of the matrix is ​​stored can be determined according to Equation 3 below.

[0185] Equation 2:

[0186] The memory device number indicating the (i,j)th element of the storage matrix = [(i-1)*Mcol+j-1+RoundDown(((i-1)*Mcol+j-1) / (bl*ChipNum))]%ChipNum

[0187] Equation 3:

[0188] The address of the memory region for the (i,j)th element of the storage matrix = Baddr + (i-1) * RoundUp(Mcol / bl) + RoundDown((j-1 - (j-1) % bl) / bl)

[0189] In Equations 2 and 3, the memory device number indicating the (i,j)th element of the storage matrix can be represented by a number corresponding to the device order. "Baddr" can represent the address of the memory region containing the (1,1)th element of the storage matrix. "Mcol" can represent the number of columns in the matrix. "bl" can represent the burst length BL. "RoundUp()" can represent the round-up function. "RoundDown()" can represent the round-down function. "ChipNum" can represent the number of memory devices MEM1 through MEM4.

[0190] In one embodiment, the base device information BASEI provided by host device 20 for burst write operations of each row of the storage matrix can indicate the memory device in which the initial element of that row is stored, as determined according to Equation 2. In another embodiment, the row address provided by host device 20 for burst write operations of each row of the storage matrix can be the row address of the initial element of that row of the matrix, as determined according to Equation 3. In yet another embodiment, the starting column address provided by host device 20 for burst write operations of each row of the storage matrix can be the column address of the initial element of that row of the matrix, as determined according to Equation 3. The initial element of each row of the matrix can be the element of the first column of the row of the matrix.

[0191] Figure 18 and Figure 19 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which the semiconductor system 200 obtains the rows of a matrix. (Refer to...) Figure 18 and Figure 19 , matrix with reference Figure 17 The described method is stored in the semiconductor system 200. Furthermore, the first memory device MEM1 to the fourth memory device MEM4 do not operate according to the burst address gap BAG or according to a burst address gap BAG with a value of one (1), which is consistent with... Figure 1 The memory device 120 is different.

[0192] When the original matrix is ​​needed, the host device 20 can perform a row read operation. When reading each row of the matrix from the semiconductor system 200, the host device 20 can use the same row address as when storing the row into the semiconductor system 200. That is, since the first to sixteenth rows of the matrix are stored in pages at first row address RAD1 to sixteenth row address RAD16 respectively, the host device 20 can provide the memory controller 210 with the address of the i-th row as part of the base address BAD to read the i-th row of the stored matrix. The host device 20 can provide the memory controller 210 with the same starting column address CAD as used when storing the matrix into the semiconductor system 200 as the remainder of the base address BAD.

[0193] Each time a row is read from the semiconductor system 200, the host device 20 can determine the base device (BASE) and provide the base device information (BASEI) to the memory controller 210. When reading each row of the matrix from the semiconductor system 200, the host device 20 can provide the semiconductor system 200 with the same base device information (BASEI) as when storing the row into the semiconductor system 200.

[0194] Specifically, whenever rows are read sequentially starting from the first row of the matrix, the host device 20 can sequentially determine the base device BASE, starting from the first memory device MEM1 and proceeding to the fourth memory device MEM4, according to device order. For example, the base device BASE could be the first memory device MEM1 when reading the first row, the second memory device MEM2 when reading the second row, the third memory device MEM3 when reading the third row, and the fourth memory device MEM4 when reading the fourth row. In this case, when the fifth row is about to be read, the base device BASE can again be the first memory device MEM1.

[0195] Reference Figure 18 The host device 20 can read the first row of the matrix from the semiconductor system 200 through a first burst read operation BR1 with a burst length BL of four (4). For the first burst read operation BR1, the host device 20 can provide the memory controller 210 with a base address BAD including the first row address RAD1 and the starting column address CAD. Moreover, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the first memory device MEM1 is a base device BASE.

[0196] Under the control of the memory controller 210, the first memory device MEM1 to the fourth memory device MEM4 can perform a first burst read operation BR1 with a burst length BL of four (4) on the first row address RAD1 and the starting column address CAD in a parallel manner. Figure 18 The diagram shows four data sets with four elements bl0, bl1, bl2 and bl3, which are simultaneously output from the first memory device MEM1 to the fourth memory device MEM4 when the burst length BL is four (4).

[0197] At this time, since the base device BASE is the first memory device MEM1, the data processing component 212 can transfer elements from the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4 respectively through line mapping operations. Therefore, the host device 20 can obtain the first row of the matrix.

[0198] Reference Figure 19The host device 20 can read the second row of the matrix from the semiconductor system 200 through a second burst read operation BR2 with a burst length BL of four (4). For the second burst read operation BR2, the host device 20 can provide the memory controller 210 with a base address BAD including the second row address RAD2 and the starting column address CAD. Moreover, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the second memory device MEM2 is a base device BASE.

[0199] Under the control of the memory controller 210, the first memory device MEM1 to the fourth memory device MEM4 can perform a second burst read operation BR2 with a burst length BL of four (4) on the second row address RAD2 and the starting column address CAD in a parallel manner.

[0200] Since the base device BASE is the second memory device MEM2, the data processing component 212 can transfer elements from the first device line group DLG1 to the fourth device line group DLG4 to the fourth system line group SLG4, the first system line group SLG1, the second system line group SLG2, and the third system line group SLG3 respectively through line mapping operations. Therefore, the host device 20 can obtain the second row of the matrix.

[0201] In the same manner as described above, host device 20 can obtain the remaining rows of the matrix to obtain the original matrix.

[0202] In one embodiment, the base device information (BASEI) provided by the host device 20 for burst read operations of reading each row of the matrix can indicate a memory device that stores the initial element of that row, as determined according to Equation 2. In another embodiment, the row address provided by the host device 20 for burst read operations of reading each row of the matrix can be the row address of the initial element of that row, as determined according to Equation 3. In yet another embodiment, the starting column address provided by the host device 20 for burst read operations of reading each row of the matrix can be the column address of the initial element of that row, as determined according to Equation 3. The initial element of each row of the matrix can be the element of the first column of that row.

[0203] Figure 20 and Figure 21 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which a semiconductor system 200 obtains the columns of a matrix. (Refer to...) Figure 20 and Figure 21 , matrix with reference Figure 17The described method is stored in the semiconductor system 200. Furthermore, the first memory device MEM1 to the fourth memory device MEM4 do not operate according to the burst address gap BAG or according to a burst address gap BAG with a value of one (1), which is consistent with... Figure 1 The memory device 120 is different.

[0204] When a transpose matrix is ​​required, the host device 20 can perform a column read operation.

[0205] By performing a burst read operation with a burst length BL of four (4), the host device 20 can read from the semiconductor system 200 a set of columns (hereinafter referred to as the column set) comprising four columns of a matrix. For example, the first column set may include the first, fifth, ninth, and thirteenth columns of the matrix (hereinafter referred to as the column set). Figure 20 (to be described), and the second column set may include the second, sixth, tenth, and fourteenth columns of the matrix (to be referred to) Figure 21 (Description to follow). Moreover, although not shown, the third column set may include the third, seventh, eleventh, and fifteenth columns of the matrix, and the fourth column set may include the fourth, eighth, twelfth, and sixteenth columns of the matrix.

[0206] To read each column set of the matrix, the number of burst read operations that each memory device will perform can be obtained by dividing the total number of rows of the matrix by the number of memory devices MEM1 to MEM4 included in the semiconductor system 200. Figure 20 In the example, four (4) is the number of burst read operations that will be performed on each column set and each memory device.

[0207] Whenever each column set of the matrix is ​​read from the semiconductor system 200, the host device 20 can provide the memory controller 210 with a set of values ​​starting from the first row address RAD1, where the numerical difference between adjacent row addresses is the total number of memory devices (e.g., Figure 20 In the example, there are four (4) row addresses. For example, whenever each column set is read from semiconductor system 200, host device 20 may provide memory controller 210 with the first row address RAD1, the fifth row address RAD5, the ninth row address RAD9, and the thirteenth row address RAD13. When subsequent column sets are read from semiconductor system 200, host device 20 may provide memory controller 210 with the same first row address RAD1, the fifth row address RAD5, the ninth row address RAD9, and the thirteenth row address RAD13. Host device 20 may provide memory controller 210 with the same starting column address CAD used when storing the matrix into semiconductor system 200.

[0208] Whenever each column set of the matrix is ​​read from the semiconductor system 200, the host device 20 can determine the base device (BASE) and provide the base device information (BASEI) to the memory controller 210. Specifically, whenever the column sets are read sequentially starting from the first column set of the matrix, the host device 20 can sequentially determine the base device (BASE) from the first memory device (MEM1) to the fourth memory device (MEM4) according to the device order. For example, the base device (BASE) may be the first memory device (MEM1) when the first column set is about to be read, the second memory device (MEM2) when the second column set is about to be read, the third memory device (MEM3) when the third column set is about to be read, and the fourth memory device (MEM4) when the fourth column set is about to be read.

[0209] During a column read operation, the host device 20 can control the address translation component 213 of the memory controller 210 to operate.

[0210] Reference Figure 20 The host device 20 can read the first column set, including the first column, the fifth column, the ninth column and the thirteenth column of the matrix, from the semiconductor system 200 through the first burst read operation BR1 to the fourth burst read operation BR4.

[0211] For a first burst read operation BR1 with a burst length BL of four (4), the host device 20 can provide the memory controller 210 with a base address BAD including the first row address RAD1 and the starting column address CAD. Furthermore, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the first memory device MEM1 is a base device BASE.

[0212] During column read operations, the address translation component 213 can operate under the control of the host device 20, unlike row read operations. Since the base device BASE is the first memory device MEM1, the address translation component 213 can generate a first device address DAD1 to be provided to the first memory device MEM1 by translating the base address BAD provided from the host device 20. Furthermore, the address translation component 213 can generate row addresses from the base address BAD, i.e., addresses that are incremented by the corresponding amounts 1, 2, and 3 from the first row address RAD1, as second device addresses DAD2 to fourth device addresses DAD4 to be provided to the second memory devices MEM2 to the fourth memory devices MEM4, respectively.

[0213] Therefore, the first memory device MEM1 can perform a first burst read operation BR1 with a burst length BL of four (4) on the first row address RAD1, the second memory device MEM2 can perform a first burst read operation BR1 with a burst length BL of four (4) on the second row address RAD2, the third memory device MEM3 can perform a first burst read operation BR1 with a burst length BL of four (4) on the third row address RAD3, and the fourth memory device MEM4 can perform a first burst read operation BR1 with a burst length BL of four (4) on the fourth row address RAD4. The first memory devices MEM1 to the fourth memory devices MEM4 can execute the first burst read operation BR1 in parallel.

[0214] Since the base device BASE is the first memory device MEM1, the data reading processing component 212 can transfer the element BRD1 from the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4 respectively through line mapping operation.

[0215] For a second burst read operation BR2 with a burst length BL of four (4), the host device 20 can provide the memory controller 210 with a base address BAD including the fifth row address RAD5 and the starting column address CAD. Furthermore, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the first memory device MEM1 is a base device BASE.

[0216] Since the base device BASE is the first memory device MEM1, the address translation component 213 can generate a first device address DAD1 to be provided to the first memory device MEM1 by translating the base address BAD provided from the host device 20. Furthermore, the address translation component 213 can generate row addresses from the base address BAD, i.e., addresses starting from the fifth row address RAD5 and incrementing by corresponding amounts 1, 2, and 3, as second device addresses DAD2 to fourth device addresses DAD4 to be provided to the second memory devices MEM2 to the fourth memory devices MEM4, respectively.

[0217] Therefore, the first memory device MEM1 can perform a second burst read operation BR2 with a burst length BL of four (4) on the fifth row address RAD5, the second memory device MEM2 can perform a second burst read operation BR2 with a burst length BL of four (4) on the sixth row address RAD6, the third memory device MEM3 can perform a second burst read operation BR2 with a burst length BL of four (4) on the seventh row address RAD7, and the memory device MEM4 can perform a second burst read operation BR2 with a burst length BL of four (4) on the eighth row address RAD8. The first memory device MEM1 to the fourth memory device MEM4 can execute the second burst read operation BR2 in parallel.

[0218] Since the base device BASE is the first memory device MEM1, the data reading processing component 212 can transfer the element BRD2 from the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4 respectively through line mapping operation.

[0219] Similarly, host device 20 and semiconductor system 200 can perform a third burst read operation BR3 and a fourth burst read operation BR4 on the ninth row address RAD9 and the thirteenth row address RAD13. Therefore, host device 20 can obtain a first column set including the first, fifth, ninth, and thirteenth columns of the matrix. Within the first column set, host device 20 can first use the first column and can store the remaining fifth, ninth, and thirteenth columns in separate memory.

[0220] Reference Figure 21 The host device 20 can read the second column set, including the second, sixth, tenth and fourteenth columns of the matrix, from the semiconductor system 200 through the fifth burst read operation BR5 to the eighth burst read operation BR8.

[0221] For a fifth burst read operation BR5 with a burst length BL of four (4), the host device 20 can provide the memory controller 210 with a base address BAD including the first row address RAD1 and the starting column address CAD. Furthermore, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the second memory device MEM2 is a base device BASE.

[0222] Since the base device BASE is the second memory device MEM2, the address translation component 213 can generate a second device address DAD2 to be provided to the second memory device MEM2 by translating the base address BAD provided from the host device 20. Furthermore, the address translation component 213 can generate row addresses from the base address BAD, i.e., addresses that are incremented by the corresponding amounts 1, 2, and 3 from the first row address RAD1, as the third device address DAD3, the fourth device address DAD4, and the first device address DAD1 to be provided to the third memory device MEM3, the fourth memory device MEM4, and the first memory device MEM1, respectively.

[0223] Therefore, the second memory device MEM2 can perform a fifth burst read operation BR5 with a burst length BL of four (4) on the first row address RAD1, the third memory device MEM3 can perform a fifth burst read operation BR5 with a burst length BL of four (4) on the second row address RAD2, the fourth memory device MEM4 can perform a fifth burst read operation BR5 with a burst length BL of four (4) on the third row address RAD3, and the first memory device MEM1 can perform a fifth burst read operation BR5 with a burst length BL of four (4) on the fourth row address RAD4. The first memory device MEM1 to the fourth memory device MEM4 can execute the fifth burst read operation BR5 in parallel.

[0224] Since the base device BASE is the second memory device MEM2, the read data processing component 212 can transfer the element BRD5 from the first device line group DLG1 to the fourth device line group DLG4 to the fourth system line group SLG4, the first system line group SLG1, the second system line group SLG2 and the third system line group SLG3 respectively through line mapping operation.

[0225] Similarly, host device 20 and semiconductor system 200 can perform sixth burst read operations BR6 through eighth burst read operations BR8 on row 5 address RAD5, row 9 address RAD9, and row 13 address RAD13. Therefore, host device 20 can obtain a second column set including the second, sixth, tenth, and fourteenth columns of the matrix. Within this second column set, host device 20 can first use the second column and can store the remaining sixth, tenth, and fourteenth columns in a separate memory.

[0226] In an embodiment, the number of burst read operations that each memory device will perform to read each column set of the matrix can be a value obtained by dividing the total number of rows of the matrix by the number of memory devices MEM1 to MEM4 included in the semiconductor system 200. In an embodiment, the base device information BASEI provided by the host device 20 for burst read operations to read each column set of the matrix can indicate the memory device that stores the initial element of the column set, as determined according to Equation 2. In an embodiment, the row address provided by the host device 20 for burst read operations to read each column set of the matrix can be a row address starting from the row address of the initial element of the column set as determined according to Equation 3, with the numerical difference between adjacent row addresses being an amount equal to the burst length BL. In an embodiment, the starting column address provided by the host device 20 for burst read operations to read each column set of the matrix can be the column address of the initial element of the column set as determined according to Equation 3. The initial element of each column set can be the element of the first row of the first column included in the column set.

[0227] In summary, the semiconductor system 200 may include multiple memory devices, each having the same device input / output bit width as the matrix, and the matrix may be stored therein during the above process, so that row read operations and column read operations can be performed efficiently.

[0228] When storage Figure 17 When storing a matrix, the first memory devices MEM1 to the fourth memory devices MEM4 do not operate according to the burst address gap BAG or operate according to a burst address gap BAG with a value of one (1). In the following text, when storing a matrix, the first memory devices MEM1 to the fourth memory devices MEM4 operate according to a burst address gap BAG with the same value as the burst length BL, which is consistent with... Figure 1 The memory device 120 is the same.

[0229] Figure 22 This illustrates storing a 16×16 matrix according to an embodiment of the present disclosure. Figure 9 A diagram illustrating the process in the semiconductor system 200. Each of the first memory devices MEM1 to the fourth memory device MEM4 can support burst address gap (BAG).

[0230] In order to store the matrix, the host device 20 can control the semiconductor system 200 to perform a burst write operation with the burst address gap BAG value being the same as the burst length BL value, for example, a value of four (4).

[0231] The host device 20 can provide matrix elements to the semiconductor system 200 through the first system line group SLG1 to the fourth system line group SLG4, which is similar to the reference... Figure 17 The process described.

[0232] When providing rows starting from the first row of the matrix, host device 20 can provide row addresses from the first row address RAD1 to the fourth row address RAD4. For example, host device 20 can provide the first row address RAD1 to memory controller 210 when providing the first row of the matrix, the second row address RAD2 to memory controller 210 when providing the second row of the matrix, the third row address RAD3 to memory controller 210 when providing the third row of the matrix, and the fourth row address RAD4 to memory controller 210 when providing the fourth row of the matrix. In this case, host device 20 can again provide the first row address RAD1 to memory controller 210 when providing the fifth row of the matrix. The number of repeated row addresses (e.g., first row address RAD1 to fourth row address RAD4) can be the same as the number of memory devices MEM1 to MEM4 included in semiconductor system 200. Furthermore, in order to store the first to fourth rows of the matrix into the semiconductor system 200, the host device 20 can provide the memory controller 210 with the same starting column address CAD1. Further, in order to store the fifth to eighth rows of the matrix into the semiconductor system 200, the host device 20 can provide the memory controller 210 with a column address CAD2 following the column address CAD1 used as the starting column address for the first to fourth rows, as the starting column address for the fifth to eighth rows. That is, whenever the addresses of the first row RAD1 to the fourth row RAD4 are repeated, the starting column address can be shifted.

[0233] Each time a row of the matrix is ​​provided to the semiconductor system 200, the host device 20 can determine the base device (BASE) and can provide the base device information (BASEI) to the memory controller 210, which is consistent with the reference. Figure 17 The description is the same. Whenever rows starting from the first row of the matrix are sequentially provided to the semiconductor system 200, the host device 20 can sequentially determine the first memory device MEM1 to the fourth memory device MEM4 as the base device according to the device order.

[0234] Based on the base address BAD and base device information BASEI provided from the host device 20, the memory controller 210 can control the first memory device MEM1 to the fourth memory device MEM4 to perform burst write operations with a burst length BL of four (4) and a burst address gap BAG of four (4). Therefore, the matrix can be stored... Figure 22 In the semiconductor system 200 shown. The details of this process may be the same as those described above, and therefore will be omitted.

[0235] Figure 23 and Figure 24 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which the semiconductor system 200 obtains the rows of a matrix. (Refer to...) Figure 23 and Figure 24 , matrix with reference Figure 22 The described method is stored in semiconductor system 200. Each of the first memory device MEM1 to the fourth memory device MEM4 can support burst address gap (BAG).

[0236] When the original matrix is ​​needed, the host device 20 can perform a row read operation.

[0237] The host device 20 can obtain each row of the matrix from the semiconductor system 200 through a burst read operation in which both the burst length BL and the burst address gap BAG are four (4).

[0238] When reading each row of the matrix from the semiconductor system 200, the host device 20 can use the same row address and the same starting column address CAD1 as when storing that row into the semiconductor system 200.

[0239] When reading each row of the matrix from the semiconductor system 200, the host device 20 can provide the semiconductor system 200 with the same basic device information BASEI as it provides to the semiconductor system 200 when storing that row in the semiconductor system 200.

[0240] Reference Figure 23 The host device 20 can read the first row of the matrix from the semiconductor system 200 through a first burst read operation BR1, where both the burst length BL and the burst address gap BAG are four (4). For the first burst read operation BR1, the host device 20 can provide the memory controller 210 with a base address BAD including the first row address RAD1 and the starting column address CAD1. Moreover, the host device 20 can provide the memory controller 210 with base device information BASEI, indicating that the first memory device MEM1 is a base device BASE.

[0241] Under the control of the memory controller 210, the first memory device MEM1 to the fourth memory device MEM4 can perform a first burst read operation BR1 on the first row address RAD1 in parallel, with the burst length BL and the burst address gap BAG both being four (4).

[0242] Since the base device BASE is the first memory device MEM1, the data processing component 212 can transfer elements from the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4 respectively through line mapping operations. Therefore, the host device 20 can obtain the first row of the matrix.

[0243] Reference Figure 24 The host device 20 can read the second row of the matrix from the semiconductor system 200 through a second burst read operation BR2, where both the burst length BL and the burst address gap BAG are four (4). For the second burst read operation BR2, the host device 20 can provide the memory controller 210 with a base address BAD including the second row address RAD2 and the starting column address CAD1. Moreover, the host device 20 can provide the memory controller 210 with base device information BASEI, which indicates that the second memory device MEM2 is a base device BASE.

[0244] Under the control of the memory controller 210, the first memory device MEM1 to the fourth memory device MEM4 can perform a second burst read operation BR2 on the second row address RAD2 in parallel, with a burst length BL and a burst address gap BAG of four (4).

[0245] Since the base device BASE is the second memory device MEM2, the data processing component 212 can transfer elements from the first device line group DLG1 to the fourth device line group DLG4 to the fourth system line group SLG4, the first system line group SLG1, the second system line group SLG2, and the third system line group SLG3 respectively through line mapping operations. Therefore, the host device 20 can obtain the second row of the matrix.

[0246] In the same manner as described above, host device 20 can obtain the remaining rows of the matrix to obtain the original matrix.

[0247] Figure 25 and Figure 26 This illustrates an embodiment of the present disclosure. Figure 9 A diagram illustrating the process by which a semiconductor system 200 obtains the columns of a matrix. (Refer to...) Figure 25 and Figure 26 , matrix with reference Figure 22 The described method is stored in semiconductor system 200. Each of the first memory device MEM1 to the fourth memory device MEM4 can support burst address gap (BAG).

[0248] When a transpose matrix is ​​required, the host device 20 can perform a column read operation.

[0249] By performing a burst read operation with a burst length BL of four (4) and a burst address gap BAG of one (1), the host device 20 can read each column set of the matrix from the semiconductor system 200.

[0250] Whenever each column of the matrix is ​​read from the semiconductor system 200, the host device 20 can provide the first row address RAD1 to the memory controller 210.

[0251] Whenever the host device 20 reads each column from the semiconductor system 200 whose quantity corresponds to the burst length BL (i.e., 4 for columns 1 through 4 in this case), the host device 20 may provide the memory controller 210 with the starting column address CAD1 used when storing the matrix into the semiconductor system 200. Whenever the host device 20 reads each of the four columns following the four columns 1 through 4, the host device 20 may provide the memory controller 210 with a column address CAD5 incremented by four (4) from the initial starting column address CAD1. Whenever the host device 20 reads each of the four columns following the four columns 5 through 8, the host device 20 may provide the memory controller 210 with a column address CAD9 incremented by eight (8) from the initial starting column address CAD1. Whenever the host device 20 reads each of the four columns following the four columns 9 through 12, the host device 20 may provide the memory controller 210 with a column address CAD13 incremented by twelve (12) from the initial starting column address CAD1.

[0252] Whenever each column of the matrix is ​​read from the semiconductor system 200, the host device 20 can determine the base device (BASE) and provide the base device information (BASEI) to the memory controller 210. Whenever columns are read sequentially starting from the first set of columns of the matrix, the host device 20 can sequentially determine the base devices (BASE) from the first memory device (MEM1) to the fourth memory device (MEM4) according to the device order.

[0253] During a column read operation, the host device 20 can control the address translation component 213 of the memory controller 210 to operate.

[0254] Reference Figure 25The host device 20 can read the first column of the matrix from the semiconductor system 200 through a first burst read operation BR1 with a burst length BL of four (4) and a burst address gap BAG of one (1). For the first burst read operation BR1 with a burst length BL of four (4) and a burst address gap BAG of one (1), the host device 20 can provide the memory controller 210 with a base address BAD including a first row address RAD1 and a starting column address CAD1. Moreover, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the first memory device MEM1 is a base device BASE.

[0255] During column read operations, the address translation component 213 can operate under the control of the host device 20, unlike row read operations. Since the base device BASE is the first memory device MEM1, the address translation component 213 can generate a first device address DAD1 to be provided to the first memory device MEM1 by translating the base address BAD provided from the host device 20. Furthermore, the address translation component 213 can generate row addresses from the base address BAD, i.e., addresses that are incremented by the corresponding amounts 1, 2, and 3 from the first row address RAD1, as second device addresses DAD2 to fourth device addresses DAD4 to be provided to the second memory devices MEM2 to the fourth memory devices MEM4, respectively.

[0256] Therefore, the first memory device MEM1 can perform a first burst read operation BR1 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the first row address RAD1, the second memory device MEM2 can perform a first burst read operation BR1 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the second row address RAD2, the third memory device MEM3 can perform a first burst read operation BR1 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the third row address RAD3, and the fourth memory device MEM4 can perform a first burst read operation BR1 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the fourth row address RAD4. The first memory devices MEM1 to the fourth memory devices MEM4 can execute the first burst read operation BR1 in parallel.

[0257] Since the base device BASE is the first memory device MEM1, the data processing component 212 can transfer elements from the first device line group DLG1 to the fourth device line group DLG4 to the first system line group SLG1 to the fourth system line group SLG4 respectively through line mapping operations. Therefore, the host device 20 can obtain the first column of the matrix.

[0258] Reference Figure 26 The host device 20 can read the second column of the matrix from the semiconductor system 200 through a second burst read operation BR2 with a burst length BL of four (4) and a burst address gap BAG of one (1). For the second burst read operation BR2 with a burst length BL of four (4) and a burst address gap BAG of one (1), the host device 20 can provide the memory controller 210 with a base address BAD including a first row address RAD1 and a starting column address CAD1. Moreover, the host device 20 can provide the memory controller 210 with base device information BASEI indicating that the second memory device MEM2 is a base device BASE.

[0259] During column read operations, the address translation component 213 can operate under the control of the host device 20, unlike row read operations. Since the base device BASE is the second memory device MEM2, the address translation component 213 can generate a second device address DAD2 to be provided to the second memory device MEM2 by translating the base address BAD provided from the host device 20. Furthermore, the address translation component 213 can generate row addresses from the base address BAD, i.e., addresses that are incremented by the corresponding amounts 1, 2, and 3 from the first row address RAD1, as the third device address DAD3, the fourth device address DAD4, and the first device address DAD1 to be provided to the third memory device MEM3, the fourth memory device MEM4, and the first memory device MEM1, respectively.

[0260] Therefore, the first memory device MEM1 can perform a second burst read operation BR2 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the fourth row address RAD4; the second memory device MEM2 can perform a second burst read operation BR2 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the first row address RAD1; the third memory device MEM3 can perform a second burst read operation BR2 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the second row address RAD2; and the fourth memory device MEM4 can perform a second burst read operation BR2 with a burst length BL of four (4) and a burst address gap BAG of one (1) on the third row address RAD3. The first memory device MEM1 to the fourth memory device MEM4 can execute the second burst read operation BR2 in parallel.

[0261] Since the base device BASE is the second memory device MEM2, the data processing component 212 can transfer elements from the first device line group DLG1 to the fourth device line group DLG4 to the fourth system line group SLG4, the first system line group SLG1, the second system line group SLG2, and the third system line group SLG3 respectively through line mapping operations. Therefore, the host device 20 can obtain the second column of the matrix.

[0262] In summary, the semiconductor system 200 can be designed to include multiple memory devices, each having the same device input / output bit width as the matrix and each configured to support burst address gap (BAG), and is designed to store the matrix therein in the above process, such that row read operations and column read operations can be performed efficiently.

[0263] According to an embodiment, the memory device, semiconductor system, and data processing system can efficiently store matrices and can read the original or transposed matrices for use at a low cost.

[0264] While specific embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the memory device, semiconductor system, and data processing system should not be limited based on the described embodiments. Rather, the memory device, semiconductor system, and data processing system described herein should be limited only by the appended claims when taken in conjunction with the foregoing description and drawings. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: A memory cell array comprises multiple memory regions, each identified by a row address and a column address; as well as The peripheral circuitry accesses the memory cell array by performing burst operations based on the address, burst length, and burst address gap provided by the memory controller, the burst operations supporting variable burst address gaps; The burst address gap is the numerical difference between adjacent column addresses where the burst operation is to be performed. The burst operations include burst write operations, and Regardless of whether the value of the burst address gap is 1 or a positive integer greater than 1, the peripheral circuit accesses the memory cell array based on the burst address gap when performing the burst write operation.

2. The memory device according to claim 1, The address mentioned includes a row address and a starting column address, and The column address to be executed for the burst operation starts from the starting column address and includes the numerical difference between adjacent column addresses having the amount of the burst address gap, as well as the number of column addresses corresponding to the burst length.

3. The memory device of claim 1, wherein the peripheral circuitry performs a burst write operation in which the value of the burst address gap is the same as the value of the burst length, to store the (i, j)th element of the matrix into a memory region having an address determined by Equation 1 below. Equation 1: address = Baddr + (i – i % (bl + 1)) Mcol + i % (bl + 1) – 1 + (j - 1) bl Where "Baddr" represents the address of the storage area storing the (1, 1)th element of the matrix, "Mcol" represents the number of columns of the matrix, "%" represents the modulo operation, and "bl" represents the burst length.

4. A semiconductor system, comprising: Memory device, comprising: A memory cell array comprising multiple memory regions; and Peripheral circuitry accesses the memory cell array by performing burst operations, which support variable burst address gaps; and The memory controller provides the memory device with addresses, burst lengths, and burst address gaps to control the burst operations. The burst address gap is the numerical difference between adjacent column addresses where the burst operation is to be performed. The burst operations include burst write operations, and The memory controller provides the memory device with a selected value from positive integers of 1 or greater as the burst address gap to control the burst write operation.

5. The semiconductor system according to claim 4, The address mentioned includes a row address and a starting column address, and The column address to be executed for the burst operation starts from the starting column address and has the numerical difference between adjacent column addresses with the amount of the burst address gap, and the number of column addresses corresponding to the burst length.

6. The semiconductor system of claim 4, wherein the memory controller controls the memory device to perform a burst write operation in which the value of the burst address gap is the same as the value of the burst length, so as to store a matrix in the memory device.

7. The semiconductor system of claim 6, wherein the memory controller stores the (i, j)th element of the matrix into a memory region having an address determined by Equation 1 below, when the accuracy of the matrix is ​​the same as the device input / output bit width of the memory device. Equation 1: address = Baddr + (i – i % (bl + 1)) Mcol + i % (bl + 1) – 1 + (j - 1) bl Where "Baddr" represents the address of the storage area storing the (1, 1)th element of the matrix, "Mcol" represents the number of columns of the matrix, "%" represents the modulo operation, and "bl" represents the burst length.

8. The semiconductor system of claim 7, wherein, in order to store each row of the matrix into the memory device, the memory controller provides the memory device with: A series of consecutive row addresses, used for the burst write operation, starting from the row address of the initial element of the row as determined by Equation 1, and... The column address of the initial element of the row, determined by Equation 1, is used as the starting column address for the burst write operation.

9. The semiconductor system of claim 7, wherein the burst operation further includes a burst read operation, and The memory controller controls the memory device to perform a burst read operation in which the value of the burst address gap is the same as the value of the burst length, so as to read each row of the matrix from the memory device.

10. The semiconductor system of claim 9, wherein, in order to read rows of the matrix from the memory device, the memory controller provides the memory device with: A series of consecutive row addresses, used for the burst read operation, starting from the row address of the initial element of the row as determined by Equation 1, and... The column address of the initial element of the row, determined by Equation 1, is used as the starting column address for the burst read operation.

11. The semiconductor system of claim 7, wherein the burst operation further includes a burst read operation, and The memory controller controls the memory device to perform a burst read operation with the burst address gap value being 1, in order to read each column of the matrix from the memory device.

12. The semiconductor system of claim 11, wherein, in order to read columns of the matrix from the memory device, the memory controller provides the memory device with: The row address used for the burst read operation, the row address starting from the row address of the initial element of the column as determined by Equation 1, and the numerical difference between adjacent row addresses being the amount of the burst length, and The column address of the initial element of the column determined by Equation 1 is used as the starting column address for the burst read operation.

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