Memory device and method of operation thereof

Abstract

Embodiments of the present disclosure relate to a memory device and an operating method thereof. The memory device includes a memory block to which a plurality of lines are connected. The memory device further includes a plurality of memory cells connected to word lines among the plurality of lines, respectively, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit. The memory device further includes a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines. The memory device additionally includes a peripheral circuit for performing a read operation on the plurality of memory cells. The peripheral circuit includes a voltage generator configured to control a signal applied to the plurality of page buffers such that the read operation is performed according to a location of the plug hole.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0071813, filed with the Korean Intellectual Property Office on June 2, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to electronic devices, and more specifically to memory devices and methods of operating thereof. Background Technology

[0004] Storage devices are devices that store data under the control of host devices such as computers, smartphones, and tablets. Storage devices include: devices configured to store data on disks (such as hard disk drives (HDDs)); and devices configured to store data in semiconductor memory (specifically, non-volatile memory, such as memory included in solid-state drives (SSDs) or memory cards).

[0005] Storage devices can include memory devices configured to store data and memory controllers configured to control the memory devices. Memory devices are classified as volatile memory devices or non-volatile memory devices. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Summary of the Invention

[0006] The embodiments provide a memory device for controlling signals applied to page buffers differentiated for each plug hole, and a method of operating the memory device.

[0007] According to one embodiment of this disclosure, a memory device includes a memory block, with a plurality of lines connected to the memory block. The memory device also includes a plurality of memory cells, each connected to a word line among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of vias, the vias being formed in a stacked structure between a drain select line and a slot among the plurality of lines. The memory device further includes a plurality of page buffers, the page buffers being connected to the plurality of memory cells via a plurality of bit lines among the plurality of lines. The memory device additionally includes peripheral circuitry for performing read operations on the plurality of memory cells. The peripheral circuitry includes a voltage generator configured to control signals applied to the plurality of page buffers such that read operations are performed according to the positions of the vias.

[0008] According to another aspect of this disclosure, there is a method for operating a memory device, the memory device including a memory block, with a plurality of lines connected to the memory block. The method includes: during a read operation on the memory block, when a plurality of memory cells, each connected to a word line among the plurality of lines, are formed as plug holes between a drain select line and a slit among the plurality of lines, distinguishing the plurality of plug holes formed in a stacked structure based on the position of the plug holes. The method further includes: controlling signals applied to a plurality of page buffers connected to the plurality of memory cells via a plurality of bit lines among the plurality of lines, based on the position of the plug holes. Attached Figure Description

[0009] Exemplary embodiments will now be described more fully with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to enable those skilled in the art to implement the present disclosure.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals refer to the same elements throughout the text.

[0011] Figure 1 It is a block diagram illustrating a storage device.

[0012] Figure 2 It's a diagram. Figure 1 The diagram shows the structure of the memory device.

[0013] Figure 3 It's a diagram. Figure 2 A diagram illustrating one embodiment of the memory cell array shown.

[0014] Figure 4 It's a diagram. Figure 3 The circuit diagram shows an embodiment of a memory block within a memory block.

[0015] Figure 5 It's a diagram. Figure 3 A circuit diagram of another embodiment of the memory block shown in the memory block diagram.

[0016] Figure 6 This is a diagram illustrating the memory cells included in a memory block with a three-dimensional structure.

[0017] Figure 7 This is a diagram illustrating a memory block with a single stacked structure.

[0018] Figure 8It is a diagram illustrating a multi-stacked structure.

[0019] Figure 9 This is a diagram illustrating the method for performing operations on each bit line.

[0020] Figure 10 It is a diagram illustrating a method for performing operations on each plug hole.

[0021] Figure 11 It is a diagram illustrating the signals controlled when performing an operation for each plug hole.

[0022] Figure 12A and Figure 12B This is a diagram illustrating the level of the signal applied to the page buffer for each plug hole during sensing operation.

[0023] Figure 13 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0024] Figure 14 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory controller shown.

[0025] Figure 15 This is a block diagram illustrating a memory card system for applying storage devices according to an embodiment of the present disclosure.

[0026] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system for applying storage devices according to an embodiment of the present disclosure.

[0027] Figure 17 This is a block diagram illustrating a user system that applies a storage device to it according to an embodiment of the present disclosure. Detailed Implementation

[0028] The specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0029] Figure 1 It is a block diagram illustrating a storage device.

[0030] refer to Figure 1 The storage device 50 may include the memory device 100 and the memory controller 200.

[0031] Storage device 50 can be a device for storing data under the control of host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0032] Depending on the host interface used for communication with host 300, storage device 50 can be manufactured as any of various types of storage devices. For example, storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro-MMC, secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0033] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of the following package types: Point-of-Package (POP), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-on-Package (WFP), and Wafer-on-Stacked Package (WSP).

[0034] Memory device 100 can store data. Memory device 100 operates under the control of memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and the plurality of memory cells may form a plurality of pages. In one embodiment, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0035] In one embodiment, memory device 100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the case where memory device 100 includes NAND flash memory is assumed and described.

[0036] In one embodiment, the memory device 100 may be implemented as a two-dimensional array structure or a three-dimensional array structure. In the following description, while an embodiment of the memory device 100 as a three-dimensional array structure is presented, this disclosure is not limited to three-dimensional array structures. This disclosure can be applied not only to flash memory devices in which the charge storage layer is configured with a floating gate (FG), but also to charge-trapped flash memory (CTF) in which the charge storage layer is configured with an insulating layer.

[0037] In one embodiment, the memory device 100 may operate using a single-level cell (SLC) method in which one of its data bits is stored in a memory cell. Alternatively, the memory device 100 may operate using a method in which at least two data bits are stored in a memory cell. For example, the memory device 100 may operate using a multi-level cell (MLC) method in which two data bits are stored in a memory cell, a three-level cell (TLC) method in which three data bits are stored in a memory cell, or a four-level cell (QLC) method in which four data bits are stored in a memory cell.

[0038] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access an address-selected region in the memory cell array. That is, memory device 100 can perform operations corresponding to commands on the address-selected region. For example, memory device 100 can perform write (programming), read, or erase operations based on the received commands. For instance, when a programming command is received, memory device 100 can program data in the address-selected region. When a read command is received, memory device 100 can read data from the address-selected region. When an erase command is received, memory device 100 can erase data stored in the address-selected region.

[0039] In one embodiment, when the memory device 100 performs a programming operation, differences in the threshold voltage distribution of memory cells between the plug holes may occur. When the memory cells are formed in a stacked structure of a three-dimensional array structure, the plug holes can be formed in vertical holes that penetrate word lines and interlayer insulating layers.

[0040] In one embodiment, the width of the memory cell included in the plug hole can be varied depending on the location of the plug hole (i.e., the upper or lower part of the plug hole). Additionally, the width of the memory cell included in each plug hole between adjacent plug holes can be varied. Therefore, when the width of the memory cell changes, differences in the threshold voltage distribution of the memory cells between plug holes may occur during programming operations.

[0041] In one embodiment, memory device 100 may distinguish page buffers from each other based on the addresses of memory cells. For example, some strings to which memory cells are connected may be connected to page buffers via even-numbered bit lines, while other strings may be connected via odd-numbered bit lines. When memory device 100 performs an operation, it may perform an operation on memory cells connected to even-numbered bit lines or on memory cells connected to odd-numbered bit lines.

[0042] However, when page buffers are differentiated based on address, differences in the threshold voltage distribution of memory cells between plug holes may occur, as described above.

[0043] Therefore, in this disclosure, to compensate for differences in the threshold voltage distribution of memory cells between sockets, a method is disclosed for distinguishing page buffers for each socket and controlling the level of the signal applied to the page buffer for each socket during a sensing operation. The sensing operation can be a read operation or a verification operation.

[0044] In one embodiment, the memory device 100 includes a voltage generator 122. The voltage generator 122 can control the signal to be applied to the page buffer for each plug hole during sensing operations. That is, the operation can be performed for each plug hole, rather than for memory cells connected to even-numbered bit lines or memory cells connected to odd-numbered bit lines. The voltage generator 122 can control the amplitude of the signal applied to the page buffer for each plug hole. In one embodiment, the amplitude of the signal means the voltage amplitude of the signal.

[0045] The memory controller 200 can control the overall operation of the memory device 50.

[0046] When a power supply voltage is applied to the storage device 50, the memory controller 200 can execute firmware (FW). When the storage device 100 is a flash memory device, the memory controller 200 can execute FW such as a flash translation layer (FTL) to control communication between the host 300 and the storage device 100.

[0047] In one embodiment, the memory controller 200 may include firmware (not shown) that receives data and logical block addresses (LBAs) from the host 300 and translates the LBAs into physical block addresses (PBAs), where the PBAs represent the addresses of memory cells in the memory device 100 where the data will be stored. Furthermore, the memory controller 200 may store a logical-physical address mapping table in a buffer memory (not shown) that establishes a mapping relationship between logical block addresses (LBAs) and physical block addresses (PBAs).

[0048] The memory controller 200 can control the memory device 100 to perform programming, reading, and erasing operations in response to requests from the host 300. For example, when a programming request is received from the host 300, the memory controller 200 can change the programming request into a programming command and provide the memory device 100 with the programming command, physical block address PBA, and data. When a read request is received from the host 300 along with a logical block address LBA, the memory controller 200 can change the read request into a read command, select the physical block address PBA corresponding to the logical block address LBA, and then provide the read command and physical block address PBA to the memory device 100. When an erase request is received from the host 300 along with a logical block address LBA, the memory controller 200 can change the erase request into an erase command, select the physical block address PBA corresponding to the logical block address LBA, and then provide the erase command and physical block address PBA to the memory device 100.

[0049] In one embodiment, the memory controller 200 can control at least two memory devices. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance.

[0050] The host 300 can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0051] Figure 2 It's a diagram. Figure 1 The diagram shows the structure of the memory device.

[0052] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0053] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLn. Each memory block in the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0054] A row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0055] Each memory cell in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0056] The peripheral circuit 120 can perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0057] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0058] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In another embodiment, the row lines RL may also include pipe select lines.

[0059] The row decoder 121 decodes the row address RADD received from the control logic 130. Based on the decoded address, the row decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz. Furthermore, the row decoder 121 can select at least one word line of the selected memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to at least one word line WL.

[0060] For example, in a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage lower than the programming voltage to the unselected word lines. In a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word lines. In a reading operation, the line decoder 121 can apply a reading voltage to the selected word line and a reading pass voltage higher than the reading voltage to the unselected word lines.

[0061] In one embodiment, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the row decoder 121 selects a memory block based on the decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0062] Voltage generator 122 operates under the control of control logic 130. Voltage generator 122 generates multiple voltages using an external power supply voltage provided to memory device 100. Specifically, voltage generator 122 can generate various operating voltages Vop used in programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130.

[0063] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0064] In one embodiment, voltage generator 122 can generate multiple voltages by using an external power supply voltage or an internal power supply voltage.

[0065] For example, voltage generator 122 may include a plurality of pump capacitors for receiving internal power supply voltages, and generate a plurality of voltages by selectively activating the plurality of pump capacitors under the control of control logic 130.

[0066] The generated voltages can be provided to the memory cell array 110 by the row decoder 121.

[0067] Page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 via first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn operate under the control of control logic 130. Specifically, the first to nth page buffers PB1 to PBn can operate in response to the page buffer control signal PBSIGNALS. For example, the first to nth page buffers PB1 to PBn can temporarily store data received via the first to nth bit lines BL1 to BLn, or sense the voltage or current of the bit lines BL1 to BLn during read or verification operations.

[0068] Specifically, during the programming operation, when a programming voltage is applied to the selected word line, the first to nth page buffers PB1 to PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first to nth bit lines BL1 to BLn. The memory cell of the selected page is programmed according to the transmitted data DATA. During the programming verification operation, the first to nth page buffers PB1 to PBn read page data by sensing the voltage or current received from the selected memory cell via the first to nth bit lines BL1 to BLn.

[0069] During the read operation, the first to nth page buffers PB1 to PBn, under the control of the column decoder 124, read data DATA from the memory cell of the selected page through the first to nth bit lines BL1 to BLn, and output the read data DATA to the input / output circuit 125.

[0070] During the erase operation, the first to nth page buffers PB1 to PBn can either float the first to nth bit lines BL1 to BLn or apply an erase voltage.

[0071] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can transfer data with the first to nth page buffers PB1 to PBn via the data line DL, or with the input / output circuitry 125 via the column line CL.

[0072] The input / output circuit 125 can transmit data from the memory controller (…). Figure 1 The command CMD and address ADDR received by 200 (as shown in the figure) are transmitted to control logic 130, or data DATA is exchanged with column decoder 124.

[0073] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the enable bit VRYBIT signal and output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0074] Control logic 130 can control peripheral circuitry 120 in response to commands CMD and address ADDR by outputting operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRYBIT. For example, control logic 130 can control the read operation of a selected memory block in response to a sub-block read command and address. Furthermore, control logic 130 can control the erase operation of selected sub-blocks included in the selected memory block in response to a sub-block erase command and address. Additionally, control logic 130 can determine whether a verification operation passes or fails by using the PASS signal or the FAIL signal. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0075] Figure 3 It's a diagram. Figure 2 A diagram illustrating one embodiment of the memory cell array 110 shown.

[0076] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). The multiple memory cells may be arranged along the +X, +Y, and +Z directions. The structure of each memory block will be referenced... Figure 4 and Figure 5 To describe in more detail.

[0077] Figure 4 It's a diagram. Figure 3The circuit diagram of any one of the memory blocks BLKa in the memory blocks BLK1-BLKz shown.

[0078] refer to Figure 4 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged along the row direction (i.e., the +X direction). Although Figure 4 The diagram illustrates the arrangement of two unit strings along the column direction (i.e., the +Y direction), but this is for ease of description, and it can be understood that three or more unit strings can be arranged along the column direction.

[0079] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0080] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0081] In one embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending along the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. Figure 4 In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors of cell strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0082] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0083] The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0084] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are connected through the channel transistor PT. The gate electrodes of the first to nth memory cells MC1 to MCn in each cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0085] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0086] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged along the row direction are connected to drain select lines extending along the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0087] The cell strings arranged in the column direction are connected to bit lines extending in the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0088] In a row-oriented cell string, memory cells connected to the same word line constitute a page. For example, memory cells in cell strings CS11 to CS1m in the first row connected to the first word line WL1 constitute one page. Memory cells in cell strings CS21 to CS2m in the second row connected to the first word line WL1 constitute another page. When either drain select line DSL1 or DSL2 is selected, a cell string arranged in a row direction can be selected. When any word line WL1 to WLn is selected, a page can be selected from the selected cell string.

[0089] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided in place of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0090] In one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKa can be improved. On the other hand, the size of the memory block BLKa increases. When the number of dummy memory cells decreases, the size of the memory block BLKa decreases. On the other hand, the operational reliability of the memory block BLKa may deteriorate.

[0091] To efficiently control at least one dummy memory cell, the dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of the memory block BLKa. When the erase operation is performed after the programming operation, the threshold voltage of the dummy memory cell controls the voltage applied to the dummy word line connected to the corresponding dummy memory cell, enabling the dummy memory cell to receive the required threshold voltage.

[0092] Figure 5 It's a diagram. Figure 3 The circuit diagram shows another embodiment of the memory block BLKb of any of the memory blocks BLK1 to BLKz shown.

[0093] refer to Figure 5 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0094] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged on the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged on the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged on the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a common source select line.

[0095] The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gate electrodes of the first to nth memory cells MC1 to MCn are respectively connected to the first to nth word lines WL1 to WLn.

[0096] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0097] therefore, Figure 5 The memory block BLKb has the same Figure 4 The circuitry of the memory block BLKa is similar to that of the circuitry, except that the pipe transistor PT is switched from... Figure 5 Each unit string in the string is excluded.

[0098] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided in place of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings in the row-direction cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings in the row-direction cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0099] Additionally, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn.

[0100] Figure 6This is a diagram illustrating the memory cells included in a memory block with a three-dimensional structure.

[0101] refer to Figure 6 The memory block can be formed as a stacked structure ST, which includes multiple word lines WL and interlayer insulating layers IT stacked in a direction perpendicular to the substrate (+Z), and plugs PLG perpendicularly penetrating the word lines WL and interlayer insulating layers IT. The word lines WL and interlayer insulating layers IT can be stacked alternately. The word lines WL can be formed of a conductive material, and the interlayer insulating layers IT can be formed of an insulating material.

[0102] The plug PLG may include a gap filler layer GF, a channel layer CHL, and a memory layer MR formed in a vertical via VH, wherein the vertical via VH perpendicularly penetrates a word line WL and an interlayer insulating layer IT. The gap filler layer GF may be formed as a cylindrical shape extending vertically (+Z) at the center of the vertical via VH. The channel layer CHL may be formed as a cylindrical shape surrounding the sidewalls of the gap filler layer GF, and the memory layer MR may be formed as a cylindrical shape surrounding the sidewalls of the channel layer CHL. The gap filler layer GF may be formed of an insulating material, and the channel layer CHL may be formed of polysilicon. Alternatively, instead of the gap filler layer GF, the channel layer CHL may be formed as a cylindrical shape at the center of the vertical via VH.

[0103] The memory layer MR may include: a tunnel insulating layer TO having a cylindrical shape, surrounding the sidewalls of the channel layer CHL; a charge trapping layer TR having a cylindrical shape, surrounding the sidewalls of the tunnel insulating layer TO; and a barrier layer BK having a cylindrical shape, surrounding the sidewalls of the charge trapping layer TR. The tunnel insulating layer TO may be formed as an oxide layer made of an insulating material, the charge trapping layer TR may be formed as a nitride layer, and the barrier layer BK may be formed as an oxide layer made of an insulating material. The tunnel insulating layer TO is the layer through which electrons tunnel between the channel layer CHL and the charge trapping layer TR, the charge trapping layer TR is the layer in which electrons are trapped, and the barrier layer BK is the layer that prevents the electrons trapped in the charge trapping layer TR from moving to the word line WL.

[0104] The memory cell includes a plug adjacent to a word line in the stacked structure ST, and the width of the memory cell is defined by each component that constitutes the plug PLG.

[0105] For example, the plug PLG is formed in the vertical hole VH that vertically penetrates the word line WL and the interlayer insulating layer IT, and therefore the width of the plug PLG is determined according to the width of the vertical hole VH.

[0106] Ideally, the width of the vertical aperture VH should be the same regardless of its location. However, due to manufacturing process characteristics, the width of the vertical aperture VH can vary depending on the height of the stacked structure ST. Therefore, since memory cells can also be formed differently depending on their height, the operating voltage in this embodiment can be set differently based on the structure of the memory cells. The structure of the memory cells can correspond to the width of the memory cells.

[0107] Additionally, although memory cells have similar structures, electrical differences may exist due to the properties of the materials constituting the memory cells or word lines WL. Therefore, word lines WL can be grouped according to the structure of the memory cells, the groups of word lines WL can be flexibly changed according to the electrical characteristics of the memory cells, and the operating voltage can be set differently according to the changed groups.

[0108] Figure 7 This is a diagram illustrating a memory block with a single stacked structure.

[0109] refer to Figure 7 A single stacked structure ST is a structure in which a vertical via VH perpendicularly penetrates the stacked word line WL and the interlayer insulating layer IT through a single etching process. Due to the etching process, the vertical via VH can be formed to have an upper width wider than its lower width. That is, the slope of the sidewalls of the vertical via VH may not be perpendicular to the substrate and may have a curved surface. For example, when the width of the lowermost part of the vertical via VH is a first width W1, the width of the middle height of the vertical via VH can be a second width W2 that is wider or narrower than the first width W1, and the width of the uppermost part of the vertical via VH can be a third width W3 that is wider than the second width W2.

[0110] Therefore, the width of the memory cells included in the plug PLG can vary depending on the position of the plug PLG. For example, a memory cell formed at the bottom of the plug PLG can have a first width W1, a memory cell formed at the middle height of the plug PLG can have a second width W2, and a memory cell formed at the top of the plug PLG can have a third width W3.

[0111] Therefore, the word lines WL included in a single stacked structure ST can be divided into multiple groups according to the structure of the memory cells. For example, word lines WL can be divided into a first group GR1 in which the memory cells have a narrow width and a second group GR2 in which the memory cells have a wide width. For example, word lines WL formed in the lower region of a first boundary word line WLb1 formed at the center of the memory string can be included in the first group GR1, and word lines WL formed in the upper region above the first boundary word line WLb1 can be included in the second group GR2.

[0112] In one embodiment, during programming or reading operations, the voltage applied to the selected word line and the voltage applied to the unselected word line can be set differently according to the first group GR1 and the second group GR2.

[0113] The boundary or reference for distinguishing the first group GR1 and the second group GR2 from each other can be set as the word line at the uppermost end of the first group GR1, the word line at the lowermost end of the second group GR2, or the region in which an interlayer insulating layer IT is formed between adjacent word lines in the first group GR1 and the second group GR2.

[0114] The boundary region that distinguishes the first group GR1 and the second group GR2 from each other can be flexibly changed through test operations of some memory cells included between the first group GR1 and the second group GR2.

[0115] Figure 8 It is a diagram illustrating a multi-stacked structure.

[0116] refer to Figure 7 and Figure 8 , Figure 8 The illustration shows when Figure 7 The diagram shows a single stack being stacked into multiple stacks. Figure 8 In the diagram, the dashed line represents any one of the multiple plug holes.

[0117] In one embodiment, multiple stacks can be stacked between a DSL selection mask (DSM) and a slit (SLIT2). The DSL selection mask (DSM) and the slit (SLIT2) can be connected via first to fourth lines H1 to H4. The DSL selection mask (DSM) is a mask marked to distinguish the drain selection lines, and the slit (SLIT2) can be a region that distinguishes the stacked areas and connects peripheral circuitry to the bottom of the stacked structure via metal.

[0118] Additionally, the first line H1 can be connected to the zero even line E0, the second even line E2, and the fourth even line E4; the second line H2 can be connected to the first even line E1 and the third even line E3; the third line H3 can be connected to the zero odd line O0, the second odd line O2, and the fourth odd line O4; and the fourth line H4 can be connected to the first odd line O1 and the third odd line O3.

[0119] In one embodiment, each of the first to fourth lines H1 to H4 can be connected to a plug hole between the DSL selection mask DSM and the slit SLT2.

[0120] For example, the first wire H1, connected to the zeroth even-numbered wire E0, can be connected to the first plug hole HOLE1 via the interlayer contact portion INTERLAYER CONTACT. Additionally, the third wire H3, connected to the zeroth odd-numbered wire O0, can be connected to the third plug hole HOLE3 via the interlayer contact portion INTERLAYER CONTACT; the second wire H2, connected to the first even-numbered wire E1, can be connected to the second plug hole HOLE2 via the interlayer contact portion INTERLAYER CONTACT; and the fourth wire H4, connected to the first odd-numbered wire O1, can be connected to the fourth plug hole HOLE4 via the interlayer contact portion INTERLAYER CONTACT.

[0121] In the manner described above, the wires connected to each bit line can be connected to the plug hole via the interlayer contact.

[0122] Figure 9 This is a diagram illustrating the method for performing operations on each bit line.

[0123] refer to Figure 8 and Figure 9 , Figure 9 The illustration shows that in Figure 8 The method for performing operations on memory cells connected to even-number bit lines BL_E in the multi-stack structure shown.

[0124] In one embodiment, an even bit line and an odd bit line that are adjacent to each other can be connected to a page buffer. For example, the zeroth even bit line E0 connected to the first line H1 and the zeroth odd bit line O0 connected to the third line H3 can be connected to a page buffer, and the first even bit line E1 connected to the second line H2 and the first odd bit line O1 connected to the fourth line H4 can be connected to a page buffer.

[0125] In one embodiment, each of the even-numbered bit line BL_E and the odd-numbered bit line BL_O can be connected to a page buffer. For example, the zeroth even-numbered bit line E0 connected to the first line H1 can be connected to a page buffer, and the zeroth odd-numbered bit line O0 connected to the third line H3 can be connected to a page buffer.

[0126] In this disclosure, it is assumed that each of the even bit line BL_E and the odd bit line BL_O is connected to a page buffer.

[0127] In one embodiment, the memory device ( Figure 1 As shown in 100, operations can be performed by distinguishing the even-numbered bit lines BL_E and the odd-numbered bit lines BL_O from each other. That is, in the memory device ( Figure 1The multiple page buffers included in 100 shown can be distinguished according to the bit lines they are connected to. Depending on whether the memory cell to which the operation is performed is connected is connected to an even bit line BL_E or an odd bit line BL_O, the operation can be performed through the page buffer connected to the corresponding bit line.

[0128] For example, memory devices ( Figure 1 The 100 shown can perform operations on memory cells connected to the zeroth to third even-numbered bit lines E0 to E3. That is, the memory device ( Figure 1 The 100 shown can perform operations on memory cells connected to the zeroth to the third even bit lines E0 to E3 through page buffers connected to the zeroth to the third even bit lines E0 to E3 respectively.

[0129] The zeroth and first even-numbered bit lines E0 and E1 can be connected to input / output device IO_01 via a page buffer, and the second and third even-numbered bit lines E2 and E3 can be connected to input / output device IO_23. Input / output devices IO_01 and IO_23 can be included in the input / output circuitry. Figure 2 In 125 shown.

[0130] However, when memory devices ( Figure 1 As shown in 100), when the page buffer is selected during programming operations by distinguishing between even-numbered bit lines BL_E and odd-numbered bit lines BL_O, differences in the threshold voltage distribution of memory cells between the plug holes may occur. That is, when the page buffer is selected relative to the bit lines and the signal applied to the page buffer is determined, the threshold voltage distribution characteristics may deteriorate due to differences in programming speed, depending on the structural differences between the plug holes, i.e., the differences in the width of memory cells between the plug holes.

[0131] Therefore, in this disclosure, the page buffer is selected for each plug hole rather than for bit lines, and the signal applied to the page buffer is determined for each plug hole, thereby providing a method to mitigate or prevent the degradation of threshold voltage distribution characteristics.

[0132] Figure 10 It is a diagram illustrating a method for performing operations on each plug hole.

[0133] refer to Figure 8 and Figure 10 , Figure 10 The diagram illustrates the use of... Figure 8 The method for performing operations on memory cells with first plug hole HOLE1 and second plug hole HOLE2 in the multi-stacked structure shown.

[0134] exist Figure 10In the middle, OFC1 and OFC2 are areas that can contact the interlayer contact portion INTERLAYER CONTACT, and respectively present the area of ​​the first line H1 and the area of ​​the second line H2. The areas of the first line H1 and the second line H2 are respectively connected to the first plug hole HOLE1 and the second plug hole HOLE2 through the interlayer contact portion INTERLAYER CONTACT.

[0135] In one embodiment, the memory device ( Figure 1 The 100 shown can perform operations by differentiating the plug holes from one another. For example, a memory device ( Figure 1 The 100 shown can be used with the first to fourth plug holes HOLE1 to HOLE4, and Figure 8 The slit SLIT2 shown in the diagram operates on the first plug hole HOLE1 and the second plug hole HOLE2 adjacent to it, and then operates on the third plug hole HOLE3 and the fourth plug hole HOLE4. Alternatively, the memory device ( Figure 1 The 100 shown can be used with the first to fourth plug holes HOLE1 to HOLE4, and Figure 8 The DLS shown performs operations on the third plug hole HOLE3 and the fourth plug hole HOLE4 adjacent to the DSM selection mask, and then performs operations on the first plug hole HOLE1 and the second plug hole HOLE2.

[0136] Therefore, when memory devices ( Figure 1 When the 100 shown performs its operation by separating the plug holes from each other, the memory device ( Figure 1 The multiple page buffers included in 100 shown can be distinguished from each other according to the plug hole, and operation can be performed by page buffers connected to bit lines corresponding to lines connected through the interlayer contact portion INTERLAYER CONTACT.

[0137] For example, memory devices ( Figure 1 As shown in Figure 100, operations can be performed on the first plug hole HOLE1 and the second plug hole HOLE2. That is, the memory device ( Figure 1 The 100 shown can be operated by page buffers corresponding to the zero and second even bit lines E0 and E2 connected to the first plug hole HOLE1 via the interlayer contact INTERLAYER CONTACT, and page buffers corresponding to the first and third even bit lines E1 and E3 connected to the second plug hole HOLE2 via the interlayer contact INTERLAYER CONTACT.

[0138] In one embodiment, when the memory device ( Figure 1When programming is performed on each plug hole (as shown in 100), the degradation of the threshold voltage distribution characteristics due to the width difference of the memory cells between the plug holes can be mitigated or prevented.

[0139] In one embodiment, when the memory device ( Figure 1 The method used to control the amplitude of the signal applied to the page buffer corresponding to the bit line connected to the plug hole when performing a sensing operation for each plug hole (100) shown in the figure may be problematic.

[0140] Figure 11 It is a diagram illustrating the signals controlled when performing an operation on each plug hole.

[0141] refer to Figure 2 and Figure 11 , Figure 11 The diagram shows... Figure 2 The first page buffer PB1 is shown among the multiple page buffers PB1 to PBn. Each of the second to nth page buffers PB2 to PBn can also be configured with... Figure 11 Same parts.

[0142] In one embodiment, the first page buffer PB1 can be connected to the first memory cell MC1 via the first bit line BL1, and can perform a bit line precharge (BL precharge) operation to charge the first bit line BL1 with charge supplied from the internal power supply voltage VCCI via the first to fifth transistors M1 to M5. The first transistor M1 is controlled by the first sensing signal PBSENSE, the second transistor M2 is controlled by the first precharge signal SA_CSOC, and the third transistor M3 is controlled by the first latch 190_1. Additionally, the fourth transistor M4 is controlled by the second precharge signal SA_PRECH_N, and the fifth transistor M5 is controlled by the second sensing signal SA_SENSE.

[0143] Furthermore, the first page buffer PB1 can discharge the charge charged into the first bit line BL1 to the internal ground voltage VSSI through the first transistor M1, the sixth transistor M6, and the seventh transistor M7. The sixth transistor M6 is controlled by the first discharge signal SA_DISCH, and the seventh transistor M7 is controlled by the first latch 190_1.

[0144] In one embodiment, the first page buffer PB1 may include a first latch 190_1, which includes a first inverter INV1 and a second inverter INV2. The first latch 190_1 can control the bit line precharge (BL precharge) operation by turning a third transistor M3 on or off via a first Q-node Q1. The first Q-node Q1b and the first Q-node Q1 have values ​​that are inverses of each other.

[0145] During the sensing operation of the first memory cell MC1, the voltage of the first sensing node SO1 is determined based on the threshold voltage of the first memory cell MC1. The first latch 190_1 can store the result obtained by sensing the threshold voltage of the first memory cell MC1 via a ninth transistor M9 connected to the first sensing node SO1. The ninth transistor M9 can be an N-type MOS transistor, and the first sensing node SO1 can be connected to the gate node of the ninth transistor M9.

[0146] Therefore, when the threshold voltage of the first memory cell MC1 is low, the first sensing node SO1 can go low during the sensing operation, and the ninth transistor M9 can be turned off. When the threshold voltage of the first memory cell MC1 is high, the sensing node SO1 can go high during the sensing operation, and the ninth transistor M9 can be turned on.

[0147] In one embodiment, the first inverter INV1 and the second inverter INV2 included in the first latch 190_1 are respectively connected to the internal power supply voltage VCCI and the internal ground voltage VSSI.

[0148] In one embodiment, the memory device ( Figure 1 The amplitude of the first sensing signal PBSENSE applied to the gate of the first transistor M1, among the signals applied to the first page buffer PB1, can be controlled differently for each plug hole. The signal applied to the first page buffer PB1 can be generated by a voltage generator ( Figure 2 As shown in 122), it is generated.

[0149] For example, when memory devices ( Figure 1 When 100 (as shown) performs a sensing operation for each plug hole, the amplitude of the first sensing signal PBSENSE can be set differently depending on the position of the plug hole. That is, the amplitude of the first sensing signal PBSENSE applied to the page buffer connected to the bit line can be controlled according to the position of the plug hole, which corresponds to the line connected through the interlayer contact.

[0150] Specifically, memory devices ( Figure 1The 100 shown can be determined based on whether the plug hole is aligned with... Figure 8 The DSL selection mask shown is adjacent to or plugs the same as... Figure 8 The slit SLT2 shown is adjacent to control the amplitude of the first sensing signal PBSENSE.

[0151] Figure 12A and Figure 12B This is a diagram illustrating the level of the signal applied to the page buffer for each plug hole during sensing operation.

[0152] refer to Figure 8 , Figure 11 , Figure 12A and Figure 12B , Figure 12A The diagram illustrates the operation performed for each plug hole. Figure 11 The first sensing signal PBSENSE shown increases as the sensor gets closer to slit SLIT2, while... Figure 12B The diagram illustrates the operation performed for each plug hole. Figure 11 The diagram shows the case where the first sensing signal PBSENSE decreases as it gets closer to slit SLIT2. In other words, the amplitude of the first sensing signal PBSENSE can increase or decrease depending on the position of the plug hole.

[0153] In one embodiment, the memory device ( Figure 1 The 100 shown can perform a sensing operation for each plug hole. The sensing operation can be a reading operation or a verification operation.

[0154] When a sensing operation is performed for each plug hole, the memory device ( Figure 1 As shown in 100), the amplitude of the first sensing signal PBSENSE applied to the page buffer corresponding to the plug hole can be controlled for each plug hole. The page buffer corresponding to the plug hole can be connected to a bit line corresponding to the line connected to the corresponding plug hole through the interlayer contact.

[0155] refer to Figure 12A When performing sensing operations for each plug hole, as the plug hole gets closer to slit SLIT2, the memory device ( Figure 1 The 100 shown can increase the amplitude of the first sensing signal PBSENSE. Alternatively, as the plug hole gets closer to the DSL selection mask DSM, the memory device ( Figure 1 The 100 shown can reduce the amplitude of the first sensing signal PBSENSE.

[0156] For example, the amplitude of VPBSENSE_H1, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the first plug hole HOLE1, can be greater than the amplitude of VPBSENSE_H2, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the second plug hole HOLE2. That is, because the first plug hole HOLE1 is closer to the slit SLIT2 than the second plug hole HOLE2, or because the first plug hole HOLE1 is farther from the DSL selection mask DSM than the second plug hole HOLE2, the amplitude of VPBSENSE_H1 can be greater than the amplitude of VPBSENSE_H2.

[0157] As described above, the amplitude of VPBSENSE_H2 can be greater than the amplitude of VPBSENSE_H3, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the third plug hole HOLE3. Additionally, the amplitude of VPBSENSE_H3 can be greater than the amplitude of VPBSENSE_H4, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the fourth plug hole HOLE4.

[0158] refer to Figure 12B When performing sensing operations for each plug hole, as the plug hole gets closer to slit SLIT2, the memory device ( Figure 1 The 100 shown can reduce the amplitude of the first sensing signal PBSENSE. Alternatively, as the plug hole gets closer to the DSL selection mask DSM, the memory device ( Figure 1 The 100 shown can increase the amplitude of the first sensing signal PBSENSE.

[0159] For example, the amplitude of VPBSENSE_H1, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the first plug hole HOLE1, can be smaller than the amplitude of VPBSENSE_H2, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the second plug hole HOLE2. That is, because the first plug hole HOLE1 is closer to the slit SLIT2 than the second plug hole HOLE2, or because the first plug hole HOLE1 is farther from the DSL selection mask DSM than the second plug hole HOLE2, the amplitude of VPBSENSE_H1 can be smaller than the amplitude of VPBSENSE_H2.

[0160] As described above, the amplitude of VPBSENSE_H2 can be smaller than the amplitude of VPBSENSE_H3, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the third plug hole HOLE3. Additionally, the amplitude of VPBSENSE_H3 can be smaller than the amplitude of VPBSENSE_H4, which is the signal applied to the gate of the first transistor M1 in the page buffer corresponding to the fourth plug hole HOLE4.

[0161] Figure 13 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0162] refer to Figure 13 In step S1301, the memory device can generate a group for each plug hole during the sensing operation. When the memory cells are formed in a stacked structure of a three-dimensional array structure, the plug holes can be formed in vertical holes that penetrate the word lines and interlayer insulating layers.

[0163] When a group is generated for each plug hole, in step S1303, the memory device may generate a signal to be applied to the page buffer for each plug hole group.

[0164] For example, sensing operations can be preferentially performed on some of the multiple plug holes. The memory device can control the signals applied to the page buffer based on whether the plug hole is close to or far from the slit SLIT2 or DSL selection mask DSM.

[0165] In one embodiment, the amplitude of the signal applied to the page buffer may increase as the plug orifice gets closer to the slit. Alternatively, the amplitude of the signal applied to the page buffer may decrease as the plug orifice gets closer to the slit.

[0166] Figure 14 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory controller shown.

[0167] refer to Figure 14 The memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device in response to requests received from the host. For example, the memory controller 1000 is configured to control reading, programming, erasing, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0168] The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

[0169] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0170] Processor 1010 can control the overall operation of memory controller 1000 and execute logical operations. Processor 1010 can communicate with an external host through host interface 1040 and with memory devices through memory interface 1060. Furthermore, processor 1010 can communicate with memory buffer 1020 through buffer control circuit 1050. Processor 1010 can use memory buffer 1020 as working memory, cache memory, or buffer memory to control the operation of memory devices.

[0171] Processor 1010 can perform the functions of a Flash Translation Layer (FTL). Processor 1010 can translate logical block addresses (LBAs) provided by the host through the FTL into physical block addresses (PBAs). The FTL can use a mapping table to receive logical block addresses (LPAs) to be translated into physical block addresses (PBAs). Depending on the mapping unit, there are several address mapping methods for the FTL. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0172] Processor 1010 is configured to randomize data received from the host. For example, processor 1010 may use a randomization seed to randomize data received from the host. The randomized data is provided as data to be stored in a memory device to be programmed in a memory cell array.

[0173] The processor 1010 can perform randomization and derandomization via driver software or firmware.

[0174] The memory buffer 1020 can be used as the working memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0175] ECC circuit 1030 can perform ECC operations. ECC circuit 1030 can perform ECC encoding on data to be written to the memory device via memory interface 1060. The ECC-encoded data can be transferred to the memory device via memory interface 1060. ECC circuit 1030 can perform ECC decoding on data received from the memory device via memory interface 1060. In one embodiment, ECC circuit 1030 can be included as a component of memory interface 1060 within memory interface 1060.

[0176] The host interface 1040 can communicate with an external host under the control of the processor 1010. The host interface 1040 can communicate with the host using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Faster (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Depleted DIMM (LRDIMM).

[0177] The buffer control circuit 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0178] The memory interface 1060 is configured to communicate with a memory device under the control of the processor 1010. The memory interface 1060 can transmit commands, addresses, and data with the memory device via a channel.

[0179] In one embodiment, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050.

[0180] In one embodiment, processor 1010 can control the operation of memory controller 1000 using code. Processor 1010 can load code from a non-volatile memory device (e.g., a device including read-only memory (ROM)) configured in memory controller 1000. In another example, processor 1010 can load code from a memory device via memory interface 1060.

[0181] In one embodiment, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus are separate from each other and do not interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0182] Figure 15 This is a block diagram illustrating a memory card system 2000 for applying storage devices according to an embodiment of the present disclosure.

[0183] refer to Figure 15 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0184] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 is configured to control read, write, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory device 2200 can interact with memory device 100 (… Figure 1 The same implementation is shown in 100).

[0185] In one embodiment, the memory controller 2100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0186] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to a specific communication protocol. In one embodiment, the memory controller 2100 can communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0187] In one embodiment, the memory device 2200 may be implemented using non-volatile memory, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque transfer magnetic RAM (STT-MRAM).

[0188] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and memory device 2200 can form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro and eMMC), an SD card (SD, miniSD, microSD and SDHC), and a universal flash memory (UFS).

[0189] In one embodiment, the memory cells included in the memory device 2200 can be formed into a three-dimensional array structure. In the three-dimensional array structure, the memory cells can be formed into a stacked structure, and plug holes can be formed in vertical holes that penetrate word lines and interlayer insulating layers. The stacked structure can be formed between the slit SLIT2 and the DSL selection mask DSM.

[0190] In one embodiment, when the memory device 2200 performs a sensing operation, the sensing operation can be performed on a per-plug hole basis. For example, the memory device 2200 may preferentially perform sensing operations on memory cells of plug holes adjacent to the slit SLIT2. Alternatively, the memory device 2200 may preferentially perform sensing operations on memory cells of plug holes adjacent to the DSL selection mask DSM.

[0191] The memory device 2200 may configure the amplitude of the signal applied to the gate of the transistor connecting the bit line and the page buffer to increase as the plug orifice gets closer to the slit SLIT2. Alternatively, the memory device 2200 may configure the amplitude of the signal applied to the gate of the transistor connecting the bit line and the page buffer to decrease as the plug orifice gets further away from the slit SLIT2.

[0192] The memory device 2200 performs a programming operation for each plug hole, so that the degradation of the threshold voltage distribution characteristics caused by the difference in the width of the memory cells between the plug holes can be mitigated or prevented.

[0193] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system 3000 with an applied storage device according to an embodiment of the present disclosure.

[0194] refer to Figure 16 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0195] In one embodiment, the SSD controller 3210 can be used as a memory controller. Figure 1 (200 as shown).

[0196] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to a signal SIG received from host 3100. In one embodiment, signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0197] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can provide power to SSD 3200 when the power supply from host 3100 is unstable. In one embodiment, auxiliary power supply 3230 may be located inside SSD 3200 or external to SSD 3200. For example, auxiliary power supply 3230 may be located on the motherboard and provide auxiliary power to SSD 3200.

[0198] Buffer memory 3240 operates as a buffer memory for SSD 3200. Auxiliary power supply 3230 can receive and charge power PWR from host 3100. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0199] In one embodiment, the memory cells included in each of the plurality of flash memories 3221 to 322n can be formed into a three-dimensional array structure. In the three-dimensional array structure, the memory cells can be formed into a stacked structure, and plug holes can be formed in vertical holes that penetrate word lines and interlayer insulating layers. The stacked structure can be formed between slit SLIT2 and the DSL selection mask DSM.

[0200] In one embodiment, when the plurality of flash memories 3221 to 322n perform sensing operations, the sensing operations can be performed on a per-plug hole basis. For example, the plurality of flash memories 3221 to 322n may preferentially perform sensing operations on memory cells of plug holes adjacent to slit SLIT2. Alternatively, the plurality of flash memories 3221 to 322n may preferentially perform sensing operations on memory cells of plug holes adjacent to DSL selection mask DSM.

[0201] Multiple flash memories 3221 to 322n can be configured to increase the amplitude of the signal applied to the gate of the transistor connecting the bit line and the page buffer as the plug orifice gets closer to the slit SLIT2. Alternatively, the multiple flash memories 3221 to 322n can be configured to decrease the amplitude of the signal applied to the gate of the transistor connecting the bit line and the page buffer as the plug orifice gets further away from the slit SLIT2.

[0202] Multiple flash memories 3221 to 322n perform programming operations for each plug hole, so that the degradation of threshold voltage distribution characteristics caused by the difference in the width of memory cells between plug holes can be mitigated or prevented.

[0203] Figure 17 This is a block diagram illustrating a user system 4000 that applies a storage device to it according to an embodiment of the present disclosure.

[0204] refer to Figure 17 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0205] Application processor 4100 can drive components included in user system 4000, operating system (OS), user programs, etc. In one embodiment, application processor 4100 may include a controller for controlling components, interfaces, graphics engines, etc., included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0206] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 4100 and the memory module 4200 can be unified into a single semiconductor package through a stacked package (PoP) based packaging.

[0207] Network module 4300 can communicate with external devices. In one embodiment, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Exemplarily, network module 4300 may be included in application processor 4100.

[0208] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored therein to application processor 4100. In one embodiment, storage module 4400 can be implemented using a non-volatile semiconductor memory, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. In one embodiment, storage module 4400 can be a removable drive device such as a memory card of user system 4000 or an external drive device.

[0209] In one embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may be connected to a reference. Figures 2 to 5 The memory device described operates in the same manner. Storage module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0210] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. In one embodiment, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0211] In one embodiment, the memory cells included in the memory module 4400 can be formed into a three-dimensional array structure. In the three-dimensional array structure, the memory cells can be formed into a stacked structure, and plug holes can be formed in vertical holes that penetrate word lines and interlayer insulating layers. The stacked structure can be formed between the slit SLIT2 and the DSL selection mask DSM.

[0212] In one embodiment, when the storage module 4400 performs a sensing operation, the sensing operation can be performed on a per-plug hole basis. For example, the storage module 4400 may preferentially perform sensing operations on memory cells in plug holes adjacent to the slit SLIT2. Alternatively, the storage module 4400 may preferentially perform sensing operations on memory cells in plug holes adjacent to the DSL selection mask DSM.

[0213] The memory module 4400 can set the amplitude of the signal applied to the gate of the transistor connecting the bit line and the page buffer to increase as the plug orifice gets closer to the slit SLIT2. Alternatively, the memory module 4400 can set the amplitude of the signal applied to the gate of the transistor connecting the bit line and the page buffer to decrease as the plug orifice gets further away from the slit SLIT2.

[0214] The storage module 4400 performs programming operations for each plug hole, so that the degradation of the threshold voltage distribution characteristics caused by the width difference of the memory cells between the plug holes can be mitigated or prevented.

[0215] According to one embodiment of this disclosure, the amplitude of the signal applied to the page buffer for each plug hole is set differently, so that degradation of the threshold voltage distribution can be prevented.

[0216] While this disclosure has been shown and described with reference to certain embodiments, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure, and that the scope of this disclosure is defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0217] In the above embodiments, all steps may be performed selectively, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0218] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

Claims

1. A memory device comprising a memory block, wherein a plurality of lines are connected to the memory block, the memory device comprising: Multiple memory cells are respectively connected to word lines among the multiple lines, wherein the multiple memory cells are formed as multiple plug holes, and the multiple plug holes are formed in a stacked structure between a drain select line and a slit among the multiple lines. Multiple page buffers are connected to the multiple memory cells via multiple bit lines among the multiple lines; as well as The peripheral circuitry is configured to perform a read operation on the memory cell of the first of the plurality of plug holes. The first plug hole includes at least two memory cells from the plurality of memory cells and is connected to at least two bit lines from the plurality of bit lines. The peripheral circuitry includes a voltage generator configured during the read operation to adjust the amplitude of a signal applied to at least two page buffers corresponding to at least two bit lines, based on the position of the first plug hole, to precharge the at least two bit lines.

2. The memory device of claim 1, wherein the voltage generator is capable of controlling the amplitude of a signal applied to a first transistor connected to each of the at least two bit lines, among the transistors included in each of the at least two page buffers, based on the position of the first plug hole.

3. The memory device of claim 2, wherein the peripheral circuitry is configured to perform the read operation on the first plug hole, which is adjacent to the drain select line, among the plurality of plug holes.

4. The memory device of claim 3, wherein as the first plug hole becomes closer to the drain select line, the voltage generator is able to increase the amplitude of the signal applied to the first transistor.

5. The memory device of claim 3, wherein as the first plug hole becomes closer to the drain select line, the voltage generator is able to reduce the amplitude of the signal applied to the first transistor.

6. The memory device of claim 3, wherein the peripheral circuitry is configured to perform the read operation on the first plug hole adjacent to the drain select line, and then perform the read operation on the second plug hole adjacent to the slit.

7. The memory device of claim 2, wherein the peripheral circuitry is configured to perform the read operation on the first plug hole, which is adjacent to the slit among the plurality of plug holes.

8. The memory device of claim 7, wherein the voltage generator is able to increase the amplitude of the signal applied to the first transistor as the first plug hole becomes closer to the drain select line.

9. The memory device of claim 7, wherein as the first plug hole becomes closer to the drain select line, the voltage generator is able to reduce the amplitude of the signal applied to the first transistor.

10. The memory device of claim 7, wherein the peripheral circuitry is configured to perform the read operation on the first plug hole adjacent to the slit, and then on the second plug hole adjacent to the drain select line.

11. A method for operating a memory device, the memory device comprising a memory block, a plurality of lines connected to the memory block, wherein the memory block includes a plurality of memory cells respectively connected to word lines among the plurality of lines and a plurality of page buffers connected to the plurality of memory cells via a plurality of bit lines among the plurality of lines, and wherein the plurality of memory cells are formed as a plurality of plug holes, the plurality of plug holes being formed in a stacked structure between a drain select line and a slot among the plurality of lines, the method comprising: Multiple plug hole groups are generated according to the positions of the multiple plug holes; A first plug hole group is determined, the first plug hole group includes at least two memory cells among the plurality of memory cells, and the first plug hole group is connected to at least two bit lines among the plurality of bit lines; as well as During the read operation of the first plug hole group, the amplitude of the signal applied to at least two page buffers corresponding to the at least two bit lines is adjusted according to the position of the first plug hole group in order to precharge the at least two bit lines.

12. The method of claim 11, wherein adjusting the amplitude of the signal comprises: The amplitude of the signal applied to the first transistor, which is connected to each of the at least two bit lines, is controlled among the transistors included in each of the at least two page buffers.

13. The method of claim 12, wherein the read operation is performed on the first plug hole group among the plurality of plug hole groups that is adjacent to the drain select line.

14. The method of claim 13, wherein adjusting the amplitude of the signal comprises: As the first plug hole group moves closer to the drain selection line, the amplitude of the signal applied to the first transistor increases.

15. The method of claim 13, wherein adjusting the amplitude of the signal comprises: As the first plug hole group moves closer to the drain selection line, the amplitude of the signal applied to the first transistor decreases.

16. The method of claim 13, wherein after the read operation is performed on the first plug hole group adjacent to the drain select line, the read operation is performed on the second plug hole group adjacent to the slit.

17. The method of claim 12, wherein the reading operation is performed on the first group of plug holes adjacent to the slit among the plurality of plug holes.

18. The method of claim 17, wherein adjusting the amplitude of the signal comprises: As the first plug hole group moves closer to the drain selection line, the amplitude of the signal applied to the first transistor increases.

19. The method of claim 17, wherein adjusting the amplitude of the signal comprises: As the first plug hole group moves closer to the drain selection line, the amplitude of the signal applied to the first transistor decreases.

20. The method of claim 17, wherein after the read operation is performed on the first plug hole group adjacent to the slit, the read operation is performed on the second plug hole group adjacent to the drain select line.

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