Memory control logic circuit and memory address redirection method

Abstract

A memory control logic and a memory address redirection method are disclosed. The memory control logic includes: a one-time programmable memory array; an array control circuit for programming the memory capacity type of the memory cell array, the corresponding region failure flags of each region in the memory cell array, and the corresponding redirection mapping tables of each region to a first array, a second array, and a third array in the one-time programmable memory array, respectively; and an address redirection circuit for converting address signals into first redirection address signals for input to the memory cell array according to the corresponding redirection mapping tables of each region in the one-time programmable memory array.

Description

Technical Field

[0001] This invention relates to memory circuits, and more particularly to a memory control logic and a memory address redirection method. Background Technology

[0002] With the continuous development of electronic products and related applications, the integration of memory and system-on-a-chip (SoC), coupled with breakthroughs in 2D / 2.5D / 3D packaging technologies, has enabled the memory industry to achieve greater flexibility and adaptability in memory design and assembly. Furthermore, as memory capacity continues to expand and semiconductor processes continue to miniaturize, it is difficult to achieve significant breakthroughs in chip yield without the support of relevant technologies (backup devices, error correction codes, etc.). If an entire memory chip has to be scrapped due to minor defects, resulting in direct cost waste and indirect environmental damage, this is something the industry would not want to see. Summary of the Invention

[0003] In view of this, the present invention provides a memory control logic and a memory address redirection method to solve the above problems.

[0004] This invention provides memory control logic disposed in a memory circuit. The memory circuit includes a memory cell array, which is divided into multiple regions, and the multiple regions include at least one damaged region. The memory circuit receives an address signal. The memory control logic includes: a one-time programmable memory array; an array control circuit for programming the memory capacity type of the memory cell array, the corresponding region failure flags of each region in the memory cell array, and the corresponding redirection maps of each region to a first array, a second array, and a third array in the one-time programmable memory array; wherein the array control circuit further performs a programming operation on the redirection maps of each region in the one-time programmable memory array according to the memory capacity type to redirect the redirection maps of each damaged region to a non-repeating good region among the multiple regions; and an address redirection circuit for converting the address signal into a first redirection address signal for input to the memory cell array according to the redirection maps of each region in the one-time programmable memory array.

[0005] In some embodiments, the first array is a two-bit array [S1,S0], and when the two-bit array [S1,S0] is 0b00, 0b01, 0b10 and 0b11, the two-bit array [S1,S0] corresponds to 100%, 50%, 25% and 12.5% ​​of the memory capacity type, respectively.

[0006] In some embodiments, one or more good regions in the plurality of regions have a first quantity, and when the proportion R of the number of the one or more good regions to the first quantity is between 75% and 100%, 50% and 75%, 25% and 50%, and 12.5% ​​and 25%, the array control circuit programs the two-bit array [S1, S0] of the first array as 0b00, 0b01, 0b10, and 0b11, respectively.

[0007] In some embodiments, the memory circuit further includes a row decoder to decode the address signal to obtain a row address signal, and the address redirection circuit converts the row address signal into the redirection address signal for input to the memory cell array according to the corresponding redirection mapping table of each region in the one-time programmable memory array.

[0008] In some embodiments, when the memory capacity is 50%, the array control circuit sequentially searches for the damaged region in the first half-region of the memory cell array. Once the array control circuit has found the damaged region in the first half-region, it sequentially searches for a good region in the second half-region of the memory cell array. When the array control circuit has found a good region in the second half-region but has not yet found a recent good region, it programs the redirection map corresponding to the damaged region as the region index corresponding to the good region, and sets the region failure flag corresponding to the good region to 1. The array control circuit further programs the redirection map corresponding to each region in the second half-region as the region index of the corresponding position in the first half-region.

[0009] In some embodiments, when the memory capacity is 25%, the array control circuit sequentially searches for the damaged region in the first quarter region of the memory cell array. Once the array control circuit has found the damaged region in the first quarter region, it sequentially searches for good regions in the remaining regions of the memory cell array. When the array control circuit has found the good region in the remaining regions and has not yet found the nearest good region, it programs the redirection map corresponding to the damaged region as the region index corresponding to the good region and sets the region failure flag corresponding to the good region to 1. The array control circuit further programs the redirection map corresponding to each region in the second, third, and fourth quarter regions of the memory cell array as the region index of the corresponding position in the first quarter region.

[0010] In some embodiments, when a good area of ​​the memory circuit becomes a new damaged area during use, the array control circuit searches for another good area in the second half of the memory cell array and programs the redirection mapping table corresponding to the new damaged area to redirect to the area index corresponding to the other good area.

[0011] In some embodiments, the address redirection circuit includes a logic circuit for converting the first redirection address signal into a second redirection address signal according to the memory capacity type and inputting it to the memory cell array.

[0012] In some embodiments, when the two-bit array [S1,S0] is 0b00, the logic circuit sets the most significant bit of the second redirection address signal to the most significant bit of the first redirection address signal. When the two-bit array [S1,S0] is not 0b00, the logic circuit sets the most significant bit of the second redirection address signal to 0. When bit S1 = 1, the logic circuit sets the second most significant bit of the second redirection address signal to 0. When bit S1 = 0, the logic circuit sets the second most significant bit of the second redirection address signal to the second most significant bit of the first redirection address signal. When the two-bit array [S1,S0] is 0b11, the logic circuit sets the third most significant bit of the second redirection address signal to 0. When the two-bit array [S1,S0] is not 0b11, the logic circuit sets the third most significant bit of the second redirection address signal to the third most significant bit of the first redirection address signal.

[0013] In some embodiments, the memory cell array further includes one or more spare regions, and the memory control logic further utilizes the one or more spare regions to replace the at least one damaged region.

[0014] The present invention further provides a memory address redirection method for a memory circuit, the memory circuit including a memory control logic and a memory cell array, the memory cell array being divided into multiple regions, and the multiple regions including at least one damaged region, wherein the memory control logic includes a one-time programmable memory array, and the memory circuit receiving an address signal. The method includes: programming the memory capacity type of the memory cell array, the corresponding region failure flags of each region in the memory cell array, and the corresponding redirection mapping tables of each region to a first array, a second array, and a third array in the one-time programmable memory array; performing a programming operation on the redirection mapping tables corresponding to each region in the one-time programmable memory array according to the memory capacity type to redirect the redirection mapping tables corresponding to each damaged region to a non-repeating good region among the multiple regions; and converting the address signal into a first redirection address signal based on the corresponding redirection mapping tables of each region in the one-time programmable memory array for input to the memory cell array.

[0015] When the memory cell array in the memory circuit is damaged, the address signal can be redirected to a good area by properly programming the one-time programmable memory array. Therefore, the memory control logic and memory address redirection method of the present invention can effectively utilize the memory capacity to improve the yield of memory chips. Attached Figure Description

[0016] Figure 1 This is a block diagram of a memory circuit according to an embodiment of the present invention.

[0017] Figures 2A to 2C This is a schematic diagram of address remapping operations according to three different embodiments of the present invention.

[0018] Figures 3-4 The following are block diagrams of memory circuits according to two different embodiments of the present invention.

[0019] Figures 5A-5B This is a schematic diagram illustrating multiple address remapping operations according to another embodiment of the present invention.

[0020] Figure 6 According to the present invention Figure 4 A schematic diagram of the address redirection circuit in the embodiment.

[0021] Figure 7A This is a flowchart of a memory address redirection method according to an embodiment of the present invention.

[0022] Figure 7B According to the present invention Figure 7A A flowchart of step S706 in the embodiment.

[0023] Attached icon number

[0024] 100, 400: Memory circuit

[0025] 110, 410: Memory control logic

[0026] 111, 411: Array control circuit

[0027] 112, 412: Address redirection circuit

[0028] 113, 413: One-time programmable memory array

[0029] 120, 420: Memory cell array

[0030] 130, 430: Line decoder

[0031] 140, 440: Column decoder

[0032] 451, 452: Inverters

[0033] 453-456: AND gate

[0034] 457: NAND gate

[0035] 1200-1208, 4200-4207: Area

[0036] 1131, 4131: First array

[0037] 1132, 4132: Second array

[0038] 1133, 4133: Third array

[0039] 4121: Logic Circuits

[0040] 200, 210, 220, 500, 510: Table

[0041] 202-202, 211, 221, 501, 511: Arrows

[0042] DQ: Data signal

[0043] S0, S1: bit

[0044] An~A0: Address signals

[0045] A n (L), A n-1 (L), A n-2 (L): Address signal

[0046] A n (i), An-1 (i), A n-2 (i): Address signal

[0047] S702-S710: Steps

[0048] S7061-S7066: Steps Detailed Implementation

[0049] Figure 1 This is a block diagram of a memory circuit according to an embodiment of the present invention.

[0050] The memory circuit 100 includes memory control logic 110, a memory cell array 120, a row decoder 130, and a column decoder 140. The memory circuit 100 receives read / write signals, control signals, a data signal DQ, and an address signal A[n:0]. The memory control logic 110 controls the memory cell array 120 based on the read / write signals and control signals (e.g., chip select (CS#), row address strobe (RAS#), column address strobe (CAS#), and write enable (WE#), etc.). Furthermore, the memory control logic 110 can also perform refresh operations on the memory cell array 120.

[0051] The total capacity of the memory space in memory cell array 120 is 2 n The memory cell array 120 can be divided into multiple regions 1200 to 1207, where each region 1200 to 1207 has the same memory space. Furthermore, the memory cell array 120 can be divided into regions 1200 to 1207 according to memory banks, memory blocks, or other partitioning methods. The row decoder 130 and column decoder 140 perform row decoding and column decoding on the address signals A[n-1:0] to transmit the row address signals and column address signals to the memory cell array 120. For example, if the total memory space capacity of the memory cell array 120 is 4Gb = 2 32 If the number of digits is 32, then n = 32.

[0052] The memory control logic 110 includes an array control circuit 111, an address redirection circuit 112, and an one-time programmable (OTP) memory array 113. The OTP memory array 113 includes a first array 1131, a second array 1132, and a third array 1133. The first array 1131 is used to record the available memory capacity of the memory cell array 120, wherein the first array 1131 is an m-bit array, which can be used to represent 2^m bits. mThe memory capacity type is specified. The second array 1132 records the region failure flags for each region; for example, a region failure flag of 0 indicates the corresponding region is available (pass) (i.e., a good region), and a region failure flag of 1 indicates the corresponding region is failed (i.e., a damaged region). The array control circuit 111 can configure the second array 1132 based on the test results of each region of the memory cell array 120. In this embodiment, the second array 1132 is an RC-bit array, and the number of regions RC = 8. The third array 1133 records a redirection mapping table to define redirection addresses to non-repeating good regions in the memory cell array 120, wherein the third array 1133 is a RAC*RC-bit array, where RAC represents the number of pins for the redirection address. In some embodiments, the OTP memory array 113 can be implemented, for example, using an electronically programmable fuse (eFuse).

[0053] Address redirection circuit 112 reads the redirection mapping table corresponding to each region in the third array 1133 and converts the address signal into a redirection address signal for input to the memory cell array 120.

[0054] In one embodiment, if the first array 1131 is a 2-bit array [S1, S0], then the combinations of different memory capacities that the first array 1131 can represent are shown in Table 1:

[0055]

[0056] Table 1

[0057] For example, when array [S1,S0] = 0b00 (note: binary value), it indicates that the memory cell array 120 is defect-free, and all regions 1200 to 1207 in the memory cell array 120 are in good condition. At this time, the address signal A[n:0] can be directly input to the memory cell array 120 without address re-mapping. When array [S1,S0] = 0b01, it indicates that some regions are invalid and unusable, but the ratio R of the number of good regions to the total number of regions in the memory cell array 120 is greater than 50% (i.e., 50% <= R < 100%). At this time, the address signal that can be used for addressing becomes A[n-1:0], so the proportion of usable memory capacity of the memory cell array 120 becomes 1 / 2 (i.e., 50%).

[0058] When array [S1,S0] = 0b10, it indicates that some areas are invalid and unusable, but the ratio R of the number of good areas to the total number of areas in memory cell array 120 is greater than 25% (i.e., 25% <= R < 50%). In this case, the address signals actually usable for addressing become A[n-2:0], so the usable memory capacity ratio of memory cell array 120 becomes 1 / 4 (i.e., 25%). When array [S1,S0] = 0b11, it indicates that some areas are invalid and unusable, but the ratio of the number of good areas to the total number of areas in memory cell array 120 is greater than 12.5%. In this case, the address signals usable for addressing become A[n-3:0], so the usable memory capacity ratio of memory cell array 120 becomes 1 / 8 (i.e., 12.5%).

[0059] Additionally, it should be noted that in this embodiment, if the ratio R is below 1 / 8 (i.e., 12.5%), the memory cell array 120 will be judged as defective during memory testing. If the memory cell array 120 can be divided into more regions, the ratio R can be adjusted downwards as needed, for example, to 1 / 16 or 1 / 32.

[0060] Figure 2A This is a schematic diagram of an address remapping operation according to an embodiment of the present invention.

[0061] Assuming that the memory address space of regions 1200 to 1207 in memory cell array 120 is contiguous, if regions 1200 to 1207 in memory cell array 120 are not damaged, then the memory address space of regions 1200 to 1207 can be separated by the highest 3 bits A[n], A[n-1], and A[n-2] of the address signal A[n:0]. For example, address signal A[n:n-2] of (0,0,0) corresponds to region 1200 (region index 0), address signal A[n:n-2] of (0,0,1) corresponds to region 1201 (region index 1), address signal A[n:n-2] of (0,1,0) corresponds to region 1202, and so on.

[0062] In the first scenario, the capacity of memory cell array 120 is reduced to half. In this embodiment, two regions in memory cell array 120 are identified as damaged regions by memory testing operations, such as regions 1200 and 1203. Therefore, the region failure flags corresponding to regions 1200 and 1203 (region indices 0 and 3) are both set to 1. Figure 2AAs shown in Table 200. Because the memory cell array 120 is divided into 8 regions and two regions are damaged regions, the usable memory capacity ratio R of the memory cell array 120 is 1 / 2 (i.e., 50%). At this time, the array control circuit 111 can program the first array 1131 in the OTP memory array 113 as [S1,S0] = 0b01, and program the redirection mapping table [RD2,RD1,RD0] corresponding to region indices 0 and 3 as 0b100 and 0b101, respectively, as shown by arrows 201 and 202.

[0063] In detail, since the proportion of good regions in the memory cell array 120 is greater than 50%, the corresponding redirection mapping address can be found in the first half region (e.g., the upper half region) of the memory cell array 120, and the redirection mapping table [RD2,RD1,RD0] in the second half region (e.g., the lower half region) of the memory cell array 120 can be directly copied from the redirection mapping table [RD2,RD1,RD0] in the first half region.

[0064] Through the above process, the highest bit A[n] of the address signal A[n:0] can be ignored, and the capacity of the memory cell array 120 can be reduced to 1 / 2. When accessing the highest bit A[n], the value of the highest bit A[n] does not need to be considered. That is, regardless of whether A[n] = 0 or 1, the memory control logic 110 can correctly access the data in the memory cell array 120.

[0065] In detail, Figure 2A In this embodiment, the array control circuit 111 sequentially searches for damaged regions in the first half-region (e.g., the upper half-region) of the memory cell array 120, for example, the region index i = 0 to 3 of the first half-region. When the array control circuit 111 finds a damaged region in the first half-region (i.e., the region failure flag = 1), the array control circuit 111 sequentially searches for good regions in the second half-region (e.g., the region index i = 4 to 7). When the array control circuit 111 finds a good region in the second half-region (e.g., region index j) and has not yet found the nearest good region (e.g., flag 1st_good_region = 0), the array control circuit 111 redirects the damaged region to the mapping table corresponding to region index j, sets the region failure flag of the good region of region index j to 1, and sets the flag 1st_good_region to 1. If the array control circuit 111 finds a good region (region index i) in the first half-region, the array control circuit 111 will program the corresponding redirection mapping table of the good region to region index i, that is, use the original region index i of the good region as its redirection mapping table.

[0066] Next, for each region index i in the second half region (e.g., the lower half region) of the memory cell array 120, the array control circuit 111 will program the redirection mapping table of each region index i (e.g., i = RC / 2 to RC-1) in the second half region to the corresponding region index (i-RC / 2) in the first half region.

[0067] Figure 2B This is a schematic diagram of an address remapping operation according to another embodiment of the present invention.

[0068] In the second scenario, the capacity of the memory cell array 120 is reduced to 1 / 4 (i.e., 25%). In this embodiment, five regions in the memory cell array 120 are identified as damaged regions by the memory test operation, such as regions 1201, 1202, 1203, 1204, and 1206. Therefore, the region failure flags corresponding to regions 1201, 1202, 1203, 1204, and 1206 (region indices 1, 2, 3, 4, and 6) are all set to 1. Figure 2B As shown in Table 210, the memory cell array 120 actually only has two good area indices left to use.

[0069] Since region 1201 of region index 0 is a good region, the address signal A[n:n-2] corresponding to region index 0 can be used directly. At this time, the array control circuit 111 programs the first array 1131 in the OTP memory array 113 as [S1,S0] = 0b10, and programs the redirection mapping table [RD2,RD1,RD0] corresponding to region index 1 as 0b101, as shown by arrow 211. Therefore, through the above process, the redirection mapping table of the first quarter region (i.e., region indexes 0 and 1) in table 210 has been established. Therefore, the redirection mapping tables [RD2,RD1,RD0] of the second quarter region (i.e., region indexes 2 and 3), the third quarter region (i.e., region indexes 4 and 5), and the fourth quarter region (i.e., region indexes 6 and 7) in table 210 can be copied to the redirection mapping table [RD2,RD1,RD0] of the first quarter region.

[0070] In detail, Figure 2BIn this embodiment, the array control circuit 111 sequentially identifies damaged regions in the first quarter region of the memory cell array 120, for example, the region index i of the first half region is 0 to (RC / 4-1). When RC=8, the region index i of the first half region includes 0 and 1. When the array control circuit 111 identifies a damaged region in the first quarter region (i.e., the region failure flag = 1), the array control circuit 111 sequentially searches for good regions in the remaining region (e.g., region index i = (RC / 4) to (RC-1), i.e., i = 2 to 7). If the array control circuit 111 finds a good region in the remaining region (e.g., region index j) and has not yet found the nearest good region (e.g., flag 1st_good_region = 0), the array control circuit 111 redirects the damaged region to the corresponding mapping table and programs it as region index j, sets the region failure flag of the good region of region index j to 1, and sets the flag 1st_good_region to 1. If the array control circuit 111 finds a good region (region index i) in the first quarter region, the array control circuit 111 will program the corresponding redirection mapping table of the good region as region index i, that is, use the original region index i of the good region as its redirection mapping table.

[0071] Next, for each region index i in the second, third, and fourth quarter regions of the memory cell array 120, the array control circuit 111 will program the redirection mapping table of each region index i in the second, third, and fourth quarter regions to the corresponding region index in the first quarter region. For example, when region index i = RC / 4 to RC / 2-1 (i.e., corresponding to the second quarter region), the array control circuit 111 will program the redirection mapping table corresponding to region index i to region index (i-RC / 4), the redirection mapping table corresponding to region index (i+RC / 4) to region index (i-RC / 4), and the redirection mapping table corresponding to region index (i+RC / 2) to region index (i-RC / 4).

[0072] Figure 2C This is a schematic diagram of an address remapping operation according to another embodiment of the present invention.

[0073] In the third scenario, the capacity of memory cell array 120 is reduced to 1 / 8 (i.e., 12.5%). In this embodiment, seven regions in memory cell array 120 are identified as damaged regions by memory test operations, such as regions 1200 to 1206. Therefore, the region failure flags corresponding to regions 1200 to 1206 (region indices 0 to 6) are all set to 1. Figure 2CAs shown in Table 220, the memory cell array 120 actually only has one good region index left to use.

[0074] The array control circuit 111 programs the first array 1131 in the OTP memory array 113 as [S1,S0] = 0b11, and programs the redirection mapping table [RD2,RD1,RD0] corresponding to region index 0 as 0b111, as shown by arrow 221. Therefore, through the above process, the redirection mapping table of the first octet (i.e., region index 0) in table 220 has been established, so the redirection mapping tables [RD2,RD1,RD0] of the second to eighth quartiles (i.e., region indices 1 to 7) in table 210 can be copied to the redirection mapping table [RD2,RD1,RD0] of the first octet.

[0075] Figure 3 This is a block diagram of a memory circuit according to another embodiment of the present invention. Please also refer to... Figure 1 and Figure 3 .

[0076] In another embodiment, the total capacity of the memory space in the memory cell array 120 is 2. n +r, where r represents the spare area. In detail, Figure 3 and Figure 1 The difference lies in Figure 3 The memory cell array 120 further includes a redundant region 1208. It should be noted that the memory cell array 120 of the present invention is not limited to containing only one redundant region, and two or more redundant regions may also be used.

[0077] In detail, when the number of spare regions in the memory cell array 120 is greater than or equal to the number of damaged regions, the memory control logic 110 can utilize its internal circuit design to completely replace the damaged regions with spare regions. At this time, the first array 113 is also programmed as [S1,S0] = 0b00, and the usable capacity ratio R of the memory cell array 120 can still be maintained at 100%, meaning the memory address space can still reach 2^35. n .

[0078] When the total number of good and spare areas in memory cell array 120 is less than the number of general areas RC, but greater than or equal to half of the number of general areas RC, array control circuit 111 will program the first array 113 as [S1,S0] = 0b01. At this time, the usable capacity ratio of memory cell array 120 is reduced to 50%, i.e., the memory address space is 2^32. n / 2. In a similar manner, the available capacity ratio R of the total number of good and spare areas of the memory cell array 120 under different ratios of the number of general areas RC can be derived.

[0079] For example, in the final test stage of the memory chip (e.g., memory circuit 100) at the manufacturing end, multiple memory chips can be sorted and classified according to their test pass numbers. These memory chips may have different available memory spaces after leaving the factory, or the user of the memory chip can use the memory controller (not shown) to read the value of the first array 1131 in the OTP memory array 113 to confirm the available memory space of the memory chip. When the power of the memory circuit is turned on, when the first array 1131 is [S1,S0]=0b01, the row decoder 130 will still transmit the row address signal of the external address signal A[n:0] to the memory control logic 110 in the original column mapping method. However, the address redirection circuit 112 in the memory control logic 110 will remap the row address signal according to the redirection mapping table of the third array 1133, so that the remapped row address can be redirected to a good area.

[0080] Figure 4 This is a block diagram of a memory circuit according to another embodiment of the present invention. Figures 5A-5B This is a schematic diagram illustrating multiple address remapping operations according to another embodiment of the present invention. Figure 6 According to the present invention Figure 4 A schematic diagram of the address redirection circuit in the embodiment. Please also refer to... Figure 4 , Figures 5A-5B and Figure 6 .

[0081] Figure 4 The memory circuit 400 in the middle is similar to Figure 1 The memory circuit 100 differs in that... Figure 4 The array control circuit 411 can perform address redirection programming operations multiple times for damaged areas in the memory cell array 420. Furthermore, the address redirection circuit 412 can be implemented by the address redirection circuit 112 in conjunction with hardware circuitry to achieve automatic masking of one or more most significant bits in the address signal A[n:0], such as... Figure 6 As shown, the details will be elaborated later.

[0082] For example, in Figure 5ATable 500 indicates that when the memory circuit 100 leaves the factory, because region 4200 (corresponding to region index 0) in the memory cell array 420 is a damaged region, the capacity of the memory cell array 420 is reduced to 1 / 2. The array control circuit 411 searches for a good region in the second half of the memory cell array 420 and redirects region 4200 to the mapping table (A). n (L),A n-1 (L),A n-2 (L)) is programmed as 0b100 (corresponding to region index 4), as shown by arrow 501. Furthermore, the array control circuit 411 programs the region failure flag corresponding to region index 4 to 1 to prevent it from being used again (i.e., considered a damaged region).

[0083] When the memory circuit 400 has been used for a period of time or during use, and memory testing reveals that region 4203 (corresponding to region index 3) has changed from a good region to a new damaged region, the array control circuit 411 can search for another good region in the second half of the memory cell array 420 and then... Figure 5B The redirection mapping table (A) corresponding to region 4203 (corresponding to region index 3) in Table 510 n (L),A n-1 (L),A n-2 (L)) is programmed as 0b101, as shown by arrow 511. Furthermore, the array control circuit 411 programs the region failure flag corresponding to region index 5 to 1 to prevent it from being used again (i.e., considered a damaged region). Therefore, when the memory circuit 400 continues to be used, other good regions of the memory cell array 420 become damaged regions. In a similar manner, the array control circuit 411 can redirect the new damaged regions to the redirection mapping table (A) corresponding to them. n (L),A n-1 (L),A n-2 (L)) is programmed to direct to the remaining good area of ​​the memory cell array 420.

[0084] Please refer to Figure 6 It should be noted that in the above embodiments, the address signal A corresponding to the redirection mapping table for each region index... n (L),A n-1 (L),A n-2 (L) (e.g., the first redirect address signal) is not the row address signal that the address redirection circuit 412 finally transmits to the memory cell array 420. For example, the address redirection circuit 412 includes address redirection circuit 112 and logic circuit 4121, and the address signal A of the redirection mapping table output by address redirection circuit 112 is not the row address signal that the address redirection circuit 112 finally transmits to the memory cell array 420. n (L), An-1 (L), A n-2 (L) will then pass through logic circuit 4121 to generate address signal A. n (i), A n-1 (i) and A n-2 (i), where the address signal A n (i), A n-1 (i) and A n-2 (i) (for example, the second redirect address signal) is the row address signal that the address redirection circuit 412 finally transmits to the memory cell array 420.

[0085] In detail, the logic circuit 4121 includes inverters 451 and 452, AND gates 453-456, and NAND gate 457. The logic circuit 4121 can adjust the generated address signal A according to the settings of the array [S1, S0] in the first array 4131. n (i), A n-1 (i) and A n-2 (i).

[0086] For example, if array [S1,S0] = 0b00, then address signal A n (i)=A n (L) means that the available memory capacity of the memory cell array 420 is 100%, and all bits in the address signal A[n:0] are valid bits that can be used for memory addressing. If array [S1,S0]≠0b00, then the address signal A n (i) = 0, meaning there is one or more damaged areas in the memory cell array 420. Therefore, the usable memory capacity of the memory cell array 420 is at most 50%, and the highest bit A of the address signal A[n:0] is... n It should be set to 0.

[0087] If bit S1 = 1, then A n-1 (i) = 0, meaning that the number of damaged areas in the memory cell array 420 has exceeded half of the total number of areas. Therefore, the usable memory capacity of the memory cell array 420 is at most 25%, and the first most significant bit A of the address signal A[n:0] is... n and the second highest position A n-1 All must be set to 0. If bit S1 ≠ 1 (i.e., S1 = 0), then A n-1 (i)=A n-1 (L), meaning that the usable memory capacity of the memory cell array 420 is at least 50%, therefore the second highest bit A in the address signal A[n:0] is... n-1 These are the valid bits that can be used for memory addressing.

[0088] If array [S1,S0] = 0b11, then address signal A n-2 (i) = 0, meaning that the usable memory capacity of memory cell array 420 is 12.5%, and the highest three bits A in address signal A[n:0] are... n A n-1 and A n-2 All must be set to 0. If array [S1,S0]≠0b11, then address signal A n-2 (i)=A n-2 (L), meaning that the usable memory capacity of the memory cell array 420 is at least 25%, therefore the third highest bit A in the address signal A[n:0] is... n-2 These are the valid bits that can be used for memory addressing.

[0089] In certain special cases, the address signal A generated by the address redirection circuit 112 n (L), A n-1 (L), A n-2 One or more bits of (L) may be floating. Through the design of logic circuit 412, the address can be redirected to the address signal A output by circuit 412. n (i), A n-1 (i) and A n-2 (i) The array [S1,S0] can be bound to 0 according to the different cases mentioned above, so as to avoid malfunction of the control logic 410.

[0090] Figure 7A This is a flowchart of a memory address redirection method according to an embodiment of the present invention. Please also refer to... Figure 4 and Figure 7A .

[0091] In step S702, the array control circuit 411 obtains the memory size type (MST) of the memory cell array 420 and the corresponding region failure flags for each region in the memory cell array 420, and programs the memory size type and the corresponding region failure flags to the OTP memory array 413. For example, if the memory cell array 420 has at least one damaged region, the memory size type can be 50%, 25%, or 12.5%, and the number of good regions (Good_regions) = total number of regions (RC) * memory size type (MST). Furthermore, the array control circuit 411 sets the array index n to 0.

[0092] In step S704, the array control circuit 411 determines the current area failure flag. If the area failure flag is 1, then steps S706, S708, and S710 are executed.

[0093] In step S706, the nearest available region is searched and the region index i of the nearest available region is obtained. Here, i is represented by a binary value.

[0094] In step S708, the corresponding redirection mapping table RD_map and the region failure flag for the current region are programmed as i (note: i is represented by a binary number) and 1, respectively.

[0095] In step S710, it is determined whether the array index n is greater than the number of good regions Good_regions. If the array index n is greater than the number of good regions Good_regions, the process ends. If the array index n is not greater than the number of good regions Good_regions, step S712 is executed to increment the array index n by 1, and the process returns to step S704.

[0096] Figure 7B According to the present invention Figure 7A The flowchart of step S706 in the embodiment is also provided. Please refer to the following: Figure 4 and Figures 7A-7B .

[0097] exist Figure 7A Step S706 includes steps S7061 to S7066, wherein step S706 can be regarded as a subfunction to return the region index i of the nearest available region.

[0098] In step S7061, the first index n and the second index m are set to 0. It should be noted that the first index n and the second index m here are for illustrative purposes only, and their values ​​are not necessarily the same as... Figure 7A The array index n is irrelevant.

[0099] In step S7062, the region failure flag corresponding to the first index n is determined. If the region failure flag corresponding to the first index n is 1, then step S7066 is executed to increment the first index n by 1. If the region failure flag corresponding to the first index n is 0, then step S7063 is executed to increment the second index m by 1, and then step S7064 is executed.

[0100] In step S7064, it is determined whether the second index m is equal to the number of good regions Good_regions + 1. If the second index m is equal to the number of good regions Good_regions + 1, then step S7065 is executed to return the first index n. In other words, in this process, the number of detected good regions is equal to the preset number of good regions Good_regions, so step S7065 needs to be executed to return the first index n. If the second index m is not equal to the number of good regions Good_regions, then step S7066 is executed to increment the first index n by 1. In other words, in this process, the number of detected good regions has not yet reached the preset number of good regions Good_regions, so step S7066 needs to be executed to increment the first index n by 1 and steps S7062 to S7064 are repeated.

[0101] In summary, when the memory cell array in a memory circuit is damaged (i.e., a defective memory chip), the address signals can be redirected to a good region by properly programming the OTP memory array. Therefore, the memory control logic and memory address redirection method of this invention can effectively utilize memory capacity to improve the yield of memory chips. Furthermore, clients do not need to use additional circuit board wiring or design when using the memory circuit, thus improving ease of use. For new damaged areas that occur during different periods of use of the memory chip, this invention also provides a highly flexible memory address redirection method that allows for multiple programming of the OTP memory array to extend the lifespan of the memory circuit.

Claims

1. A memory control logic circuit, characterized in that, A memory circuit is configured to receive an address signal. The memory control logic circuit includes: One-time programmable memory array; An array control circuit is used to program the available memory capacity ratio of the memory cell array, the corresponding region failure flags of each region in the memory cell array, and the corresponding redirection mapping tables of each region to the first array, the second array, and the third array in the one-time programmable memory array. The array control circuit further performs a programming operation on the redirection mapping table corresponding to each region in the one-time programmable memory array based on the proportion of available memory capacity, so as to redirect the redirection mapping table corresponding to each damaged region to a non-repeating good region among the multiple regions; and An address redirection circuit is used to convert the address signal into a first redirection address signal for input to the memory cell array based on the redirection mapping table corresponding to each region in the one-time programmable memory array. The failure flag for that area indicates whether the corresponding area is the damaged area; The address redirection circuit blocks one or more of the most significant bits of the first redirection address signal; and The address redirection circuit binds the first redirection address signal to a preset value according to the first array.

2. The memory control logic circuit as described in claim 1, characterized in that, The first array is a two-dimensional array, and the ratio of the number of good regions to the number of good regions is the usable ratio of a region, wherein: When the two-bit array has a first binary value, a second binary value, a third binary value, and a fourth binary value, these correspond to 100%, 50%, 25%, and 12.5% ​​of the available memory capacity, respectively; and When the available percentage of the area is 100%, greater than or equal to 50% and less than 100%, greater than or equal to 25% and less than 50%, or greater than or equal to 12.5% ​​and less than 25%, the array control circuit programs the two-bit array of the first array into the first binary value, the second binary value, the third binary value, and the fourth binary value, respectively.

3. The memory control logic circuit as described in claim 2, characterized in that, The memory circuit further includes a row decoder to decode the address signal to obtain a row address signal, and the address redirection circuit converts the row address signal into the redirection address signal for input to the memory cell array according to the corresponding redirection mapping table of each region in the one-time programmable memory array.

4. The memory control logic circuit as described in claim 2, characterized in that, When the available memory capacity is 50%, the array control circuit sequentially searches for the damaged area in the first half of the memory cell array. Once the array control circuit has located the damaged area in the first half-region, it sequentially searches for the good area in the second half-region of the memory cell array. The array control circuit further programs the redirection mapping table corresponding to each region in the second half region as the region index of the corresponding position in the first half region.

5. The memory control logic circuit as described in claim 2, characterized in that, When the available memory capacity is 25%, the array control circuit sequentially searches for the damaged area in the first quarter region of the memory cell array. Once the array control circuit has located the damaged area within the first quarter region, it sequentially searches for the good areas within the remaining regions of the memory cell array. When the array control circuit has found a good region in the remaining area but has not yet found the nearest good region, the array control circuit programs the redirection mapping table corresponding to the damaged region into the region index corresponding to the good region, and sets the region failure flag corresponding to the good region to 1. The array control circuit further programs the redirection mapping table corresponding to each region of the second, third, and fourth quarter regions of the memory cell array into the region index of the corresponding position in the first quarter region.

6. The memory control logic circuit as described in claim 2, characterized in that, When a good area of ​​the memory circuit becomes a new damaged area during use, the array control circuit searches for another good area in the second half of the memory cell array and programs the redirection mapping table corresponding to the new damaged area to redirect to the area index corresponding to the other good area.

7. The memory control logic circuit as described in claim 6, characterized in that, The address redirection circuit includes a logic circuit for converting the first redirection address signal into a second redirection address signal based on the proportion of available memory capacity, and inputting it to the memory cell array.

8. The memory control logic circuit as described in claim 7, characterized in that, When the two-bit array is the first binary value, the logic circuit sets the most significant bit of the second redirection address signal to the most significant bit of the first redirection address signal; and when the two-bit array is not the first binary value, the logic circuit sets the most significant bit of the second redirection address signal to 0. When the two-bit array is the third binary value, the logic circuit sets the second most significant bit of the second redirection address signal to 0, and when the two-bit array is the second binary value, the logic circuit sets the second most significant bit of the second redirection address signal to the second most significant bit of the first redirection address signal. When the two-bit array is the fourth binary value, the logic circuit sets the third most significant bit of the second redirect address signal to 0, and when the two-bit array is not the fourth binary value, the logic circuit sets the third most significant bit of the second redirect address signal to the third most significant bit of the first redirect address signal.

9. The memory control logic circuit as described in claim 1, characterized in that, The memory cell array further includes one or more spare areas, and the memory control logic circuit further utilizes the one or more spare areas to replace the at least one damaged area.

10. A memory address redirection method, characterized in that, A method for a memory circuit, the memory circuit including a memory control logic circuit and a memory cell array, wherein the memory cell array is divided into multiple regions, and the multiple regions include at least one damaged region, wherein the memory control logic circuit includes a one-time programmable memory array, and the memory circuit receives an address signal, the method comprising: The available memory capacity ratio of the memory cell array, the corresponding region failure flags of each region in the memory cell array, and the corresponding redirection mapping tables of each region are programmed into the first, second, and third arrays of the one-time programmable memory array. Based on the available memory capacity ratio, a programming operation is performed on the redirection map corresponding to each region in the one-time programmable memory array to redirect the redirection map corresponding to each damaged region to a non-overlapping good region among the plurality of regions; and Based on the redirection mapping table corresponding to each region in the one-time programmable memory array, the address signal is converted into a first redirection address signal for input to the memory cell array; The failure flag for that area indicates whether the corresponding area is the damaged area; The address redirection circuit blocks one or more of the most significant bits of the first redirection address signal; and The address redirection circuit binds the first redirection address signal to a preset value according to the first array.

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