写禁止时间的获取方法、装置、测试机台及存储介质
By establishing the relationship between address hold time, address setup time, and write disable time, the problem of difficulty in testing write disable time of storage devices in the prior art is solved, and the evaluation and optimization of address line consistency of storage devices is realized.
CN115440288BActive Publication Date: 2026-07-17INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2021-06-04
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing technologies make it difficult to effectively test the write disable time (tWHWL) parameter of storage devices, resulting in an inability to accurately assess the address line consistency of storage devices and affecting product quality.
Method used
By establishing the relationship between address hold time, address setup time, and write disable time, the write disable time can be calculated using address hold time and address setup time, thereby evaluating the address line consistency of storage devices.
Benefits of technology
It enables accurate assessment of address line consistency of storage devices, improves the optimization capabilities of storage devices, and ensures the accuracy and reliability of write operations.
✦ Generated by Eureka AI based on patent content.
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Figure CN115440288B_ABST
Abstract
本发明公开了写禁止时间的获取方法、装置、测试机台及存储介质，所述方法包括：获取存储器件的地址保持时间以及地址建立时间；基于地址保持时间以及地址建立时间，得到写禁止时间，其中，写禁止时间为禁止向存储器件的地址位进行写入操作的时间长度。本申请能够基于地址保持时间以及地址建立时间，得到写禁止时间，从而反应出存储器件地址线一致性的好坏。
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