Decoding system and method for local enhancement

Abstract

The present disclosure relates to decoding systems and methods for local enhancement. Embodiments of the present disclosure provide a scheme to decode small subgraphs that are very likely to include some errors. A controller is configured to control a first decoder to decode data read from a memory device using a parity check matrix of an error correction code, extract one or more subgraphs from an entire bipartite graph of the parity check matrix defined by a plurality of variable nodes and a plurality of check nodes when a certain condition is satisfied, and control a second decoder to decode a decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraph.

Description

Technical Field

[0001] Embodiments of this disclosure relate to decoding schemes for memory systems. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with multiple memory devices, i.e., multiple data storage devices. The data storage devices are used as either the main memory or auxiliary memory devices in the portable electronic devices.

[0003] Because memory devices have no moving parts, memory systems using them offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs). Memory systems can use various types of decoders. Summary of the Invention

[0004] Aspects of the present invention include a system and a decoding method thereof having an enhanced decoder for decoding small subgraphs that are highly likely to contain some errors.

[0005] In one aspect of the invention, a memory system includes: a memory device for storing data encoded using error correction codes; and a controller including a first decoder having a first precision and a second decoder having a second precision greater than the first precision. The controller is configured to: control the first decoder to decode data read from the memory device using a parity check matrix of the error correction codes; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, defined by a plurality of variable nodes and a plurality of check nodes, when certain conditions are met; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

[0006] In another aspect of the invention, a method for operating a memory system including a memory device storing data encoded using error correction codes and a controller includes: controlling a first decoder having a first precision to decode data read from the memory device using a parity check matrix of the error correction codes; extracting one or more subgraphs from the entire bipartite graph of the parity check matrix defined by a plurality of variable nodes and a plurality of check nodes when certain conditions are met; and controlling a second decoder having a second precision greater than the first precision to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0011] Figure 4 This is a diagram illustrating the distribution of states of different types of cells in a memory device according to an embodiment of the present invention.

[0012] Figure 5A This is a diagram illustrating an example of Gray encoding for a multilayer cell (MLC) according to an embodiment of the present invention.

[0013] Figure 5B This is a diagram illustrating the state distribution of a page in a multi-layer cell (MLC) according to an embodiment of the present invention.

[0014] Figure 6A This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC) according to an embodiment of the present invention.

[0015] Figure 6B This is a diagram illustrating the state distribution of a page in a three-layer cell (TLC) according to an embodiment of the present invention.

[0016] Figure 7 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0017] Figure 8 This is a diagram illustrating a decoding apparatus according to an embodiment of the present invention.

[0018] Figure 9This is a flowchart illustrating a method for operating a decoding device according to an embodiment of the present invention.

[0019] Figure 10 The different degree distributions of the parity check matrix are shown.

[0020] Figure 11 This is a flowchart illustrating the subgraph extraction and use of a decoding apparatus according to an embodiment of the present invention.

[0021] Figure 12 This is a flowchart illustrating a subgraph extraction scheme according to a first embodiment of the present invention.

[0022] Figure 13 This is a flowchart illustrating a subgraph extraction scheme according to a second embodiment of the present invention. Detailed Implementation

[0023] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrase are not necessarily directed to the same(s) embodiments(s). The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0024] This invention can be embodied in a variety of ways, including as a process, apparatus, system, computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by memory linked to the processor. In this specification, these embodiments or any other form of the invention that may be employed can be referred to as technology. Generally, the order of operation of the disclosed processes can vary within the scope of this invention. Unless otherwise stated, components described as suitable for performing a task, such as processors or memory, can be implemented as general components temporarily configured to perform that task at a given time or manufactured as specific components to perform that task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores adapted to process data such as computer program instructions.

[0025] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the computer, processor, controller, or other signal processing device described herein, or an element other than those described herein. Because the algorithms (or operations of the computer, processor, controller, or other signal processing device) upon which the methods are based are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0026] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0027] The following detailed description of embodiments of the invention is provided in conjunction with the accompanying drawings, which illustrate aspects of the invention. The invention has been described in conjunction with these embodiments, but the invention is not limited to any particular embodiment. The scope of the invention is limited only by the claims. The invention covers many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for illustrative purposes only; the invention may be practiced according to the claims without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail, so as not to unnecessarily obscure the invention.

[0028] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0029] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0030] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as: a desktop computer, a workstation, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 may include portable electronic devices such as: a mobile phone, a smartphone, an e-book reader, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0031] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as a component of a variety of electronic devices such as: computers, ultra-mobile personal computers (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, computer networks, telematics networks, or a component of a computing system.

[0032] The memory system 10 may include a controller 100 and a memory device 200. The controller 100 can control the overall operation of the memory device 200.

[0033] The memory device 200 can perform one or more erase, program, and read operations under the control of the controller 100. The memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals.

[0034] The controller 100 and memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the semiconductor memory system 10 is used with an SSD, the performance of host devices coupled to the memory system 10 (e.g., Figure 1 The operating speed of the main unit 5).

[0035] The controller 100 and memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the controller 100 and memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), reduced-size multimedia cards (RS-MMC), micro versions of MMC (MMCmicro), secure digital cards (SD cards), mini secure digital cards (miniSD cards), micro secure digital cards (microSD cards), secure digital high-capacity (SDHC) cards, and / or universal flash memory (UFS).

[0036] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0037] Reference Figure 2 The memory system 10 may include a controller 100 and a memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 The host device 5) operates upon request and, in particular, stores data to be accessed by the host device.

[0038] The memory device 200 can store data to be accessed by the host device.

[0039] The memory device 200 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0040] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device, and can store data provided from the host device into the memory device 200.

[0041] The controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0042] Storage device 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data used by controller 100 and memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0043] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device for read and write operations in storage device 200. For storing data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0044] Control component 120 can control the overall operation of memory system 10 and control write or read operations of memory device 200 in response to write or read requests from host device. Control component 120 can drive firmware called Flash Translation Layer (FTL) to control the overall operation of memory system 10. For example, FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block disposal. L2P mapping is called logical block addressing (LBA).

[0045] ECC component 130 can detect and correct errors in data read from memory device 200 during read operations. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC component 130 may not correct the error bits, but instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0046] In various embodiments, ECC component 130 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or means for appropriate error correction operations.

[0047] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0048] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120.

[0049] Memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer array 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (I / O) circuitry 270. Memory cell array 210 may include multiple memory blocks 211 capable of storing data. Voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for memory cell array 210. Peripheral circuitry may perform programming, reading, or erasing operations on memory cell array 210. Control circuitry 220 may control peripheral circuitry.

[0050] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0051] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. In response to a line address generated by the control circuit 220, the line decoder 240 can select at least one memory block among the plurality of memory blocks 211 and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0052] Page buffer array 250 can be accessed via bit line BL ( Figure 3 (As shown) is connected to the memory cell array 210. The page buffer array 250 can precharge the bit line BL with a positive voltage during programming and reading operations, send data to and receive data from the selected memory block, or temporarily store the transmitted data in response to page buffer control signals generated by the control circuit 220.

[0053] The column decoder 260 can send data to and receive data from the page buffer array 250, or send data to and receive data from the input / output circuit 270.

[0054] Input / output circuit 270 can input from external devices (e.g., Figure 1 The controller 100 receives commands and addresses and sends them to the control circuit 220 to transmit data from the external device to the column decoder 260, or outputs data from the column decoder 260 to the external device through the input / output circuit 270.

[0055] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0056] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0057] Reference Figure 3 Storage block 211 may include multiple word lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel, with multiple word lines located between DSL and SSL.

[0058] The memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be formed as a multi-level cell. For example, each of the memory cells may be formed as a single-level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-level cell (QLC) storing 4 bits of data.

[0059] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells across cell strings can be connected to their respective word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0060] Page buffer array 250 may include multiple page buffers (PB) 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0061] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include (multiple) NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a single NAND flash memory with the controller embedded within the memory chip.

[0062] Figure 4 This is a diagram illustrating the distribution of state or programming voltage (PV) levels of different types of cells in a memory device according to an embodiment of the present invention.

[0063] Reference Figure 4 Each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) for storing 1 bit of data, a multi-level cell (MLC) for storing 2 bits of data, a three-level cell (TLC) for storing 3 bits of data, or a four-level cell (QLC) for storing 4 bits of data. Typically, all memory cells in a particular memory device have the same type, but this is not required.

[0064] An SLC can include two states, P0 and P1. P0 can represent the erase state, and P1 can represent the programmable state. Since an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to the set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can represent the erase state, and P1 through P3 can represent the programmable state. Since an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to the set encoding method. A TLC can include eight states, P0 through P7. Among these states, P0 can represent the erase state, and P1 through P7 can represent the programmable state. Since a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to the set encoding method. A QLC can include sixteen states, P0 through P15. Among these states, P0 can represent the erase state, and P1 through P15 can represent the programmable state. Since a QLC can be set to one of sixteen different states, each QLC can be programmed or store four bits according to the set encoding method.

[0065] Return to reference Figure 2 and Figure 3 The memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, such as... Figure 3As shown. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided at the bit line when the word line is asserted. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0066] Figure 5A This is a diagram illustrating an example of encoding a multilayer cell (MLC) according to an embodiment of the present invention.

[0067] Reference Figure 5A The MLC can be programmed using a setting type of encoding. The MLC can have four programming states, including an erase state E (or PV0) and first programming states PV1 through third programming states PV3. Eraser state E (or PV0) can correspond to "11". First programming state PV1 can correspond to "10". Second programming state PV2 can correspond to "00". Third programming state PV3 can correspond to "01".

[0068] In MLC, such as Figure 5B As shown, there are two types of pages: LSB pages and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For MSB pages, the single threshold is VT1. VT1 distinguishes between the first programming state PV1 and the second programming state PV2. For LSB pages, the two thresholds are threshold VT0 and threshold VT2. VT0 distinguishes between the erase state E and the first programming state PV1. VT2 distinguishes between the second programming state PV2 and the third programming state PV3.

[0069] Figure 6A This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC) according to an embodiment of the present invention.

[0070] Reference Figure 6ATLCs can be programmed using Gray code. A TLC can have eight programming states, including an erase state E (or PV0) and first programming states PV1 through seventh programming states PV7. Eraser state E (or PV0) can correspond to "111". First programming state PV1 can correspond to "011". Second programming state PV2 can correspond to "001". Third programming state PV3 can correspond to "000". Fourth programming state PV4 can correspond to "010". Fifth programming state PV5 can correspond to "110". Sixth programming state PV6 can correspond to "100". Seventh programming state PV7 can correspond to "101".

[0071] In TLC, such as Figure 6B As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds include threshold VT0, which distinguishes between erase state E and first programming state PV1, and threshold VT4, which distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between first programming state PV1 and second programming state PV2. VT3 distinguishes between third programming state PV3 and fourth programming state PV4. VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds include VT2 and VT6. VT2 distinguishes between second programming state PV2 and third programming state PV3. VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0072] Figure 7 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0073] Reference Figure 7 The memory system may include a controller 100 and a memory device 200. The memory device 200 may include a NAND flash memory device having memory cells such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). In various embodiments, the memory device 200 may include a NAND flash memory device having QLC memory cells (i.e., QLC).

[0074] The controller 100 can receive commands from the host and provide the received commands to the memory device 200. For example, the controller 100 receives a write command and corresponding write data, and controls the memory device 200 to perform a programming operation on the write data. As another example, the controller 100 receives a read command and controls the memory device 200 to perform a read operation on the data corresponding to the read command. The controller 100 then transmits the read data corresponding to the read command to the host.

[0075] The controller 100 may include an encoder 700A and a decoder 700B. During programming operations, the encoder 700A can perform encoding operations on the written data based on a set encoding scheme. During reading operations, the decoder 700B can perform decoding operations on the read data based on a set decoding scheme corresponding to the encoding scheme. The following will refer to... Figures 8 to 13 Describe the decoding scheme. Although not in Figure 7 As shown, however, the controller 100 and memory device 200 may include, for example... Figure 2 The various other components shown and execution Figure 1 and Figure 2 The operation described herein. In an embodiment, encoder 700A and decoder 700B can be configured to... Figure 2 The controller 100 shown is implemented using the ECC component 130. Other suitable arrangements may also be used, as described below. Typically, the encoder 700A and decoder 700B can be implemented by hardware, software, firmware, or any suitable combination thereof.

[0076] One implementation of the controller may include two decoders with different precision (or power) in a system-on-a-chip (SoC). Figure 8In the example shown, the decoding device 800 may have a hierarchical decoding architecture, comprising a first decoder 810 with a first precision and a second decoder 820 with a second precision greater than the first precision. As an example and not in any limitation, the first decoder 810 may be a bit-flip (BF) decoder, and the second decoder 820 may be a minimum-sum (MS) decoder. The BF decoder 810 has a smaller gate count (i.e., a smaller area), consumes less power, but has weaker error correction capability (i.e., lower precision). Compared to the BF decoder 810, the MS decoder 820 has a higher gate count, consumes more power, and can correct more errors (i.e., higher precision). Once the BF decoder 810 fails to correct a codeword, the codeword can be sent to the MS decoder 820 for a second decoding attempt. Most codewords can be decoded by the low-power BF decoder 810, while a minority of codewords (e.g., 1% to 5% of codewords) can be decoded by the high-power MS decoder 820. Therefore, this scheme improves energy consumption. However, since both decoders need to be implemented in the SoC, the gate count and peak power can be high despite low power consumption. In particular, in mobile applications, the error correction code (ECC) decoder engine can account for more than 60% of the SoC gate count, while mobile applications typically require a low gate count to keep costs down.

[0077] Therefore, embodiments of the present invention provide an architecture for a decoding device comprising two different decoders and a method for operating these two decoders to address gate counting and peak power issues in the decoding device while maintaining low power consumption. The embodiments can be applied to, for example... Figure 8 The illustrated decoding device 800 includes two decoders 810 and 820 with different decoding accuracies and powers. In one embodiment, the first decoder 810 and the second decoder 820 may be a bit-flip (BF) decoder and a minimum-sum (MS) decoder, respectively. In another embodiment, the first decoder 810 and the second decoder 820 may be a low-precision MS decoder and a high-precision MS decoder, respectively. In yet another embodiment, the first decoder 810 and the second decoder encoder 820 may be an MS decoder and a Bahl, Cocke, Jelinek, and Raviv (BCJR) decoder, respectively. Although embodiments can be implemented in various ways as described above, for example... Figure 8 The decoding apparatus 800, which includes a BF decoder 810 and an MS decoder 820, is illustrated in the description of an embodiment. This embodiment allows for the optimization of gate count, peak power, and energy consumption within the decoding apparatus.

[0078] It has been observed that for most failures from the BF decoder 810, the remaining errors are tightly interconnected. The BF decoder 810 is insufficient to correct such errors because it does not generate and propagate reliability information between variable nodes (VNs) and check nodes (CNs) in the bipartite graph (e.g., a Tanner graph) of the underlying error-correcting code (e.g., a low-density parity-check (LDPC) code). Furthermore, it has been observed that once reliability information is generated and propagated along the edges between variable nodes and check nodes in a specific subgraph of the bipartite graph (caused by small neighborhoods of typically few remaining errors), the remaining errors can be recovered. This observation implies that a comprehensive MS decoder that generates and propagates soft information along the entire graph is unnecessary. Therefore, embodiments provide a decoding system that includes a locally enhanced decoder (hereinafter referred to as a mini-MS decoder, as indicated by 830) for decoding very small subgraphs that are highly likely to include some remaining errors, while keeping the rest of the graph decoded by the BF decoder 810.

[0079] Figure 9 This is a flowchart illustrating a method 900 for operating a decoding device according to an embodiment of the present invention. In the embodiment, the decoding device may be a decoding device 800 that includes a BF decoder 810 and a mini MS decoder 830 instead of a full MS decoder 820, such as... Figure 8 As shown.

[0080] Reference Figure 9 Method 900 may include operations 910 to 960 and may be performed by Figure 7 The controller 100 controls the data. The controller 100 can read data (or codewords) from the memory device 200 and control the BF decoder 810 to decode the data (910). The BF decoder 810 can perform BF decoding on the data using a parity matrix of an error correction code (e.g., a low-density parity-check (LDPC) code).

[0081] Controller 100 can determine whether a specific condition is met. In some embodiments, the specific condition may include a stuck BF decoder 810 (930). That is, when the BF decoder 810 is stuck and making no progress, the mini-MS decoder 830 may be kicked in. This condition can be identified by checking the checksum along successive decoding iterations of the BF decoder 810. When the checksum result is below a specific threshold for a large number of iterations of BF decoding (i.e., when the checksum result is less than a set threshold), controller 100 may kick in the mini-MS decoder 830. Alternatively, controller 100 may kick in the mini-MS decoder 830 when any oscillation of the BF decoder 810 is detected. This oscillation detection scheme is described in U.S. Patent Application Serial No. 17 / 124,203, entitled "Oscillation Detection and Mitigation in Bit-Flipping Decoders," which is incorporated herein by reference in its entirety.

[0082] When a specific condition (930, Yes) is met, controller 100 can perform subgraph extraction and initialization (940) for mini-MS decoder 830. Controller 100 can extract one or more subgraphs from the entire bipartite graph of the parity check matrix. The bipartite graph can be defined by multiple variable nodes and multiple parity nodes. Each subgraph can be determined based on unsatisfied parity nodes and neighboring nodes selected from multiple neighboring nodes of satisfied parity nodes. In some embodiments, the selected neighboring nodes can have a set distance from the unsatisfied parity nodes (e.g., distance 1 or distance 2). The identification and extraction of subgraphs are described in detail below.

[0083] The mini MS decoder 830 can be initialized using the channel input value or the bit value at the end of the BF decoder 810, or a combination of both.

[0084] After performing subgraph extraction and initialization, controller 100 can control mini MS decoder 830 to decode the data using a submatrix of the parity check matrix corresponding to the extracted subgraph.

[0085] In some cases, the subgraph does not contain all errors. This means that the global checksum and / or cyclic redundancy check (CRC) are not satisfied. In this case, after decoding by the mini-MS decoder 830, the BF decoder 810 can continue decoding by obtaining a hard decision (HD) value from the mini-MS decoder 830. In some embodiments, the HD value is obtained by performing hard decision decoding on the output of the mini-MS decoder 830. The HD value includes binary values ​​0 and 1. Iteration between the BF decoder 810 and the mini-MS decoder 830 can continue until the set maximum number of iterations (920) is reached. At the end of each BF decoding iteration, the BF decoder 810 can test whether all syndromes (e.g., LDPC syndrome and CRC syndrome) are zero. When it is determined that the test passed, the BF decoder 810 can terminate by declaring success. When it is determined that the maximum number of iterations (920, yes) has been reached, the BF decoder 810 can terminate by declaring decoding failure (960).

[0086] As described above, the controller 100 can perform subgraph identification and extraction. In some embodiments, the subgraph operated by the mini MS decoder 830 can be defined by some of the imposed subgraphs among unsatisfied checks (check nodes) and satisfied distance-1 and distance-2 neighbor nodes. The distance-1 neighbor nodes of a check node can be variable nodes connected to that check node. The distance-2 neighbor nodes of check node C can be variable nodes of the same check node connected to the distance-1 neighbor nodes of check node C.

[0087] In the error base region, it has been observed that some error modes occur more frequently compared to most error modes. These modes and their variations are determined based on the error modes of the BF decoder 810. For example, when the parity check matrix might have... Figure 10 As shown in the different degree distributions, it has been studied and observed that specific structures (error patterns) can be extracted from the parity check matrix. Figure 10 In the diagram, the x-axis represents variable nodes, and the y-axis represents the verification equation. Two subgraph extraction algorithms (schemes) are described in detail below. The Mini MS Decoder 830 can focus on smaller graphs where most errors occur. This improves decoding performance when most errors appear in the subgraph and the Mini MS Decoder 830 can decode the error patterns. When the BF Decoder 810 is applied, the remaining errors can be corrected.

[0088] Figure 11 This is a flowchart illustrating the subgraph extraction and use of a decoding apparatus 800 including a BF decoder 810 and a mini MS decoder 830 according to an embodiment of the present invention.

[0089] Reference Figure 11 Two subgraph extraction schemes, Scheme A and Scheme B, can be controlled by controller 100 and used in the mini-MS decoder 830. As an example and not a limitation, for the subgraph extraction scheme, consider variable nodes with two distinct degrees, namely degree a (degree-a) and degree b (degree-b). The degree-a variable node can be a variable node connected to "a" check nodes. Similarly, the degree-b variable node can be a variable node connected to "b" check nodes. Here, a and b can be integers. In some embodiments, for irregular LDPC codes with more than two specific degrees, controller 100 can classify multiple degrees into the degree-a category, classify the remaining degrees into the degree-b category, and apply the subgraph extraction algorithm. Controller 100 can target variable nodes with two distinct degrees (i.e., degree-a and degree-b) in the errors, where these variable nodes are at most distance-2 apart.

[0090] For each subgraph extraction scheme, the input may include a parity check matrix and unsatisfied checks, and the output may include variable nodes in the subgraph and a submatrix of the parity check matrix corresponding to the subgraph.

[0091] The mini MS decoder 830 can receive the output according to the selected subgraph extraction scheme and perform MS decoding using the received output. The BF decoder 810 can receive the decoding output of the subgraph variable nodes decoded by the mini MS decoder 830 and the status information of the remaining variable nodes, and perform BF decoding using the received decoding output and status information.

[0092] Figure 12 This is a flowchart illustrating a subgraph extraction scheme (Scheme A) 1200 according to a first embodiment of the present invention.

[0093] exist Figure 12 In this subgraph extraction scheme 1200, the input may include a parity check matrix, a decoded coset, and a parity check equation. In its simplest form, the coset may include all vectors with the same parity check. The output of the subgraph extraction scheme 1200 may include the variables in the subgraph and the corresponding submatrices.

[0094] In the example shown, the subgraph extraction scheme 1200 may include operations 1210 to 1230 for each of the unsatisfied check equations (nodes) based on the decoding result of the BF decoder 810.

[0095] In operation 1210, controller 100 may increase the distance-1 weight of each variable node connected to the unsatisfied check equation (node).

[0096] In operation 1220, controller 100 can find the degree-a variable nodes connected to the verification equation and add them to the search list. Further, controller 100 can find other equations that include the degree-a variables in the search list and are satisfied. Additionally, controller 100 can find the degree-b variable nodes connected to these satisfied equations and increase their distance-2 weights by a set value (e.g., 1).

[0097] In operation 1230, controller 100 can extract a subgraph with degree-a variable nodes in the search list and degree-b variable nodes with a distance-2 weight greater than 1.

[0098] It has been observed that when the subgraph extraction scheme 1200 is applied, 80% of the error patterns are successfully decoded using a mini-MS decoder 83 followed by a BF decoder 810. The subgraph extraction scheme 1200 can be generalized to different degree distributions and different distances from unsatisfied check equations.

[0099] Figure 13 This is a flowchart illustrating a subgraph extraction scheme (Scheme B) 1300 according to a second embodiment of the present invention.

[0100] exist Figure 13 In this context, the input to subgraph extraction scheme 1300 may include a parity check matrix and unsatisfied checks. The output of subgraph extraction scheme 1300 may include variables in the subgraph, decoded cosets, and check equations.

[0101] In the example shown, the subgraph extraction scheme 1300 may include operations 1310 to 1340 for each of the unsatisfied check equations (nodes) based on the decoding result of the BF decoder 810.

[0102] In operation 1310, controller 100 may increase the distance-1 weight of each variable node connected to the unsatisfied check equation.

[0103] In operation 1320, controller 100 can find the degree-a variable nodes connected to the verification equation and add them to the first search list. Further, controller 100 can find other equations that include the degree-a variables in the first search list and are satisfied. Additionally, controller 100 can find the degree-b variable nodes connected to these satisfied equations and increase their distance-2 weights by a set value (e.g., 1).

[0104] In operation 1330, controller 100 can find the degree-b variable connected to the check equation and add it to the second search list.

[0105] In operation 1340, controller 100 may extract a subgraph having degree-a variable nodes in a first search list and degree-b variables with a distance-2 weight greater than 1. Further, controller 100 may add degree-b variable nodes that appear in a second search list and have a distance-2 weight of at least 1.

[0106] It has been observed that when the subgraph extraction scheme 1300 is applied, 96.6% of the error patterns are successfully decoded using a mini MS decoder 830 followed by a BF decoder 810. The subgraph extraction scheme 1300 can be generalized to different degree distributions and different distances from unsatisfied check equations.

[0107] As described above, the embodiments provide a scheme to replace the higher-precision decoder among two decoders in a decoding device with an enhanced decoder that operates on subgraphs within the entire bipartite graph. Therefore, the embodiments can reduce the gate count and peak power in the decoding device while maintaining low power consumption.

[0108] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are exemplary and not restrictive. The invention is intended to cover all modifications and substitutions falling within the scope of the claims. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A memory system, comprising: A memory device for storing data encoded using error correction codes; as well as The controller includes a first decoder having a first precision and a second decoder having a second precision greater than the first precision. The controller mentioned above: The first decoder is controlled to decode data read from the memory device by using the parity check matrix of the error correction code; When certain conditions are met, one or more subgraphs are extracted from the entire bipartite graph of the parity check matrix, which is defined by multiple variable nodes and multiple check nodes. The one or more subgraphs are determined based on unsatisfied check nodes and neighboring nodes selected from multiple neighboring nodes that satisfy the check nodes. as well as The second decoder is controlled to use the submatrix of the parity check matrix corresponding to the extracted subgraph to decode the decoding result of the first decoder.

2. The memory system according to claim 1, wherein the first decoder includes a bit-flip decoder, i.e., a BF decoder, and the second decoder includes a minimum sum decoder, i.e., an MS decoder.

3. The memory system of claim 1, wherein the specific condition includes when the checksum along a successive decoding iteration using the first decoder is less than a threshold.

4. The memory system of claim 1, wherein the specific condition includes when oscillation of the first decoder is detected.

5. The memory system of claim 1, wherein the selected adjacent node has a predetermined distance from the node whose check is not satisfied.

6. The memory system of claim 1, wherein each of the subgraphs includes a first set of variable nodes connected to the unsatisfied check node, and a second set of variable nodes connected to the satisfied check node as adjacent nodes at a distance-1 or distance-2 from the first set of variable nodes.

7. The memory system of claim 6, wherein the first group of variable nodes includes variable nodes with a degree-a distribution to the unsatisfied check nodes, and the second group of variable nodes includes variable nodes with a degree-b distribution to the unsatisfied check nodes and a distance-2 weight to the first group of variable nodes.

8. The memory system of claim 1, wherein the controller terminates the decoding operation when the maximum number of iterations of the first decoder is reached.

9. A method of operating a memory system, the memory system comprising a memory device storing data encoded using error correction codes and a controller, the method comprising: The first decoder, which has a first precision, is controlled to decode data read from the memory device by using a parity check matrix of the error correction code; When certain conditions are met, one or more subgraphs are extracted from the entire bipartite graph of the parity check matrix, which is defined by multiple variable nodes and multiple check nodes. The one or more subgraphs are determined based on unsatisfied check nodes and neighboring nodes selected from multiple neighboring nodes that satisfy the check nodes. as well as The second decoder, which has a second precision greater than the first precision, uses a submatrix of the parity check matrix corresponding to the extracted subgraph to decode the decoding result of the first decoder.

10. The method of claim 9, wherein the first decoder includes a bit-flipping decoder, i.e., a BF decoder, and the second decoder includes a minimum sum decoder, i.e., an MS decoder.

11. The method of claim 9, wherein the specific condition includes when the checksum along a successive decoding iteration using the first decoder is less than a threshold.

12. The method of claim 9, wherein the specific condition includes detecting an oscillation of the first decoder.

13. The method of claim 9, wherein the selected adjacent node has a set distance from the node that did not meet the verification requirement.

14. The method of claim 9, wherein each of the subgraphs includes a first set of variable nodes connected to the unsatisfied check node, and a second set of variable nodes connected to the satisfied check node as adjacent nodes at a distance-1 or distance-2 from the first set of variable nodes.

15. The method of claim 14, wherein the first group of variable nodes includes variable nodes with a degree-a distribution to the unsatisfied check nodes, and the second group of variable nodes includes variable nodes with a degree-b distribution to the unsatisfied check nodes and a distance-2 weight to the first group of variable nodes.

16. The method of claim 9, further comprising: When the maximum number of iterations of the first decoder is reached, the controller terminates the decoding operation.

Images