System and method for detecting erratic programming in a memory system

Abstract

A storage device includes a non-volatile memory having a control circuit communicatively coupled to an array of memory cells arranged in a plurality of word lines. The control circuit is configured to program the memory cells in a plurality of programming cycles. A programming cycle includes applying a program pulse to a selected word line of the plurality of word lines. The programming cycle also includes applying a verify pulse V N to the selected word line to simultaneously verify a lower tail of memory cells being programmed to a data state N and an upper tail of memory cells already programmed to a data state N-1. The data state N-1 has a lower voltage threshold than the data state N. A method of programming a non-volatile memory device and an apparatus are also disclosed.

Description

Technical Field

[0001] This technology relates to the operation of memory devices, and more particularly to the detection of unstable programming. Background Technology

[0002] Many memory devices are provided as internal components, semiconductors, or integrated circuits in computers or other electronic devices. There are many different types of memory, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, etc. In EEPROM or Flash NAND array architectures, memory cells can be arranged in a matrix of rows and columns, such that the gate of each memory cell is coupled to a word line via a row. Memory cells can also be arranged in strings, such that the memory cells in a given string are connected in series from source to drain between a common source line and a common bit line. Summary of the Invention

[0003] The programming techniques disclosed herein are provided to detect unstable programming during programming operations with minimal additional programming time.

[0004] One aspect of this disclosure relates to a storage device including a non-volatile memory with control circuitry communicatively coupled to an array of memory cells arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming cycles. Each programming cycle includes applying a programming pulse to a selected word line among the plurality of word lines. The programming cycle also includes applying a verification pulse V to the selected word line. N This is to simultaneously verify the lower tail of a memory cell being programmed as data state N and the upper tail of a memory cell being programmed as data state N-1. Data state N-1 has a lower voltage threshold than data state N.

[0005] According to another aspect of this disclosure, the control circuit is configured to stop programming the memory cell of the selected word line in response to a failure to verify the upper tail of the data state N-1.

[0006] According to another aspect of this disclosure, the control circuit is configured to incrementally increase the voltage of the programming pulse between programming cycles.

[0007] According to another aspect of this disclosure, the control circuit is configured to prohibit further programming of the memory cell being programmed as data state N in response to the successful verification of the lower tail of data state N, and to incrementally advance the verified data state (N = N + 1).

[0008] According to another aspect of this disclosure, the verification pulse is a low verification voltage V.NL Furthermore, in subsequent programming cycles, in response to the lower tail verification passing in data state N, during the application of the programming pulse, the programming of the memory cell to data state N is slowed down by applying a bias voltage to at least one bit line coupled to at least one memory cell in the selected word line, and the verification pulse is adjusted to a high verification voltage V. NH .

[0009] According to another aspect of this disclosure, a low verification voltage V is used. NL To verify the upper tail of the memory cell programmed as data state N-1.

[0010] According to another aspect of this disclosure, a high verification voltage V is used. NH To verify the upper tail of the memory cell programmed as data state N-1.

[0011] Another aspect of this disclosure relates to a method for programming a non-volatile memory device. The method includes the steps of: providing a memory device comprising an array of memory cells arranged in a plurality of word lines. The method further includes the steps of: performing a plurality of programming cycles to program the memory cells to at least one programmed data state. The programming cycle includes applying a programming pulse to a selected word line among the plurality of word lines, and applying a verification pulse V to the selected word line. N This is to simultaneously verify the lower tail of a memory cell being programmed as data state N and the upper tail of a memory cell being programmed as data state N-1. Data state N-1 has a lower voltage threshold than data state N.

[0012] According to another aspect of this disclosure, the method further includes the step of: stopping the programming of the memory cell of the selected word line in response to the verification failure at the upper tail of the data state N-1.

[0013] According to another aspect of this disclosure, the method further includes the step of incrementally increasing the voltage of the programming pulse between programming cycles.

[0014] According to another aspect of this disclosure, the method further includes the step of: in response to the verification of the lower tail of data state N and prohibiting further programming of the memory cell being programmed as data state N, incrementally increasing the verified data state (N = N + 1).

[0015] According to another aspect of this disclosure, the verification pulse is a low verification voltage V. NL Furthermore, in subsequent programming cycles, in response to the lower tail verification of data state N passing, during the application of the programming pulse, the programming of the memory cell to data state N is slowed down by applying a bias voltage to at least one bit line coupled to the memory cell being programmed to data state N, and the verification pulse is adjusted to a high verification voltage V.NH .

[0016] According to another aspect of this disclosure, a low verification voltage V is used. NL To verify the upper tail of the memory cell programmed as data state N-1.

[0017] According to another aspect of this disclosure, a high verification voltage V is used. NH To verify the upper tail of the memory cell programmed as data state N-1.

[0018] Another aspect of this disclosure relates to an apparatus including a non-volatile memory comprising an array of memory cells arranged in a plurality of word lines. The non-volatile memory also includes control circuitry electrically communicating with the memory cells, the control circuitry being configured to program the memory cells in a plurality of programming cycles. The programming cycle includes applying a programming pulse to a selected word line among the plurality of word lines to program a non-inhibited memory cell of the selected word line, and applying a verification pulse V to the selected word line. N The system simultaneously verifies the lower tail of a memory cell being programmed into data state N and the upper tail of a memory cell that is disabled and in data state N-1. In response to successful verification of the lower tail of the memory cell programmed into data state N, further programming of the memory cell being programmed into data state N is disabled, and data state N (N = N+1) is advanced. In response to failure of the upper tail of the memory cell in data state N-1, the control circuit stops programming the selected word line.

[0019] According to another aspect of the invention, the control circuit is configured to incrementally increase the voltage of the programming pulse between programming cycles.

[0020] According to another aspect of this disclosure, the memory cells are configured to be programmed to have at least two bits per memory cell.

[0021] According to another aspect of this disclosure, the pulse V is verified. N It is a low verification voltage V NL Furthermore, in subsequent programming cycles, in response to the lower tail verification passing of data state N, during the application of the programming pulse, the programming of the memory cell to data state N is slowed down by applying a bias voltage to at least one bit line of at least one memory cell coupled to at least one of the selected word lines being programmed to data state N, and the verification pulse is adjusted to a high verification voltage V. NH .

[0022] According to another aspect of this disclosure, a low verification voltage V is used. NL To verify the upper tail of the memory cell programmed as data state N-1.

[0023] According to another aspect of this disclosure, a high verification voltage V is used. NH To verify the upper tail of the memory cell programmed as data state N-1. Attached Figure Description

[0024] The following description, with reference to the exemplary embodiments depicted in the accompanying drawings, will be presented in more detail. It should be understood that these drawings merely depict exemplary embodiments of the present disclosure and should therefore not be considered as limiting its scope. The present disclosure is described and explained with additional features and details using the accompanying drawings, wherein:

[0025] Figure 1A This is a block diagram of an example memory device;

[0026] Figure 1B This is a block diagram of an example control circuit;

[0027] Figure 2 Depicting Figure 1A A block of memory cells in an example two-dimensional configuration of a memory array;

[0028] Figure 3A and Figure 3B A cross-sectional view of an example floating-gate memory cell in a NAND string is depicted;

[0029] Figure 4A and Figure 4B A cross-sectional view of an example charge-trapping memory cell in a NAND string is depicted;

[0030] Figure 5 An example block diagram of the sensing block SB1 in Figure 1 is depicted;

[0031] Figure 6A This is a perspective view of the set of blocks in an example three-dimensional configuration of the memory array in Figure 1;

[0032] Figure 6B Depicting Figure 6A Example cross-sectional view of one of the blocks;

[0033] Figure 6C Depicting Figure 6B A graph showing the diameter of memory holes in a stack;

[0034] Figure 6D Depicting Figure 6B A close-up view of region 722 of the stacked body;

[0035] Figure 7A Depicting Figure 6B A top view of an example wordline layer WLL0 of a stacked body;

[0036] Figure 7B Depicting Figure 6BA top view of the top dielectric layer DL19 of an example stack;

[0037] Figure 8A Depicting Figure 7A Example NAND string in sub-block SBa-SBd;

[0038] Figure 8B Another example diagram depicting the NAND string in the sub-block;

[0039] Figure 9 The diagram illustrates the Vth distribution of data states in a TLC memory system;

[0040] Figure 10 The diagram illustrates the Vth distribution of the data state of a memory cell that has undergone unstable programming.

[0041] Figure 11 The waveforms of the example memory cell programming operation are depicted;

[0042] Figure 12A The diagram illustrates the Vth distribution for the two data states and the verification voltage applied during the two-phase programming operation.

[0043] Figure 12B The diagram illustrates the distribution of Vth for two data states and its relationship with... Figure 12A The verification voltage applied during different two-phase programming operations; and

[0044] Figure 13 This is a flowchart illustrating an example method for programming multiple memory cells in a memory device. Detailed Implementation

[0045] Techniques for programming memory devices are provided to protect memory cells from overprogramming, which results in a poor upper threshold voltage Vt tail in the distribution of certain programmed data states in multi-bit memory cells per cell, while minimizing additional programming time and reducing programming failures.

[0046] The following discussion pertains to various embodiments of this disclosure. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as limiting or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0047] Programming a set of memory cells typically involves applying a series of programming voltages to the memory cells after they have been provided in an erased data state. Each programming voltage is applied during a programming cycle, also known as a programming verification iteration. For example, the programming voltage can be applied to a selected word line connected to the control gate of the memory cell. In one approach, incremental step-pulse programming is performed, where the programming voltage is increased by one step in each successive programming cycle. Within each programming cycle, a verification operation is performed after the programming voltage to determine whether the memory cell has been successfully programmed. When programming of a memory cell is complete, it may be locked (disabled) from further programming, while programming of other memory cells continues in subsequent programming cycles.

[0048] Each memory cell can be associated with a data state based on the data written in the programming command. A memory cell can be in an erased data state, or it can be programmed to a programmed data state different from the erased data state. (See reference) Figure 9 In an example three-bit-per-cell (TLC) memory device, there are eight total data states, including an erased data state (ER) and seven programmed data states, referred to as S1, S2, S3, S4, S5, S6, and S7 (contemplate other naming conventions), which have increasing threshold voltages. In other embodiments, the memory device may be one-bit, two-bit, four-bit, or five-bit per cell. In a one-bit-per-cell (SLC) memory device, there are two data states, including an erased data state and one programmed data state. In a two-bit-per-cell (MLC) memory device, there are four data states, including an erased data state and three programmed data states. In a four-bit-per-cell (QLC) memory device, there are 16 data states, including an erased data state and 15 programmed data states. In a five-bit-per-cell (PLC) memory device, there are 32 data states, including an erased data state and 31 programmed data states.

[0049] When a programming command is issued, the written data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the memory cell is to be programmed. Each programmed data state is associated with a predetermined verification voltage, such that the memory cell is considered programmed when a read (sensing) operation determines that its threshold voltage (Vth) is higher than the associated verification voltage. Figure 9In the code, the verification voltages are labeled Vv1-Vv7 for data states S1-S7 respectively. The read (sensing) operation determines whether the Vth of the memory cell is above the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, it indicates that the memory cell is in a conducting state, such that Vth is less than the control gate voltage. If the current is relatively low, it indicates that the memory cell is in a non-conducting state, such that Vth is higher than the control gate voltage.

[0050] In some cases, unstable behavior (such as a sudden increase in tunneling efficiency, anomalous programming control verification, or anomalous verification sensing) can lead to overprogramming of memory cells, resulting in an anomalous upper tail shape in the Vt distribution of certain memory cells, such as... Figure 10 As shown. Some programming methods fail to detect these unstable cells during programming, but they will cause failures during subsequent read operations. One method to detect such unstablely programmed memory cells is to perform Unstable Programming Detection (EPD) after the programming operation has been completed. However, EPD increases programming time (Tpgm) and correspondingly reduces performance. Furthermore, when EPD detects programming failures due to unstable overprogrammed memory cells, data recovery may be difficult or impossible.

[0051] As discussed in further detail below, this paper teaches programming techniques to detect such unstable memory cells during programming operations with zero or minimal increments on Tpgm.

[0052] Figure 1A This is a block diagram of an example memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 can be addressed by word lines via row decoder 124 and by bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks SB1, SB2, ..., SBp (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0053] Memory structure 126 can be two-dimensional or three-dimensional. Memory structure 126 can include an array of one or more memory cells comprising a three-dimensional array. Memory structure 126 can include a monolithic three-dimensional memory structure in which multiple memory levels are formed on (but not therein) a single substrate (such as a wafer), without any intermediate substrate. Memory structure 126 can include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed on a silicon substrate. Memory structure 126 can be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0054] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0055] For example, a storage area 113 can be provided for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, verification voltage, etc. Location parameters may indicate the location of memory cells within the entire NAND string array, the location of memory cells within a specific NAND string group, the location of memory cells on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector, the substrate or material constituting the contact connector, etc.

[0056] The on-chip address decoder 114 provides an address interface between addresses used by the host or memory controller and hardware addresses used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. It may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, the sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0057] In some embodiments, some components may be combined. In various designs, one or more components (individually or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of the following: control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0058] The control circuitry may include programming circuitry configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells allocated to represent one of a plurality of data states and memory cells allocated to represent another of the plurality of data states; the programming and verification operations include a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuitry programs a word line and then applies a verification signal to the word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that have passed a verification test for one data state. The control circuitry may further include a determining circuit configured to determine a specific programming and verification iteration among the plurality of programming and verification iterations based on an amount by which the count exceeds a threshold, in which a verification test is performed on another data state of the memory cells allocated to represent another data state.

[0059] For example, Figure 1B This is a block diagram of an example control circuit 150, which includes a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0060] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. This ECC engine can correct several read errors that occur when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0061] Multiple storage devices 122a, 122b include code such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access the code from storage device 126a of memory structure 126 (such as a reserved area of ​​memory cells in one or more word lines). For example, the code may be used by controller 122 to access memory structure 126 for operations such as programming, reading, and erasing. The code may contain boot code and control code (e.g., an instruction set). The boot code is software that initializes controller 122 during a boot or startup process and enables controller 122 to access memory structure 126. The code may be used by controller 122 to control one or more memory structures 126. Upon startup, processor 122c retrieves the boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor 122c. This control code contains drivers for performing basic tasks such as controlling and allocating memory, specifying the priority of instruction processing, and controlling input and output ports.

[0062] Typically, control code may contain instructions to perform the functions described herein (including the steps in the flowcharts discussed further below) and provide voltage waveforms (including those discussed further below).

[0063] In one embodiment, the host is a computing device (e.g., a laptop, desktop computer, smartphone, tablet, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) to program the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0064] Other types of non-volatile memory besides NAND flash memory can also be used.

[0065] Semiconductor memory devices include volatile memory devices such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”), non-volatile memory devices such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured as NAND or NOR.

[0066] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-changing storage elements such as antifuse or phase-change materials, and optional switching elements such as diodes or transistors. As yet another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0067] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a NAND flash memory device (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a collection of transistors connected in series, including memory cells and SG transistors.

[0068] NAND memory arrays can be configured such that the array consists of multiple memory strings, where each string comprises multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible, for example, a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0069] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which the layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after their formation. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0070] Memory elements can be arranged in an ordered array (such as in multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0071] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the main surface of the substrate, and the x and y directions are substantially parallel to the main surface of the substrate) structure.

[0072] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., in the y-direction)), where each column has multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xy-plane), resulting in a three-dimensional arrangement of memory elements having multiple vertically stacked elements on a memory plane. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0073] As a non-limiting example, in a three-dimensional array of NAND strings, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed as a NOR configuration and a ReRAM configuration.

[0074] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Alternatively, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device level of the array is typically formed on a layer below the memory device level of the array. However, layers of adjacent memory device levels in a monolithic three-dimensional memory array may be shared between memory device levels or may have intermediate layers.

[0075] Again, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple layers of memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0076] Figure 2 The illustrations depict three types of memory architectures utilizing interleaved memory strings. For example, reference numeral 201 illustrates a first example memory architecture, reference numeral 203 illustrates a second example memory architecture, and reference numeral 205 illustrates a third example memory architecture. In some embodiments, as shown, the memory architecture may include an array of interleaved NAND strings.

[0077] Figure 2 The illustration shows blocks 200 and 210 of memory cells in an example two-dimensional configuration of the memory array 126 of Figure 1. The memory array 126 may include a plurality of such blocks 200 and 210. Each example block 200, 210 includes several NAND strings and corresponding bit lines (e.g., BL0, BL1, ...) shared between blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The NAND strings are connected at their other ends to a source-side select gate (SGS), which is in turn connected to a common source line 220. Sixteen word lines (e.g., WL0-WL15) extend between the SGS and the SGD. In some cases, dummy word lines that do not contain user data may also be used in the memory array adjacent to the select gate transistor. Such dummy word lines can shield edge data word lines from certain edge effects.

[0078] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, such as... Figure 3A and 3B The type shown is correct. However, other types of non-volatile memory can also be used. These will be discussed in further detail below. Figure 4A and 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric, formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”), is sandwiched between the surface of a semiconductor substrate above the conductive control gate and the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a limited area. The stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form separate select transistors.

[0079] In another approach, NROM cells are used. As an example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across a channel between source and drain diffusion. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charge of the other data bits is located in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0080] Figure 3A Cross-sectional views of example floating-gate memory cells 300, 310, and 320 in a NAND string are illustrated. In this figure, bit lines or NAND string directions travel into the page, and word lines travel from left to right. As an example, word line 324 extends across the NAND string containing corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunneling oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunneling oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunneling oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is in a different corresponding NAND string. An interlayer polycrystalline dielectric (IPD) layer 328 is also illustrated. Control gates 302, 312, and 322 constitute the word line portion. Figure 3B A cross-sectional view along the contact line connector 329 is provided.

[0081] Control gates 302, 312, and 322 are wrapped around floating gates 304, 314, and 321, increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is almost no space for the IPD layer 328 between control gates 302, 312, and 322 and two adjacent floating gates 302, 312, and 322.

[0082] As an alternative, such as Figure 4A and Figure 4B As shown, planar or flat memory cells 400, 410, 420 have been developed, wherein the control gates 402, 412, 422 are planar or flat; that is, they are not wrapped around the floating gate, and their only contact with the charge storage layer 428 is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is fabricated to be much thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transfer, where electrons can travel through the floating gate after tunneling through the tunneling oxide during programming.

[0083] Figure 4A A cross-sectional view of example charge-trapping memory cells 400, 410, and 420 in a NAND string is depicted. This view shows the memory cells 400, 410, and 420 in the word line direction, including flat control gates and charge-trapping regions, as a two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126 of FIG. 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. Compared to floating-gate MOSFET technology, which uses conductors such as doped polysilicon to store electrons, this technology uses insulators such as SiN films to store electrons. As an example, word line 424 extends across a NAND string containing corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are IPD layer 428, charge trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer 404, 414, and 421 extends continuously within its corresponding NAND string. The flat configuration of the control gate can be manufactured thinner than a floating gate. Furthermore, memory cells can be placed more closely together.

[0084] Figure 4B The diagram shows Figure 4A The structure is shown in a cross-sectional view along the contact connector 429. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433, ... 435, and an SGD transistor 436. Passages in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. The control gate 402 and the floating gate layer can be polysilicon, and the tunneling oxide layer can be silicon oxide, as an example. The IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0085] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well 457. The channel voltage Vch can be directly applied to the channel region of the substrate.

[0086] Figure 5 An example block diagram of the sensing block SB1 of Figure 1 is illustrated. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with this set of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage is provided to each sensing circuit independently, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include the precharge circuit 561, a memory 562, and a processor 563. Memory 562 may store processor-executable code to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, and 553b associated with sensing circuits 550a, 551a, 552a, and 553a, setting bit values ​​in the latches, and providing voltages for setting pre-charge levels in the sensing nodes of sensing circuits 550a, 551a, 552a, and 553a. Further example details of the sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, and 553a are provided below.

[0087] In some embodiments, a memory cell may include a flag register comprising a set of latches storing flag bits. In some embodiments, the number of flag registers may correspond to the number of data states. In some embodiments, one or more flag registers may be used to control a type of verification technique used when verifying a memory cell. In some embodiments, the output of the flag bits may modify associated logic of the device, such as address decoding circuitry, to select a specified block of cells. Batch operations (e.g., erase operations, etc.) may be performed using flags set in the flag registers, or (as in implicit addressing) a combination of flag registers and address registers, or alternatively by direct addressing using address registers alone.

[0088] Figure 6A This is a perspective view of a set 600 of blocks in an example three-dimensional configuration of the memory array 126 in Figure 1. On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include a voltage driver 605, which may be connected to the control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are driven together. The substrate 601 may also carry circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, and one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned as conductive paths to carry signals from the circuitry. Each block BLK0, BLK1, BLK2, BLK3 comprises a stacked region of memory cells, where alternating layers of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides, from which vertical contacts extend upwards to an upper metal layer to form connections with conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks extending in the x and / or y directions can be used.

[0089] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path of the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path of the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0090] Figure 6B The diagram shows Figure 6A An example cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3 is shown. This block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0-WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0-DL19. Furthermore, a region of the stack 610 including NAND strings NS1 and NS2 is illustrated. Each NAND string includes memory holes 618 and 619 filled with material forming memory cells adjacent to the word lines. Region 622 of the stack 610 is... Figure 6D This is shown in more detail below and discussed in more detail below.

[0091] The stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of the source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as slots filled with metal) 617, 620 may be periodically provided across the stack 610 as interconnects extending through the stack 610, such as connecting source lines to specific contact lines above the stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently filled with metal. A portion of the bit line BL0 is also shown. A conductive via 621 connects the drain terminal 615 to BL0.

[0092] Figure 6C The diagram shows Figure 6B A graph showing the diameter of memory holes in a stack. The vertical axis is... Figure 6B The stack is aligned, and the width (wMH) is illustrated, for example, the diameter of memory holes 618 and 619. As an example, repeat... Figure 6A The word line layers WLL0-WLL10 are located at their respective heights z0-z10 within the stack. In such memory devices, the memory vias etched through the stack have a high aspect ratio. For example, a depth-to-diameter ratio of approximately 25-30 is common. The memory vias can have a circular cross-section. Due to the etching process, the width of the memory via can vary along its length. Typically, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the via near the select gate, causing the diameter to become slightly wider before gradually decreasing from the top to the bottom of the memory via.

[0093] Due to the non-uniformity in the width of memory vias, programming speeds, including the programming slope and erase speed of memory cells, can vary based on their location along the memory vias (e.g., based on their height in the stack). In the case of smaller diameter memory vias, the electric field across the tunneling oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define groups of adjacent word lines with diameters similar to (e.g., within a defined diameter range) of the memory vias and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0094] Figure 6D The diagram shows Figure 6B A close-up view of region 622 of the stack 610. Memory cells are formed at different levels of the stack, at the intersection of word line layers and memory vias. In this example, SGD transistors 680 and 681 are provided above dummy memory cells 682, 683 and data memory cells MC. Atomic layer deposition can be used, for example, to deposit several layers along the sidewalls (SW) of the memory via 630 and / or within each word line layer. For example, each column (e.g., a pillar formed by material within the memory via 630) may include a charge trapping layer or film 663 such as SiN or other nitrides, a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layers may include a barrier oxide / barrier high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in the memory via 630. In other methods, some of the layers can be in the control gate layer. Additional pillars are similarly formed in different memory vias. The pillars can form the pillared active regions (AA) of the NAND string.

[0095] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are introduced from the channel into the charge trapping layer and then pass through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During the erase operation, the electrons return to the channel.

[0096] Each of the memory vias 630 may be filled with a plurality of annular layers, including a barrier oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. The core region of each of the memory vias 630 is filled with a bulk material, and the plurality of annular layers are located between the core region and the word line in each of the memory vias 630.

[0097] NAND strings can be viewed as having floating body channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked vertically within a stack and separated from each other by dielectric layers.

[0098] Figure 7A The diagram shows... Figure 6B A top view of an example word line layer WLL0 of the stack 610. As mentioned, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. Thus, a vertical NAND string is formed. Source lines are connected to the NAND string below the stack, and bit lines are connected to the NAND string above the stack.

[0099] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each of which includes a group of NAND strings with a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layer within the block can be divided into regions. Each region extends within the corresponding sub-block and can extend between contact line connectors (e.g., slots) periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. This process may include replacing the sacrificial material of the word line layer with metal. Typically, the distance between the contact line connectors should be relatively small to account for limitations on the distance that the etchant can travel laterally to remove the sacrificial material, and limitations on the distance that the metal can travel to fill the voids created by removing the sacrificial material. For example, the distance between the contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of the memory vias and contact line connectors should also consider limitations on the number of bit lines that can extend across regions while each bit line connects to a different memory cell. After the word line layer is machined, the contact line connectors can optionally be filled with metal to provide interconnection through the stack.

[0100] In this example, four rows of memory holes exist between adjacent contact line connectors. Here, a row is a group of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. The word line layer or word line is divided into regions WLL10a, WLL10b, WLL10c, and WLL10d, each connected by contact line 713. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 713 is then connected to the voltage driver of the word line layer. Region WLL10a has example memory holes 710, 711 along contact line 712. Region WLL10b has example memory holes 714, 715. Region WLL10c has example memory holes 716, 717. Region WLL10d has example memory holes 718, 719. Memory holes are also... Figure 7B As shown in the diagram. Each memory hole can be a portion of the corresponding NAND string. For example, memory holes 710, 714, 716, and 718 can be portions of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0101] Each circle represents a cross-section of a memory aperture at the word line layer or SG layer. The example circles shown by dashed lines represent the material within the memory aperture and the memory cells provided by adjacent word line layers. For example, memory cells 820 and 821 are in WLL0a, memory cells 824 and 825 are in WLL0b, memory cells 826 and 827 are in WLL0c, and memory cells 828 and 829 are in WLL0d. These memory cells share a common height within the stack.

[0102] Contact line connectors (e.g., slots, such as slots filled with metal) 801, 802, 803, and 804 may be located between and near the edges of regions WLL10a-WLL10d. Contact line connectors 801, 802, 803, and 804 provide a conductive path from the bottom to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line connects to a voltage driver in a peripheral region of the memory device. Figure 7A Further details on the sub-block SBa-SBd can be found in [link to relevant documentation]. Figure 8A .

[0103] Figure 7B The diagram shows... Figure 6BThe image shows a top view of the top dielectric layer DL19 of an example stack. The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a corresponding voltage driver. This allows a collection of memory cells in one region of the word line layer to be programmed simultaneously, with each memory cell connected to the corresponding NAND string of the corresponding bit line. A voltage can be set on each bit line to enable or disable programming during each programming voltage.

[0104] Region DL19a has example memory holes 710, 711 along contact line 712, which coincides with bit line BL0. Several bit lines extend above and connect to the memory holes, as indicated by the "X" symbol. BL0 connects to a set of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 connects to a set of memory holes including memory holes 710, 714, 716, and 718. Also illustrated are... Figure 7A The contact wire connectors (e.g., slots, such as slots filled with metal) are 701, 702, 703, and 704, because they extend vertically through the stack. The bit lines can be numbered in the x-direction in the sequence BL0-BL23 across the DL19 layers.

[0105] Different sets of bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent row of cells adjacent to the first row at the left edge.

[0106] Figure 11 Waveform 1100 of an example memory cell programming operation is depicted, which can be used to detect unstable programming with little or no increase in Tpgm by simultaneously examining the upper tail of a memory cell with a programmed data state and the lower tail of the next successive data state memory cell. This programming operation can be a full-sequence programming operation or one or more passes in a multi-pass programming operation. The horizontal axis depicts time, and the vertical axis depicts the control gate or word line voltage applied to the selected word line.

[0107] As shown, the pulse chain comprises multiple programming loops or programming verification iterations. Each programming loop consists of a programming Vpgm pulse, followed by one or more verification pulses, depending on the data state being programmed in a particular programming loop. For simplicity, a square wave is depicted for each pulse; however, other shapes are possible, such as multi-level or ramp shapes. Furthermore, Incremental Step Pulse Programming (ISPP) is used in this example, where the Vpgm pulse amplitude steps by a fixed amount (e.g., dVpgm) in each successive programming loop. This example uses ISPP in a single programming pass to complete the programming. ISPP can also be used for any one or two programming passes in a multi-pass operation.

[0108] The pulse chain includes Vpgm pulses whose amplitude gradually increases with each programming cycle using a fixed step size (dVpgm). A new pulse chain begins at an initial Vpgm pulse level and ends at a final Vpgm pulse level not exceeding the maximum allowed level. Pulse chain 1100 includes a series of Vpgm pulses 1101-1115, which are applied to selected word lines comprising a set of non-volatile memory cells. One or more verification voltage pulses 1116-1129 are provided after each Vpgm pulse, as an example, based on the target data state being verified.

[0109] The magnitudes of verification pulses 1116-1129 correspond to both the upper tail of a programmed data state and the lower tail of the next successive data state. For lower tail verification, if the Vth of a memory cell is determined to be less than the verification voltage, the memory cell is considered to have failed verification. For upper tail verification, if the Vth of a memory cell is less than the verification voltage, the memory cell is considered to have passed verification, and if its Vth is greater than the verification voltage, it is considered to have failed verification. Conversely, for lower tail verification, if the Vth of a memory cell is greater than the verification voltage, the memory cell is considered to have passed verification, and if its Vth is less than the verification voltage, it is considered to have failed verification.

[0110] In each programming cycle, after the verification pulse or pulses 1116-1129 are completed, a bit scan operation is performed to count the number of memory cells that failed in the simultaneous verification. For each of the upper and lower tail verifications, if the number of memory cells that failed in the lower tail verification is less than the predetermined failure bit count (FBC), the verification operation is considered to have failed. As discussed in further detail below, if the lower tail verification passes, those memory cells are considered fully programmed and are prohibited from further programming, while programming of the remaining data states continues until programming of all data states is complete. If the lower tail verification fails, those memory cells are not prohibited and programming continues into the next programming cycle. If the upper tail verification passes, programming continues until programming of all remaining data states is complete, but if the upper tail verification fails, the entire programming operation is considered to have failed.

[0111] exist Figure 9 In this embodiment, the same single verification voltage is used to simultaneously verify the upper tail of a data state and the lower tail of the next successive data state. For example, verification voltage Vv1 can be used to verify the upper tail of the Er data state and the lower tail of the S1 data state. Similarly, Vv2 can be used to verify the upper tail of the S1 data state and the lower tail of the S2 data state. Continuing, Vv3 can be used to verify the upper tail of the S2 data state and the lower tail of the S3 data state. This pattern continues up to Vv7, which is used to verify the upper tail of the S6 data state and the lower tail of the S7 data state. In other words, in this example, a specific verification voltage can be selected to simultaneously verify the upper tail of the N-1 data state and the lower tail of the N data state. In some embodiments, verification of the upper tail of the last programmed data state (e.g., data state S7 in a TLC) can be skipped.

[0112] In some embodiments, the programming operation may include two verification phases at different voltages to verify the lower tail of the data state. For example, in one embodiment, during programming to data state N, once the low verification voltage V is completed... VNL The programming process begins with applying a Vpgm pulse to the word line to slow down the programming of one or more memory cells. During this process, a rapid write (QPW) bias voltage is then applied to the selected bit line coupled to the memory cell. Programming of those memory cells then continues until a high verification voltage Vpgm is applied. VNH Continue until verification is complete. For this operation, you can use V. VNL or V VNH To verify the upper tail of the memory cell that has been programmed to state N-1. For example, in Figure 12A In the middle, apply V V2L To verify the upper tail of data state S1, where the shaded area represents the memory cell where the upper tail verification failed, and... Figure 12B In the middle, apply V V2H To verify the upper tail of data state S1, the shaded area represents the memory cell where the upper tail verification failed.

[0113] Now for reference Figure 13 The diagram illustrates a flowchart of an example method for programming a memory cell. This method can be used to program any type of multi-bit-per-cell memory device, such as an MLC, TLC, QLC, or PLC. At step 1300, the data state N, indicating that the data is being programmed, is set to 1; Vpgm is set to a predetermined initial Vpgm; and the loop counter (Loop) is set to 1.

[0114] At step 1302, a Vpgm programming pulse is applied to the selected word line to program all undisabled memory cells. In some embodiments, undisabled memory cells are any memory cells programmed into an incomplete programming data state. Programming of disabled memory cells can be prevented by applying a disable voltage to the bit line associated with those memory cells.

[0115] At step 1304, one or more verification pulses are applied to the selected word line to simultaneously verify the lower tail of the memory cell being programmed as data state N and the upper tail of the memory cell being programmed as data state N-1. In some examples, where data state N is data state S1, then data state N-1 is Er data state, and where data state N is data state S2, then data state N-1 is data state S1. A bit scan operation can then be performed to count the number of memory cells that pass or fail for each of the upper tail verification and lower tail verification.

[0116] At step 1306, it is determined whether the memory cell programmed to data state N-1 has passed the upper tail verification, i.e., whether the FBC is below an acceptable threshold. If the answer at step 1306 is "no" (upper tail verification of data state N-1 has failed), then at step 1322, programming has failed. Advantageously, because programming failure is detected during the programming operation (as opposed to after programming has been completed), the programming operation can be retried on another memory block without losing any data. Furthermore, time can be saved by stopping the failed programming operation before completion.

[0117] At decision step 1308, it is determined whether the memory cell being programmed into data state N has passed the lower tail verification, i.e., whether the FBC is below an acceptable threshold.

[0118] If the answer at decision step 1308 is no (the lower tail validation of data state N fails), the method continues to decision step 1310.

[0119] At decision step 1310, it is determined whether the loop Loop is less than a predetermined maximum loop count (Loop_Max). If the answer at decision step 1310 is No (Loop=Loop_Max), the method proceeds to step 1322, and programming has failed.

[0120] If the answer at decision step 1310 is Yes (Loop<Loop_Max), then at step 1312, Vpgm is incrementally increased (Vpgm=Vpgm+dVpgm), and Loop is incrementally increased (Loop=Loop+1). The method then returns to step 1302.

[0121] If the answer at decision step 1308 is "Yes" (data state N passes lower tail verification), the method proceeds to decision step 1314. At decision step 1314, it is determined whether data state N is the final data state. For example, for an MLC memory device, data state S3 is the final data state; for a TLC memory device, data state S7 is the final data state; and for a QLC memory device, data state S15 is the final data state. If the answer at decision step 1314 is "Yes", the method proceeds to step 1316, and the programming operation is completed.

[0122] If the answer at decision step 1314 is "No", then at step 1318, further programming of the memory cells of data state N is inhibited. At step 1320, N is incrementally advanced (N=N+1), and the method proceeds to the aforementioned decision step 1310.

[0123] Programming continues until programming fails at step 1308 or is completed at step 1316.

[0124] In some embodiments, before inhibiting programming of the memory cells of data state N at step 1318 and incrementing the programmed data state at step 1320, an additional loop may be added to account for adjustments in lower tail verification (shifting the verify pulse from V NL increase to V NH ). In such embodiments, upper tail verification may occur with the V NL or V NH programming step.

[0125] Several aspects of this disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware or software embodiment (including, but not limited to, firmware, resident software, microcode, etc.), or may be a combination of hardware and software components, which may generally be collectively referred to as a "circuit," "module," "apparatus," or "system." Furthermore, aspects of this disclosure may be in the form of a computer program process embodied in one or more non-transitory computer-readable storage media, for example, storing computer-readable and / or executable program code.

[0126] Furthermore, various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish between components with different names but the same function. Within the scope of the various functional units described in the following disclosure, referred to as “modules,” such characterization is intended not to unduly limit the scope of potential implementation mechanisms. For example, a “module” can be implemented as hardware circuitry comprising custom-designed very large-scale integrated circuits (VLSI) or gate arrays, or off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In further examples, modules can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, modules can also be implemented, at least in part, by software executed by various types of processors. For example, a module may include a segment of executable code that constitutes one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such modules be physically located together, but rather that they may include different instructions stored in different locations, and when executed together, these instructions include the identified module and achieve the module’s intended purpose. Executable code may consist of a single instruction or a set of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In software, or partial software, or module implementations, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, devices, or apparatuses, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may consist of any tangible and / or non-transitory medium capable of containing and / or storing programs for use thereon or for use in conjunction with instructions executed by a system, device, processor, or apparatus.

[0127] Similarly, for the purposes of this disclosure, the term "component" can include any tangible, physical, and non-transitory device. For example, a component can be in the form of hardware logic circuitry consisting of custom VLSI circuitry, gate arrays, or other integrated circuits, or of off-the-shelf semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic device. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component can consist of one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages, or other discrete electrical devices) that are in an electrically communicative configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied in or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0128] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, circuit components can provide a return path for current. In contrast, in an open-loop configuration, although a return path for current is not included, the circuit components can still be considered to form a circuit. For example, an integrated circuit is referred to as a circuit regardless of whether it is coupled to ground (as a return path for current). In some example embodiments, a circuit may include a collection of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In further examples, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes and packages, or other discrete electrical devices, which are in an electrically communicative configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs). The circuit can also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other example embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, modules as defined above can be embodied in or implemented as circuits in some embodiments.

[0129] It should be understood that the exemplary embodiments disclosed herein may consist of one or more microprocessors and specific stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other components to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combinations of certain functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the following reference to "controller" should be defined to include a single circuit component, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field-programmable gate array (FPGA), and / or a processor with control software, or a combination thereof.

[0130] Furthermore, as may be used herein, the terms “program,” “software,” “software application,” etc., refer to a sequence of instructions designed to be executed on a computer-implemented system. Therefore, “program,” “software,” “application,” “computer program,” or “software application” can include subroutines, functions, procedures, object methods, object implementations, executable applications, applets, service applets, source code, object code, shared libraries / dynamically loaded libraries, and / or other specific sequences of instructions designed to be executed on a computer system.

[0131] Furthermore, the terms “coupled,” “coupled,” or “coupled” used herein are intended to indicate a direct or indirect connection. Thus, if a first device is coupled or coupled to a second device, the connection can be either a direct connection or an indirect connection via another device (or component).

[0132] The use of terms such as “embodiment,” “one embodiment,” “example embodiment,” “specific embodiment,” or other similar terms in this document is intended to indicate a particular feature, structure, function, operation, or characteristic described in connection with an embodiment present in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one embodiment,” “in an embodiment,” “in an example embodiment,” etc., may, but not necessarily, refer to the same embodiment, but rather to “one or more, but not all, embodiments,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and are therefore to be interpreted as “including, but not limited to…”, unless expressly stated otherwise. Moreover, without further limitations, an element beginning with “comprising…” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element.

[0133] Unless otherwise expressly stated, the terms “a,” “an,” and “the” also mean “one or more.” Furthermore, the phrase “at least one of A and B,” as may be used herein and / or in the following claims, indicates a choice of A or B, or both A and B, similar to the phrase “and / or,” where A and B are variables indicating a particular object or property. If there are more than two variables in the phrase, the phrase is defined herein as including only one variable, any one of the variables, any combination (or subcombination) of any variables, and all variables.

[0134] Furthermore, as used herein, the terms “approximately” or “around” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated value (e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant digit.

[0135] Furthermore, unless otherwise expressly stated, any list of items set forth herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive. Additionally, unless otherwise expressly stated, the term “set” as used herein shall be interpreted as “one or more,” and in the case of “multiple sets,” according to set theory, shall be interpreted as a multiple (or many) of “one or more,” “one or more,” and / or “multiple or many.”

[0136] The foregoing detailed description has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise forms disclosed. Many modifications and variations are possible in light of the above description. The described embodiments were chosen to best explain the principles of the present technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and with various modifications as suited to the particular intended use. The scope of the present technology is defined by the appended claims.

Claims

1. A storage device, comprising: A non-volatile memory includes control circuitry communicatively coupled to an array of memory cells arranged in a plurality of word lines, wherein the control circuitry is configured to program the memory cells of the plurality of word lines in a plurality of programming cycles, the programming cycles comprising: Apply a programming pulse to the selected word line among the plurality of word lines; as well as Apply a verification pulse V to the selected word line N This is to simultaneously verify the lower tail of the memory cell being programmed to data state N and the upper tail of the memory cell being programmed to data state N-1, wherein data state N-1 has a lower voltage threshold than data state N; and The verification pulse mentioned above is a low verification voltage V. NL Furthermore, in subsequent programming cycles, in response to the lower tail verification passing in data state N, during the application of the programming pulse, the programming of the memory cell to data state N is slowed down by applying a bias voltage to at least one bit line coupled to at least one memory cell in the selected word line, and the verification pulse is adjusted to a high verification voltage V. NH .

2. The storage device of claim 1, wherein the control circuitry is configured to stop programming the memory cell of the selected word line in response to a failure to verify the upper tail of the data state N-1.

3. The storage device of claim 1, wherein the control circuit is configured to incrementally increase the voltage of the programming pulse between programming cycles.

4. The storage device of claim 1, wherein the control circuitry is configured to prohibit further programming of the memory cell being programmed to data state N in response to the successful verification of the lower tail of data state N, and to incrementally advance the verified data state (N = N + 1).

5. The storage device of claim 1, wherein the low verification voltage V is used. NL To verify the upper tail of the memory cell programmed as data state N-1.

6. The storage device of claim 1, wherein the high verification voltage V is used. NH To verify the upper tail of the memory cell programmed as data state N-1.

7. A method for programming a non-volatile memory device, comprising the following steps: A memory device is provided, the memory device comprising an array of memory cells arranged in a plurality of word lines; Perform multiple programming loops to program the memory cell into at least one programmed data state, the programming loop comprising: The programming pulse is applied to the selected word line among the plurality of word lines, and Apply a verification pulse V to the selected word line N To simultaneously verify the lower tail of the memory cell being programmed to data state N and the upper tail of the memory cell being programmed to data state N-1, wherein data state N-1 has a lower voltage threshold than data state N; and The verification pulse mentioned above is a low verification voltage V. NL Furthermore, in subsequent programming cycles, in response to the lower tail verification passing of data state N, during the application of the programming pulse, the programming of the memory cell to data state N is slowed down by applying a bias voltage to at least one bit line coupled to the memory cell being programmed to data state N, and the verification pulse is adjusted to a high verification voltage V. NH .

8. The method of claim 7, further comprising the step of stopping the programming of the memory cell of the selected word line in response to a verification failure at the upper tail of data state N-1.

9. The method of claim 7, further comprising the step of incrementally increasing the voltage of the programming pulse between programming cycles.

10. The method of claim 7, further comprising the steps of prohibiting further programming of the memory cell programmed as data state N in response to the verification of the lower tail of data state N and incrementally increasing the verified data state (N = N + 1).

11. The method of claim 7, wherein the low verification voltage V is used. NL To verify the upper tail of the memory cell programmed as data state N-1.

12. The method of claim 7, wherein the high verification voltage V is used. NH To verify the upper tail of the memory cell programmed as data state N-1.

13. A memory device, comprising: Non-volatile memory, comprising an array of memory cells arranged in multiple word lines; A control circuit electrically communicating with the memory cell, the control circuit being configured to program the memory cell in a plurality of programming cycles, the programming cycle comprising: A programming pulse is applied to a selected word line among the plurality of word lines to program the non-disabled memory cell of the selected word line. Apply a verification pulse V to the selected word line N This is to simultaneously verify the lower tail of the memory cell that is being programmed to data state N and the upper tail of the memory cell that is disabled and in data state N-1. In response to the successful verification of the lower tail of the memory cell being programmed as data state N, further programming of the memory cell being programmed as data state N is prohibited, and the data state N is incrementally advanced (N = N + 1). In response to a failure at the upper tail of the memory cell in data state N-1, programming the selected word line is stopped; and The verification pulse V N It is a low verification voltage V NL Furthermore, in subsequent programming cycles, in response to the lower tail verification passing of data state N, during the application of the programming pulse, the programming of the memory cell to data state N is slowed down by applying a bias voltage to at least one bit line of at least one memory cell coupled to at least one of the selected word lines being programmed to data state N, and the verification pulse is adjusted to a high verification voltage V. NH .

14. The memory device of claim 13, wherein the control circuitry is configured to incrementally increase the voltage of the programming pulse between programming cycles.

15. The memory device of claim 13, wherein the memory cells are configured to be programmed to have at least two bits per memory cell.

16. The memory device of claim 13, wherein the low verification voltage V is used. NL To verify the upper tail of the memory cell programmed as data state N-1.

17. The memory device of claim 13, wherein the high verification voltage V is used. NH To verify the upper tail of the memory cell programmed as data state N-1.

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