Embedded wafer structure and method of forming the same

Abstract

Embodiments of the present application provide a method for forming a buried wafer structure, comprising: forming a first longitudinal fan-out layer on a first carrier; disposing a first chip on the first carrier, the first chip being beside the first longitudinal fan-out layer; and forming a first routing layer on the first longitudinal fan-out layer and the first chip. The present application aims to provide a buried wafer structure and a method for forming the same, so as to improve the performance of the buried wafer structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to embedded wafer structures and methods for forming the same. Background Technology

[0002] With the trend of miniaturization in packaged products, components are increasingly stacked vertically within the packaged products, resulting in multiple conductive pillars that conduct signals along the longitudinal direction within the packaged products.

[0003] Generally, conductive pillars are encapsulated using a first molding compound. The mold thickness depends on the component thickness. If the component is thicker, the difficulty of forming the conductive pillars increases. In addition to considering the aspect ratio affecting the number of conductive pillars, with a given number of conductive pillars, laser-formed pillars are wider at the top and narrower at the bottom. Therefore, the higher the pillar, the larger the maximum width, which in turn increases the lateral size of the package. Electroplated pillars, on the other hand, require segmented electroplating to consider process capabilities, and the increased height further increases the electroplating cost. Summary of the Invention

[0004] In view of the problems existing in related technologies, the purpose of this invention is to provide an embedded wafer structure and a method for forming the same, so as to improve the performance of the embedded wafer structure.

[0005] Embodiments of this application provide a method for forming an embedded wafer structure, comprising: forming a first vertical fan-out layer on a first carrier; placing a first chip on the first carrier, the first chip being located next to the first vertical fan-out layer; and forming a first circuit layer on the first vertical fan-out layer and the first chip.

[0006] In some embodiments, a first molding compound is used to encapsulate a first vertical fan-out layer and a first chip before forming the first circuit layer.

[0007] In some embodiments, a second chip is formed that is laterally connected to the first longitudinal fan-out layer prior to the formation of the first molding compound.

[0008] In some embodiments, in a top view, the sidewall of the second chip is parallel to the sidewall of the first chip.

[0009] In some embodiments, in a top view, the sidewall of the second chip is not parallel to the sidewall of the first chip.

[0010] In some embodiments, a passive element is formed between a first chip and a second chip, and the passive element is formed on the side of the first chip and the second chip that is farther apart.

[0011] In some embodiments, after the first circuit layer is formed, the first carrier is removed, and the first chip and the second chip are disposed on the second circuit layer.

[0012] In some embodiments, a third chip is formed on the first circuit layer after the second circuit layer is formed.

[0013] In some embodiments, after the second circuit layer is formed, a via is formed that penetrates the first circuit layer, the first molding compound, and the second circuit layer.

[0014] In some embodiments, the pads on the top surface of the first chip are connected to the first circuit layer.

[0015] An embodiment of this application provides an embedded wafer structure, comprising: a second circuit layer; a first vertical fan-out layer located on the second circuit layer; a first chip located on the second circuit layer and adjacent to the first vertical fan-out layer; a first molding compound encapsulating the first vertical fan-out layer and the first chip; a first circuit layer located above the first vertical fan-out layer and the first chip, and electrically connected to the first vertical fan-out layer, wherein the first chip is separated from the first vertical fan-out layer by the first molding compound.

[0016] In some embodiments, the device further includes a second chip that is in lateral contact with the first longitudinal fan-out layer.

[0017] In some embodiments, in a top view, the sidewall of the second chip is parallel to the sidewall of the first chip.

[0018] In some embodiments, in a top view, the sidewall of the second chip is not parallel to the sidewall of the first chip.

[0019] In some embodiments, the chip further includes a fourth chip that is laterally contacted with the first longitudinal fan-out layer and is opposite to the second chip.

[0020] In some embodiments, the device further includes a fifth chip disposed on the second circuit layer, wherein the fifth chip is disposed side by side with the first chip.

[0021] In some embodiments, the device further includes a sixth chip disposed above the first chip, with the back face of the sixth chip facing the back face of the first chip.

[0022] In some embodiments, the sixth chip is electrically connected to the first circuit layer.

[0023] In some embodiments, it further includes: a third chip located on the first line layer and electrically connected to the first line layer.

[0024] In some embodiments, the first molding compound contacts the first circuit layer and the second circuit layer. Attached Figure Description

[0025] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0026] Figures 1 to 31 A cross-sectional view is shown of the process of forming the embedded wafer structure of this application.

[0027] Figures 32 to 42 Embedded wafer structures according to different embodiments of this application are shown. Detailed Implementation

[0028] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0029] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0030] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0031] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0032] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0033] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0034] See Figure 1 A first seed layer 12 is formed on the third carrier 10.

[0035] See Figure 2 A first mask layer 20 is formed on the first seed layer 12. In some embodiments, the first mask layer 20 includes a photoresist (PR) material, and a first exposure process 21 is performed to cure the first mask layer 20.

[0036] See Figure 3 The first mask layer 20 is patterned to expose the first seed layer 12, and a first metal layer 30 is formed on the first seed layer 12.

[0037] See Figure 4 The remaining first mask layer 20 is removed, leaving the first seed layer 12 and the first metal layer 30. The first metal layer 30 is used as an etching mask to pattern the first seed layer 12.

[0038] See Figure 5 The steps of forming a dielectric layer, a seed layer, and a metal layer are repeated on the first metal layer 30 to form a first longitudinal fan-out layer 50 located on the third carrier 10.

[0039] See Figure 6A plurality of second chips 60 are placed on a first vertical fan-out layer 50 using a first clamp 61. In some embodiments, the interior of the first clamp 61 is configured as a vacuum environment to hold the second chips 60.

[0040] See Figure 7 Multiple second chips 60 are encapsulated using a second molding compound 70.

[0041] See Figure 8 A plurality of seventh chips 80 are placed on a second carrier 82 using a second clamp 81. In some embodiments, the interior of the second clamp 81 is configured as a vacuum environment to hold the seventh chips 80.

[0042] See Figure 9 A plurality of seventh chips 80 are encapsulated using a third molding compound 90. A first dielectric layer 92 is formed on the plurality of seventh chips 80. In some embodiments, the first dielectric layer 92 comprises a polyamide (PA) material, and a second exposure process 91 is performed on the first dielectric layer 92 to cure it.

[0043] See Figure 10 The first dielectric layer 92 is patterned, and a second seed layer 100 is formed on the patterned first dielectric layer 92.

[0044] See Figure 11 A second mask layer 110 is formed on the second seed layer 100. In some embodiments, the second mask layer 110 includes a photoresist (PR) material, and a third exposure process 111 is performed to cure the second mask layer 110.

[0045] See Figure 12 The second mask layer 110 is patterned to expose the second seed layer 100, and a second metal layer 120 is formed on the second seed layer 100.

[0046] See Figure 13 Remove the remaining second mask layer 110, leaving the second seed layer 100 and the second metal layer 120.

[0047] See Figure 14 The steps of forming a dielectric layer, a seed layer, and a metal layer are repeated to form a second vertical fan-out layer 140 on multiple seventh chips 80.

[0048] See Figure 15 Remove the second carrier 82.

[0049] See Figure 16 Remove the third carrier 10.

[0050] See Figure 17 The second chip 60 and the seventh chip 80 are connected one by one through the first bonding layer 170.

[0051] See Figure 18 In some embodiments, the second molding compound 70 and the third molding compound 90 comprise the same material. The stack is cut using a cutting tool 182 to form a monolithic insert 180. The insert 180 includes a corresponding pair of second chips 60 and seventh chips 80, and a first longitudinal fan-out layer 50 and a second longitudinal fan-out layer 140 respectively located on the second chips 60 and the seventh chips 80.

[0052] See Figure 19 The insert 180 is held in place by a third clamp 191. In some embodiments, the interior of the third clamp 191 is configured as a vacuum environment to hold the insert 180.

[0053] See Figures 20 to 21 Rotate the third clamp 191 and use the fourth clamp 201 to hold the side wall of the insert 180.

[0054] See Figure 22 The insert 180 is placed on the first carrier 220.

[0055] See Figure 23 The first chip 230 is held by the fifth clamp 231 and placed on the first carrier 220. The first chip 230 is located next to the insert 180 and next to the first vertical fan-out layer 50.

[0056] See Figure 24 The insert 180 and the first chip 230 are encapsulated using the first molding compound 240.

[0057] See Figure 25 Remove the first carrier 220.

[0058] See Figure 26 This forms a first redistribution layer 262 and a second redistribution layer 264 located above and below the first chip 230, respectively.

[0059] See Figure 27 A third dielectric layer 272 and a fourth dielectric layer 274 are formed on the first redistribution layer 262 and the second redistribution layer 264, respectively. In some embodiments, the third dielectric layer 272 and the fourth dielectric layer 274 comprise a polyamide (PA) material, and a fourth exposure process 271 is performed on the third dielectric layer 272 and the fourth dielectric layer 274 to cure them.

[0060] See Figure 28The third dielectric layer 272 and the fourth dielectric layer 274 are patterned, and an opening 282 is formed through the third dielectric layer 272 and the fourth dielectric layer 274. A third seed layer 280 is formed on the patterned third dielectric layer 272 and the fourth dielectric layer 274 and in the opening 282.

[0061] See Figure 29 A third mask layer 290 is formed on the third seed layer 280. In some embodiments, the third mask layer 290 includes a photoresist (PR) material, and a fifth exposure process 291 is performed to cure the third mask layer 290.

[0062] See Figure 30 The third mask layer 290 is patterned to expose the third seed layer 280, and a third metal layer 300 is formed on the third seed layer 280 to form a via 302 located in the opening 282. Thus, a first circuit layer 302 and a second circuit layer 304 are formed, located below and above the first chip 230, respectively.

[0063] See Figure 31The remaining third mask layer 290 is removed, leaving a third seed layer 280 and a third metal layer 300. The third seed layer 280 is patterned using the third metal layer 300 as a mask. Connectors 312 connected to the third metal layer 300 are formed on the first redistribution layer 262. In some embodiments, the connectors 312 are solder balls. This forms the embedded wafer structure 310 of this application. The accompanying drawings of the embodiments of this application use a single embedded wafer structure 310 as an example. In actual industrial manufacturing, the entire structure includes multiple embedded wafer structures 310, which are then diced to obtain a monolithic embedded wafer structure 310. In some embodiments, the aspect ratio of the second chip 60 and the seventh chip 80 of this application is 100 to 500. In some embodiments, the width of the second chip 60 and the seventh chip 80 is 50 μm to 200 μm, and the height is 5 mm to 20 mm. In some embodiments, the width ratio of the first vertical fan-out layer 50 to the width of the second chip 60 is 0.01 to 10. In some embodiments, the linewidth / spacing of the lines in the first vertical fan-out layer 50 and the second vertical fan-out layer 140 is 2μm / 2μm, and the diameter of the vias in the first vertical fan-out layer 50 and the second vertical fan-out layer 140 is 5μm to 20μm. In some embodiments, the linewidth / spacing of the lines in the first circuit layer 302 and the second circuit layer 304 is 10μm / 10μm, and the diameter of the vias in the first circuit layer 302 and the second circuit layer 304 is 10μm to 30μm. In some embodiments, the height and width of the embedded wafer structure 310 are 1mm to 80mm. In some embodiments, the connector 312 can be a controlled-collapse chip connection (C4) bump, solder bump, ball grid array (BGA) or land grid array (LGA), pillar, or a combination of two or more of these. In some embodiments, the dielectric layers of this application may be organic materials, such as polyimide (PI), epoxy resin, polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg resin (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); or / and inorganic materials, such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), nitrides (e.g., SiNx). In some embodiments, the seed layer and metal layer of this application may be Cu, Ni, Ti, W, or Pt alloys.

[0064] Figure 32 Different embodiments of this application are shown, and Figure 31 compared to, Figure 31The backs of the second chip 60 and the seventh chip 80 face each other, and Figure 32 This includes the second chip 60 and the seventh chip facing each other on their active sides. Figure 31 The second chip 60 and the seventh chip 80 are adjacent to each other, and Figure 32 The second chip 60 and the seventh chip are opposite to each other.

[0065] Figure 33 Different embodiments of this application are shown, and Figure 31 compared to, Figure 33 It also includes a third chip 330, located on the first circuit layer 302.

[0066] Figure 34 Different embodiments of this application are shown, and Figure 31 In contrast, the second chip 60 and the seventh chip 80, along with their attached vertical fan-out structures, are located on either side of the first chip 230.

[0067] Figure 35 A top view according to an embodiment of the present application is shown, in which the sidewall of the second chip 60 is parallel to the sidewall of the first chip 230.

[0068] Figure 36 It shows the relationship with Figure 35 In the top view of different embodiments, the sidewall of the second chip 60 is not parallel to the sidewall of the first chip 230. The passive element 360 is formed between the first chip 230 and the second chip 60, and the passive element 360 is formed on the side of the first chip 230 and the second chip 60 that is farther apart.

[0069] Figure 37 Different embodiments of this application are shown, and Figure 31 compared to, Figure 37 The embedded chip structure includes two pairs of second chips 60 and seventh chips 80 in the horizontal direction.

[0070] Figure 38 Different embodiments of this application are shown, and Figure 31 compared to, Figure 38 The embedded chip structure includes two pairs of second chips 60 and seventh chips 80 in the horizontal direction. Figure 38 It also includes a fifth chip 380, which is disposed on the second circuit layer 304, and the fifth chip 380 is disposed side by side with the first chip 230. Figure 38 It also includes a sixth chip 382, ​​which is disposed above the first chip 230, with the back face of the sixth chip 382 facing the back face of the first chip 230.

[0071] Figure 39 Different embodiments of this application are shown, and Figure 31In contrast, connectors 312 are formed on the upper and lower sides of the first chip 230, and connectors 312 are formed as bumps.

[0072] Figure 40 Different embodiments of this application are shown, and Figure 31 and Figure 39 In contrast, connector 312 is formed on the underside of the first chip 230, and connector 312 is formed as a solder ball.

[0073] Figure 41 Different embodiments of this application are shown, and Figure 31 In comparison, both the first line layer 302 and the second line layer 304 include more redistribution layers.

[0074] Figure 42 Different embodiments of this application are shown, and Figure 31 In contrast, the second vertical fan-out layer 140 connected to the seventh chip also has leads 420.

[0075] The embedded wafer structure of the embodiments of this application provides a vertical fan-out structure, which allows the lines in the fan-out structure next to the chip to have a smaller linewidth / pitch (e.g., L / S < 2μm / 2μm) and provides more inputs / outputs (I / O) than conventional packages.

[0076] Embodiments of the present invention utilize a pre-fabricated fan-out layer longitudinally bonded into an embedded wafer structure to replace conductive pillars. The thickness of the fan-out layer is much smaller than the width of conventional conductive pillars, thereby reducing the size of the embedded wafer structure and increasing the number of longitudinally connected inputs / outputs.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for forming an embedded wafer structure, characterized in that, include: A second chip is formed that is laterally connected to a first vertical fan-out layer, the first vertical fan-out layer being on the opposite side of the crystal back of the second chip, wherein the linewidth / spacing of the lines in the first vertical fan-out layer is less than 2μm / 2μm; The first vertical fan-out layer and the second chip, which are connected together, are rotated and placed on the first carrier to form the first vertical fan-out layer located on the first carrier. The first chip is placed on the first carrier, and the first chip is located next to the first vertical fan-out layer; The first vertical fan-out layer, the second chip, and the first chip are encapsulated using a first molding compound. After removing the first carrier, a first circuit layer is formed above the first vertical fan-out layer and the first chip, and a second circuit layer is formed below the first vertical fan-out layer and the first chip. The first vertical fan-out layer is located between the first circuit layer and the second circuit layer, and the rotated first vertical fan-out layer faces or moves away from the sidewall of the first chip, thereby replacing the conductive pillar with the rotated first vertical fan-out layer.

2. The method for forming an embedded wafer structure according to claim 1, characterized in that, After the second circuit layer is formed, a via is formed through the first circuit layer, the first molding compound, and the second circuit layer, and a third chip is formed on the first circuit layer.

3. An embedded wafer structure, characterized in that, The embedded wafer structure is formed using any one of claims 1-2, and the embedded wafer structure comprises: Second line layer; The first vertical fan-out layer is located on the second line layer; The first chip is located on the second circuit layer, and the first chip is located next to the first vertical fan-out layer; A first molding compound encapsulates the first vertical fan-out layer and the first chip; A first circuit layer is located above the first vertical fan-out layer and the first chip, and the first circuit layer is electrically connected to the first vertical fan-out layer. The first chip is separated from the first longitudinal fan-out layer by the first molding compound.

4. The embedded wafer structure according to claim 3, characterized in that, Also includes: The seventh chip is in lateral contact with the first vertical fan-out layer, and the active side of the second chip and the active side of the seventh chip face each other.

5. The embedded wafer structure according to claim 3, characterized in that, Also includes: The fifth chip is disposed on the second circuit layer, and the fifth chip is disposed side by side with the first chip.

6. The embedded wafer structure according to claim 3, characterized in that, Also includes: A sixth chip is disposed above the first chip, with the back face of the sixth chip facing the back face of the first chip, and the sixth chip is electrically connected to the first circuit layer.

7. The embedded wafer structure according to claim 3, characterized in that, Also includes: The third chip is located on the first circuit layer and is electrically connected to the first circuit layer.

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