A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof. The method comprises: providing a substrate, the substrate comprising an isolation structure and an active region defined by the isolation structure; performing a first etching process on the substrate to form a groove exposing the active region, a part of the active region exposed by the groove being defined as a contact region; performing a first surface treatment process to planarize a surface of the contact region; forming a first contact material layer covering at least a sidewall and a bottom of the groove; performing a second etching process to remove a part of the first contact material layer at the bottom of the groove to expose the contact region; performing a second surface treatment process to planarize a surface of the contact region; and forming a second contact material layer covering at least a sidewall of the first contact material layer and filling the groove.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Dynamic Random Access Memory (DRAM), as an important semiconductor device, can be used to store data or programs for data processing in electronic devices. However, in practical applications, DRAM often suffers from high power consumption. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an isolation structure and an active region defined by the isolation structure; performing a first etching process on the substrate to form a groove exposing the active region, the portion of the active region exposed by the groove being defined as a contact region; performing a first surface treatment process to planarize the surface of the contact region; forming a first contact material layer, the first contact material layer at least covering the sidewalls and bottom of the groove; performing a second etching process to remove the portion of the first contact material layer located at the bottom of the groove to expose the contact region; performing a second surface treatment process to planarize the surface of the contact region; and forming a second contact material layer, the second contact material layer at least covering the sidewalls of the first contact material layer and filling the groove.

[0004] In some embodiments, at least one of the first surface treatment process and the second surface treatment process includes: oxidizing the surface of the contact area using a first wet process; and removing the oxidized portion of the surface of the contact area using a first dry process.

[0005] In some embodiments, the reagents used in the first wet process include hydrogen peroxide solution.

[0006] In some embodiments, at least one of the first surface treatment process and the second surface treatment process includes: oxidizing the surface of the contact area using a second wet process and removing the oxidized portion of the surface of the contact area; and removing the residue after the second wet process using a second dry process.

[0007] In some embodiments, the reagents used in the second wet process include an ozonohydrofluoric acid solution.

[0008] In some embodiments, at least one of the first surface treatment process and the second surface treatment process includes: oxidizing the surface of the contact area using a third dry process; removing the residue after the third dry process using a cleaning process; and removing the oxidized portion of the surface of the contact area using a fourth dry process.

[0009] In some embodiments, the first contact material layer and the second contact material layer are made of the same material, and the first contact material layer and the second contact material layer together form a contact material layer.

[0010] In some embodiments, the material of the contact material layer includes a polycrystalline semiconductor material.

[0011] In some embodiments, after forming the second contact material layer, the preparation method further includes: thinning the contact material layer and doping the thinned contact material layer to obtain a contact layer; and performing a third surface treatment process to planarize the surface of the contact layer.

[0012] In some embodiments, the doping process includes ion implantation and annealing.

[0013] In some embodiments, the third surface treatment process includes: oxidizing the surface of the contact layer using a first wet process; and removing the oxidized portion of the surface of the contact layer using a first dry process.

[0014] In some embodiments, the third surface treatment process includes: oxidizing the surface of the contact layer using a second wet process and removing the oxidized portion of the surface of the contact layer; and removing the residue after the second wet process using a second dry process.

[0015] In some embodiments, the third surface treatment process includes: oxidizing the surface of the contact layer using a third dry process; and removing the oxidized portion of the surface of the contact layer using a fourth dry process.

[0016] In some embodiments, after performing the third surface treatment process, the preparation method further includes: forming a bit line material layer on the contact layer; etching the bit line material layer and the contact layer to form a bit line structure located on the contact region.

[0017] In some embodiments, the bit line material layer includes a metal material layer located on the contact layer.

[0018] In some embodiments, performing a first etching process on the substrate includes: forming a mask material layer on the substrate; patterning the mask material layer to obtain a mask layer; and etching the substrate using the mask layer as a mask to form the groove.

[0019] This disclosure also provides a semiconductor structure fabricated using the method described in any of the foregoing embodiments.

[0020] In the semiconductor structure fabrication method provided in this disclosure, by performing a first surface treatment process, the damage to the contact area surface caused by the first etching process can be mitigated, resulting in a smooth surface in the contact area. This improves the quality of the first contact material layer formed thereon, ensuring a good contact surface between it and the contact area. Simultaneously, by performing a second surface treatment process, the damage to the contact area surface caused by the second etching process can be mitigated, resulting in a smooth surface in the contact area. This improves the quality of the second contact material layer formed thereon, ensuring a good contact surface between it and the contact area. In this disclosure, the first and second contact material layers together fill the groove structure located above the contact area. These two material layers can be used as the contact structure of the semiconductor structure. Because this contact structure has high quality and can form a good contact surface with the contact area, the fabrication method provided in this disclosure can significantly reduce the contact resistance between the contact structure and the contact area, and effectively reduce the power consumption of the semiconductor structure.

[0021] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0024] Figures 2 to 18 This is a process flow diagram of the semiconductor structure fabrication process provided in the embodiments of this disclosure; wherein, Figure 17 Figure (1) is a top view schematic diagram of the formation of the bit line material layer provided in an embodiment of this disclosure. Figure 17 Figure (2) is a schematic diagram of the structure for forming a bit line material layer provided in an embodiment of this disclosure;

[0025] Figure 18 Figure (1) is a top view of the bit line formation provided in an embodiment of this disclosure. Figure 18 Figure (2) is a schematic diagram of the structure for forming bit lines provided in an embodiment of this disclosure. Detailed Implementation

[0026] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0028] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] In the structure of Dynamic Random Access Memory (DRAM), the bit line contact structure is an important component. One end of the bit line contact structure is connected to the active region located in the substrate, and the other end is connected to the bit line structure. If the quality of the bit line contact structure produced during the fabrication process is poor, it is easy to generate a large contact resistance or poor contact between the bit line contact structure and the active region or bit line. When the DRAM is subsequently used in the working environment, the above situation can easily cause a significant increase in power consumption or even make the device unable to function properly.

[0033] Therefore, there are still many problems in the fabrication methods of dynamic random access memory that need to be improved.

[0034] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0035] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes the following steps:

[0036] Step S101: Provide a substrate, the substrate including an isolation structure and an active region defined by the isolation structure;

[0037] Step S102: Perform a first etching process on the substrate to form a groove that exposes the active region, wherein the portion of the active region exposed by the groove is defined as a contact region;

[0038] Step S103: Perform a first surface treatment process to flatten the surface of the contact area;

[0039] Step S104: Form a first contact material layer, the first contact material layer at least covering the sidewalls and bottom of the groove;

[0040] Step S105: Perform a second etching process to remove the portion of the first contact material layer located at the bottom of the groove, thereby exposing the contact area;

[0041] Step S106: Perform a second surface treatment process to flatten the surface of the contact area;

[0042] Step S107: Form a second contact material layer, the second contact material layer at least covering the sidewall of the first contact material layer and filling the groove.

[0043] Thus, by performing the first surface treatment process, the damage to the contact area surface caused by the first etching process can be mitigated, resulting in a smooth surface in the contact area. This improves the quality of the first contact material layer formed thereon, ensuring a good contact surface between it and the contact area. Simultaneously, by performing the second surface treatment process, the damage to the contact area surface caused by the second etching process can be mitigated, resulting in a smooth surface in the contact area. This improves the quality of the second contact material layer formed thereon, ensuring a good contact surface between it and the contact area. In this embodiment, the first and second contact material layers together fill the groove structure located above the contact area. These two material layers can be used as the contact structure of the semiconductor structure. Because this contact structure has high quality and can form a good contact surface with the contact area, the fabrication method provided in this embodiment can significantly reduce the contact resistance between the contact structure and the contact area, and effectively reduce the power consumption of the semiconductor structure.

[0044] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged off-scale for ease of explanation, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0045] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 2 to 18 This is a process flow diagram of the semiconductor structure fabrication process provided in the embodiments of this disclosure; wherein, Figure 17 Figure (1) is a top view schematic diagram of the formation of the bit line material layer provided in an embodiment of this disclosure. Figure 17 Figure (2) is a schematic diagram of the structure for forming a bit line material layer provided in an embodiment of this disclosure; Figure 18 Figure (1) is a top view of the bit line formation provided in an embodiment of this disclosure. Figure 18 Figure (2) is a schematic diagram of the structure for forming bit lines provided in an embodiment of this disclosure.

[0046] First, execute step S101, as follows: Figure 2 As shown, a substrate 10 is provided, the substrate 10 including an isolation structure STI and an active region 11 defined by the isolation structure STI.

[0047] Here, the substrate can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate.

[0048] In some embodiments, the material of the isolation structure STI includes, but is not limited to, at least one or a combination of oxides, nitrides, and oxynitrides. In some specific embodiments, the material of the isolation structure STI can be a composite layer composed of silicon oxide, silicon nitride, and silicon oxide. However, it is not limited to this; in actual processes, the isolation structure STI can also be made of other materials, which can be flexibly selected according to the actual situation and are not specifically limited here.

[0049] In some embodiments, such as Figure 3 As shown, after providing the substrate 10, the fabrication method further includes forming a stacked material layer 13 on the substrate 10, wherein the stacked material layer 13 may include a first sublayer 131, a second sublayer 132, a third sublayer 133 and a fourth sublayer 134.

[0050] Optionally, the material of the first sublayer 131 includes, but is not limited to, oxides, such as silicon oxide; the material of the second sublayer 132 includes, but is not limited to, nitrides, such as silicon nitride; the material of the third sublayer 133 includes, but is not limited to, semiconductor materials, such as polysilicon; and the material of the fourth sublayer 134 includes, but is not limited to, oxides, such as silicon oxide.

[0051] Next, proceed to step S102, as follows: Figures 4 to 6As shown, a first etching process is performed on the substrate 10 to form a groove T that exposes the active region 11, and the portion of the active region 11 exposed by the groove T is defined as the contact region P.

[0052] In some embodiments, a first etching process is performed on the substrate 10, including:

[0053] A mask material layer M1a is formed on the substrate 10;

[0054] Pattern the mask material layer M1a to obtain the mask layer M1;

[0055] Using the mask layer M1 as a mask, the substrate 10 is etched to form the groove T.

[0056] Optionally, in some embodiments, such as Figures 4 to 6 As shown, when a stacked material layer 13 is formed on the substrate 10, the first etching process performed on the substrate 10 includes:

[0057] A mask material layer M1a is formed on the stacked material layer 13;

[0058] Pattern the mask material layer M1a to obtain the mask layer M1;

[0059] Using the mask layer M1 as a mask, an etching process is performed on the stacked material layer 13 to form a first sub-groove T1 in the stacked material layer 13;

[0060] A first etching process is performed on substrate 10 to remove a portion of substrate 10 located below the first sub-groove T1 to form a second sub-groove T2;

[0061] Among them, the first sub-groove T1 and the second sub-groove T2 together constitute groove T.

[0062] Here, the mask material layer includes, but is not limited to, photoresist, also known as photoresist, which is a light-sensitive substance. Typically, photoresist can transfer the desired micro-pattern from the photomask (mask) to the structure to be processed through photolithography processes such as exposure and development via photochemical reactions.

[0063] Understandable, such as Figure 6 As shown, during the etching process of substrate 10 to form groove T, the surface of active region 11 exposed by groove T, that is, the surface of contact region P, will usually generate a certain first damage 21. The first damage 21 makes the surface of contact region P uneven. When other material layers need to be formed on the surface of contact region P in the future, the interface quality between the formed material layer and contact region P is poor, with many defects, which easily leads to material shedding, peeling and other phenomena, seriously affecting the stability of the final semiconductor structure.

[0064] Furthermore, if other material layers formed on the surface of the contact region P are conductive materials, the poor interface quality between them and the contact region P can easily lead to a large contact resistance between the conductive material layer and the contact region P, thereby significantly increasing the power consumption of the semiconductor structure. On the other hand, when the first damage 21 exists, the quality of the conductive material grown on the contact region P will also be poor, causing the resistance of the conductive material itself to increase, further increasing the power consumption of the semiconductor structure.

[0065] To reduce the adverse effects of the first damage 21 on the subsequently formed material layer or structure, this disclosure provides various processing methods to improve the interface quality between the contact area P and the material formed on its surface after the first etching process. The following will describe the various embodiments in more detail with reference to the accompanying drawings in the next step (step S103).

[0066] Next, proceed to step S103, as follows: Figures 6 to 8 As shown, a first surface treatment process is performed to planarize the surface of the contact area P.

[0067] In practice, after performing the first etching process on the substrate 10 and before performing the first surface treatment process, the method further includes:

[0068] An ashing and cleaning process is performed to remove the mask layer M1, polymers, particles and impurities generated during the etching process.

[0069] Here, the gas introduced to perform the ashing process may include at least one of hydrogen (H2) and nitrogen (N2); for example, in some embodiments, the gas introduced to perform the ashing process may be a mixture of hydrogen (H2) and nitrogen (N2).

[0070] Optionally, in some embodiments, the cleaning process performed after the first etching process includes, but is not limited to, a wet cleaning process, which may be performed once or multiple times. In practice, the number of cleaning cycles can be flexibly selected according to the situation, and no specific limitation is made here. It is understood that the wet cleaning process can further clean the semiconductor structure after the first etching process, providing good preparation conditions for the subsequent production processes.

[0071] In some embodiments of this disclosure, performing the first surface treatment process includes:

[0072] The surface of the contact area P is oxidized using a first wet process;

[0073] The oxidized portion of the surface of the contact area P is removed using a first dry process.

[0074] Here, the first wet process can occur after the cleaning process, and the reagent used in the first wet process includes hydrogen peroxide solution. In some embodiments, the reagent used in the first wet process may also include water in addition to hydrogen peroxide solution.

[0075] Understandable, such as Figure 6 and Figure 7 As shown, the first damage 21 on the surface of the contact area P can be oxidized using a hydrogen peroxide solution to form a first oxide layer 22. Compared to the first damage 21, the first oxide layer 22 formed after oxidation is easier to remove in the subsequent first dry process, which is beneficial for obtaining a contact area P with a smooth surface. For example, the volume ratio of hydrogen peroxide to deionized water in the hydrogen peroxide solution is 1:50, but it is not limited to this.

[0076] In some embodiments, the first dry process includes, but is not limited to, a dry cleaning process, which can remove the first oxide layer 22 and the residues generated after the first etching process, so that the contact area P obtains a surface with high flatness (e.g., Figure 8 As shown), this is for the subsequent formation of the first contact material layer ( Figure 9 The process operation shown provides favorable preparation conditions.

[0077] In other embodiments of this disclosure, reference continues to be made. Figures 6 to 8 As shown, the first surface treatment process includes:

[0078] The surface of the contact area P is oxidized using a second wet process, and the oxidized portion of the surface of the contact area P is removed.

[0079] The residue from the second wet process is removed using a second dry process.

[0080] Here, the second wet process can occur after the cleaning process, and the reagents used in the second wet process include an ozonated hydrofluoric acid solution (i.e., a mixed solution of ozone water and hydrofluoric acid). In some embodiments, the concentration of the ozonated hydrofluoric acid solution is between 700 ppm and 900 ppm, such as 750 ppm, 800 ppm, 850 ppm, etc. Optionally, the ozonated hydrofluoric acid solution can be introduced for 30 seconds, but is not limited to this; the introduction time can also be other values, such as 10 seconds, 20 seconds, 25 seconds, 35 seconds, etc., without specific limitation, and can be adjusted according to specific circumstances in actual operation.

[0081] Optionally, in this embodiment, a second wet process is performed by introducing an ozonated hydrofluoric acid solution to oxidize the first damage 21 on the surface of the contact area P to obtain a first oxide layer 22, and the first oxide layer 22 generated can be removed from the contact area P during this step.

[0082] In practice, the second dry process includes, but is not limited to, dry cleaning processes. The second dry process can remove various residues and impurities generated after the first etching process and the second wet process, thereby enabling the contact area P to obtain a surface with high flatness (e.g., Figure 8 As shown), this is the subsequent first contact material layer ( Figure 9 The formation of (as shown) provides favorable preparation conditions.

[0083] Unlike the two embodiments above, where the ashing and cleaning processes are performed before the first surface treatment, in actual operation, the first surface treatment process can also be performed directly after the first etching process. For example:

[0084] In some embodiments of this disclosure, such as Figures 6 to 8 As shown, the first surface treatment process includes:

[0085] The surface of the contact area P is oxidized using a third dry process;

[0086] The residue from the third dry process is removed by a cleaning process.

[0087] The oxidized portion of the surface of the contact area P is removed using the fourth dry process.

[0088] Here, the third dry process includes an ashing process. Optionally, in this embodiment, during the ashing process, oxygen can be introduced to oxidize the first damage 21 on the surface of the contact area P to form a first oxide layer 22. The third dry process can remove the mask layer M1, polymers, particles and impurities generated during the etching process.

[0089] Here, the gas introduced to perform the ashing process may include at least one of hydrogen (H2) and nitrogen (N2) in addition to oxygen; for example, in some embodiments, the gas introduced to perform the ashing process may also include a mixture of hydrogen (H2) and nitrogen (N2) in addition to oxygen.

[0090] Understandably, after the third dry process (ashing process), the residue generated after the third dry process can be removed by performing a cleaning process.

[0091] Optionally, the fourth dry process may include, but is not limited to, a dry cleaning process. The dry cleaning process can remove the oxidized part of the surface of the contact area P, i.e., the first oxide layer 22, so that the contact area P obtains a smooth surface, providing good preparation conditions for the formation of subsequent materials.

[0092] Unlike the two embodiments above, which require subsequent wet and dry processes after ashing and cleaning to obtain a contact area with a smooth surface, this embodiment incorporates the ashing and cleaning processes into the first surface treatment process. This allows for a single fourth dry process after the ashing (third dry process) and cleaning processes to achieve the desired smooth surface. Therefore, this embodiment significantly simplifies the process for obtaining a smooth contact area compared to other embodiments, effectively improving production efficiency.

[0093] Next, continue with step S104, as follows: Figure 9 As shown, a first contact material layer 121 is formed, which at least covers the sidewalls and bottom of the groove T.

[0094] Optionally, the material of the first contact material layer 121 may include a polycrystalline semiconductor material, such as polycrystalline silicon or other polycrystalline semiconductor materials.

[0095] Understandably, when the surface of the contact area P is flat and the material of the first contact layer is polycrystalline silicon, the first contact material layer 121 grown on the surface of the contact area P is more likely to obtain a single crystal structure (the single crystal structure is beneficial to reducing the contact resistance between the two). The first contact material layer 121 formed has high quality, and the interface quality between the contact area P and the first contact material layer 121 is also good. Therefore, the preparation method provided in this embodiment can reduce the resistance of the first contact material layer 121 itself and can effectively reduce the contact resistance between the first contact material layer 121 and the contact area P, so that the semiconductor structure finally formed can significantly reduce power consumption when applied.

[0096] Next, proceed to step S105, as follows: Figure 10 and Figure 11 As shown, a second etching process is performed to remove the portion of the first contact material layer 121 located at the bottom of the groove T, so as to expose the contact area P.

[0097] Here, the second etching process may include at least one of dry etching process or wet etching process. The specific etching process to be used can be flexibly determined according to the actual situation, and no specific limitation is made here.

[0098] In some embodiments, performing a second etching process includes:

[0099] A mask material layer (not shown) is formed on a substrate and an etching process is performed to form a patterned mask layer M2, which exposes a portion of the first contact material layer 121 located at the bottom of the groove T.

[0100] Using the patterned mask layer M2 as a mask, the first contact material layer 121 is etched to remove the portion of the first contact material layer 121 located at the bottom of the groove T, so as to expose the contact area P.

[0101] Here, the mask material layer includes, but is not limited to, photoresist.

[0102] Understandable, such as Figure 10 As shown, during the etching process to remove the portion of the first contact material layer 121 located at the bottom of the groove T, a certain amount of second damage 23 is usually generated on the surface of the contact area P exposed by the first contact material layer 121. The second damage 23 makes the surface of the contact area P uneven. When other material layers need to be formed on the surface of the contact area P in the future, the interface quality between the formed material layer and the contact area P is poor, with many defects, which easily leads to material shedding, peeling and other phenomena, seriously affecting the stability of the final semiconductor structure.

[0103] Furthermore, if other material layers formed on the surface of contact region P are conductive materials, the poor interface quality between them and contact region P can easily lead to a large contact resistance between the conductive material layer and contact region P, thereby significantly increasing the power consumption of the semiconductor structure. On the other hand, when the second damage 23 exists, the quality of the conductive material grown on contact region P will also be poor, causing the resistance of the conductive material itself to increase, further increasing the power consumption of the semiconductor structure.

[0104] To reduce the adverse effects of the second damage 23 on the subsequently formed material layer or structure, this disclosure provides various processing methods to improve the interface quality between the contact area P and the material formed on its surface after the second etching process. The following will describe the various embodiments in more detail with reference to the accompanying drawings in the next step (step S106).

[0105] Next, proceed to step S106, as follows: Figures 10 to 12 As shown, a second surface treatment process is performed to planarize the surface of the contact area P.

[0106] In some embodiments of this disclosure, the preparation method further includes, prior to performing the second surface treatment process:

[0107] An ashing and cleaning process is performed to remove the patterned mask layer M2, polymers, particles, and impurities generated during the etching process.

[0108] Here, the gas introduced to perform the ashing process may include at least one of hydrogen (H2) and nitrogen (N2); for example, in some embodiments, the gas introduced to perform the ashing process may be a mixture of hydrogen (H2) and nitrogen (N2).

[0109] Optionally, in some embodiments, the cleaning process performed after the first etching process includes, but is not limited to, a wet cleaning process, which may be performed once or multiple times. In practice, the number of cleaning cycles can be flexibly selected according to the situation, and no specific limitation is made here. It is understood that the wet cleaning process can further clean the semiconductor structure after the first etching process, providing favorable conditions for the execution of subsequent processes.

[0110] In some embodiments, such as Figure 11 and 12 As shown, after performing the ashing and cleaning processes, the second surface treatment process is performed, including:

[0111] The surface of the contact area P is oxidized using a first wet process;

[0112] The oxidized portion of the surface of the contact area P is removed using a first dry process.

[0113] Here, the reagents used in the first wet process include hydrogen peroxide solution. Optionally, in some embodiments, the reagents used in the first wet process may also include water in addition to hydrogen peroxide solution.

[0114] Understandable, such as Figure 10 and Figure 11 As shown, the second damage 23 on the surface of the contact area P can be oxidized by hydrogen peroxide solution to form a second oxide layer 24. Compared with the second damage 23, the second oxide layer 24 formed after oxidation is easier to remove in the subsequent first dry process, so as to obtain a contact area P with a flat surface.

[0115] In some embodiments, the first dry process includes, but is not limited to, a dry cleaning process, which can remove the second oxide layer 24 and the residues generated after the second etching process, so that the contact area P obtains a surface with high flatness (e.g., Figure 12 As shown), this is for the subsequent formation of the second contact material layer 122 ( Figure 13 The process operation shown provides favorable preparation conditions.

[0116] In other embodiments of this disclosure, reference continues to be made. Figures 10 to 12 As shown, the preparation method further includes the following steps before performing the second surface treatment process:

[0117] An ashing process is performed to remove the patterned mask layer M2.

[0118] Here, the gas introduced to perform the ashing process may include at least one of hydrogen (H2) and nitrogen (N2); for example, in some embodiments, the gas introduced to perform the ashing process may be a mixture of hydrogen (H2) and nitrogen (N2).

[0119] In this embodiment, such as Figure 11 and 12 As shown, after the ashing process, the second surface treatment process is performed, including:

[0120] The surface of the contact area P is oxidized using a second wet process, and the oxidized portion of the surface of the contact area P is removed.

[0121] The residue from the second wet process is removed using a second dry process.

[0122] Here, after the ashing process, a cleaning process is also included. Optionally, in some embodiments, the second wet process can be performed simultaneously with the cleaning process. For example, during the cleaning process, an oxidizing agent can be introduced to oxidize the surface of the contact area P and remove the oxidized portion of the surface of the contact area P. Compared with the previous embodiment, this embodiment achieves a certain degree of integration and synchronization of the cleaning process and the second wet process, which can effectively save process time and improve production efficiency.

[0123] Optionally, the reagent used in the second wet process includes an ozonated hydrofluoric acid solution. In some embodiments, the concentration range of the ozonated hydrofluoric acid solution can be consistent with the concentration of the ozonated hydrofluoric acid solution used in the first surface treatment process, for example, a concentration range between 700 ppm and 900 ppm, such as 750 ppm, 800 ppm, 850 ppm, etc. Optionally, the ozonated hydrofluoric acid solution can be introduced for 30 seconds, but is not limited to this; the introduction time can also be other values, such as 10 seconds, 20 seconds, 25 seconds, 35 seconds, etc.

[0124] However, not limited to this, in some other embodiments, when the reagent used in the second wet process is an ozonohydrofluoric acid solution, the reagent concentration and solution introduction time used in the second surface treatment process may be different from those used in the first surface treatment process. The specific concentration can be selected according to the actual situation, and no specific restrictions are made here.

[0125] Optionally, in this embodiment, a second wet process is performed by introducing an ozonated hydrofluoric acid solution to oxidize the second damage 23 on the surface of the contact area P to obtain a second oxide layer 24, and the generated second oxide layer 24 can be removed from the contact area P during this step.

[0126] In practice, the second dry process includes, but is not limited to, dry cleaning processes. The second dry process can remove various residues and impurities generated after the first etching process and the second wet process, thereby enabling the contact area P to obtain a surface with high flatness (e.g., Figure 12 As shown), this is the subsequent second contact material layer ( Figure 13 The formation of (as shown) provides favorable preparation conditions.

[0127] Unlike the two embodiments above, which involve performing at least one ashing process before the second surface treatment, in practice, the second surface treatment process can be performed directly after the second etching process. For example:

[0128] In some embodiments of this disclosure, such as Figures 10 to 12 As shown, the second surface treatment process includes:

[0129] The surface of the contact area P is oxidized using a third dry process;

[0130] The residue from the third dry process is removed by a cleaning process.

[0131] The oxidized portion of the surface of the contact area P is removed using the fourth dry process.

[0132] Here, the third dry process includes an ashing process. Optionally, in this embodiment, during the ashing process, oxygen can be introduced to oxidize the second damage 23 on the surface of the contact area P to form a second oxide layer 24. The third dry process can remove the patterned mask layer M2, polymers, particles and impurities generated during the etching process.

[0133] Here, the gas introduced to perform the ashing process may include at least one of hydrogen (H2) and nitrogen (N2) in addition to oxygen; for example, in some embodiments, the gas introduced to perform the ashing process may be a mixture of hydrogen (H2) and nitrogen (N2) in addition to oxygen.

[0134] Understandably, after the third dry process (ashing process), the residue generated after the third dry process can be removed by performing a cleaning process.

[0135] Optionally, the fourth dry process may include, but is not limited to, a dry cleaning process. The dry cleaning process can remove the oxidized part of the surface of the contact area P, namely the second oxide layer 24, so that the contact area P obtains a smooth surface, providing good preparation conditions for the formation of subsequent materials.

[0136] Unlike the two embodiments above, which either exclude the ashing and cleaning processes from the second surface treatment process, this embodiment incorporates the ashing and cleaning processes into the second surface treatment process. This allows for the acquisition of a contact area with a smooth surface by performing only one fourth dry process after the ashing process (third dry process) and the cleaning process. Therefore, compared to other embodiments, this embodiment significantly simplifies the process for obtaining a contact area with a smooth surface, effectively improving production efficiency.

[0137] Finally, proceed with step S107, as follows: Figure 13 As shown, a second contact material layer 122 is formed, which at least covers the sidewall of the first contact material layer 121 and fills the groove T.

[0138] In some embodiments, the first contact material layer 121 and the second contact material layer 122 are made of the same material, and the first contact material layer 121 and the second contact material layer 122 together form contact material layer 12a.

[0139] In some embodiments, the material of the contact material layer 12a includes a polycrystalline semiconductor material. Optionally, the material of the contact material layer 12a includes, but is not limited to, polycrystalline silicon.

[0140] Here, due to the execution of the first and second surface treatment processes, the contact area P has a relatively flat surface, which makes it easier for the contact material layer 12a formed thereon to obtain a single crystal structure (the single crystal structure is beneficial to reduce the contact resistance between the two), thus giving it higher quality and reducing the resistance of the material layer itself; in addition, a better interface quality can also be obtained between the contact area P and the contact material layer 12a, thereby effectively reducing the contact resistance between the two.

[0141] Understandably, in practice, after forming the contact material layer 12a, other processing steps can be performed to obtain other structures, such as:

[0142] Optionally, in any of the above embodiments, such as Figures 13 to 16 As shown, after forming the second contact material layer 122, the preparation method further includes:

[0143] The contact material layer 12a is thinned and then doped to obtain the contact layer 12.

[0144] A third surface treatment process is performed to planarize the surface of the contact layer 12.

[0145] Optionally, during the thinning process, the fourth sub-layer 134 in the stacked material layer 13 can be removed, and part of the height of the third sub-layer 133 can be removed, so that after the thinning process is performed, the upper surfaces of the third sub-layer 133, the first contact material layer 121 and the second contact material layer 122 are flush. At this time, the third sub-layer 133, the first contact material layer 121 and the second contact material layer 122 can together form the contact layer 12.

[0146] Thinning processes can effectively reduce the height and volume of semiconductor structures, resulting in a semiconductor structure with a smaller weight.

[0147] In some embodiments, the doping process includes ion implantation and annealing.

[0148] Here, the doping type used in the doping process includes at least one of N-type doping or P-type doping. When N-type doping is used, the dopant atoms used in the ion implantation process include, but are not limited to, at least one or a combination of phosphorus (P), arsenic (As), or antimony (Sb) or other N-type dopant atoms. When P-type doping is used, the dopant atoms used in the ion implantation process include, but are not limited to, at least one or a combination of boron, indium, or other P-type dopant atoms. The doping process significantly improves the conductivity of the contact layer, reduces the resistance of the contact layer and the contact resistance between the contact layer and the contact area, thereby effectively reducing the power consumption of the final semiconductor structure.

[0149] In the embodiments of this disclosure, the third surface treatment process can be implemented in a variety of ways, and the methods used are similar to the first and second surface treatment processes. The following describes several embodiments of the third surface treatment process provided in this disclosure with reference to the accompanying drawings.

[0150] Understandable, such as Figure 14 As shown, during the thinning process, a third damage 25 is easily generated on the surface of the contact layer 12. This damage can be prevented from adversely affecting the performance of the semiconductor structure by performing a third surface treatment process.

[0151] Optionally, before performing the third surface treatment process, the method further includes:

[0152] An ashing and cleaning process is performed to remove the photoresist layer that covers other areas during the thinning process, as well as polymers, particles, and impurities generated during the etching process.

[0153] In this embodiment, the gas introduced to perform the ashing process can be at least one of hydrogen (H2) and nitrogen (N2); for example, in some embodiments, the gas introduced to perform the ashing process can also be a mixture of hydrogen (H2) and nitrogen (N2).

[0154] In some embodiments of this disclosure, such as Figures 14 to 16 As shown, the third surface treatment process includes:

[0155] The surface of the contact layer 12 is oxidized using a first wet process;

[0156] The oxidized portion of the surface of the contact layer 12 is removed using a first dry process.

[0157] In this embodiment, the reagent used to perform the first wet process includes hydrogen peroxide, and the treatment method is basically the same as that used in the first surface treatment process when hydrogen peroxide is used as the reagent, so it will not be described in detail here.

[0158] By performing the third surface treatment process of this embodiment, the third damage 25 can be oxidized to form a third oxide layer 26 and then removed, thereby enabling the contact layer 12 to obtain a smooth surface.

[0159] In other embodiments of this disclosure, reference continues to be made. Figures 14 to 16 Performing the third surface treatment process includes:

[0160] The surface of the contact layer 12 is oxidized using a second wet process, and the oxidized portion of the surface of the contact layer 12 is removed.

[0161] The residue from the second wet process is removed using a second dry process.

[0162] In this embodiment, the reagents used to perform the second wet process include an ozonated hydrofluoric acid solution, and the treatment method is basically the same as that used in the first surface treatment process with an ozonated hydrofluoric acid solution, so it will not be described in detail here.

[0163] In this embodiment, the concentration and introduction time of the ozonated hydrofluoric acid solution during the second wet process can be the same as the settings in other embodiments when using the ozonated hydrofluoric acid solution. For example, the concentration range is between 700ppm and 900ppm, such as 750ppm, 800ppm, 850ppm, etc. Optionally, the introduction time of the ozonated hydrofluoric acid solution can be 30S, but it is not limited to this. The introduction time can also be other values, such as 10S, 20S, 25S, 35S, etc.

[0164] However, not limited to this, in some other embodiments, when the reagent used in the second wet process is an ozonohydrofluoric acid solution, the reagent concentration and solution introduction time used in the third surface treatment process may be different from those in the first surface treatment process. The concentration can be selected according to the actual situation, and no specific restrictions are made here.

[0165] Understandably, in this embodiment, by performing the third surface treatment process of this embodiment, the third damage 25 can be oxidized to form a third oxide layer 26 and then removed, thereby enabling the contact layer 12 to obtain a smooth surface.

[0166] In yet another embodiment of this disclosure, such as Figures 14 to 16 As shown, the third surface treatment process includes:

[0167] The surface of the contact layer 12 is oxidized using a third dry process;

[0168] The oxidized portion of the surface of the contact layer 12 is removed using a fourth dry process.

[0169] In this embodiment, the surface of the contact layer 12 can be oxidized with oxygen, and the treatment method is basically the same as when oxygen is used in the first surface treatment process.

[0170] For example, the third dry process may include an ashing process. Optionally, in this embodiment, during the ashing process, oxygen can be introduced to oxidize the third damage 25 on the surface of the contact layer 12 to form a third oxide layer 26. The third dry process can remove the photoresist layer, polymers, particles and impurities generated during the etching process, etc., that are covered on other areas during the thin process.

[0171] Here, the gas introduced to perform the ashing process may include at least one of hydrogen (H2) and nitrogen (N2) in addition to oxygen; for example, in some embodiments, the gas introduced to perform the ashing process may also include a mixture of hydrogen (H2) and nitrogen (N2) in addition to oxygen.

[0172] Understandably, after the third dry process (ashing process), a cleaning process can be performed to remove the residues generated after the third dry process.

[0173] Optionally, the fourth dry process may include, but is not limited to, a dry cleaning process. The dry cleaning process can remove the oxidized portion of the surface of the contact layer 12, namely the third oxide layer 26, so that the contact layer 12 has a smooth surface, providing good preparation conditions for the formation of subsequent materials.

[0174] Unlike the two embodiments above, which require wet and dry processes after ashing and cleaning to obtain a contact layer with a smooth surface, this embodiment incorporates the ashing and cleaning processes into the third surface treatment process. This allows for a single fourth dry process after the ashing (third dry process) and cleaning processes to obtain the contact layer with a smooth surface. Therefore, compared to other embodiments, this embodiment significantly simplifies the process for obtaining a contact layer with a smooth surface and effectively improves production efficiency.

[0175] In summary, the embodiments of this disclosure provide a variety of methods for obtaining a contact layer with a flat surface, which enables the subsequent material layer formed on the contact layer to also obtain high quality, and enables the contact surface between the two to also have high interface quality, thereby effectively reducing contact resistance and ultimately reducing the power consumption of the semiconductor structure.

[0176] In practice, the specific implementation method can be flexibly selected according to the specific situation, and no specific restrictions are imposed here.

[0177] In some embodiments, such as Figure 17 and Figure 18 As shown, after performing the third surface treatment process, the preparation method further includes:

[0178] A bit line material layer 14a is formed on the contact layer 12;

[0179] The bit line material layer 14a and the contact layer 12 are etched to form a bit line structure 14 located on the contact area.

[0180] Optionally, the bit line material layer 14a includes a metal material layer located on the contact layer 12. In some specific embodiments, the metal material layer may include, but is not limited to, at least one or a combination of tungsten, titanium, cobalt, other metal materials, etc.

[0181] In this embodiment, since the surface of the contact layer 12 has good flatness, the bit line 14 structure formed on it can obtain good quality, and a good contact surface can be formed between the contact layer 12 and the bit line 14, so as to effectively reduce the contact resistance between the two, thereby significantly reducing the power consumption of the semiconductor structure.

[0182] In summary, in the method provided in the embodiments of this disclosure, since the contact resistance between the contact layer and the contact area, as well as the contact resistance between the contact layer and the bit line, are effectively reduced, and the formed contact layer and bit line structures have high quality, the semiconductor structure can achieve better performance while reducing power consumption.

[0183] This disclosure also provides a semiconductor structure, such as... Figure 18 As shown, the semiconductor structure includes:

[0184] Substrate 10;

[0185] An isolation structure STI located in substrate 10 and an active region 11 defined by the isolation structure STI;

[0186] The groove (not shown in the figure) located on a portion of the active region 11, the portion of the active region 11 exposed by the groove (not shown in the figure) is defined as the contact region P;

[0187] A contact layer 12 is located on the contact area P, and the contact layer 12 and the contact area P have a flat contact surface;

[0188] Bit line 14, and a flat contact surface between bit line 14 and contact layer 12.

[0189] It is understood that the semiconductor structure can be fabricated using the methods described in any of the above embodiments.

[0190] In the structure provided in the embodiments of this disclosure, the contact resistance between the contact layer and the contact area, as well as the contact resistance between the contact layer and the bit line, are effectively reduced, and the contact layer and bit line structures have high quality, so that the semiconductor structure can achieve better performance while reducing power consumption.

[0191] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to any semiconductor structure or other semiconductor device including this structure, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor device belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0192] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an isolation structure and an active region defined by the isolation structure; A first etching process is performed on the substrate to form a groove that exposes the active region, the portion of the active region exposed by the groove being defined as a contact region; Perform a first surface treatment process to flatten the surface of the contact area; A first contact material layer is formed, the first contact material layer at least covering the sidewalls and bottom of the groove; A second etching process is performed to remove the portion of the first contact material layer located at the bottom of the groove, thereby exposing the contact area; A second surface treatment process is performed to flatten the surface of the contact area; A second contact material layer is formed, which at least covers the sidewalls of the first contact material layer and fills the groove.

2. The preparation method according to claim 1, characterized in that, At least one of the first surface treatment process and the second surface treatment process includes: The surface of the contact area is oxidized using a first wet process; The oxidized portion of the surface of the contact area is removed using a first dry process.

3. The preparation method according to claim 2, characterized in that, The reagents used in the first wet process include hydrogen peroxide solution.

4. The preparation method according to claim 1, characterized in that, At least one of the first surface treatment process and the second surface treatment process includes: The surface of the contact area is oxidized using a second wet process, and the oxidized portion of the surface of the contact area is removed. The residue from the second wet process is removed using a second dry process.

5. The preparation method according to claim 4, characterized in that, The reagents used in the second wet process include ozonated hydrofluoric acid solution.

6. The preparation method according to claim 1, characterized in that, At least one of the first surface treatment process and the second surface treatment process includes: The surface of the contact area is oxidized using a third dry process; The residue from the third dry process is removed by a cleaning process. The oxidized portion of the contact area surface is removed using the fourth dry process.

7. The preparation method according to claim 1, characterized in that, The first contact material layer and the second contact material layer are made of the same material, and the first contact material layer and the second contact material layer together form a contact material layer.

8. The preparation method according to claim 7, characterized in that, The material of the contact material layer includes polycrystalline semiconductor materials.

9. The preparation method according to claim 7, characterized in that, After forming the second contact material layer, the preparation method further includes: The contact material layer is thinned, and the thinned contact material layer is doped to obtain a contact layer. A third surface treatment process is performed to planarize the surface of the contact layer.

10. The preparation method according to claim 9, characterized in that, The doping process includes ion implantation and annealing.

11. The preparation method according to claim 9, characterized in that, The third surface treatment process includes: The surface of the contact layer is oxidized using a first wet process; The oxidized portion of the contact layer surface is removed using a first dry process.

12. The preparation method according to claim 9, characterized in that, The third surface treatment process includes: The surface of the contact layer is oxidized using a second wet process, and the oxidized portion of the surface of the contact layer is removed. The residue from the second wet process is removed using a second dry process.

13. The preparation method according to claim 9, characterized in that, The third surface treatment process includes: The surface of the contact layer is oxidized using a third dry process; The oxidized portion of the contact layer surface is removed using a fourth dry process.

14. The preparation method according to claim 9, characterized in that, After performing the third surface treatment process, the preparation method further includes: A bit line material layer is formed on the contact layer; The bit line material layer and the contact layer are etched to form a bit line structure located on the contact area.

15. The preparation method according to claim 14, characterized in that, The bit line material layer includes a metal material layer located on the contact layer.

16. The preparation method according to any one of claims 1-8, characterized in that, Perform a first etching process on the substrate, including: A mask material layer is formed on the substrate; Pattern the mask material layer to obtain the mask layer; Using the mask layer as a mask, the substrate is etched to form the groove.

17. A semiconductor structure, characterized in that, It is made by any one of claims 1-16.

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