Semiconductor device structure and method of forming

Abstract

Semiconductor device structures and methods of formation are disclosed. The present disclosure relates to integrated chip structures. An integrated chip structure includes a first die that predominantly has a first plurality of integrated chip devices coupled to a first plurality of interconnects over a first substrate. The first plurality of integrated chip devices is of a first type of integrated chip device. The integrated chip structure also includes a second die that predominantly has a second plurality of integrated chip devices coupled to a second plurality of interconnects over a second substrate. The second plurality of integrated chip devices is of a second type of integrated chip device that is different from the first type of integrated chip device. One or more inter-die connectors are between the first die and the second die and are configured to electrically couple the first die and the second die.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to the structure and method of forming semiconductor devices. Background Technology

[0002] The integrated circuit manufacturing industry frequently uses scaling to develop new products (such as new chips). Scaling is a process that reduces the minimum feature size on an integrated circuit or makes it smaller. By reducing the minimum feature size on an integrated circuit, the performance of individual devices on the integrated circuit can be improved (e.g., power consumption, speed, etc.). Summary of the Invention

[0003] According to the first aspect of this disclosure, An integrated chip structure includes: a first chiplet, the first chiplet dominantly including a first plurality of integrated chip devices coupled to a first plurality of interconnects on a first substrate, the first plurality of integrated chip devices being a first type of integrated chip device; a second chiplet, the second chiplet dominantly including a second plurality of integrated chip devices coupled to a second plurality of interconnects on a second substrate, the second plurality of integrated chip devices being a second type of integrated chip device different from the first type of integrated chip devices; one or more chiplet-to-chip connectors disposed between the first chiplet and the second chiplet and configured to electrically couple the first chiplet and the second chiplet; and wherein the first plurality of interconnects has a first minimum width, the first minimum width being different from a second minimum width of the second plurality of interconnects.

[0004] According to the second aspect of this disclosure, An integrated chip structure includes: a first chiplet, the first chiplet dominantly including an NMOS transistor disposed on or within a first substrate, wherein the NMOS transistor includes a first gate structure having a first gate length, the first gate structure being disposed between first source / drain regions having a first doping type; a second chiplet, the second chiplet dominantly including a PMOS transistor disposed on or within a second substrate, wherein the PMOS transistor includes a second gate structure having a second gate length different from the first gate length, the second gate structure being disposed between second source / drain regions having a second doping type different from the first doping type; and one or more chiplet connectors, the one or more chiplet connectors being disposed between the first chiplet and the second chiplet, wherein the one or more chiplet connectors are configured to electrically couple the NMOS transistor and the PMOS transistor.

[0005] According to the third aspect of this disclosure, the following is provided:A method for forming an integrated chip structure includes: processing a first substrate according to a first manufacturing process to form a first chiplet having a first plurality of devices, wherein the first plurality of devices are first type integrated chip devices; processing a second substrate according to a second manufacturing process to form a second chiplet having a second plurality of devices, wherein the second plurality of devices are second type integrated chip devices different from the first type integrated chip devices; and electrically coupling the first plurality of devices in the first chiplet to the second plurality of devices in the second chiplet via one or more interlayer connectors. Attached Figure Description

[0006] Various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 Three-dimensional views of some embodiments of an integrated chip structure comprising one or more chiplets, each of which is a single type of integrated chip device, are shown.

[0008] Figure 2 Cross-sectional views of some embodiments of an integrated chip structure are shown, which includes multiple small chips, each of which has a single type of integrated chip device.

[0009] Figure 3 Cross-sectional views of some additional embodiments of an integrated chip structure comprising multiple chiplets, each of which is a single type of device having a single type of contact etch stop layer strain.

[0010] Figure 4 Cross-sectional views of some additional embodiments of an integrated chip structure comprising multiple chiplets, each of which is a single type of device having a single type of sidewall spacer strain, are shown.

[0011] Figure 5 Cross-sectional views of some additional embodiments of an integrated chip structure comprising multiple chiplets, each of which is a single type of device comprising a single type of source / drain material, are shown.

[0012] Figure 6 Cross-sectional views of some additional embodiments of an integrated chip structure comprising multiple chiplets, each of which is a single type of device having a single type of transistor structure.

[0013] Figure 7Cross-sectional views of some additional embodiments of an integrated chip structure comprising multiple chiplets, each of which predominantly has a single type of device including a single channel orientation, are shown.

[0014] Figure 8 Cross-sectional views of some embodiments of an integrated chip structure comprising multiple chiplets, each of which predominantly has a single type of transistor device and one or more passive devices are shown.

[0015] Figures 9A-9B Some embodiments of power management circuits with different components associated with different chiplets are shown.

[0016] Figures 10A-10B Some alternative embodiments of power management circuits with different components associated with different chiplets are shown.

[0017] Figure 11 Cross-sectional views of some embodiments of a packaged integrated chip structure comprising multiple small chips, each of which has a single dominant type of integrated chip device are shown.

[0018] Figure 12A-16C Cross-sectional views of some embodiments of a method for forming an integrated chip structure comprising multiple small chips, each of which has a single type of integrated chip device dominantly.

[0019] Figure 17 Flowcharts of some embodiments of a method for forming an integrated chip structure comprising multiple small chips, each of which has a single dominant type of integrated chip device are shown. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0022] For decades, the semiconductor industry has made integrated circuits (ICs) faster and more power-efficient by reducing the size of features on ICs (e.g., gate length, interconnect width, etc.). Reducing the size of features on ICs is often referred to as semiconductor scaling. In industry, different manufacturing processes (e.g., technology nodes or process nodes) are used to produce integrated chips that include devices with different minimum feature sizes. For example, the gate length of a transistor in a 28-nanometer (nm) technology node is typically smaller than the gate length of a transistor in a 45-nanometer (nm) technology node. Generally, smaller technology nodes have smaller transistors, which is both faster and more power-efficient.

[0023] In recent years, as scaling has become more difficult, alternative manufacturing processes (e.g., using different strains and / or materials on the integrated chip) have been employed to enhance device performance. Because not all device types benefit equally from scaling and / or other manufacturing process enhancements, the overall performance of an IC is often optimized by attempting to balance manufacturing processes to meet the needs of multiple different device types (e.g., NMOS transistors, PMOS transistors, passive devices, etc.). However, because different device types are optimized through different manufacturing processes, the resulting IC may have suboptimal overall performance. For example, a manufacturing process that forms both NMOS and PMOS transistors on a single chip may optimize the operation of one type of device (e.g., NMOS transistors) without optimizing the performance of another type (e.g., PMOS transistors). Therefore, this manufacturing process balancing sacrifices the optimal performance of one or more device types within the integrated chip.

[0024] In some embodiments, this disclosure relates to an integrated chip structure configured to optimize the performance of different device types within an integrated chip structure. The integrated chip structure includes a plurality of chiplets formed using different manufacturing processes. The plurality of chiplets are coupled together via one or more chiplet interconnects. A respective chiplet among the plurality of chiplets predominantly includes a single type of device, which differs from the single type of devices of the remaining chiplets. For example, the integrated chip structure may include a first chiplet and a second chiplet, the first chiplet predominantly including a PMOS transistor formed using a first manufacturing process (e.g., a 65nm technology node process), and the second chiplet predominantly including an NMOS transistor formed using a second manufacturing process (e.g., a 45nm technology node process). By using different manufacturing processes to form different types of devices, it is possible to use manufacturing processes optimized for the performance of each type of device to form different types of devices separately, thereby mitigating the negative impact of manufacturing process balance between different device types (e.g., degrading integrated chip performance).

[0025] Figure 1 Three-dimensional views of some embodiments of an integrated chip structure 100 are shown. The integrated chip structure 100 includes a plurality of chiplets, each of which has a single type of integrated chip device.

[0026] The integrated chip structure 100 includes a plurality of chiplets 102-108. In some embodiments, the plurality of chiplets 102-108 may include a first chiplet 102, a second chiplet 104, a third chiplet 106, and a fourth chiplet 108. One or more of the plurality of chiplets 102-108 predominantly include a single type of integrated chip device (e.g., including more than 80% of the single type of integrated chip devices; including more than 90% of the single type of integrated chip devices; including more than 95% of the single type of integrated chip devices; including more than 99% of the single type of integrated chip devices; including approximately 100% of the single type of integrated chip devices; including only a single type of integrated chip device). In some embodiments, the single type of integrated chip device may be a single type of transistor device. In other embodiments, the single type of integrated chip device may be a passive device (e.g., a capacitor, resistor, or inductor, etc.) or a gate driver circuit, etc.

[0027] For example, in some embodiments, the first chiplet 102 may dominantly include a first plurality of integrated chip devices as a first type of integrated chip device (e.g., an NMOS transistor), and the second chiplet 104 may dominantly include a second plurality of integrated chip devices as a second type of integrated chip device (e.g., a PMOS transistor). In some embodiments, the first chiplet 102 may dominantly include the first type of integrated chip device and have no second type of device. In some embodiments, the first chiplet 102 may include only the first type of integrated chip device.

[0028] In some embodiments, the plurality of chiplets 102-108 may each comprise a single type of integrated chip device, wherein the single type of integrated chip device on each of the plurality of chiplets 102-108 is formed by different manufacturing processes. For example, in some embodiments, a first chiplet 102 may predominantly comprise an NMOS device formed by a first manufacturing process (which optimizes the performance of NMOS devices), a second chiplet 104 may predominantly comprise a PMOS device formed by a second manufacturing process (which optimizes the performance of PMOS devices), a third chiplet 106 may predominantly comprise passive devices (e.g., inductors, capacitors, or resistors) formed by a third manufacturing process (which optimizes the performance of passive devices), and a fourth chiplet 108 may predominantly comprise a transistor device defining one or more gate driver circuits formed by a fourth manufacturing process (which optimizes the performance of one or more gate driver circuits). In some embodiments, the different manufacturing processes may be different technology node processes. For example, in some embodiments, the first manufacturing process may include a first technology node process (e.g., a 7nm technology node process), the second manufacturing process may include a second technology node process (e.g., a 14nm technology node process), the third manufacturing process may include a third technology node process (e.g., a 65nm technology node process), and the fourth manufacturing process may include a fourth technology node process (e.g., a 45nm technology node process). In some alternative embodiments, the first technology node process may be the same as the second technology node process. In some alternative embodiments, the third technology node process may be the same as the fourth technology node process. In other embodiments, different manufacturing processes may provide different materials, different strains, or different channel orientations, etc., for the IC devices within each of the plurality of chiplets 102-108.

[0029] Different types of integrated chip devices within multiple chiplets 102-108 are coupled together via one or more chiplet connectors 110. The one or more chiplet connectors 110 are configured to allow different types of integrated chip devices to operate together to perform functions. In some embodiments, the one or more chiplet connectors 110 may include one or more of the following: redistribution layer (RDL), copper pillars, conductive bumps (e.g., microbumps), solder joints, copper-to-copper joints, copper-to-aluminum-copper joints, aluminum-copper-to-aluminum-copper joints, or through-substrate-via (TSV) joints, etc. In some embodiments, the multiple chiplets 102-108 may be stacked on top of each other in a multi-dimensional chip structure (e.g., a three-dimensional integrated chip (3D IC) structure). For example, in some embodiments, a second chiplet 104, a third chiplet 106, and a fourth chiplet 108 may be stacked on the upper surface of a first chiplet 102. In such embodiments, the first chiplet 102 may have a larger area than the second chiplet 104, the third chiplet 106, and the fourth chiplet 108.

[0030] By incorporating multiple small chips 102-108, each primarily comprising a single type of integrated chip device, different types of integrated chip devices can be formed using manufacturing processes optimized for the performance of each type. Forming different types of integrated chip devices through manufacturing processes optimized for the performance of each type avoids device degradation due to manufacturing process balancing and improves the overall performance of the integrated chip structure.

[0031] Figure 2 Cross-sectional views of some additional embodiments of an integrated chip structure 200 comprising multiple chiplets, each of which is predominantly a single type of integrated chip device are shown.

[0032] The integrated chip structure 200 includes a plurality of chips 102-108 coupled to each other via chiplet connectors 110. In some embodiments, the plurality of chips 102-108 may include a first chiplet 102, a second chiplet 104, a third chiplet 106, and a fourth chiplet 108. The plurality of chips 102-108 respectively dominantly include different types of integrated chip devices.

[0033] For example, in some embodiments, the first chiplet 102 may dominantly include a first plurality of transistor devices 212 as transistor devices of a first type. In some additional embodiments, the first chiplet 102 may include only transistor devices of the first type. The first plurality of transistor devices 212 each include a first gate structure 212g disposed between the first source / drain regions 212s. In some embodiments, the first type of transistor device is an NMOS transistor, such that the first plurality of transistor devices 212 are NMOS transistors. In such embodiments, the first source / drain regions 212s may include a first doping type (e.g., n-type doping), while the channel region extending below the first gate structure 212g and between the first source / drain regions 212s may include a second doping type (e.g., p-type doping). In some embodiments, the first gate structure 212g may have a first gate length 215.

[0034] In some embodiments, the first chiplet 102 may further include a first plurality of interconnects 206a disposed within a first interlayer dielectric (ILD) structure 204a on a first substrate 202a. In some embodiments, the first plurality of interconnects 206a may include conductive contacts, interconnect lines, and / or interconnect vias. In some embodiments, the first plurality of interconnects 206a may include a first conductive contact disposed on one of the first plurality of transistor devices 212 and having a first contact width 216. In some embodiments, the first plurality of interconnects 206a may be coupled to one or more front-side bonding structures 208 disposed on the first ILD structure 204a. In various embodiments, the one or more front-side bonding structures 208 may include a redistribution layer, bonding pad, or under-bump metallurgy (UBM) structure, etc. In some additional embodiments, the first plurality of interconnects 206a may also be coupled to one or more first back-side bonding structures 210a via a first through-substrate via (TSV) 214a. One or more first back-side bonding structures 210a are separated from the first ILD structure 204a by a first substrate 202a. In various embodiments, the first back-side bonding structure 210a may include a redistribution layer, bonding pads, or a UBM structure, etc. In some embodiments, one or more first back-side bonding structures 210a may be disposed on or within a first passivation structure 211a disposed on the first substrate 202a.

[0035] In some embodiments, the second chiplet 104 may include a second plurality of transistor devices 218, which are second-type transistor devices different from the first-type transistor devices. In some additional embodiments, the second chiplet 104 may include only second-type transistor devices. Each of the second plurality of transistor devices 218 includes a second gate structure 218g disposed between second source / drain regions 218s within the second substrate 202b. In some embodiments, the second-type transistor devices are PMOS transistors, and therefore the second plurality of transistor devices 218 are PMOS transistors. In such embodiments, the second source / drain regions 218s may include a second doping type (e.g., p-type doping), while the channel region extending below the second gate structure 218g and between the second source / drain regions 218s may include a first doping type (e.g., n-type doping). In some embodiments, the second gate structure 218g may include a second gate length 220 that is different from (e.g., greater than) the first gate length 215. In some embodiments, a second plurality of interconnects 206b are disposed within a second ILD structure 204b above the second substrate 202b. In some embodiments, the second plurality of interconnects 206b may include conductive contacts disposed on one of the second plurality of transistor devices 218 and having a second contact width 222. In some embodiments, the first plurality of interconnects 206a has a first minimum width (e.g., a first contact width 216), which is different from the second minimum width (e.g., the second contact width 222) of the second plurality of interconnects 206b. For example, in some embodiments, the second contact width 222 is greater than the first contact width 216. In some embodiments, the second plurality of interconnects 206b may be coupled to one or more second back-side bonding structures 210b via a second TSV 214b, which are disposed on and / or within a second passivation structure 211b on the back side of the second substrate 202b.

[0036] In some embodiments, the third chiplet 106 may dominantly include passive devices 224 (e.g., capacitors, inductors, or resistors) on and / or within the third substrate 202c. In some embodiments, the third chiplet 106 may not have transistor devices. For example, the third chiplet 106 may not have NMOS transistor devices or PMOS transistor devices. In some additional embodiments, the third chiplet 106 may include only passive devices 224. In some embodiments, the passive device 224 may include a capacitor having a first electrode separated from a second electrode by a capacitor dielectric structure. In other embodiments, the passive device 224 may include an inductor. In other embodiments, the passive device 224 may include a resistor. In some embodiments, a third plurality of interconnects 206c are disposed within a third ILD structure 204c on the third substrate 202c. The third plurality of interconnects 206c may include conductive contacts disposed on one of the passive devices 224 and having a third contact width 226 that is different from (e.g., greater than) the first contact width 216 and / or the second contact width 222. In some embodiments, the third plurality of interconnects 206c may be coupled to one or more third back-side bonding structures 210c located on and / or within a third passivation structure 211c disposed on the back side of the third substrate 202c.

[0037] In some embodiments, the fourth chiplet 108 may dominantly include a third plurality of transistor devices 228 defining one or more gate driver circuits. In some additional embodiments, the fourth chiplet 108 may include only transistor devices defining one or more gate driver circuits. In some embodiments, the third plurality of transistor devices 228 may include a third gate structure 228g between third source / drain regions 228s within the fourth substrate 202d. In some embodiments, the third gate structure 228g may include a third gate length 230 that is different from (e.g., greater than) a first gate length 214 and / or a second gate length 220. In some embodiments, a fourth plurality of interconnects 206d are disposed within a fourth ILD structure 204d on the fourth substrate 202d. In some embodiments, the fourth plurality of interconnects 206d may be coupled to one or more fourth back-side bonding structures 210d located on and / or within a fourth passivation structure 211d disposed on the back side of the fourth substrate 202d. The fourth plurality of interconnects 206d may include conductive contacts disposed on one of the third plurality of transistor devices 228 and having a fourth contact width 232 that is different from (e.g., greater than) the first contact width 216, the second contact width 222 and / or the third contact width 226.

[0038] Although Figure 2 An integrated chip structure 200 comprising different chiplets is illustrated, each chiplet having a dominant type of integrated chip device (e.g., NMOS device, PMOS device, etc.). However, it should be understood that in additional embodiments, the different types of integrated chip devices within each chiplet may have other dominant features and / or additional features. For example, different integrated chip devices within the same chiplet may have the same strain, gate orientation, and / or material, etc. Figure 3-7 Cross-sectional views of some additional embodiments of an integrated chip structure comprising multiple chiplets, each of which dominantly has a single type of integrated chip device containing the same features are shown.

[0039] Figure 3 Cross-sectional views of some embodiments of an integrated chip structure 300 comprising multiple chiplets, each of which is a single type of device having a single type of contact etch stop layer strain.

[0040] The integrated chip structure 300 includes a plurality of chiplets 102-108. In some embodiments, the plurality of chiplets 102-108 may include a first chiplet 102, a second chiplet 104, a third chiplet 106, and a fourth chiplet 108. In some embodiments, the first chiplet 102 may dominantly include a first plurality of transistor devices 212 (e.g., NMOS transistors), the second chiplet 104 may dominantly include a second plurality of transistor devices 218 (e.g., PMOS transistors), the third chiplet 106 may dominantly include one or more passive devices 224, and the fourth chiplet 108 may dominantly include a third plurality of transistor devices 228 configured to operate as one or more gate driver circuits.

[0041] The first plurality of transistor devices 212 may include a first gate structure 212g disposed on a first well region 302a within a first substrate 202a. In some embodiments, the first well region 302a may be disposed between one or more first isolation structures 304a, each of which includes one or more dielectric materials disposed within a trench in the first substrate 202a. The first gate structure 212g is disposed on the first substrate 202a and between first source / drain regions 212s. One or more first sidewall spacers 306a are disposed along opposite sides of the first gate structure 212g. A first contact etch stop layer (CESL) 308a is disposed on the first substrate 202a and along the sidewall of the first gate structure 212g. A first plurality of interconnects 206a are disposed within a first ILD structure 204a on the first CESL 308a. In some embodiments, the first CESL 308a includes a first type of strain. In some embodiments, the first type of strain may be tensile strain.

[0042] The second chiplet 104 may be a second gate structure 218g disposed on a second well region 302b disposed within a second substrate 202b. The second gate structure 218g is disposed on the second substrate 202b and between second source / drain regions 218s. One or more second sidewall spacers 306b are arranged along opposite sides of the second gate structure 218g. A second CESL 308b is disposed on the second substrate 202b and along the sidewall of the second gate structure 218g. A second plurality of interconnects 206b are disposed within a second ILD structure 204b on the second substrate 202b. In some embodiments, the second CESL 308b includes a second type of strain different from the first type of strain. In some embodiments, the second type of strain may include compressive strain.

[0043] Although NMOS and PMOS transistors are typically formed using the same CESL fabrication process for both NMOS and PMOS transistors, it should be understood that strained CESLs have different effects on different types of transistors. For example, a CESL with tensile strain can enhance the performance of NMOS transistors, while a CESL with compressive strain can enhance the performance of PMOS transistors. Therefore, by forming a first CESL 308a on the first plurality of transistor devices 212 and a second CESL 308b on the second plurality of transistor devices 218, it is possible to optimize device performance for both NMOS and PMOS transistors within the same integrated chip structure.

[0044] Figure 4 Cross-sectional views of some embodiments of an integrated chip structure 400 comprising multiple chiplets are shown, each chiplet having a single type of device including a single type of sidewall spacer strain.

[0045] The integrated chip structure 400 includes a plurality of chiplets 102-108. In some embodiments, the plurality of chiplets 102-108 may include a first chiplet 102 and a second chiplet 104, wherein the first chiplet 102 dominantly includes a first plurality of transistor devices 212, and the second chiplet 104 dominantly includes a second plurality of transistor devices 218.

[0046] A first plurality of transistor devices 212 may include a first gate structure 212g disposed on a first substrate 202a. One or more first sidewall spacers 306a are disposed along the opposite side of the first gate structure 212g. In some embodiments, the one or more first sidewall spacers 306a include a first type of strain. In some embodiments, the first type of strain may include tensile strain. A second plurality of transistor devices 218 may include a second gate structure 218g disposed on a second substrate 202b. One or more second sidewall spacers 306b are disposed along the opposite side of the second gate structure 218g. In some embodiments, the one or more second sidewall spacers 306b include a second type of strain different from the first type of strain. In some embodiments, the second type of strain may include compressive strain.

[0047] While NMOS and PMOS transistors are typically formed using a fabrication process that applies the same sidewall spacer strain to both, it has been recognized that strained sidewall spacers have different effects on different types of transistors. For example, sidewall spacers with tensile strain can enhance the performance of NMOS transistors, while sidewall spacers with compressive strain can enhance the performance of PMOS transistors. Therefore, by forming one or more first sidewall spacers 306a around the first plurality of transistor devices 212 and one or more second sidewall spacers 306b around the second plurality of transistor devices 218, it is possible to optimize device performance for both NMOS and PMOS transistors within the same integrated chip structure.

[0048] Figure 5 Cross-sectional views of some embodiments of an integrated chip structure 500 comprising multiple chiplets, each of which is a single type of device having a single type of source / drain strain.

[0049] The integrated chip structure 500 includes a plurality of chiplets 102-108. In some embodiments, the plurality of chiplets 102-108 may include a first chiplet 102 and a second chiplet 104, wherein the first chiplet 102 dominantly includes a first plurality of transistor devices 212, and the second chiplet 104 dominantly includes a second plurality of transistor devices 218.

[0050] The first plurality of transistor devices 212 may include a first gate structure 212g disposed on the first substrate 202a and between the first source / drain regions 212s. In some embodiments, the first source / drain regions 212s may include a first type of semiconductor material. For example, the first source / drain regions 212s may include silicon carbide. The second plurality of transistor devices 218 may include a second gate structure 218g disposed on the second substrate 202b and between the second source / drain regions 218s. In some embodiments, the second source / drain regions 218s may include a second type of semiconductor material different from the first type of semiconductor material. For example, the second source / drain regions 218s may include silicon germanium.

[0051] Figure 6 Cross-sectional views of some embodiments of an integrated chip structure 600 comprising multiple chiplets, each of which is a single type of device having a single type of transistor structure.

[0052] The integrated chip structure 600 includes a plurality of chiplets 102-108. In some embodiments, the plurality of chiplets 102-108 may include a first chiplet 102 and a second chiplet 104, wherein the first chiplet 102 dominantly includes a first plurality of transistor devices 212, and the second chiplet 104 dominantly includes a second plurality of transistor devices 218.

[0053] The first plurality of transistor devices 212 may have a first transistor structure. In some embodiments, the first transistor structure may include a FinFET structure. In such an embodiment, a first substrate 202a includes one or more fins 202f of semiconductor material extending outward from an upper surface of the first substrate 202a. An isolation structure 602 is arranged along the opposite side of the one or more fins 202f of semiconductor material. A first gate structure 212g surrounds the one or more fins of semiconductor material. Source / drain regions (not shown) are disposed on the opposite side of the fins 202f of semiconductor material such that the channel regions of the plurality of FinFET devices extend in-page or out-of-page. In other embodiments, the first type of transistor structure may include a gate-all-around (GAA) transistor structure, a nanosheet transistor structure, or a planar FET structure, etc.

[0054] The second plurality of transistor devices 218 may have a second transistor structure different from the first transistor structure. In some embodiments, the second transistor structure may include a planar FET structure. In such an embodiment, each of the plurality of planar transistor devices includes a second gate structure 218g disposed above the upper surface of the second substrate 202b and between second source / drain regions 218s within the upper surface of the second substrate 202b. In other embodiments, the second type of transistor structure may include a FinFET transistor structure, a gate all-around (GAA) transistor structure, or a nanosheet transistor structure, etc.

[0055] Figure 7 Cross-sectional views of some embodiments of an integrated chip structure 700 comprising multiple chiplets, each of which predominantly has a single type of device including a single channel orientation.

[0056] The integrated chip structure 700 includes a plurality of chiplets 102-108. In some embodiments, the plurality of chiplets 102-108 may include chiplet 102 and a second chiplet 104, wherein the first chiplet 102 dominantly includes a first plurality of transistor devices 212 and the second chiplet 104 dominantly includes a second plurality of transistor devices 218.

[0057] The first plurality of transistor devices 212 may include a first gate structure 212g disposed on a first substrate 202a. The first gate structure 212g is located between first source / drain regions 212s. A first channel region 212c is disposed below the first gate structure 212g and between the first source / drain regions 212s. In some embodiments, the upper surface of the first substrate 202a may face a first direction 702 (i.e., a line perpendicular to the upper surface of the first substrate 202a may extend in the first direction 702), and the first channel region 212c may extend along a second direction 704. For example, in some embodiments, the first direction 702 may be a

[100] direction (e.g., a direction perpendicular to the (100) crystal plane), and the second direction 704 may be along the (110) crystal plane.

[0058] The second plurality of transistor devices 218 may include a second gate structure 218g disposed on the second substrate 202b. The second gate structure 218g is located between the second source / drain regions 218s. A second channel region 218c is disposed below the second gate structure 218g and between the second source / drain regions 218s. In some embodiments, the upper surface of the second substrate 202b may face a third direction 706 (i.e., a line perpendicular to the upper surface of the second substrate 202b may extend along the third direction 706), and the second channel region 218c may extend along a fourth direction 708. For example, in some embodiments, the third direction 706 may be the

[110] direction (e.g., a direction perpendicular to the (110) crystal plane), and the fourth direction 708 may be along the (110) crystal plane.

[0059] Typically, NMOS and PMOS devices are fabricated on the same wafer. However, it has been recognized that the majority charge carriers of NMOS and PMOS devices differ, and these different majority charge carriers have different mobilities in different directions. For example, electrons have the highest mobility in the {100} crystal plane, while holes have the highest mobility in the {110} crystal plane. Therefore, by forming a first plurality of transistor devices 212 having a first channel region 212c along a first crystal plane (e.g., along the (100) crystal plane) and a second plurality of transistor devices 218 having a second channel region 218c along a second crystal plane (e.g., along the (110) crystal plane), it is possible to optimize the performance of both NMOS and PMOS transistors.

[0060] Figure 8 An alternative embodiment of an integrated chip structure 800 with one or more chiplets is shown, which predominantly comprise a single type of transistor device.

[0061] The integrated chip structure 800 includes a first chiplet 102, a second chiplet 104, and a third chiplet 106. The first chiplet 102 includes a first plurality of transistor devices 212 (dominantly NMOS devices). The second chiplet 104 includes a second plurality of transistor devices 218 (dominantly PMOS devices). The third chiplet 106 includes a third plurality of transistor devices 228 (dominantly defining one or more gate driver circuits).

[0062] In some embodiments, one or more of the first chiplet 102, the second chiplet 104, and the third chiplet 106 may further include one or more passive devices. For example, in some embodiments, the first chiplet 102 may dominantly include a first plurality of transistor devices 212 and one or more first passive devices 224a (e.g., one or more capacitors, inductors, etc.). In some additional embodiments, the second chiplet 104 may dominantly include a second plurality of transistor devices 218 and one or more second passive devices 224b (e.g., one or more inductors, capacitors, etc.). In some additional embodiments, the third chiplet 106 may dominantly include a third plurality of transistor devices 228 and one or more third passive devices 224c (e.g., one or more resistors, inductors, etc.). Because passive devices can be unaffected by some manufacturing process enhancements (e.g., different strains and / or materials), passive devices can be integrated into chiplets with a single type of transistor device without significantly affecting the performance of the passive devices.

[0063] Figure 9A Some embodiments of an exemplary schematic diagram of a power management circuit 900 are shown, which has different components associated with different chiplets.

[0064] Power management circuit 900 includes a buck converter with gate driver circuitry 902 coupled to a first gate G1 of high-side driver 904 and a second gate G2 of low-side driver 906. In some embodiments, high-side driver 904 includes a gate coupled to an input voltage (V). IN The high-side driver 904 has a PMOS transistor with a first source S1, and the low-side driver 906 may include an NMOS transistor with a second source S2 coupled to ground (GND). The first drain D1 of the high-side driver 904 is also coupled to the second drain D2 of the low-side driver 906 at a shared node. This shared node is also coupled to the output voltage (V) configured to be output. OUTThe resonant circuit includes an inductor 908 and a capacitor 910. During operation, the gate driver circuit 902 is configured to switch the high-side driver 904 and the low-side driver 906. The resonant circuit is configured to store energy and then dissipate the energy to generate an output voltage (V). OUT The output voltage (V) OUT ) has relative to the input voltage (V IN The reduced voltage value allows it to be used as a DC-DC converter.

[0065] In some embodiments, the gate driver circuit 902 may be disposed on the fourth chip 108, the high-side driver 904 may be disposed on the second chip 104, the low-side driver 906 may be disposed on the first chip 102, and the resonant circuit may be disposed on the third chip 106. Figure 9B Cross-sectional view 912 shows some embodiments of an integrated chip structure including chiplets, each of which includes... Figure 9A Components of a buck converter circuit.

[0066] Buck converters are typically formed on a single substrate using the same process and materials. However, by forming each buck converter circuit assembly on different chiplets, the performance of the buck converter circuit can be improved by optimizing the devices within each converter assembly. For example, in some embodiments, the buck converter circuit can be housed within the power management integrated circuit (PMIC) of a smartphone and configured to receive an input voltage V from a battery. IN (Having values ​​in the range of approximately 3.7V (volts) to approximately 5V), and the output voltage (V) OUT (Having values ​​in the range of approximately 3.7V to approximately 5V) the output is sent to the application processor (AP). In some such embodiments, the buck converter circuit can be configured to operate at frequencies between approximately 100kHz and approximately 10MHz and output a current in the range of approximately 0.5A to approximately 3A.

[0067] In other embodiments, the buck converter circuit may be located within the server's PMIC and configured to receive an input voltage V from the motherboard. IN (with values ​​in the range of approximately 5V to approximately 12V), and the output voltage (V) OUT (Having a value in the range of about 0.6V to about 1.2V) outputs to the central processing unit (CPU). In some such embodiments, the buck converter circuit can be configured to operate at a frequency between about 100kHz and about 10MHz and output a current in the range of about 20A to about 100A.

[0068] In some other embodiments, the buck converter circuit may be located within the smartphone wireless charging system and configured to receive the input voltage V from the wireless charging pad receiver. IN (with values ​​in the range of approximately 12V to approximately 20V), and the output voltage (V) OUT (Having a value in the range of about 3.7V to about 5V) outputs to the battery. In some such embodiments, the buck converter circuit can be configured to operate at a frequency between about 205kHz or about 6.78MHz and output a current in the range of about 0.5A to about 3A.

[0069] In other embodiments, other types of circuitry can also be formed from components disposed on different chiplets. For example, in some additional embodiments, the power management circuitry may include a boost converter circuit having components disposed on different chiplets. By disposing the components of the boost converter on different chiplets, the boost converter can achieve good performance. For example, in some embodiments, the disclosed boost converter circuitry may be disposed within the PMIC of a smartphone and configured to receive an input voltage V from the battery. IN (Having values ​​in the range of approximately 3.7V (volts) to approximately 5V), and the output voltage (V) OUT (Having a value in the range of about 6V to about 32V) the output is sent to the display circuit. In some such embodiments, the boost converter can be configured to operate at a frequency between about 10kHz and about 100kHz.

[0070] Figure 10A Some alternative embodiments of the power management circuit 1000 are shown, which has different components associated with different chiplets.

[0071] The power management circuit 1000 includes a buck converter comprising a gate driver circuit 902 coupled to a first gate G1 of a high-side driver 904 and a second gate G2 of a low-side driver 906. A resonant circuit is coupled to a first drain D1 of the high-side driver 904 and a second drain D2 of the low-side driver 906. The resonant circuit includes an inductor 908 and a capacitor 910.

[0072] In some embodiments, the gate driver circuit 902 may be disposed on the fourth chiplet 108, the high-side driver 904 may be disposed on the second chiplet 104, the low-side driver 906 may be disposed on the first chiplet 102, and the inductor 908 and the capacitor 910 may be disposed on one of the first chiplet 102, the second chiplet 104, and the third chiplet 106. For example, Figure 10BA cross-sectional view 1002 shows some embodiments of an integrated chip structure, which includes a first chiplet of an inductor 908 with an NMOS transistor having a high-side driver 904 and a resonant circuit, a second chiplet of a capacitor 910 with a PMOS transistor having a low-side driver and a resonant circuit, and a third chiplet 106 with a gate driver circuit 902.

[0073] It should be understood that the disclosed integrated chip structure can be packaged in a variety of package types. Figure 11 Cross-sectional views of some embodiments of an integrated chip structure 1100 are shown, which includes a plurality of small chips packaged in a CoWoS (Chip on Wafer) package.

[0074] The packaged integrated chip structure 1100 includes a plurality of chiplets 102-108 disposed on a carrier substrate 1102 (e.g., an interpolator substrate). Each of the plurality of chiplets 102-108 has a single dominant type of integrated chip device. In some embodiments, a molding compound 1104 is also disposed on the carrier substrate 1102 and surrounding the plurality of chiplets 102-108.

[0075] Multiple chiplets 102-108 are electrically coupled to a carrier substrate 1102 via multiple microbumps 1108. Multiple through-substrate vias (TSVs) 1110 extend through the carrier substrate 1102 and electrically couple the multiple microbumps 1108 to multiple solder bumps 1114. In some embodiments, one or more redistribution layers 1112a and / or 1112b may be disposed along the top and / or bottom of the carrier substrate 1102 to provide lateral wiring between the TSVs 1110 and the multiple microbumps 1108 and / or the multiple solder bumps 1114.

[0076] Figure 12A-16C Cross-sectional views 1200-1604 illustrate some embodiments of a method for forming an integrated chip structure comprising multiple small chips, each dominantly possessing a single type of integrated chip device. While the method is described... Figure 12A-16C However, it should be understood that Figure 12A-16C The structure disclosed herein is not limited to this method, but can be an independent structure.

[0077] like Figure 12A As shown in cross-sectional view 1200, a first substrate 202a is provided. In various embodiments, the first substrate 202a can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or associated epitaxial layer.

[0078] like Figure 12B As shown in cross-sectional view 1202, a plurality of first transistor devices 212 are formed within a first substrate 202a. Most of the devices within the first substrate 202a are the plurality of first transistor devices 212. In some embodiments, the plurality of first transistor devices 212 can be formed by forming a first gate structure 212g on the first substrate 202a. In some embodiments, the first gate structure 212g can be formed by depositing a first gate dielectric film and a first gate electrode film on the first substrate 202a. Subsequently, the first gate dielectric film and the first gate electrode film are patterned to form a first gate dielectric 212d and a first gate electrode 212e. In some embodiments, the first gate structure 212g can be formed to have a first gate length 214. A first source / drain region 212s is formed along the opposite side of the first gate structure 212g. In some embodiments, one or more first sidewall spacers 306a can be formed along the opposite side of the first gate structure 212g. In some embodiments, the one or more first sidewall spacers 306a can be formed to have a first type of strain (e.g., tensile strain).

[0079] In some embodiments, the first plurality of transistor devices 212 may include NMOS transistors. In some such embodiments, the first well region 302a may be implanted into the first substrate 202a before forming the first gate structure 212g on the first substrate 202a. In some embodiments, the first well region 302a may be formed by a first implantation process of implanting a dopant having a second doping type (e.g., p-type) (e.g., boron, aluminum, etc.) into the first substrate 202a. In some embodiments, a second implantation process may then be performed to implant a dopant having a first doping type (e.g., n-type) (e.g., phosphorus, arsenic, antimony, etc.) into the first well region 302a. In some alternative embodiments, the first plurality of transistor devices 212 may include epitaxial source / drain regions having a first semiconductor material formed within the first substrate 202a. In some embodiments, the first semiconductor material may include silicon carbide.

[0080] like Figure 12CAs shown in cross-sectional view 1204, a first CESL 308a is formed on a first substrate 202a and on a first plurality of transistor devices 212. The first CESL 308a may include a nitride (e.g., silicon nitride) or a carbide (e.g., silicon carbide). In some embodiments, the first CESL 308a may have a first type of strain (e.g., tensile strain). A first plurality of interconnects 206a may be formed within a first ILD structure 204a, which is formed on the first CESL 308a. In some embodiments, the first plurality of interconnects 206a may each be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming an ILD layer on the first substrate 202a, etching the ILD layer to form via holes and / or trenches, and filling the via holes and / or trenches with a conductive material. In some embodiments, the ILD layer can be deposited by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), etc.), and conductive materials (e.g., tungsten, copper, aluminum, etc.) can be formed by a deposition process and / or an electroplating process (e.g., electroplating, electroless plating, etc.).

[0081] like Figure 12D As shown in cross-sectional view 1206, the first substrate 202a can be thinned to reduce its thickness. In various embodiments, the first substrate 202a can be thinned by etching and / or mechanically grinding the back side of the first substrate 202a to reduce its thickness from a first thickness t1 to a second thickness t2. In some embodiments, the first thickness t1 can be in the range of about 700 μm to about 800 μm. In some embodiments, the second thickness t2 can be in the range of about 20 μm to about 80 μm.

[0082] like Figure 12EAs shown in cross-sectional view 1208, a first TSV 214a is formed extending through a first substrate 202a. In some embodiments, the first TSV 214a can be formed by performing a first etching process to pattern the first substrate 202a and form sidewalls of the first substrate 202a extending through the first substrate 202a and defining the first TSV opening. In some embodiments, the first TSV opening extends through a first CESL 308a and a first ILD structure 204a to expose one of a first plurality of interconnects 206a. A conductive material is formed within the TSV opening. The conductive material can be formed by a deposition process and / or an electroplating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material may include copper or aluminum, etc. After the conductive material is formed within the TSV opening, a planarization process can be performed to remove excess conductive material and define the first TSV 214a extending through the first substrate 202a.

[0083] A first back-side bonding structure 210a is formed along the back side of the first substrate 202a. The first back-side bonding structure 210a may be formed on and / or within a first passivation structure 211a formed along the back side of the first substrate 202a.

[0084] like Figure 12F As shown in cross-sectional view 1210, the first substrate 202a is singulated to form a plurality of first chips 102a-102b. In some embodiments, the first substrate 202a can be singulated by a dicing process that mounts the first substrate 202a onto the adhesive surface of a dicing tape 1212. Then, a wafer saw cuts the first substrate 202a along dicing lines 1214 to separate the first substrate 202a into a plurality of first chips 102-102b.

[0085] like Figure 13A As shown in cross-sectional view 1300, a second substrate 202b is provided. In various embodiments, the second substrate 202b can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or associated epitaxial layer.

[0086] like Figure 13BAs shown in cross-sectional view 1302, a second plurality of transistor devices 218 are formed within a second substrate 202b. The second plurality of transistor devices 218 may include most of the devices within the second substrate 202b. In some embodiments, the second plurality of transistor devices 218 may be formed by forming a second gate structure 218g on the second substrate 202b. In some embodiments, the second gate structure 218g may be formed by depositing a second gate dielectric film and a second gate electrode film on the second substrate 202b. Subsequently, the second gate dielectric film and the second gate electrode film are patterned to form a second gate dielectric 218d and a second gate electrode 218e. In some embodiments, the second gate structure 218g may be formed to have a second gate length 220 that is different from (e.g., greater than) the first gate length 214. Second source / drain regions 218s are formed along the opposite side of the second gate structure 218g. In some embodiments, the second source / drain regions 218s may include epitaxial source / drain regions having a second semiconductor material formed within the second substrate 202b. In some embodiments, the second semiconductor material may include silicon germanium. In some embodiments, one or more second sidewall spacers 306b may be formed along the opposite side of the second gate structure 218g. In some embodiments, the one or more second sidewall spacers 306b may be formed to have a connection with one or more first sidewall spacers ( Figure 12B The first type of strain (e.g., compressive strain) is different from the second type of strain (e.g., compressive strain) of 306a).

[0087] In some embodiments, the first plurality of transistor devices 212 may include PMOS transistors. In some such embodiments, a second well region 302b may be implanted into the second substrate 202b between one or more second isolation structures 304b before the second gate structure 218g is formed on the second substrate 202b. In some embodiments, the second well region 302b may be formed by a first implantation process that implants a dopant having a first doping type (e.g., n-type) (e.g., phosphorus, arsenic, antimony, etc.) into the second substrate 202b. In some embodiments, a second implantation process may subsequently be performed to implant a dopant having a second doping type (e.g., p-type) (e.g., boron, aluminum, etc.) into the second well region 302b. In some alternative embodiments, the second plurality of transistor devices 218 may include epitaxial source / drain regions having a second semiconductor material formed within the second substrate 202b. In some embodiments, the second semiconductor material may include silicon germanium.

[0088] It has been recognized that in the first substrate (e.g., Figure 12BForming an NMOS device on substrate 202a) and a PMOS device on substrate 202b can improve the power consumption and / or performance of the NMOS and PMOS devices. Furthermore, since the fabrication process for forming the NMOS and PMOS devices can be streamlined, the cost and cycle time of the fabrication process can also be improved. For example, forming NMOS and PMOS devices on the same substrate may require more masks than forming them on separate substrates.

[0089] like Figure 13C As shown in cross-sectional view 1304, a second CESL 308b is formed on a second substrate 202b and on a plurality of transistor devices 218. The second contact etch stop layer 308b may include a nitride (e.g., silicon nitride) or a carbide (e.g., silicon carbide). In some embodiments, the second CESL 308b may have a common characteristic with respect to the first CESL (…). Figure 12C The first type of strain (e.g., compressive strain) is different from the second type of strain (e.g., compressive strain). A second plurality of interconnects 206b may be formed within the second ILD structure 204b, which is formed on the second CESL 308b.

[0090] like Figure 13D As shown in cross-sectional view 1306, the second substrate 202b can be thinned to reduce its thickness. In various embodiments, the second substrate 202b can be thinned by etching and / or mechanically grinding the back side of the second substrate 202b to reduce its thickness (e.g., from a first thickness t1 in the range of about 700 μm to about 800 μm to a second thickness t2 in the range of about 20 μm to about 80 μm).

[0091] like Figure 13E As shown in cross-sectional view 1308, the second TSV 214b is formed to extend through the second substrate 202b. A second back-side bonding structure 210b is formed along the back side of the second substrate 202b. The second back-side bonding structure 210b may be formed on and / or within the second passivation structure 211b formed along the back side of the second substrate 202b.

[0092] like Figure 13F As shown in cross-sectional view 1310, the second substrate 202b is divided to form a plurality of second chiplets 104a-104b. In some embodiments, the second substrate 202b can be divided by a dicing process that mounts the second substrate 202b onto an adhesive surface of a dicing tape 1212. A wafer saw then cuts the second substrate 202b along dicing lines 1312 to separate the second substrate 202b into a plurality of second chiplets 104a-104b.

[0093] like Figure 14A As shown in cross-sectional view 1400, a third substrate 202c is provided. In various embodiments, the third substrate 202c can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or associated epitaxial layer.

[0094] like Figure 14B As shown in cross-sectional view 1402, a plurality of passive devices 224 are formed on and / or within a third substrate 202c. In some embodiments, the plurality of passive devices 224 may include a capacitor having a first conductive layer 225a, which is separated from a second conductive layer 225c by a capacitor dielectric layer 225b. In other embodiments, the plurality of passive devices 224 may include inductors or resistors, etc.

[0095] like Figure 14C As shown in cross-sectional view 1404, the third CESL 308c is formed on the third substrate 202c. A third plurality of interconnects 206c can be formed within the third ILD structure 204c, which is formed on the third CESL 308c.

[0096] like Figure 14D As shown in cross-sectional view 1406, the third substrate 202c can be thinned to reduce its thickness. In various embodiments, the third substrate 202c can be thinned by etching and / or mechanically grinding the back side of the third substrate 202c to reduce its thickness (e.g., from a first thickness t1 in the range of about 700 μm to about 800 μm to a second thickness t2 in the range of about 20 μm to about 80 μm).

[0097] like Figure 14E As shown in cross-sectional view 1408, the third TSV 214c is formed to extend through the third substrate 202c. A third back-side bonding structure 210c is formed along the back side of the third substrate 202c. The third back-side bonding structure 210c may be formed on and / or within the third passivation structure 211c formed along the back side of the third substrate 202c.

[0098] like Figure 14FAs shown in cross-sectional view 1410, the third substrate 202c is diced to form a plurality of third chiplets 106a-106b. In some embodiments, the third substrate 202c can be diced by a dicing process that mounts the third substrate 202c onto an adhesive surface of a dicing tape 1212. A wafer saw then cuts the third substrate 202c along dicing lines 1412 to separate the third substrate 202c into a plurality of third chiplets 106a-106b.

[0099] like Figure 15A As shown in cross-sectional view 1500, a fourth substrate 202d is provided. In various embodiments, the fourth substrate 202d can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or associated epitaxial layer.

[0100] like Figure 15B As shown in cross-sectional view 1502, a third plurality of transistor devices 228 are formed on and / or within a fourth substrate 202d. The third plurality of transistor devices 228 may include a majority of the devices within the fourth substrate 202d. In some embodiments, the third plurality of transistor devices 228 may define one or more gate driver circuits. In some embodiments, the third plurality of transistor devices 228 may be formed having a third gate structure having a third gate length 230 that is different from (e.g., greater than) a first gate length 214 and / or a second gate length 220. In some embodiments, the third gate structure 228g may include a third gate electrode 228e, which is separated from the fourth substrate 202d by a third gate dielectric 228d. In some embodiments, the third gate structure 228g may be formed over a third well region 302d between one or more third isolation structures 304d.

[0101] like Figure 15C As shown in cross-sectional view 1504, a fourth CESL 308d is formed on a fourth substrate 202d and over a third plurality of transistor devices 228. The fourth CESL 308d may include nitrides (e.g., silicon nitride) or carbides (e.g., silicon carbide). A fourth plurality of interconnects 206d may be formed within a fourth ILD structure 204d, which is formed on the fourth CESL 308d.

[0102] like Figure 15DAs shown in cross-sectional view 1506, the fourth substrate 202d can be thinned to reduce its thickness. In various embodiments, the fourth substrate 202d can be thinned by etching and / or mechanically grinding the back side to reduce its thickness (e.g., from a first thickness in the range of about 700 μm to about 800 μm to a second thickness in the range of about 20 μm to about 80 μm).

[0103] like Figure 15E As shown in cross-sectional view 1508, the fourth TSV 214d is formed extending through the fourth substrate 202d. A fourth back-side bonding structure 210d is formed along the back side of the fourth substrate 202d. The fourth back-side bonding structure 210d may be formed on and / or within the fourth passivation structure 211d formed along the back side of the fourth substrate 202d.

[0104] like Figure 15F As shown in cross-sectional view 1510, the fourth substrate 202d is diced to form a plurality of fourth chiplets 108a-108b. In some embodiments, the fourth substrate 202d can be divided by a dicing process that mounts the fourth substrate 202d onto the adhesive surface of a dicing tape 1212. Then, a wafer saw cuts the fourth substrate 202d along the dicing line 1512 to separate the fourth substrate 202d into a plurality of fourth chiplets 108a-108b.

[0105] like Figure 16A As shown in cross-sectional view 1600, a first chip 102a of a plurality of first chips 102a-102b is coupled to a second chip 104a of a plurality of second chips 104a-104b. In some embodiments, the first chip 102a can be coupled to the second chip 104a via a first chip-to-chip connector 110a. In some embodiments, the first chip-to-chip connector 110a may include solder bumps, copper pillars, microbumps (having a width in the range of about 5 μm to about 30 μm), or other suitable bump structures.

[0106] like Figure 16B As shown in cross-sectional view 1602, a third chip 106a of a plurality of third chips 106a-106b is coupled to a first chip 102a. In some embodiments, the third chip 106a may be coupled to the first chip 102a via a second chip-to-chip connector 110b. In some embodiments, the second chip-to-chip connector 110b may include solder bumps, copper pillars, microbumps (having a width in the range of about 5 μm to about 30 μm), or other suitable bump structures.

[0107] like Figure 16CAs shown in cross-sectional view 1604, a fourth chip 108a of a plurality of fourth chips 108a-108b is coupled to a first chip 102a. In some embodiments, the fourth chip 108a may be coupled to the first chip 102a via a third chip-to-chip connector 110c. In some embodiments, the third chip-to-chip connector 110c may include solder bumps, copper pillars, microbumps (having a width ranging from about 5 μm to about 30 μm), or other applicable bump structures.

[0108] Figure 17 Flowcharts of some embodiments of a method 1700 for forming an integrated chip structure comprising multiple chiplets, each of which has a single type of integrated chip device dominantly.

[0109] Although the disclosed method 1700 is shown and described herein as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the shown actions are required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0110] At action 1702, the first substrate may be processed according to a first manufacturing process to form a first chiplet dominantly having a first plurality of devices, wherein the first plurality of devices are first type integrated chip devices. In some embodiments, the first type integrated chip device may be an NMOS transistor. In some embodiments, the first manufacturing process may be a manufacturing process associated with a first technology node (e.g., a 7nm technology node). In some embodiments, the first manufacturing process may be performed according to actions 1704-1706.

[0111] At action 1704, the first semiconductor wafer can be processed according to the first manufacturing process to form the first plurality of devices. Figures 12A-12E Cross-sectional views 1200-1208 are shown for some embodiments corresponding to action 1704.

[0112] At action 1706, the first semiconductor wafer can be separated into a first plurality of chips, including a first chiplet. Figure 12F A cross-sectional view 1210 is shown, corresponding to some embodiments of action 1706.

[0113] At action 1708, the second substrate may be processed according to a second manufacturing process to form a second chiplet that predominantly has a second plurality of devices, wherein the second plurality of devices are second type integrated chip devices. In some embodiments, the second type integrated chip device may be a PMOS transistor. In some embodiments, the second manufacturing process may be a manufacturing process associated with a second technology node (e.g., a 14nm technology node). Figures 13A-13F Cross-sectional views 1300-1310 are shown for some embodiments corresponding to action 1708.

[0114] At action 1710, in some embodiments, a third substrate may be processed according to a third manufacturing process to form a third chiplet that predominantly has a third plurality of devices, wherein the third plurality of devices are third type integrated chip devices. In some embodiments, the third type integrated chip device may be a passive device (e.g., a capacitor, inductor, or resistor). In some embodiments, the third manufacturing process may be a manufacturing process associated with a third technology node (e.g., a 45nm technology node). Figure 14A-14F Cross-sectional views 1400-1410 are shown for some embodiments corresponding to action 1710.

[0115] In action 1712, in some embodiments, a fourth substrate may be processed according to a fourth manufacturing process to form a fourth chiplet that predominantly has a fourth plurality of devices, wherein the fourth plurality of devices are fourth type integrated chip devices. In some embodiments, the fourth type integrated chip device may be a gate driver circuit. In some embodiments, the fourth manufacturing process may be a manufacturing process associated with a fourth technology node (e.g., a 32nm technology node). Figure 15A-15F Cross-sectional views 1500-1510 are shown for some embodiments corresponding to action 1712.

[0116] In action 1714, the first chiplet, the second chiplet, the third chiplet, and the fourth chiplet are coupled together through one or more chiplet connectors to form an integrated chip structure. Figures 16A-16C Cross-sectional views 1600-1604 are shown for some embodiments corresponding to action 1714.

[0117] Therefore, in some embodiments, this disclosure relates to an integrated chip structure comprising a plurality of chiplets, each and dominantly comprising different types of integrated chip devices.

[0118] In some embodiments, this disclosure relates to an integrated chip structure. The integrated chip structure includes: a first chiplet, the first chiplet dominantly including a first plurality of integrated chip devices coupled to a first plurality of interconnects on a first substrate, the first plurality of integrated chip devices being a first type of integrated chip device; a second chiplet, the second chiplet dominantly including a second plurality of integrated chip devices coupled to a second plurality of interconnects on a second substrate, the second plurality of integrated chip devices being a second type of integrated chip device different from the first type of integrated chip device; one or more chiplet-to-chip connectors disposed between the first chiplet and the second chiplet and configured to electrically couple the first chiplet and the second chiplet; and wherein the first plurality of interconnects has a first minimum width, the first minimum width being different from a second minimum width of the second plurality of interconnects. In some embodiments, the first chiplet includes only the first type of integrated chip device. In some embodiments, the first chiplet does not include the second type of integrated chip device. In some embodiments, the first type of integrated chip device is an NMOS transistor, and the second type of integrated chip device is a PMOS transistor. In some embodiments, the NMOS transistor includes a first gate structure having a first gate length, and the PMOS transistor includes a second gate structure having a second gate length different from the first gate length. In some embodiments, the first plurality of interconnects includes a first conductive contact having the first minimum width, and the second plurality of interconnects includes a second conductive contact having a second minimum width different from the first minimum width. In some embodiments, the integrated chip structure further includes: a third chiplet, the third chiplet dominantly including a third plurality of integrated chip devices, the third plurality of integrated chip devices being a third type of integrated chip device different from the first type of integrated chip device and the second type of integrated chip device; and a fourth chiplet, the fourth chiplet dominantly including a fourth plurality of integrated chip devices, the fourth plurality of integrated chip devices being a fourth type of integrated chip device different from the first type of integrated chip device, the second type of integrated chip device, and the third type of integrated chip device. In some embodiments, the third chiplet does not have transistor devices. In some embodiments, the third type of integrated chip device is a passive device, and the fourth type of integrated chip device is a gate driver circuit.

[0119] In other embodiments, this disclosure relates to an integrated chip structure. The integrated chip structure includes: a first chiplet, the first chiplet dominantly including an NMOS transistor disposed on or within a first substrate, wherein the NMOS transistor includes a first gate structure having a first gate length, the first gate structure being disposed between first source / drain regions having a first doping type; a second chiplet, the second chiplet dominantly including a PMOS transistor disposed on or within a second substrate, the PMOS transistor including a second gate structure having a second gate length different from the first gate length, the second gate structure being disposed between second source / drain regions having a second doping type different from the first doping type; and one or more chiplet connectors arranged between the first chiplet and the second chiplet, wherein the one or more chiplet connectors are configured to electrically couple the NMOS transistor and the PMOS transistor. In some embodiments, the integrated chip structure further includes: a first plurality of conductive contacts, the first plurality of conductive contacts being in contact with the NMOS transistor entity and having a bottom surface of a first width; and a second plurality of conductive contacts, the second plurality of conductive contacts being in contact with the PMOS transistor entity and having a bottom surface of a second width, the second width being different from the first width. In some embodiments, the second gate length is greater than the first gate length. In some embodiments, the integrated chip structure further includes: a third chiplet, the third chiplet dominantly comprising passive devices disposed on or within a third substrate; and a fourth chiplet, the fourth chiplet dominantly comprising one or more gate driver circuits disposed on or within a fourth substrate. In some embodiments, the first chiplet is larger than the second chiplet, the third chiplet, and the fourth chiplet. In some embodiments, the second chiplet, the third chiplet, and the fourth chiplet are disposed on the upper surface of the first chiplet. In some embodiments, the integrated chip structure further includes: a first contact etch stop layer, the first contact etch stop layer being disposed on the first substrate and having a first type of strain; and a second contact etch stop layer, the second contact etch stop layer being disposed on the second substrate and having a second type of strain different from the first type of strain. In some embodiments, the integrated chip structure further includes: a first sidewall spacer disposed along the opposite side of the first gate structure and having a first type of strain; and a second sidewall spacer disposed along the opposite side of the second gate structure and having a second type of strain different from the first type of strain.In some embodiments, a first channel region extending below the first gate structure extends along a first crystal plane in a first direction; and a second channel region extending below the first gate structure extends along a second crystal plane in a second direction, the second direction being different from the first direction.

[0120] In other embodiments, this disclosure relates to a method for forming an integrated chip structure. The method includes: processing a first substrate according to a first manufacturing process to form a first chiplet dominantly having a first plurality of devices, wherein the first plurality of devices are first type integrated chip devices; processing a second substrate according to a second manufacturing process to form a second chiplet dominantly having a second plurality of devices, wherein the second plurality of devices are second type integrated chip devices different from the first type integrated chip devices; and electrically coupling the first plurality of devices in the first chiplet to the second plurality of devices in the second chiplet via one or more interlayer connectors. In some embodiments, the first type integrated chip device is an NMOS transistor; and the second type integrated chip device is a PMOS transistor.

[0121] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of this disclosure.

[0122] Example

[0123] Example 1. An integrated chip structure comprising: a first chiplet, the first chiplet dominantly including a first plurality of integrated chip devices coupled to a first plurality of interconnects on a first substrate, the first plurality of integrated chip devices being a first type of integrated chip device; a second chiplet, the second chiplet dominantly including a second plurality of integrated chip devices coupled to a second plurality of interconnects on a second substrate, the second plurality of integrated chip devices being a second type of integrated chip device different from the first type of integrated chip device; one or more chiplet-to-chip connectors disposed between the first chiplet and the second chiplet and configured to electrically couple the first chiplet and the second chiplet; and wherein the first plurality of interconnects has a first minimum width, the first minimum width being different from a second minimum width of the second plurality of interconnects.

[0124] Example 2. The integrated chip structure according to Example 1, wherein the first chiplet comprises only the first type of integrated chip device.

[0125] Example 3. The integrated chip structure according to Example 1, wherein the first chiplet does not have the second type of integrated chip device.

[0126] Example 4. The integrated chip structure according to Example 1, wherein the first type of integrated chip device is an NMOS transistor; and wherein the second type of integrated chip device is a PMOS transistor.

[0127] Example 5. The integrated chip structure according to Example 4, wherein the NMOS transistor includes a first gate structure having a first gate length, and the PMOS transistor includes a second gate structure having a second gate length different from the first gate length.

[0128] Example 6. The integrated chip structure according to Example 1, wherein the first plurality of interconnects includes a first conductive contact having the first minimum width, and the second plurality of interconnects includes a second conductive contact having a second minimum width different from the first minimum width.

[0129] Example 7. The integrated chip structure according to Example 1 further includes: a third chiplet, the third chiplet dominantly comprising a third plurality of integrated chip devices, the third plurality of integrated chip devices being a third type of integrated chip device different from the first type of integrated chip device and the second type of integrated chip device; and a fourth chiplet, the fourth chiplet dominantly comprising a fourth plurality of integrated chip devices, the fourth plurality of integrated chip devices being a fourth type of integrated chip device different from the first type of integrated chip device, the second type of integrated chip device and the third type of integrated chip device.

[0130] Example 8. The integrated chip structure according to Example 7, wherein the third chiplet has no transistor devices.

[0131] Example 9. The integrated chip structure according to Example 8, wherein the third type of integrated chip device is a passive device; and wherein the fourth type of integrated chip device is a gate driver circuit.

[0132] Example 10. An integrated chip structure comprising: a first chiplet, the first chiplet dominantly including an NMOS transistor disposed on or within a first substrate, wherein the NMOS transistor includes a first gate structure having a first gate length, the first gate structure being disposed between first source / drain regions having a first doping type; a second chiplet, the second chiplet dominantly including a PMOS transistor disposed on or within a second substrate, wherein the PMOS transistor includes a second gate structure having a second gate length different from the first gate length, the second gate structure being disposed between second source / drain regions having a second doping type different from the first doping type; and one or more chiplet connectors disposed between the first chiplet and the second chiplet, wherein the one or more chiplet connectors are configured to electrically couple the NMOS transistor and the PMOS transistor.

[0133] Example 11. The integrated chip structure according to Example 10 further includes: a first plurality of conductive contacts, the first plurality of conductive contacts being in contact with the NMOS transistor entity and having a bottom surface with a first width; and a second plurality of conductive contacts, the second plurality of conductive contacts being in contact with the PMOS transistor entity and having a bottom surface with a second width, the second width being different from the first width.

[0134] Example 12. The integrated chip structure according to Example 10, wherein the second gate length is greater than the first gate length.

[0135] Example 13. The integrated chip structure according to Example 10 further includes: a third chiplet, the third chiplet dominantly comprising passive devices disposed on or within a third substrate; and a fourth chiplet, the fourth chiplet dominantly comprising one or more gate driver circuits disposed on or within a fourth substrate.

[0136] Example 14. The integrated chip structure according to Example 13, wherein the first chiplet is larger than the second chiplet, the third chiplet, and the fourth chiplet.

[0137] Example 15. The integrated chip structure according to Example 13, wherein the second chiplet, the third chiplet, and the fourth chiplet are disposed on the upper surface of the first chiplet.

[0138] Example 16. The integrated chip structure according to Example 10 further includes: a first contact etch stop layer disposed on the first substrate and having a first type of strain; and a second contact etch stop layer disposed on the second substrate and having a second type of strain different from the first type of strain.

[0139] Example 17. The integrated chip structure according to Example 10 further includes: a first sidewall spacer disposed along the opposite side of the first gate structure and having a first type of strain; and a second sidewall spacer disposed along the opposite side of the second gate structure and having a second type of strain different from the first type of strain.

[0140] Example 18. An integrated chip structure according to Example 10, wherein a first channel region extending below the first gate structure extends along a first crystal plane in a first direction; and wherein a second channel region extending below the first gate structure extends along a second crystal plane in a second direction, the second direction being different from the first direction.

[0141] Example 19. A method of forming an integrated chip structure, comprising: processing a first substrate according to a first manufacturing process to form a first chiplet having a first plurality of devices, wherein the first plurality of devices are first type integrated chip devices; processing a second substrate according to a second manufacturing process to form a second chiplet having a second plurality of devices, wherein the second plurality of devices are second type integrated chip devices different from the first type integrated chip devices; and electrically coupling the first plurality of devices in the first chiplet to the second plurality of devices in the second chiplet via one or more interlayer connectors.

[0142] Example 20. The method according to Example 19, wherein the first type of integrated chip device is an NMOS transistor; and wherein the second type of integrated chip device is a PMOS transistor.

Claims

1. An integrated chip structure, comprising: The first chiplet, which predominantly includes a first plurality of integrated chip devices coupled to a first plurality of interconnects on a first substrate, wherein the first plurality of integrated chip devices are a first type of integrated chip devices. The second chiplet, which predominantly includes a second plurality of interconnected integrated chip devices coupled to a second substrate, the second plurality of interconnected integrated chip devices being a second type of integrated chip devices different from the first type of integrated chip devices; One or more chiplet connectors are disposed between the first chiplet and the second chiplet and are configured to electrically couple the first chiplet and the second chiplet; and The first plurality of interconnects has a first minimum width, which is different from the second minimum width of the second plurality of interconnects.

2. The integrated chip structure according to claim 1, wherein, The first small chip includes only the first type of integrated chip device.

3. The integrated chip structure according to claim 1, wherein, The first chip does not have the second type of integrated chip device.

4. The integrated chip structure according to claim 1, in, The first type of integrated chip device is an NMOS transistor; and The second type of integrated chip device is a PMOS transistor.

5. The integrated chip structure according to claim 4, wherein, The NMOS transistor includes a first gate structure having a first gate length, and the PMOS transistor includes a second gate structure having a second gate length different from the first gate length.

6. The integrated chip structure according to claim 1, wherein, The first plurality of interconnects includes a first conductive contact having the first minimum width, and the second plurality of interconnects includes a second conductive contact having a second minimum width different from the first minimum width.

7. The integrated chip structure according to claim 1, further comprising: The third small chip, which predominantly includes a third plurality of integrated chip devices, is a third type of integrated chip device that is different from the first type of integrated chip device and the second type of integrated chip device; as well as The fourth small chip, which predominantly includes a fourth plurality of integrated chip devices, is a fourth type of integrated chip device that is different from the first type of integrated chip device, the second type of integrated chip device and the third type of integrated chip device.

8. The integrated chip structure according to claim 7, wherein, The third small chip does not contain transistors.

9. The integrated chip structure according to claim 8, in, The third type of integrated chip device is a passive device; and The fourth type of integrated chip device is a gate driver circuit.

10. An integrated chip structure, comprising: A first chiplet, the first chiplet dominantly comprising an NMOS transistor disposed on or within a first substrate, wherein the NMOS transistor comprises a first gate structure having a first gate length, the first gate structure being disposed between first source / drain regions having a first doping type; The second chiplet, which predominantly includes a PMOS transistor disposed on or within a second substrate, wherein the PMOS transistor includes a second gate structure having a second gate length different from the first gate length, the second gate structure being disposed between second source / drain regions having a second doping type different from the first doping type; One or more chiplet connectors are disposed between the first chiplet and the second chiplet, wherein the one or more chiplet connectors are configured to electrically couple the NMOS transistor and the PMOS transistor; First plurality of conductive contacts, the first plurality of conductive contacts being in contact with the NMOS transistor body and having a bottom surface of a first width; and A second plurality of conductive contacts are in contact with the PMOS transistor body and have a bottom surface of a second width, which is different from the first width.

11. The integrated chip structure according to claim 10, wherein, The second gate length is greater than the first gate length.

12. The integrated chip structure according to claim 10, further comprising: The third chip, which predominantly includes passive devices disposed on or within a third substrate; as well as The fourth chiplet dominantly includes one or more gate driver circuits disposed on or within a fourth substrate.

13. The integrated chip structure according to claim 12, wherein, The first small chip is larger than the second small chip, the third small chip, and the fourth small chip.

14. The integrated chip structure according to claim 12, wherein, The second, third, and fourth small chips are disposed on the upper surface of the first small chip.

15. The integrated chip structure according to claim 10, further comprising: A first contact etch stop layer is disposed on the first substrate and has a first type of strain; as well as A second contact etch stop layer is disposed on the second substrate and has a second type of strain different from the first type of strain.

16. The integrated chip structure according to claim 10, further comprising: A first sidewall spacer is disposed along the opposite side of the first gate structure and has a first type of strain; as well as A second sidewall spacer is disposed along the opposite side of the second gate structure and has a second type of strain different from the first type of strain.

17. The integrated chip structure according to claim 10, in, A first channel region extending below the first gate structure extends along a first crystal plane in a first direction; and The second channel region extending below the first gate structure extends along the second crystal plane in a second direction, which is different from the first direction.

18. A method for forming an integrated chip structure, comprising: The first substrate is processed according to a first manufacturing process to form a first chiplet having a first plurality of devices, wherein the first plurality of devices are first type integrated chip devices of a first plurality of interconnects coupled to the first substrate. The second substrate is processed according to a second manufacturing process to form a second chiplet that predominantly has a second plurality of devices, wherein the second plurality of devices are a second plurality of interconnected second type integrated chip devices, different from the first type of integrated chip devices, coupled onto the second substrate; and A first plurality of devices within the first chiplet are electrically coupled to a second plurality of devices within the second chiplet via one or more interlayer connectors. The first plurality of interconnects has a first minimum width, which is different from the second minimum width of the second plurality of interconnects.

19. The method according to claim 18, in, The first type of integrated chip device is an NMOS transistor; and The second type of integrated chip device is a PMOS transistor.

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