Semiconductor structure and method of forming the same

Abstract

The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a substrate, the substrate comprising an active region; forming a word line in the substrate, the word line comprising a first part and a second part at the end of the first part, the second part protruding from the first part in a direction perpendicular to the substrate; forming a dielectric layer covering the substrate; etching the dielectric layer and part of the substrate to form a first contact hole exposing the second part and a second contact hole exposing the active region simultaneously. When forming the first contact hole exposing the word line, the present application can reduce etching time and improve etching efficiency, and can avoid the etching depth of the second contact hole exposing the active region being too large, reduce damage to the inside of the active region, and reduce the leakage current inside the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in computers and other electronic devices. The active region, peripheral gate region, bit lines, and word lines in DRAM all need to be electrically connected to the peripheral circuit (PC) via contact plugs to conduct electrical signals from the peripheral circuit to the active region, peripheral gate region, bit lines, and word lines. To simplify the manufacturing process, the active region, peripheral gate region, bit lines, and word lines are typically etched simultaneously to form contact holes for connection to the peripheral circuit in each region. Therefore, when the etching of the contact holes connecting the word lines to the peripheral circuit is completed, the etching depth of the contact holes connecting the active region and the peripheral circuit increases, leading to an increase in leakage current. It also increases the etching depth of the contact holes connecting the bit lines to the peripheral circuit, causing penetration of the oxide layer beneath the bit lines, affecting the electrical isolation performance of the oxide layer, and increasing the RC (resistance-capacitance) delay effect.

[0003] Therefore, how to reduce the damage to the active region and bit lines when forming contact holes for connecting word lines to peripheral circuits, improve the yield of semiconductor structures, and improve the electrical performance of semiconductor structures are technical problems that urgently need to be solved. Summary of the Invention

[0004] This invention provides a semiconductor structure and its formation method to solve the problem that existing technologies easily damage other areas when forming contact holes for connecting word lines and peripheral circuits, thereby improving the electrical performance of the semiconductor structure and increasing its yield.

[0005] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:

[0006] A substrate is provided, wherein the substrate includes an active region;

[0007] A word line is formed within the substrate, the word line comprising a first portion and a second portion located at the end of the first portion, the second portion protruding from the first portion in a direction perpendicular to the substrate;

[0008] A dielectric layer is formed covering the substrate;

[0009] The dielectric layer and a portion of the substrate are etched to form a first contact hole exposing the second portion, and simultaneously to form a second contact hole exposing the active region.

[0010] Optionally, the substrate includes a storage region and a peripheral region located outside the storage region, and the active region is located within the substrate of the storage region; the specific steps of forming word lines within the substrate include:

[0011] The substrate is etched to form a groove that penetrates the storage region and extends to the peripheral region in a direction parallel to the substrate;

[0012] The groove is filled with conductive material to form the first portion located in the storage area and the second portion located in the peripheral area.

[0013] Optionally, the specific steps for forming the first portion located in the storage area and the second portion located in the peripheral area include:

[0014] A first conductive material is deposited in the groove and on the surface of the substrate to form a conductive layer covering the storage area and the peripheral area;

[0015] The conductive layer is etched to form the first portion and the second portion.

[0016] Optionally, the specific steps for etching the conductive layer include:

[0017] A shielding layer is formed, which covers the surface of the conductive layer located in the peripheral region;

[0018] Remove the conductive layer on the substrate surface located in the storage region, and use the conductive layer remaining in the storage region as the initial first part and the conductive layer remaining in the peripheral region as the initial second part;

[0019] The initial first portion and the initial second portion are partially etched back, with the initial first portion remaining in the groove of the storage area as the first portion and the initial second portion remaining in the groove of the peripheral area as the second portion.

[0020] Optionally, before depositing the first conductive material in the groove and on the substrate surface, the following steps are further included:

[0021] A diffusion barrier layer is formed on the inner wall of the groove.

[0022] Optionally, the peripheral region is distributed around the outer periphery of the storage region; the specific steps for forming a shielding layer covering the conductive layer located in the peripheral region include:

[0023] Photoresist material is deposited in the peripheral region to form the shielding layer, which covers the conductive layer located in the peripheral region and exposes the conductive layer located in the storage region.

[0024] Optionally, before forming the dielectric layer covering the substrate, the following steps are further included:

[0025] Bit lines are formed on the substrate.

[0026] Optionally, the specific steps for forming the dielectric layer covering the substrate include:

[0027] A dielectric material is deposited on the substrate to form a dielectric layer covering the substrate surface and the bit lines.

[0028] Optionally, the specific steps of forming a first contact hole exposing the second portion and simultaneously forming a second contact hole exposing the active region include:

[0029] The dielectric layer and the substrate are etched to form a first contact hole exposing the second portion, a second contact hole exposing the active region, and a third contact hole exposing the bit line.

[0030] Optionally, the bit line extends from the storage region to the peripheral region;

[0031] The third contact hole exposes the bit line located in the peripheral region.

[0032] Optionally, the following steps may also be included:

[0033] A second conductive material is filled into the first contact hole, the second contact hole, and the third contact hole, thereby forming a first contact plug that contacts the second portion, a second contact plug that contacts the active region, and a third contact plug that contacts the bit line.

[0034] Optionally, the following steps may also be included:

[0035] A first peripheral circuit electrically connected to the first contact plug, a second peripheral circuit electrically connected to the second contact plug, and a third peripheral circuit electrically connected to the third contact plug are formed.

[0036] Optionally, the thickness ratio of the second part to the thickness of the first part is (7:4) to (7:6).

[0037] To address the above problems, the present invention also provides a semiconductor structure, comprising:

[0038] A substrate having an active region therein;

[0039] A word line, located within the substrate, the word line comprising a first portion and a second portion located at the end of the first portion, the second portion protruding from the first portion in a direction perpendicular to the substrate;

[0040] A dielectric layer covering the substrate;

[0041] A first contact plug penetrates the dielectric layer and a portion of the substrate, and contacts the second portion;

[0042] The second contact plug penetrates at least through the dielectric layer and is in contact with the active region.

[0043] Optionally, the substrate includes a storage region and a peripheral region located outside the storage region, wherein the active region is located within the substrate of the storage region;

[0044] The first part is located in the storage area, and the second part is located in the peripheral area.

[0045] Optional, also includes:

[0046] A groove is located within the substrate;

[0047] A diffusion barrier layer covers the inner wall of the groove;

[0048] The letter lines are located on the surface of the diffusion barrier layer and fill the groove.

[0049] Optional, also includes:

[0050] Bit lines are located on the substrate;

[0051] The dielectric layer covers the substrate surface and the bit line.

[0052] Optional, also includes:

[0053] The third contact plug penetrates at least through the dielectric layer and is in contact with the bit line.

[0054] Optionally, the bit line extends from the storage region to the peripheral region;

[0055] The third contact plug contacts the bit line located in the peripheral region.

[0056] Optional, also includes:

[0057] The first peripheral circuit has one end of the first contact plug in contact with the second part and the other end electrically connected to the first peripheral circuit.

[0058] The second peripheral circuit has one end of the second contact plug in contact with the active area and the other end electrically connected to the second peripheral circuit.

[0059] The third peripheral circuit has one end of the third contact plug in contact with the bit line and the other end electrically connected to the third peripheral circuit.

[0060] Optionally, the thickness ratio of the second part to the thickness of the first part is (7:4) to (7:6).

[0061] The semiconductor structure and its formation method provided by the present invention, by setting the word line to include a first part and a second part located at the end of the first part, and such that the second part protrudes from the first part in a direction perpendicular to the substrate, that is, the top surface of the second part is higher than the top surface of the first part, on the one hand, can reduce the etching time and improve the etching efficiency when forming the first contact hole exposing the word line; on the other hand, can reduce the etching depth of the exposed word line, thereby avoiding excessive etching depth of the second contact hole exposing the active region, reducing damage to the inside of the active region, reducing the leakage current inside the semiconductor structure, improving the yield of the semiconductor structure, and improving the electrical performance of the semiconductor structure. Attached Figure Description

[0062] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of the present invention;

[0063] Appendix Figure 2A-2M This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of the present invention;

[0064] Appendix Figures 3A-3C This is a schematic diagram of the semiconductor structure in a specific embodiment of the present invention. Detailed Implementation

[0065] The specific embodiments of the semiconductor structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0066] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of the present invention. Figure 2A-2M This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of the present invention. For example... Figure 1 , Figures 2A-2M As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:

[0067] Step S11, providing a substrate 20, wherein the substrate 20 includes an active region 25, such as Figure 2A As shown.

[0068] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 10 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 10 also has a plurality of active regions 25 arranged in an array, and adjacent active regions 25 are isolated from each other by a shallow trench isolation structure.

[0069] Step S12: Forming word lines within the substrate 20. The word lines include a first portion 28 and a second portion 29 located at the end of the first portion 28. The second portion 29 protrudes from the first portion 28 in a direction perpendicular to the substrate 20. Figure 2I and Figure 2J As shown, Figure 2J yes Figure 2I A top-view structural diagram.

[0070] The second portion 29 protruding from the first portion 28 in a direction perpendicular to the substrate 20 means that, in this direction, the top surface of the second portion 29 is above the top surface of the first portion 28 (i.e., the top surface of the second portion 29 is higher than the top surface of the first portion 28). The bottom surface of the second portion 29 may be lower than the bottom surface of the first portion 28, or it may be flush with the bottom surface of the first portion 28.

[0071] Optionally, the substrate 20 includes a storage region CA and a peripheral region PA located outside the storage region CA, and the active region is located within the substrate 20 of the storage region CA; the specific steps for forming word lines within the substrate 20 include:

[0072] The substrate 20 is etched to form a groove 24 that penetrates the storage region CA and extends to the peripheral region PA along a direction parallel to the substrate 20, as shown below. Figure 2B As shown;

[0073] The groove 24 is filled with conductive material to form the first portion 28 located in the storage region CA and the second portion 29 located in the peripheral region PA, as follows. Figure 2I and Figure 2J As shown.

[0074] Specifically, the peripheral region PA is distributed around the outer periphery of the storage region CA. It extends from the surface of the substrate 20 along a direction perpendicular to the substrate 20 (e.g., Figure 2B The substrate 20 is etched along the Z-axis direction to form the groove 24 that does not penetrate the substrate 20. In a direction parallel to the surface of the substrate 20 (e.g., along the Z-axis direction), the groove 24 is etched to form the groove 24 that does not penetrate the substrate 20. Figure 2BAlong the X-axis direction (as shown in the image), the groove 24 penetrates the storage region CA and extends to the peripheral region PA. Multiple grooves 24 are arranged in a direction parallel to the surface of the substrate 20 (e.g., along the X-axis direction). Figure 2B The grooves are arranged parallel to each other along the Y-axis. Then, conductive materials such as tungsten are filled into the grooves 24 to form the first portion 28 located in the storage region CA and the second portion 29 located in the peripheral region PA, as shown below. Figure 2I and Figure 2J As shown.

[0075] Optionally, the specific steps for forming the first portion 28 located in the storage region CA and the second portion 29 located in the peripheral region PA include:

[0076] A first conductive material is deposited within the groove 24 and on the surface of the substrate 20 to form a conductive layer 22 covering the storage region CA and the peripheral region PA, such as... Figure 2C As shown;

[0077] The conductive layer 22 is etched to form the first portion 28 and the second portion 29.

[0078] Optionally, the specific steps for etching the conductive layer 22 include:

[0079] A shielding layer 23 is formed, which covers the surface of the conductive layer 22 located in the peripheral region PA, such as... Figure 2A and Figure 2D As shown, Figure 2D yes Figure 2A A top-view structural diagram;

[0080] The conductive layer 22 located on the surface of the substrate 20 in the storage region CA is removed. The conductive layer 22 remaining in the storage region CA is designated as the initial first part 26, and the conductive layer 22 remaining in the peripheral region PA is designated as the initial second part 27. Figure 2E , Figure 2F , Figure 2G and Figure 2H As shown, Figure 2F yes Figure 2E Top view structural diagram, Figure 2H yes Figure 2G A top-view structural diagram;

[0081] The initial first portion 26 and the initial second portion 27 are partially etched back. The initial first portion 26 remaining in the groove 24 of the storage region CA is designated as the first portion 28, and the initial second portion 27 remaining in the groove 24 of the peripheral region PA is designated as the second portion 29. Figure 2I and Figure 2J As shown.

[0082] Optionally, the peripheral region PA is distributed around the outer periphery of the storage region CA; the specific steps of forming a shielding layer 23 covering the conductive layer 22 located in the peripheral region PA include:

[0083] Photoresist material is deposited on the peripheral region PA to form the shielding layer 23, which covers the conductive layer 22 located in the peripheral region PA and exposes the conductive layer 22 located in the storage region CA.

[0084] Specifically, after depositing a first conductive material in the groove 24 and on the surface of the substrate 20 to form a conductive layer 22 covering the storage region CA and the peripheral region PA, photoresist is coated on the conductive layer 22 of the peripheral region PA to form the shielding layer 23. Figure 2A and Figure 2D As shown. Those skilled in the art can also choose other materials to form the shielding layer 23 according to actual needs, as long as a relatively high etching selectivity ratio is ensured between the shielding layer 23 and the conductive layer 22, for example, an etching selectivity ratio greater than 3 between the shielding layer 23 and the conductive layer 22. Next, the conductive layer 22 exposed in the storage region CA is etched to remove the portion of the conductive layer 22 outside the groove 24 and the portion of the conductive layer 22 inside the groove 24, forming as shown. Figure 2E and Figure 2F The structure shown is obtained after removing the shielding layer 23. Figure 2G and Figure 2H The structure is shown. Then, based on the required word line thickness, partially etch the initial first portion 26 and partially the initial second portion 27. The initial first portion 26 remaining in the groove 24 of the storage region CA becomes the first portion 28, and the initial second portion 27 remaining in the groove 24 of the peripheral region PA becomes the second portion 29, as shown. Figure 2I and Figure 2J As shown. In this specific embodiment, the character line formed is an embedded character line.

[0085] This specific embodiment illustrates the process of etching the first conductive material to form the first portion 28 and the second portion 29 after the first conductive material is simultaneously deposited in the storage region CA and the peripheral region PA. Those skilled in the art can also form the first portion 28 and the second portion 29 with different thicknesses directly through a deposition process, without etching, according to actual needs.

[0086] Optionally, before depositing the first conductive material within the groove 24 and on the surface of the substrate 20, the following steps are further included:

[0087] A diffusion barrier layer 21 is formed on the inner wall of the groove 24.

[0088] The diffusion barrier layer 21 can be made of, but is not limited to, TiN. The diffusion barrier layer 21 can increase the adhesion between the first conductive material and the inner wall of the groove 24, and also prevent conductive particles in the first conductive material from diffusing into the substrate 20.

[0089] Step S13, forming a dielectric layer 30 covering the substrate 20, such as Figure 2K and Figure 2L As shown, Figure 2L is Figure 2K A top-view structural diagram, in Figure 2L The active region 25, the first part 28 and the second part 29 described herein are not visible, so they are represented by dashed lines.

[0090] Optionally, before forming the dielectric layer covering the substrate 20, the following steps are further included:

[0091] A bit line 31 is formed on the substrate 20, such as Figure 2M As shown.

[0092] Specifically, the bit line 31 is located above the word line, and the extension direction of the bit line 31 intersects the extension direction of the word line. For example, the bit line 31 along... Figure 2M Extending along the Y-axis, the word line along Figure 2M It extends along the X-axis. Multiple bit lines 31 are arranged in parallel.

[0093] Optionally, the specific steps for forming the dielectric layer 30 covering the substrate 20 include:

[0094] A dielectric material is deposited on the substrate 20 to form a dielectric layer 30 covering the surface of the substrate 20 and the bit line 31. The material of the dielectric layer 30 may be, but is not limited to, a nitride material, such as silicon nitride.

[0095] Step S14: Etch the dielectric layer 30 and a portion of the substrate 20 to form a first contact hole 32 exposing the second portion 29, and simultaneously form a second contact hole (not shown) exposing the active region 25.

[0096] Optionally, the specific steps of forming a first contact hole 32 exposing the second portion 29 and simultaneously forming a second contact hole exposing the active region 25 include:

[0097] The dielectric layer 30 and the substrate 20 are etched to form a first contact hole 32 exposing the second portion 29, a second contact hole exposing the active region 25, and a third contact hole 33 exposing the bit line 31.

[0098] Optionally, the bit line 31 extends from the storage region CA to the peripheral region PA;

[0099] The third contact hole 33 exposes the bit line 31 located in the peripheral region PA.

[0100] Specifically, after the dielectric layer 30 is formed, the dielectric layer 30 and a portion of the substrate 20 are etched, while simultaneously forming the first contact hole 32 exposing the second portion 29, the second contact hole exposing the active region 25 within the substrate 20, the third contact hole 33 exposing the bit line 31 located in the peripheral region PA, and the fourth contact hole 34 located in the peripheral region PA.

[0101] In this specific embodiment, since the second portion 29 protrudes above the first portion 28, the etching time can be shortened during the etching process of forming the first contact hole 32. Furthermore, over-etching of the active region 25, the bit line 31, and the peripheral gate can be effectively avoided, reducing damage to these components and thus reducing leakage current within the semiconductor structure. Additionally, because the first portion 29 protrudes above the first portion 28, it can also be over-etched to increase the contact area between the first contact plug subsequently formed within the first contact hole 32 and the word line, thereby reducing the RC delay effect.

[0102] Optionally, the method for forming the semiconductor structure further includes the following steps:

[0103] A second conductive material is filled into the first contact hole 32, the second contact hole, and the third contact hole 33, thereby forming a first contact plug that contacts the second portion 29, a second contact plug that contacts the active region 25, and a third contact plug that contacts the bit line 31.

[0104] The second conductive material can be the same as the first conductive material, for example, both being tungsten.

[0105] Optionally, the method for forming the semiconductor structure further includes the following steps:

[0106] A first peripheral circuit electrically connected to the first contact plug, a second peripheral circuit electrically connected to the second contact plug, and a third peripheral circuit electrically connected to the third contact plug are formed.

[0107] The thickness difference between the second portion 29 and the first portion 28 should not be too small to avoid insufficient protection of the active region and the bit line 31; the thickness difference between the second portion 29 and the first portion 28 should not be too large to avoid increasing the internal resistance of the semiconductor structure. Optionally, the thickness ratio of the second portion 29 to the first portion 28 is 7:4 to 7:6. For example, if the thickness of the second portion 29 is 140 nm, then the corresponding thickness range of the first portion 28 can be 80 nm to 120 nm.

[0108] Furthermore, this specific embodiment also provides a semiconductor structure. (See attached document) Figures 3A-3C This is a schematic diagram of a semiconductor structure in a specific embodiment of the present invention. The semiconductor structure provided in this specific embodiment can adopt, for example... Figure 1 , Figures 2A-2M The semiconductor structure shown is formed using the method described. Figure 3A - As shown in Figure 3C, the semiconductor structure includes:

[0109] Substrate 20, wherein the substrate 20 has an active region 25;

[0110] The word line is located within the substrate 20. The word line includes a first portion 28 and a second portion 29 located at the end of the first portion 28. The second portion 29 protrudes from the first portion 28 in a direction perpendicular to the substrate 20.

[0111] Dielectric layer 30 covers the substrate 20;

[0112] The first contact plug penetrates the dielectric layer 30 and a portion of the substrate 20, and contacts the second portion 29;

[0113] The second contact plug penetrates at least through the dielectric layer 30 and contacts the active region 25.

[0114] Optionally, the substrate 20 includes a storage region CA and a peripheral region PA located outside the storage region CA, and the active region 25 is located within the substrate 20 of the storage region CA;

[0115] The first portion 28 is located in the storage area CA, and the second portion 29 is located in the peripheral area PA.

[0116] Optionally, the semiconductor structure further includes:

[0117] The groove 24 is located within the substrate 20;

[0118] A diffusion barrier layer 21 covers the inner wall of the groove 24;

[0119] The letter lines are located on the surface of the diffusion barrier layer 21 and fill the groove 24.

[0120] Optionally, the semiconductor structure further includes:

[0121] Bit line 31 is located on the substrate 20;

[0122] The dielectric layer 30 covers the surface of the substrate 20 and the bit line 31.

[0123] Optionally, the semiconductor structure further includes:

[0124] The third contact plug penetrates at least through the dielectric layer 30 and contacts the bit line 31.

[0125] Optionally, the bit line 31 extends from the storage region CA to the peripheral region PA;

[0126] The third contact plug contacts the bit line 31 located in the peripheral region PA.

[0127] Optionally, the semiconductor structure further includes:

[0128] The first peripheral circuit has one end of the first contact plug in contact with the second part 29 and the other end electrically connected to the first peripheral circuit.

[0129] The second peripheral circuit has one end of the second contact plug in contact with the active area 25 and the other end electrically connected to the second peripheral circuit.

[0130] The third peripheral circuit has one end of the third contact plug in contact with the bit line 31 and the other end electrically connected to the third peripheral circuit.

[0131] Optionally, the thickness of the second portion 29 is 1.2 to 5 times the thickness of the first portion 28.

[0132] The semiconductor structure and its formation method provided in this specific embodiment, by setting the word line to include a first part and a second part located at the end of the first part, and making the second part protrude from the first part in a direction perpendicular to the substrate, that is, the top surface of the second part is higher than the top surface of the first part, on the one hand, can reduce the etching time and improve the etching efficiency when forming the first contact hole exposing the word line; on the other hand, can reduce the etching depth of the exposed word line, thereby avoiding excessive etching depth of the second contact hole exposing the active region, reducing damage to the inside of the active region, reducing the leakage current inside the semiconductor structure, improving the yield of the semiconductor structure, and improving the electrical performance of the semiconductor structure.

[0133] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, wherein the substrate includes an active region; A word line is formed within the substrate, the word line comprising a first portion and a second portion located at the end of the first portion, the second portion protruding from the first portion in a direction perpendicular to the substrate; A dielectric layer is formed covering the substrate; The dielectric layer and a portion of the substrate are etched to form a first contact hole exposing the second portion, and simultaneously to form a second contact hole exposing the active region; the substrate includes a storage region and a peripheral region located outside the storage region, and the active region is located within the substrate of the storage region; The specific steps for forming word lines within the substrate include: The substrate is etched to form a groove that penetrates the storage region and extends to the peripheral region in a direction parallel to the substrate; The groove is filled with conductive material to form the first portion located in the storage area and the second portion located in the peripheral area.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming the first portion located in the storage area and the second portion located in the peripheral area include: A first conductive material is deposited in the groove and on the surface of the substrate to form a conductive layer covering the storage area and the peripheral area; The conductive layer is etched to form the first portion and the second portion.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The specific steps for etching the conductive layer include: A shielding layer is formed, which covers the surface of the conductive layer located in the peripheral region; Remove the conductive layer on the substrate surface located in the storage region, and use the conductive layer remaining in the storage region as the initial first part and the conductive layer remaining in the peripheral region as the initial second part; The initial first portion and the initial second portion are partially etched back, with the initial first portion remaining in the groove of the storage area as the first portion and the initial second portion remaining in the groove of the peripheral area as the second portion.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, Before depositing the first conductive material within the groove and on the substrate surface, the following steps are also included: A diffusion barrier layer is formed on the inner wall of the groove.

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The peripheral region is distributed around the outer periphery of the storage region; the specific steps for forming a shielding layer covering the conductive layer located in the peripheral region include: Photoresist material is deposited in the peripheral region to form the shielding layer, which covers the conductive layer located in the peripheral region and exposes the conductive layer located in the storage region.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming the dielectric layer covering the substrate, the following steps are also included: Bit lines are formed on the substrate.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The specific steps for forming the dielectric layer covering the substrate include: A dielectric material is deposited on the substrate to form a dielectric layer covering the substrate and the bit lines.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The specific steps for forming a first contact hole exposing the second portion and simultaneously forming a second contact hole exposing the active region include: The dielectric layer and the substrate are etched to form a first contact hole exposing the second portion, a second contact hole exposing the active region, and a third contact hole exposing the bit line.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The bit line extends from the storage area to the peripheral area; The third contact hole exposes the bit line located in the peripheral region.

10. The method for forming a semiconductor structure according to claim 8, characterized in that, It also includes the following steps: A second conductive material is filled into the first contact hole, the second contact hole, and the third contact hole, thereby forming a first contact plug that contacts the second portion, a second contact plug that contacts the active region, and a third contact plug that contacts the bit line.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, It also includes the following steps: A first peripheral circuit electrically connected to the first contact plug, a second peripheral circuit electrically connected to the second contact plug, and a third peripheral circuit electrically connected to the third contact plug are formed.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness ratio of the second part to the thickness of the first part is (7:4) to (7:6).

13. The method for forming a semiconductor structure according to claim 1, characterized in that, Etching the dielectric layer and a portion of the substrate to form a first contact hole exposing the second portion, and simultaneously forming a second contact hole exposing the active region, includes: While etching the dielectric layer to form the first contact hole exposing the second portion, the dielectric layer and a portion of the substrate are etched to form the second contact hole exposing the active region.

14. The method for forming a semiconductor structure according to claim 1, characterized in that, Etching the dielectric layer and a portion of the substrate to form a first contact hole exposing the second portion, and simultaneously forming a second contact hole exposing the active region, includes: The first contact hole is formed by etching the dielectric layer and penetrates the dielectric layer. The second contact hole is formed by etching the dielectric layer and a portion of the substrate and penetrates at least the dielectric layer.

15. The method for forming a semiconductor structure according to claim 1, characterized in that, The second portion protrudes from the first portion in a direction opposite to the substrate.

16. The method for forming a semiconductor structure according to claim 1, characterized in that, The second portion protrudes from the first portion in a direction opposite to the dielectric layer.

17. The method for forming a semiconductor structure according to claim 1, characterized in that, The second portion protrudes from the first portion in a direction opposite to the substrate, and also protrudes from the first portion in a direction opposite to the dielectric layer.

18. A semiconductor structure, characterized in that, include: A substrate having an active region therein; A word line, located within the substrate, the word line comprising a first portion and a second portion located at the end of the first portion, the second portion protruding from the first portion in a direction perpendicular to the substrate; A dielectric layer covering the substrate; The first contact plug penetrates the dielectric layer and contacts the second portion; The second contact plug penetrates at least through the dielectric layer and is in contact with the active region.

19. The semiconductor structure according to claim 18, characterized in that, The substrate includes a storage region and a peripheral region located outside the storage region, and the active region is located within the substrate of the storage region; The first part is located in the storage area, and the second part is located in the peripheral area.

20. The semiconductor structure according to claim 18, characterized in that, Also includes: A groove is located within the substrate; A diffusion barrier layer covers the inner wall of the groove; The letter line is located on the surface of the diffusion barrier layer and fills the groove.

21. The semiconductor structure according to claim 19, characterized in that, Also includes: Bit lines are located on the substrate; The dielectric layer covers the substrate and the bit line.

22. The semiconductor structure according to claim 21, characterized in that, Also includes: The third contact plug penetrates at least through the dielectric layer and is in contact with the bit line.

23. The semiconductor structure according to claim 22, characterized in that, The bit line extends from the storage area to the peripheral area; The third contact plug is located in the bit line contact of the peripheral region.

24. The semiconductor structure according to claim 23, characterized in that, Also includes: The first peripheral circuit has one end of the first contact plug in contact with the second part and the other end electrically connected to the first peripheral circuit. The second peripheral circuit has one end of the second contact plug in contact with the active area and the other end electrically connected to the second peripheral circuit. The third peripheral circuit has one end of the third contact plug in contact with the bit line and the other end electrically connected to the third peripheral circuit.

25. The semiconductor structure according to claim 18, characterized in that, The thickness ratio of the second part to the thickness of the first part is (7:4) to (7:6).

26. The semiconductor structure according to claim 18, characterized in that, The second portion protrudes from the first portion in a direction opposite to the substrate.

27. The semiconductor structure according to claim 18, characterized in that, The second portion protrudes from the first portion in a direction opposite to the dielectric layer.

28. The semiconductor structure according to claim 18, characterized in that, The second portion protrudes from the first portion in a direction opposite to the substrate, and also protrudes from the first portion in a direction opposite to the dielectric layer.

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