Single-time programmable memory element and method of making the same

Abstract

A one-time programmable memory element and a method for fabricating the same are disclosed. The method for fabricating the one-time programmable memory element includes forming a first gate structure and a second gate structure on a substrate, forming a diffusion region on both sides of the first gate structure and the second gate structure, forming a silicified metal layer beside the first gate structure, and patterning the first gate structure to form a third gate structure and a fourth gate structure.

Description

Technical Field

[0001] This invention relates to a single-use programmable memory element, and more particularly to a single-use programmable memory element comprising a metal gate. Background Technology

[0002] Semiconductor memory devices are widely used in various electronic devices. For example, non-volatile memory (NV) is widely used in mobile phones, digital cameras, personal digital assistants (PDAs), and other applications. Generally, NV primarily includes multi-time programmable (MTP) memory and one-time programmable (OTP) memory. Compared to rewritable memory, OTP offers advantages such as lower manufacturing costs and greater data security. However, OTP can only be programmed once; once the bits of specific memory cells within a designated memory block are overwritten via a one-time data write program, those specific cells cannot be programmed again.

[0003] Since current single-use programmable memory (SUM) devices still have drawbacks such as weak read current in read mode and long stress time in program mode, improving the architecture of existing SUM devices to solve these problems is an important issue today. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a single-programmable memory element. First, a first gate structure and a second gate structure are formed on a substrate. Then, a diffusion region is formed on both sides of the first gate structure and the second gate structure. A metal silicide layer is formed next to the first gate structure. The first gate structure is then patterned to form a third gate structure and a fourth gate structure.

[0005] Another embodiment of the present invention discloses a single-programmable memory element, which mainly includes a first shallow trench isolation and a second shallow trench isolation disposed in a substrate, a first gate structure disposed on the first shallow trench isolation and the substrate, and a second gate structure disposed on the second shallow trench isolation and the substrate, wherein no silicide metal layer is disposed between the first gate structure and the second gate structure.

[0006] Another embodiment of the present invention discloses a single-programmable memory element, which mainly includes a first shallow trench isolation and a second shallow trench isolation disposed in a substrate, a diffusion isolation structure disposed between the first shallow trench isolation and the second shallow trench isolation, a first gate structure disposed on the first shallow trench isolation, the substrate and the diffusion isolation structure, and a second gate structure disposed on the second shallow trench isolation, the substrate and the diffusion isolation structure. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0008] Figures 2 to 5 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0009] Figures 6 to 9 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0010] Explanation of main component symbols

[0011] 12: Base

[0012] 14: Input / Output Area

[0013] 16: Core Area

[0014] 18: Single-programmable capacitor area

[0015] 20 Static Random Access Memory Area

[0016] Unit 22

[0017] 24: Surrounding Area

[0018] 26: Unit Area

[0019] 28: Surrounding Area

[0020] 32: Shallow trench isolation

[0021] 34: Gate structure

[0022] 36: Gate structure

[0023] 38: Gate structure

[0024] 40: Gate dielectric layer

[0025] 42: High dielectric constant dielectric layer

[0026] 44: Gate material layer

[0027] 46: Hard Mask

[0028] 48: Diffusion Zone

[0029] 50: Siliconized metal layer

[0030] 52: Gate structure

[0031] 54: Gate structure

[0032] 56: Groove

[0033] 60: Interlayer dielectric layer

[0034] 62: Work function metal layer

[0035] 64: Low-resistivity metal layer

[0036] 66: Hard Mask

[0037] 70: Contact plug

[0038] 72: Diffusion isolation structure Detailed Implementation

[0039] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 1 This is a block diagram of a semiconductor element according to an embodiment of the present invention. Figures 2 to 5 This is a top view and cross-sectional schematic diagram of the semiconductor device fabricated in the single-programmable capacitor region. For example... Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and an input / output region 14, a core region 16, a single-programmable capacitor region 18, and a static random access memory region 20 are defined on the substrate. The single-programmable capacitor region 18 may include a cell region 22 and a peripheral region 24, and the static random access memory region 20 may also include a cell region 26 and a peripheral region 28.

[0040] In this embodiment, it is preferable to fabricate, for example, metal-oxide-semiconductor transistors in the input / output region 14 and the core region 16 in subsequent fabrication processes, while it is preferable to fabricate an integrated structure of metal-oxide-semiconductor transistors and single-programmable capacitors in the single-programmable capacitor region 18. Furthermore, since the focus of this invention is on patterning the gate structure of the source lines in the single-programmable capacitor region 18 after forming the metal silicide layer, the components in the input / output region 14, the core region 16, and the static random access memory region 20 are preferably not shown in subsequent fabrication processes.

[0041] Please continue to refer to Figure 2 , Figure 2 The left side is a top view of a semiconductor device fabricated according to an embodiment of the present invention. Figure 2 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line AA'. Figure 2As shown, shallow trench isolation (STI) 32 is then formed in the substrate 12 of the single programmable capacitor region 18, and then an ion implantation process is performed to implant N-type or P-type dopants into the substrate 12 to form a trap region in the substrate 12 in each region.

[0042] Next, multiple gate structures 34, 36, and 38 are formed on the substrate 12. For example... Figure 2 As shown in the top view on the left, the gate structures 34, 36, and 38 preferably extend along a first direction, such as the Y direction. The gate structure 36 in the middle is preferably a source line, while the gate structures 34 and 38 on either side of the gate structure 36 are character lines. In this embodiment, the gate structures 34, 36, and 38 can be fabricated according to manufacturing process requirements using a gate-first fabrication process, a high-k-first fabrication process (gate first), and a high-k-last fabrication process (gate last). Taking the high-k-first fabrication process of this embodiment as an example, a high-k-last layer can be formed sequentially from silicon oxide, silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiO2). A gate dielectric layer 40 or dielectric layer composed of oxyfluoride (SiOF), a high dielectric constant dielectric layer 42, a gate material layer 44 composed of polysilicon, and a selective hard mask 46 are placed on a substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etch or successive etch step, a portion of the hard mask 46, a portion of the gate material layer 44, a portion of the high dielectric constant dielectric layer 42, and a portion of the gate dielectric layer 40 are removed. Then, the patterned photoresist is stripped to form gate structures 34, 36, and 38 on the substrate 12, which are composed of the patterned gate dielectric layer 40, the patterned high dielectric constant dielectric layer 42, the patterned gate material layer 44, and the patterned hard mask 46.

[0043] In this embodiment, the high dielectric constant dielectric layer 42 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0044] Then, at least one spacer wall (not shown) is formed on the sidewalls of each gate structure 34, 36, and 38, and a diffusion region 48 or a source / drain region is formed in the substrate 12 on one or both sides of the gate structures 34, 36, and 38. In this embodiment, the spacer wall can be a single spacer wall or a composite spacer wall, for example, it can include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall can contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The diffusion region 48 or the source / drain region can contain different dopants depending on the conductivity type of the transistor being disposed, for example, it can contain P-type dopants or N-type dopants.

[0045] Please continue to refer to Figure 3 , Figure 3 The left side shows a continuation of an embodiment of the present invention. Figure 2 A top view of a semiconductor device. Figure 3 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line BB'. For example... Figure 3As shown, a metallization fabrication process can then be performed to form a metallization layer 50 on the surface of the substrate 12 on both sides of the gate structures 34, 36, and 38. It should be noted that, since the source line or the gate structure 36 located in the center is not yet patterned and divided into two parts at this stage, and a hard mask 46 is provided on the gate electrode or gate material layer 44 made of polysilicon, the formed metallization layer 50 is only located on the surface of the substrate 12 on both sides of the gate structures 34, 36, and 38, but not directly above the gate structures 34, 36, and 38.

[0046] Please continue to refer to Figure 4 , Figure 4 The left side shows a continuation of an embodiment of the present invention. Figure 3 A top view of a semiconductor device. Figure 4 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line CC'. For example... Figure 4 As shown, the gate structure 36 or source line is then patterned to form a gate structure 52 and a gate structure 54. More specifically, the patterning process performed in this stage can be performed by first forming a patterned mask (not shown), for example, a patterned photoresist, along a second direction such as the X direction to cover part of the gate structure 36. Then, using the patterned mask as a mask, part of the gate structure 36 is removed by etching to divide the gate structure 36 into two parts, including the lower gate structure 52 and the upper gate structure 54, and a groove 56 is formed between the two gate structures 52 and 54. It should be noted that since the silicon metal layer 50 has been formed on both sides of the gate structure 36 before separating the gate structure 36, the groove 56 formed after separating the gate structure 36 into gate structures 52 and 54 from the left top view angle preferably exposes the surface of the substrate 12 rather than the silicon metal layer 50.

[0047] It should also be noted that, although the gate dielectric layer 40 and the high dielectric constant dielectric layer 42 are retained on the surface of the substrate 12 between the tail ends of the two gate structures 52 and 54 when the gate structure 36 is patterned in the right cross section of this embodiment, it is not limited to this. According to other embodiments of the present invention, the gate dielectric layer 40 and the high dielectric constant dielectric layer 42 between the tail ends of the gate structures 52 and 54 can be removed when the gate structure 36 is patterned, and the surface of the substrate 12 is exposed. This variation is also within the scope of the present invention.

[0048] Please continue to refer to Figure 5 , Figure 5 The left side shows a continuation of an embodiment of the present invention. Figure 4 A top view of a semiconductor device. Figure 5 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line DD'. For example... Figure 5As shown, an interlayer dielectric layer 60 made of silicon oxide can then be formed on the gate structures 34, 38, 52, 54 and the shallow trench isolation 32. A planarization process is then performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 60 and the hard mask 46, exposing the gate material layer 44 made of polysilicon, so that the upper surface of each gate material layer 44 is flush with the upper surface of the interlayer dielectric layer 60. Subsequently, a metal gate replacement process is performed to convert the gate structures 34, 38, 52, 54 into metal gates. For example, a patterned mask (not shown) can be selectively formed to cover the gate structures 34, 38, 52, and 54. Then, a selective dry or wet etching process can be performed, such as using an etching solution like ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 46 and gate material layer 44 in the gate structures 34, 38, 52, and 54 to form a groove (not shown) in the interlayer dielectric layer 60. Subsequently, a conductive layer containing a work function metal layer 62 and a low impedance metal layer 64 is sequentially formed in the groove, and a planarization process is then performed to make the surfaces of the U-shaped work function metal layer 62 and the low impedance metal layer 64 flush with the surface of the interlayer dielectric layer 60.

[0049] In this embodiment, the work function metal layer 62 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 62 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 62 and the low impedance metal layer 64. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 54 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Since the conversion of a dummy gate to a metal gate according to the metal gate replacement fabrication process is a well-known technique in this field, it will not be described in detail here. Next, a portion of the work function metal layer 62 and a portion of the low impedance metal layer 64 may be removed to form a groove (not shown). Then, a hard mask 66 is filled into the groove and made flush with the surface of the interlayer dielectric layer 60. The hard mask 66 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0050] Subsequently, another interlayer dielectric layer (not shown) can be selectively formed on the gate structures 34, 38, 52, 54 formed by the metal gates and the interlayer dielectric layer 60, and a pattern transfer fabrication process is performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 60 next to the gate structures 34, 38 to form multiple contact holes (not shown) and expose the diffusion region 48 and / or the top of the gate material layer 44. Then, the desired conductive material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove part of the conductive material to form contact plugs 70 and electrically connect each diffusion region 48. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0051] Please refer to again Figure 5 , Figure 5 A schematic diagram of a single-programmable memory element according to an embodiment of the present invention is also disclosed. (See attached diagram.) Figure 5 As shown in the top left view, the single-programmable memory element mainly includes gate structure 52 and gate structure 54 extending along the Y direction on the substrate 12, gate structure 34 extending along the same Y direction on one side of gate structures 52 and 54, gate structure 38 extending along the Y direction on the other side of gate structures 52 and 54, diffusion region 48 and silicide metal layer 50 disposed on the substrate 12 on both sides of gate structures 34, 38, 52 and 54, and shallow trench isolation 32 surrounding diffusion region 48.

[0052] from Figure 5 From the cross-sectional view on the right, the single-programmable memory element includes a first shallow trench isolation (such as the shallow trench isolation 32 on the left) and a second shallow trench isolation (such as the shallow trench isolation 32 on the right) disposed within the substrate 12. The gate structure 52 is disposed on the shallow trench isolation 32 on the left and on the substrate 12, while the gate structure 54 is disposed on the shallow trench isolation 32 on the right and on the substrate 12. It should be noted that although silicide metal layers 50 are provided on the substrate 12 on both sides of the gate structures 52 and 54, in this embodiment, no silicide metal layer 50 is disposed or present between the tail ends of the gate structures 52 and 54. In other words, from... Figure 5 Looking at the left side diagram, the edges of the silicide metal layer 50 on both sides of the gate structures 52 and 54 are preferably aligned with the edges of the gate structures 52 and 54 along the Y direction, but do not extend to the surface of the substrate 12 between the gate structures 52 and 54.

[0053] Furthermore, although this embodiment uses a high-k first process to fabricate a metal gate transistor, it is not limited to this. According to other embodiments of the present invention, a high-k last process can also be used to fabricate the metal gate. Figure 5 The gate structure 52 and 54 in the right-hand diagram preferably includes a U-shaped high dielectric constant dielectric layer disposed between the U-shaped work function metal layer 62 and the substrate 12. This variation is also within the scope of this invention.

[0054] Please refer to Figures 6 to 9 , Figures 6 to 9 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figures 6 to 9 This is a top view and cross-sectional view of a semiconductor element fabricated in a single-programmable capacitor region. Please refer to the following first: Figure 6 , Figure 6 The left side is a top view of a semiconductor device fabricated according to an embodiment of the present invention. Figure 6 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line EE'. (Example) Figure 6As shown, a shallow trench isolation (STI) 32 and a diffusion break structure 72 are first formed in the substrate 12 of the single programmable capacitor region 18. Then, an ion implantation process is performed to implant N-type or P-type dopants into the substrate 12 to form a well region in the substrate 12 in each region.

[0055] It should be noted that the diffusion isolation structure 72 can be formed by first forming a patterned mask (not shown) on the substrate 12, and then using the patterned mask (not shown) to perform an etching process to remove a portion of the substrate 12 along a direction perpendicular to the direction to which the gate structure (not shown) will be formed (e.g., the X direction) to form a trench. Then, a dielectric material such as silicon oxide or silicon nitride is filled into the trench to form the diffusion isolation structure 72. In this embodiment, the shallow trench isolation 32 and the diffusion isolation structure 72 can be formed together in the same fabrication process or separately in different fabrication process steps, and the shallow trench isolation 32 and the diffusion isolation structure 72 can contain the same or different dielectric materials, all of which are within the scope of this invention. Since the fabrication of shallow trench isolation and diffusion isolation structures is a well-known technique in the art, it will not be described in detail here.

[0056] Next, multiple gate structures 34, 36, and 38 are formed on the substrate 12. For example... Figure 6As shown on the left, the gate structures 34, 36, and 38 preferably extend along a first direction, such as the Y direction, while the aforementioned diffusion isolation structure 72 extends along a second direction, such as the X direction. The gate structure 36 preferably spans directly above the diffusion isolation structure 72. The gate structure 36 in the middle is preferably a source line, and the gate structures 34 and 38 on either side of the gate structure 36 are character lines. As in the aforementioned embodiment, the gate structures 34, 36, and 38 can be fabricated according to manufacturing process requirements using a gate-first fabrication process, a high-k first fabrication process, or a high-k last fabrication process. Taking the high-k first fabrication process of this embodiment as an example, a high-k dielectric layer can be formed sequentially from silicon oxide, silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiO2). A gate dielectric layer 40 or dielectric layer composed of oxyfluoride (SiOF), a high dielectric constant dielectric layer 42, a gate material layer 44 composed of polysilicon, and a selective hard mask 46 are placed on a substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etch or successive etch step, a portion of the hard mask 46, a portion of the gate material layer 44, a portion of the high dielectric constant dielectric layer 42, and a portion of the gate dielectric layer 40 are removed. Then, the patterned photoresist is stripped to form gate structures 34, 36, and 38 on the substrate 12, which are composed of the patterned gate dielectric layer 40, the patterned high dielectric constant dielectric layer 42, the patterned gate material layer 44, and the patterned hard mask 46.

[0057] Please continue to refer to Figure 7 , Figure 7 The left side shows a continuation of an embodiment of the present invention. Figure 6 A top view of a semiconductor device. Figure 7 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line FF'. For example... Figure 7As shown, the gate structure 26 or source line is then patterned to form a gate structure 52 and a gate structure 54. More specifically, the patterning process performed in this stage can be performed by first forming a patterned mask (not shown), for example, a patterned photoresist, along a second direction such as the X direction to cover part of the gate structure 36, and then using the patterned mask as a mask to remove part of the gate structure 36 by etching, dividing the gate structure 36 into two parts, including the lower gate structure 52 and the upper gate structure 54, and simultaneously forming a groove 56 between the two gate structures 52 and 54 to expose the diffusion isolation structure 72. As in the aforementioned embodiments, although the gate dielectric layer 40 and the high dielectric constant dielectric layer 42 are retained on the surface of the substrate 12 between the tail ends of the two gate structures 52 and 54 when the gate structure 36 is patterned, it is not limited to this. According to other embodiments of the present invention, the gate dielectric layer 40 and the high dielectric constant dielectric layer 42 between the tail ends of the gate structures 52 and 54 can be removed when the gate structure 36 is patterned, and the surface of the diffusion isolation structure 72 is exposed. This variation is also within the scope of the present invention.

[0058] Please continue to refer to Figure 8 , Figure 8 The left side shows a continuation of an embodiment of the present invention. Figure 7 A top view of a semiconductor device. Figure 8 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line GG'. Figure 8 As shown, at least one spacer wall (not shown) is then formed on the sidewalls of each gate structure 34, 38, 52, 54, and a diffusion region 48 or a source / drain region is formed within the substrate 12 on one or both sides of the gate structures 34, 38, 52, 54. In this embodiment, the spacer wall can be a single spacer wall or a composite spacer wall, for example, it may include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The diffusion region 48 or the source / drain region may contain different dopants depending on the conductivity type of the transistor being disposed, for example, it may contain P-type dopants or N-type dopants.

[0059] Subsequently, a metallization fabrication process can be performed to form a metallization layer 50 on the surface of the substrate 12 on both sides of the gate structures 34, 38, 52, 54 or on both sides of the source lines and character lines. It should be noted that, since a diffusion isolation structure 72 is already provided in the source lines or in the substrate 12 located in the center between the gate structures 52 and 54, which has been divided into two parts, the diffusion isolation structure 72 will not react with metal to form a metallization layer 50 when the metallization layer 50 is formed on the surface of the substrate 12 on both sides of the source lines and character lines.

[0060] Please continue to refer to Figure 9 , Figure 9 The left side shows a continuation of an embodiment of the present invention. Figure 8 A top view of a semiconductor device. Figure 9 The right side shows a cross-sectional view of a semiconductor device fabricated along the left tangent line HH'. For example... Figure 9 As shown, an interlayer dielectric layer 60 made of silicon oxide can then be formed on the gate structures 34, 38, 52, 54 and the shallow trench isolation 32. A planarization process is then performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 60 and the hard mask 46, exposing the gate material layer 44 made of polysilicon, so that the upper surface of each gate material layer 44 is flush with the upper surface of the interlayer dielectric layer 60. Subsequently, a metal gate replacement process is performed to convert the gate structures 34, 38, 52, 54 into metal gates. For example, a patterned mask (not shown) can be selectively formed to cover the gate structures 34, 38, 52, and 54. Then, a selective dry or wet etching process can be performed, such as using an etching solution like ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 46 and gate material layer 44 in the gate structures 34, 38, 52, and 54 to form a groove (not shown) in the interlayer dielectric layer 60. Subsequently, a conductive layer containing a work function metal layer 62 and a low impedance metal layer 64 is sequentially formed in the groove, and a planarization process is then performed to make the surfaces of the U-shaped work function metal layer 62 and the low impedance metal layer 64 flush with the surface of the interlayer dielectric layer 60.

[0061] Subsequently, another interlayer dielectric layer (not shown) can be selectively formed on the gate structures 34, 38, 52, 54 formed by the metal gates and the interlayer dielectric layer 60, and a pattern transfer fabrication process is performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 60 next to the gate structures 34, 38 to form multiple contact holes (not shown) and expose the diffusion region 48 and / or the top of the gate material layer 44. Then, the desired conductive material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove part of the conductive material to form contact plugs 70 and electrically connect each diffusion region 48. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0062] Please refer to again Figure 9 , Figure 9 A schematic diagram of a single-programmable memory element according to an embodiment of the present invention is also disclosed. (See attached diagram.) Figure 9 As shown in the top left view, the single-programmable memory element mainly includes gate structure 52 and gate structure 54 extending along the Y direction on the substrate 12, gate structure 34 extending along the same Y direction on one side of gate structures 52 and 54, gate structure 38 extending along the Y direction on the other side of gate structures 52 and 54, diffusion region 48 and silicide metal layer 50 are disposed on the substrate 12 on both sides of gate structures 34, 38, 52 and 54, shallow trench isolation 32 surrounds diffusion region 48 and diffusion isolation structure 72 is disposed between gate structures 52 and 54.

[0063] from Figure 9 From the cross-sectional view on the right, the single-programmable memory element includes a first shallow trench isolation (such as the shallow trench isolation 32 on the left) and a second shallow trench isolation (such as the shallow trench isolation 32 on the right) disposed within the substrate 12. The gate structure 52 is disposed on the shallow trench isolation 32 on the left and on the substrate 12, while the gate structure 54 is disposed on the shallow trench isolation 32 on the right and on the substrate 12. In this embodiment, because a diffusion isolation structure 72 is provided between the tail ends of the gate structures 52 and 54, although a silicide metal layer 50 is provided on the substrate 12 on both sides of the gate structures 52 and 54, the surface of the diffusion isolation structure 72 between the tail ends of the gate structures 52 and 54 is not provided with or has no silicide metal layer 50.

[0064] As in the foregoing embodiments, although this embodiment uses a high-k first process to fabricate a metal gate transistor, it is not limited to this. According to other embodiments of the present invention, a high-k last process can also be used to fabricate the metal gate. Figure 9 The gate structures 52 and 54 on the right side preferably include a U-shaped high dielectric constant dielectric layer disposed between the U-shaped work function metal layer 62 and the substrate 12. This variation is also within the scope of this invention.

[0065] Generally, in current methods for fabricating one-time programmable memory (IPM) devices, the source lines are typically divided into two parts using photolithography and etching processes before the formation of the metal silicide layer. Since the ends of the two separated source lines are exposed before the metal silicide fabrication process, a metal silicide layer is formed not only on the diffusion regions on both sides of the source lines but also between the ends of the two separated source lines during the subsequent metal silicide fabrication process. This metal silicide layer in this location can easily affect the performance of the entire IPM device. To improve this problem, the present invention can choose to form a metal silicide layer on the diffusion regions on both sides of the source lines and then use a pattern transfer process to divide the source lines into two parts to form the two gate structures 52 and 54 in the first embodiment described above. In this way, no metal silicide layer is formed on the substrate surface at the ends of the two gate structures.

[0066] In addition, another embodiment of the present invention may pre-form a diffused isolation structure in the substrate where the source line is subsequently divided into two parts, in addition to forming a shallow trench isolation in the substrate before the gate structure is formed. Since this diffused isolation structure can serve as an insulating barrier between the tail ends of the two source lines, the silicide layer will not be formed on the substrate surface between the tail ends of the two separated source lines or gate structures 52 and 54, regardless of whether the source lines are patterned before the silicide layer is formed or separated after the silicide layer is formed.

[0067] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A once-programmable memory element, characterized in that, Include: The first and second shallow trenches are located within the substrate; A diffusion isolation structure is disposed between the first shallow trench isolation and the second shallow trench isolation; A first gate structure is disposed on the first shallow trench isolation, the substrate, and the diffusion isolation structure; A second gate structure is disposed on the second shallow trench isolation, the substrate, and the diffusion isolation structure, wherein the first gate structure and the second gate structure are source lines; as well as A metal silicide layer is disposed on the surface of the substrate, wherein, in the top view structure of the single-programmable memory element, the metal silicide layer is located on both sides of the first gate structure and the second gate structure and is not located between the opposing ends of the first gate structure and the second gate structure.

2. The single-programmable memory element of claim 1, wherein the first gate structure and the second gate structure extend on the substrate along a first direction.

3. The single-programmable memory element as claimed in claim 2, further comprising: A third gate structure extends along the first direction to one side of the first gate structure; and A fourth gate structure extends along the first direction on the other side of the first gate structure.

4. The single-programmable memory element as claimed in claim 3, wherein the metal silicide layer is disposed between the first gate structure and the third gate structure.

5. The single-programmable memory element as claimed in claim 3, wherein the metal silicide layer is disposed between the first gate structure and the fourth gate structure.

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