Semiconductor memory devices

Abstract

One embodiment of the present invention provides a semiconductor memory device capable of improving reliability. The semiconductor memory device of this embodiment includes a housing, a substrate, a controller, and a semiconductor memory component. The controller is configured to control the semiconductor memory component. The controller has a first wall portion and a second wall portion located on a first side relative to the substrate in a first direction that is the thickness direction of the substrate, and a third wall portion and a fourth wall portion located on a second side opposite to the first side relative to the substrate in the first direction. The first wall portion and the second wall portion are formed to be separable from each other. The third wall portion and the fourth wall portion are formed to be separable from each other.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-093092 (filed on June 2, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0004] A semiconductor memory device is known to have a housing, a substrate housed in the housing, a heating element mounted on the substrate, and a semiconductor memory element mounted on the substrate. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor memory device capable of achieving improved reliability.

[0006] A semiconductor memory device according to an embodiment includes a housing, a substrate, a controller, and a semiconductor memory component. The controller is configured to control the semiconductor memory component. The substrate is housed in the housing and includes a first region and a second region different from the first region. The controller is mounted in one of the first region and the second region. The semiconductor memory component is mounted in the other of the first region and the second region. The housing has: a first wall portion located on a first side relative to the substrate and facing the first region in a first direction that is the thickness direction of the substrate; a second wall portion located on the first side relative to the substrate in the first direction and facing the second region; a third wall portion located on a second side opposite to the first side relative to the substrate in the first direction and facing the first region; and a fourth wall portion located on a second side relative to the substrate in the first direction and facing the second region. The first wall portion and the second wall portion are formed to be separable from each other. The third wall portion and the fourth wall portion are formed to be separable from each other. Attached Figure Description

[0007] Figure 1 This is a perspective view of a semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a perspective view of the substrate unit according to the first embodiment.

[0009] Figure 3 This is a bottom view showing the substrate unit of the first embodiment.

[0010] Figure 4 This is a top view showing the substrate unit of the first embodiment.

[0011] Figure 5 This is a perspective view showing the housing of the first embodiment.

[0012] Figure 6 This is a perspective view showing the first component of the first embodiment.

[0013] Figure 7 This is a perspective view showing the second component of the first embodiment.

[0014] Figure 8 This is a diagram illustrating the mounting method of the second component relative to the first component in the first embodiment.

[0015] Figure 9 It is along Figure 1 The cross-sectional view of the semiconductor memory device shown is along line F9-F9.

[0016] Figure 10 It is along Figure 9 The cross-sectional view of the semiconductor memory device shown is along line F10-F10.

[0017] Figure 11 This is a bottom view showing a portion of the lower wall of the housing according to the first embodiment.

[0018] Figure 12 This is a perspective view showing the shell of the second embodiment, exploded.

[0019] Figure 13 This is a perspective view showing the shell of the third embodiment.

[0020] Figure 14 This is a perspective view showing the shell of the fourth embodiment, exploded.

[0021] Explanation of reference numerals in the attached figures

[0022] 1… Semiconductor memory device; 10, 10A, 10B, 10C… Housing; 23… Controller (heat-generating component); 24… Power conversion component (heat-generating component); 25… Power circuit component (heat-generating component); 27… Semiconductor memory component; 28… Capacitor (electronic component); 31… Lower wall; 32… Upper wall; 33… First side wall; 34… Second side wall; 41… First lower wall portion; 42… Second lower wall portion; 51… First upper wall portion; 52… Second upper wall portion; 61… The… Three connecting parts, 62… fourth connecting part, M1… first component, M2… second component, M3A… third component, M4A… fourth component, M5B… fifth component, M6B… sixth component, M7C… seventh component, M8C… eighth component, M9C… ninth component, M10C… tenth component, R1… first region, R2… second region, S1… first gap, S2… second gap, S3… third gap, S4… fourth gap, S5… fifth gap, S6… sixth gap Detailed Implementation

[0023] Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions will be labeled with the same reference numerals. Furthermore, repeated descriptions of these components will sometimes be omitted. In this application, the terms "parallel," "orthogonal," or "same" may also include cases of "substantially parallel," "substantially orthogonal," or "substantially same," respectively. In this application, "connection" is not limited to mechanical connections and may also include electrical connections. Furthermore, "connection" is not limited to the case of multiple constituent elements being directly connected, but may also include cases where other elements are sandwiched between them for connection.

[0024] Here, we first define the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction. The +X direction, -X direction, +Y direction, and -Y direction are related to the first surface 21a of the substrate 21 described later (refer to...). Figure 9 The +X direction is parallel to the direction from the first upper wall portion 51 of the housing 10 (described later) toward the second upper wall portion 52 (see reference). Figure 1 The -X direction is the direction opposite to the +X direction. Without distinguishing between the +X and -X directions, it is simply referred to as the "X direction". The +Y and -Y directions are directions that intersect (e.g., are orthogonal) the X direction. The +Y direction is the direction from the first sidewall 33 of the housing 10 (described later) toward the second sidewall 34 (see reference). Figure 1 The -Y direction is the direction opposite to the +Y direction. Without distinguishing between the +Y and -Y directions, it is simply referred to as the "Y direction".

[0025] The +Z and -Z directions are directions that intersect (e.g., are orthogonal) the X and Y directions, and are the thickness directions of the substrate 21 described later. The +Z direction is the direction from the first lower wall portion 41 of the housing 10 described later toward the first upper wall portion 51 (see reference). Figure 9 The -Z direction is the direction opposite to the +Z direction. Without distinguishing between the +Z and -Z directions, it is simply referred to as the "Z direction." In this application, for ease of explanation, the +Z direction side is sometimes referred to as "upper" and the -Z direction side as "lower." However, these do not limit the direction of gravity. The +Z direction is an example of a "first direction." The +X direction is an example of a "second direction." The +Y direction is an example of a "third direction."

[0026] (First Implementation)

[0027] <1. Overall Structure of Semiconductor Memory Devices>

[0028] Reference Figures 1 to 11 The semiconductor storage device 1 according to the first embodiment will be described below. The semiconductor storage device 1 is, for example, a storage device such as an SSD (Solid State Drive). The semiconductor storage device 1 is installed in information processing devices such as servers and personal computers, and is used as a storage area of ​​the information processing device. In this application, the information processing device in which the semiconductor storage device 1 is installed is referred to as a "host device".

[0029] Figure 1 This is a perspective view showing a semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a housing 10, a substrate unit 20, and a plurality of fixing members 80. For ease of explanation, the substrate unit 20 will be described first, followed by the housing 10 and the fixing members 80.

[0030] <2. Substrate Unit>

[0031] First, the substrate unit 20 will be described. For example... Figure 1 As shown, the substrate unit 20 is housed in the housing 10.

[0032] Figure 2 This is a perspective view of the substrate unit 20. The substrate unit 20 includes, for example, a substrate 21, an external connection connector 22, a controller 23, a power conversion component 24, a power supply circuit component 25, multiple DRAM (Dynamic Random Access Memory) units 26, multiple semiconductor memory units 27, and multiple capacitors 28.

[0033] The substrate 21 is plate-shaped along both the X and Y directions. For example, the substrate 21 is an elongated rectangular shape. The substrate 21 is a printed wiring board, having an insulating substrate and a wiring pattern disposed on the insulating substrate. Multiple through holes 21ha for the fixing member 80 to pass through are provided at the four corners of the substrate 21. Additionally, for example, positioning pins 41c (see reference) are provided on the substrate 21. Figure 6 Insert one or more through holes 21hb and supply / stop pin 42c (refer to) Figure 7 Insert one or more through holes 21hc.

[0034] The substrate 21 has a first end 21e1 and a second end 21e2 located on the opposite side of the first end 21e1 in the X direction. The first end 21e1 is the end on the X-direction side. The first end 21e1 protrudes to the outside of the housing 10 through the opening O of the housing 10 (see reference). Figure 1 The substrate 21 has a first surface 21a and a second surface 21b located on the opposite side of the first surface 21a in the Z direction. The first surface 21a faces the -Z direction. The second surface 21b faces the +Z direction.

[0035] Figure 3 This is a bottom view showing the substrate unit 20. Figure 4 This is a top view showing the substrate unit 20. In this embodiment, the substrate 21 has a first region R1 and a second region R2. In this application, the "region of the substrate" is not limited to a region on a specific surface of the substrate 21, but may include a portion of each of multiple surfaces of the substrate 21 (e.g., the first surface 21a and the second surface 21b).

[0036] like Figure 3 as well as Figure 4 As shown, the first region R1 and the second region R2 are arranged in the +X direction in the order of first region R1 and second region R2. That is, the first region R1 is located in the X direction at a position closer to the first end 21e1 of the substrate 21 than the second region R2. The second region R2 is located in the X direction at a position closer to the second end 21e2 of the substrate 21 than the first region R1.

[0037] An external connector 22 is disposed at the first end 21e1 of the substrate 21 and is exposed outside the housing 10 through the opening O. The external connector 22 has a plurality of metal terminals 22a arranged in the Y direction. The external connector 22 is capable of connecting to the connector of the host device.

[0038] Controller 23 is mounted in a first region R1 of substrate 21. Controller 23 may be mounted, for example, on a first surface 21a of substrate 21. Controller 23 uniformly controls the entire semiconductor memory device 1. Controller 23 may be, for example, a semiconductor package comprising a System on a Chip (SoC) that integrates host interface circuitry relative to the host device, control circuitry controlling multiple DRAMs 26, and control circuitry controlling multiple semiconductor memory components 27, all within a single semiconductor chip. Controller 23 is a component that generates heat during operation and is an example of a "heat-generating component." For example, controller 23 is at a higher temperature than semiconductor memory components 27. Furthermore, in this application, "a component is mounted in a certain region" means that more than half of the component is mounted in that region, which may include cases where a portion of the component protrudes from that region.

[0039] A power conversion component 24 is mounted in a first region R1 of the substrate 21. For example, the power conversion component 24 is mounted on a first surface 21a of the substrate 21. The power conversion component 24 is, for example, a DC-DC converter. The power conversion component 24 converts the power supplied from the host device into the power required by the components (controller 23, DRAM 26, semiconductor memory component 27, etc.) contained in the substrate unit 20, and supplies the converted power to each component. The power conversion component 24 is a component that generates heat during operation and is an example of a "heat-generating component." For example, the power conversion component 24 has a higher temperature compared to the semiconductor memory component 27.

[0040] A power supply circuit component 25 is mounted in a first region R1 of the substrate 21. The power supply circuit component 25 may also be mounted on a second surface 21b of the substrate 21. The power supply circuit component 25 may have a PMIC (Power Management IC) for example, providing power management functions. The power supply circuit component 25 performs power control on the various components (controller 23, DRAM 26, semiconductor memory component 27, etc.) contained in the substrate unit 20. The power supply circuit component 25 is a component that generates heat during operation and is an example of a "heat-generating component." For example, the power supply circuit component 25 has a higher temperature compared to the semiconductor memory component 27.

[0041] Multiple DRAMs 26 are mounted in a first region R1 of substrate 21. The multiple DRAMs 26 include a first DRAM 26A and a second DRAM 26B. The first DRAM 26A is mounted on a first surface 21a of substrate 21. The second DRAM 26B is mounted on a second surface 21b of substrate 21. Each DRAM 26 is a semiconductor package containing a volatile semiconductor memory chip. Each DRAM 26 can be used as a data buffer for temporarily storing write-object data received from a host device and read-object data read from one or more semiconductor memory components 27. However, the semiconductor memory device 1 may also not have DRAMs 26.

[0042] Multiple semiconductor memory components 27 are mounted on a second region R2 of a substrate 21. The multiple semiconductor memory components 27 include multiple first semiconductor memory components 27A and multiple second semiconductor memory components 27B. The multiple first semiconductor memory components 27A are mounted on a first surface 21a of the substrate 21 and arranged in the X and Y directions. The multiple second semiconductor memory components 27B are mounted on a second surface 21b of the substrate 21 and arranged in the X and Y directions. Each semiconductor memory component 27 is a semiconductor package containing a non-volatile semiconductor memory chip. Each semiconductor memory component 27 is, for example, a NAND flash memory.

[0043] However, the semiconductor memory component 27 is not limited to NAND flash memory, but may also be NOR memory, MRAM (Magnetoresistive Random Access Memory), resistance-varying memory, or other types of memory devices. That is, the "semiconductor memory component" is not limited to a component that includes a memory element that stores data based on the accumulated state of charge, but may also be a component that includes a memory element that stores data based on magnetic state or resistance state, etc.

[0044] The plurality of capacitors 28 includes a plurality of first capacitors 28A and a plurality of second capacitors 28B. The plurality of first capacitors 28A are mounted on a first surface 21a of the substrate 21. The plurality of first capacitors 28A are, for example, disposed between the controller 23 and a plurality of first semiconductor memory devices 27A. The plurality of second capacitors 28B are mounted on a second surface 21b of the substrate 21. The plurality of second capacitors 28B are, for example, disposed between a second DRAM 26B and a plurality of second semiconductor memory devices 27B. Each capacitor 28 has a power backup function for data protection in the event of an unexpected power outage. For example, in the event of an unexpected power outage from the host device, the plurality of capacitors 28 supply power to the controller 23, the plurality of DRAMs 26, and the plurality of semiconductor memory devices 27 for a certain period of time. Each capacitor 28 is, for example, an aluminum electrolytic capacitor. However, the capacitor 28 is not limited to the above example. The capacitor 28 is an example of an "electronic component".

[0045] <3. Shell>

[0046] <3.1 Overall Structure of the Shell>

[0047] Next, the housing 10 will be described.

[0048] Figure 5 This is a perspective view of the housing 10. The housing 10 has, for example, a lower wall 31, an upper wall 32, a first side wall 33, and a second side wall 34.

[0049] The lower wall 31 is located at the end of the housing 10 on the -Z direction side and is exposed outside the housing 10. That is, the lower wall 31 is located on the -Z direction side relative to the substrate unit 20. The lower wall 31 is plate-shaped along the X and Y directions. The lower wall 31 includes a first lower wall portion 41 and a second lower wall portion 42. The first lower wall portion 41 extends from the -Z direction side towards the first region R1 of the substrate 21 (refer to...). Figure 9 The second lower wall portion 42 is located on the +X direction side relative to the first lower wall portion 41. The second lower wall portion 42 is disposed at the same position (same height) as the first lower wall portion 41 in the Z direction. The second lower wall portion 42 extends from the -Z direction side towards the second region R2 of the substrate 21 (refer to...). Figure 9 The first lower wall portion 41 and the second lower wall portion 42 are plate-shaped along the X and Y directions, respectively. The first lower wall portion 41 and the second lower wall portion 42 have the same thickness. The Z-direction side is an example of a "first side". The first lower wall portion 41 is an example of a "first wall portion". The second lower wall portion 42 is an example of a "second wall portion".

[0050] The upper wall 32 is located at the end of the housing 10 on the +Z direction side and is exposed outside the housing 10. That is, the upper wall 32 is located on the +Z direction side relative to the substrate unit 20. The upper wall 32 is plate-shaped along the X and Y directions. The upper wall 32 includes a first upper wall portion 51 and a second upper wall portion 52. The first upper wall portion 51 extends from the +Z direction side towards the first region R1 of the substrate 21 (refer to...). Figure 9 The second upper wall portion 52 is located on the +X direction side relative to the first upper wall portion 51. The second upper wall portion 52 is disposed at the same position (same height) as the first upper wall portion 51 in the Z direction. The second upper wall portion 52 extends from the +Z direction side towards the second region R2 of the substrate 21 (refer to...). Figure 9 The first upper wall portion 51 and the second upper wall portion 52 are plate-shaped along the X and Y directions, respectively. The first upper wall portion 51 and the second upper wall portion 52 have the same thickness. The +Z direction side is an example of a "second side". The first upper wall portion 51 is an example of a "third wall portion". The second upper wall portion 52 is an example of a "fourth wall portion".

[0051] The first sidewall 33 is located at the end of the housing 10 on the -Y direction side and is exposed outside the housing 10. That is, the first sidewall 33 is located on the -Y direction side relative to the substrate unit 20. The first sidewall 33 is plate-shaped along both the X and Z directions. The first sidewall 33 spans the lower wall 31 and the upper wall 32 in the Z direction. That is, the first sidewall 33 covers the space between the lower wall 31 and the upper wall 32 from the -Y direction side. In this embodiment, the first sidewall 33 extends along the entire length of the first upper wall portion 51 and the entire length of the second upper wall portion 52 in the X direction. The first sidewall 33 is an example of a "fifth wall portion".

[0052] The second sidewall 34 is located at the end of the housing 10 on the +Y direction side and is exposed outside the housing 10. That is, the second sidewall 34 is located on the +Y direction side relative to the substrate unit 20. The second sidewall 34 is plate-shaped along both the X and Z directions. The second sidewall 34 spans the lower wall 31 and the upper wall 32 in the Z direction. That is, the second sidewall 34 covers the space between the lower wall 31 and the upper wall 32 from the +Y direction side. In this embodiment, the second sidewall 34 extends along the entire length of the first upper wall portion 51 and the entire length of the second upper wall portion 52 in the X direction. The second sidewall 34 is an example of a "sixth wall portion".

[0053] The housing 10 includes the aforementioned lower wall 31, upper wall 32, first side wall 33, and second side wall 34, and is a flat rectangular cylindrical shape. In this embodiment, the housing 10 includes a first component M1 and a second component M2. The first component M1 and the second component M2 are separate. The first component M1 and the second component M2 are assembled to form the housing 10. The first component M1 and the second component M2 can be separated from each other. This will be described in detail below.

[0054] <3.2 First Component>

[0055] Figure 6 This is a perspective view showing the first component M1. The first component M1 includes, for example, a first lower wall portion 41, a second upper wall portion 52, a first side wall 33, and a second side wall 34. For example, the first component M1 is integrally formed from a metal material by extrusion or other processes.

[0056] The first lower wall portion 41 has a plate-shaped wall body 41a, a pair of support portions 41b, a first recess U1, a first portion U2a of a second recess U2, and one or more positioning pins 41c. The pair of support portions 41b, the first recess U1, the first portion U2a of the second recess U2, and the one or more positioning pins 41c are provided on the surface of the wall body 41a in the +Z direction.

[0057] A pair of support portions 41b are provided at the ends of the first lower wall portion 41 in the -X direction. The pair of support portions 41b are separated in the Y direction and located at the two ends of the first lower wall portion 41. The pair of support portions 41b protrudes from the surface of the wall body 41a in the +Z direction. The first end portion 21e1 of the substrate 21 is placed on the pair of support portions 41b. Each of the pair of support portions 41b is provided with a locking hole 41h for engaging the fixing member 80.

[0058] The first recess U1 and the first portion U2a of the second recess U2 are recessed from the surface of the wall body 41a in the -Z direction. The first recess U1 is located at a position corresponding to the controller 23, avoiding the recess of the controller 23 (see reference). Figure 9 The second recess U2 is located at a position corresponding to the plurality of first capacitors 28A, and is a recess that avoids the plurality of first capacitors 28A (see reference). Figure 9 In this embodiment, a portion (first portion U2a) of the second recess U2 is provided in the first lower wall portion 41.

[0059] The positioning pin 41c protrudes from the surface of the wall body 41a in the +Z direction. The positioning pin 41c is inserted into the through hole 21hb of the substrate 21 for positioning the substrate unit 20.

[0060] The second upper wall portion 52 is located on the +X and +Z direction sides relative to the first lower wall portion 41. The second upper wall portion 52 has a plate-shaped wall body 52a and a pair of support portions 52b. The pair of support portions 52b are provided on the surface of the wall body 52a on the -Z direction side. The pair of support portions 52b are provided at the ends of the second upper wall portion 52 on the +X direction side. The pair of support portions 52b are separated in the Y direction and located at both ends of the second upper wall portion 52. The pair of support portions 52b protrude from the wall body 52a in the -Z direction. The pair of support portions 52b abut against the second end portion 21e2 of the substrate 21. Each of the pair of support portions 52b has a through hole 52h for the passage of a fixing member 80.

[0061] The first sidewall 33 is located at the end of the first component M1 in the -Y direction. The first sidewall 33 connects the end of the first lower wall portion 41 in the -Y direction and the end of the second upper wall portion 52 in the -Y direction. On the other hand, the second sidewall 34 is located at the end of the first component M1 in the +Y direction. The second sidewall 34 connects the end of the first lower wall portion 41 in the +Y direction and the end of the second upper wall portion 52 in the +Y direction. In this embodiment, the thickness T2 of the first sidewall 33 and the second sidewall 34 in the Y direction is thinner than the thickness T1 of the first lower wall portion 41 in the Z direction (e.g., the thickness of the wall body 41a).

[0062] With the above configuration, the region in the first component M1 where the first lower wall portion 41 is located is formed into a bowl shape that opens in the +Z direction. Furthermore, the region in the first component M1 where the second upper wall portion 52 is located is formed into a bowl shape that opens in the -Z direction.

[0063] <3.3 Second Component>

[0064] Figure 7 This is a perspective view showing the second component M2. The second component M2 includes, for example, a second lower wall portion 42, a first upper wall portion 51, a third connecting portion 61, and a fourth connecting portion 62. For example, the second component M2 is integrally formed from metal material through extrusion or other processes.

[0065] The second lower wall portion 42 has a plate-shaped wall body 42a, a pair of support portions 42b, a second portion U2b of a second recess U2, and one or more anti-rotation pins 42c. The pair of support portions 42b, the second portion U2b of the second recess U2, and the one or more anti-rotation pins 42c are provided on the surface of the wall body 42a in the +Z direction.

[0066] A pair of support portions 42b are provided at the +X direction end of the second lower wall portion 42. The pair of support portions 42b are separated in the Y direction and located at both ends of the second lower wall portion 42. The pair of support portions 42b protrudes from the surface of the wall body 42a in the +Z direction. The second end portion 21e2 of the substrate 21 is placed on the pair of support portions 42b. Each of the pair of support portions 42b is provided with a locking hole 42h for engaging the fixing member 80.

[0067] The second portion U2b of the second recess U2 is recessed from the surface of the wall body 42a in the -Z direction. The second portion U2b of the second recess U2 is adjacent to the first portion U2a of the second recess U2 of the first lower wall portion 41 in the X direction. In other words, the second recess U2 is provided throughout the first lower wall portion 41 and the second lower wall portion 42.

[0068] Anti-rotation pin 42c protrudes from the surface of wall body 42a in the +Z direction. Anti-rotation pin 42c is inserted into through hole 21hc of substrate 21, for example, to suppress rotation of substrate unit 20 during assembly.

[0069] The +X direction end of the second lower wall portion 42 protrudes in the +X direction more than the +X direction end of the second upper wall portion 52. The +X direction end of the second lower wall portion 42 functions as a handle for the operator to hold when installing the semiconductor memory device 1 onto the host device. The +X direction end of the second lower wall portion 42 is provided with one or more holes H for fixing or positioning the semiconductor memory device 1 relative to the host device.

[0070] The first upper wall portion 51 is located on the -X direction side and the +Z direction side relative to the second lower wall portion 42. The first upper wall portion 51 has a plate-shaped wall body 51a and a pair of support portions 51b. The pair of support portions 51b are provided on the surface of the wall body 51a on the -Z direction side. The pair of support portions 51b are provided at the ends of the first upper wall portion 51 on the -X direction side. The pair of support portions 51b are separated in the Y direction and located at the two ends of the first upper wall portion 51. The pair of support portions 51b protrude from the wall body 51a in the -Z direction. The pair of support portions 51b abut against the first end 21e1 of the substrate 21. Each of the pair of support portions 51b has an insertion hole 51h for the fixing member 80 to pass through.

[0071] The third connecting portion 61 and the fourth connecting portion 62 are disposed in the Y direction between the first sidewall 33 and the second sidewall 34 of the first component M1. The third connecting portion 61 is, for example, located at the end of the second component M2 in the -Y direction. The third connecting portion 61 connects the end of the first upper wall portion 51 in the -Y direction and the end of the second lower wall portion 42 in the -Y direction. On the other hand, the fourth connecting portion 62 is, for example, located at the end of the second component M2 in the +Y direction. The fourth connecting portion 62 connects the end of the first upper wall portion 51 in the +Y direction and the end of the second lower wall portion 42 in the +Y direction. The substrate unit 20 is disposed between the third connecting portion 61 and the fourth connecting portion 62 in the Y direction.

[0072] In this embodiment, the third connecting portion 61 and the fourth connecting portion 62 extend obliquely relative to the X direction, respectively, from the end of the first upper wall portion 51 on the +X direction side toward the end of the second lower wall portion 42 on the -X direction side. The length L2 of each of the third connecting portion 61 and the fourth connecting portion 62 in the X direction is greater than the length L1 of each of the first sidewall 33 and the second sidewall 34 in the X direction (refer to...). Figure 6From another perspective, the width W (e.g., maximum width) of the third connecting portion 61 and the fourth connecting portion 62 in the X direction is shorter than the length L1 of the first sidewall 33 and the second sidewall 34 in the X direction. In this embodiment, the thickness T3 of the third connecting portion 61 and the fourth connecting portion 62 in the Y direction is shorter than the thickness T4 of the second lower wall portion 42 in the Z direction (refer to...). Figure 7 For example, the thickness of the wall body 42a is thin.

[0073] Figure 8 This diagram illustrates the mounting method of the second component M2 relative to the first component M1. In this embodiment, the second component M2 is inserted between one side wall 33 and the second side wall 34 in an obliquely inclined position relative to the first component M1. Then, as... Figure 8 As indicated by arrow A, the second component M2 is rotated relative to the first component M1 so that the first upper wall portion 51 is parallel to the first lower wall portion 41, and the second lower wall portion 42 is parallel to the second upper wall portion 52. Thus, the first component M1 and the second component M2 are combined to form the housing 10.

[0074] <3.4 Relationship between the housing and the substrate unit>

[0075] Figure 9 It is along Figure 1 The cross-sectional view of line F9-F9 of the semiconductor memory device 1 shown. Figure 9 As shown, the first lower wall portion 41 extends laterally from the -Z direction towards the controller 23 and the power conversion component 24. The first lower wall portion 41 houses a thermally conductive component 71A (e.g., a thermally conductive sheet) and connects to the controller 23. The first lower wall portion 41 also houses a thermally conductive component 71B (e.g., a thermally conductive sheet) and connects to the power conversion component 24. Conversely, the second lower wall portion 42 extends laterally from the -Z direction towards a plurality of first semiconductor memory components 27A. The second lower wall portion 42 houses a thermally conductive component 71C (e.g., a thermally conductive sheet) and connects to the plurality of first semiconductor memory components 27A. Alternatively, one or more of the thermally conductive components 71A, 71B, and 71C may be omitted.

[0076] The first upper wall portion 51 extends laterally from the +Z direction toward the power circuit component 25. A thermally conductive component 71D (e.g., a thermally conductive sheet) is sandwiched within the first upper wall portion 51 and connected to the power circuit component 25. Conversely, the second upper wall portion 52 extends laterally from the +Z direction toward a plurality of second semiconductor memory components 27B. A thermally conductive component 71E (e.g., a thermally conductive sheet) is sandwiched within the second upper wall portion 52 and connected to the plurality of second semiconductor memory components 27B. Alternatively, one or more of the thermally conductive components 71D and 71E may be omitted.

[0077] In this embodiment, the lower wall 31 has a first gap S1 between the first lower wall portion 41 and the second lower wall portion 42 in the X direction. The length direction of the first gap S1 is along the Y direction (refer to...). Figure 5 The first gap S1 is provided, for example, across the entire width of the second component M2 in the Y direction. The first gap S1 suppresses heat conduction from the first lower wall portion 41 toward the second lower wall portion 42. The first gap S1 is a portion with a lower thermal conductivity than the first lower wall portion 41. The first gap S1 is an example of a "first portion".

[0078] Similarly, the upper wall 32 has a second gap S2 between the first upper wall portion 51 and the second upper wall portion 52 in the X direction. The length direction of the second gap S2 is along the Y direction (see reference). Figure 5 The second gap S2 is provided, for example, across the entire width of the second component M2 in the Y direction. The second gap S2 suppresses heat conduction from the first upper wall portion 51 toward the second upper wall portion 52. The second gap S2 is a portion with a lower thermal conductivity than the first upper wall portion 51. The second gap S2 is an example of a "second portion".

[0079] In this embodiment, the first gap S1 and the second gap S2 are exposed outside the housing 10. Air flowing outside the housing 10 can flow into the housing 10 through the first gap S1 and the second gap S2. In this embodiment, by providing the first gap S1 and the second gap S2, interference between the first component M1 and the second component M2 during the assembly of the housing 10 can be avoided. That is, by providing the first gap S1 and the second gap S2, the second component M2 is assembled in an oblique posture relative to the first component M1, and then the second component M2 can be rotated relative to the first component M1.

[0080] like Figure 9 As shown, the housing 10 has a first end 10e1 and a second end 10e2 opposite to the first end 10e1 in the X direction. The first end 10e1 is the end on the -X direction side. The second end 10e2 is the end on the +X direction side. The first gap S1 (i.e., the boundary between the first lower wall portion 41 and the second lower wall portion 42) is located in the X direction closer to the center of the housing 10 than the first end 10e1 and the second end 10e2. Similarly, the second gap S2 (i.e., the boundary between the first upper wall portion 51 and the second upper wall portion 52) is located in the X direction closer to the center of the housing 10 than the first end 10e1 and the second end 10e2.

[0081] Figure 10 It is along Figure 9The diagram shows a cross-sectional view of the semiconductor memory device 1 along line F10-F10. In this embodiment, the second lower wall portion 42 is disposed between the first sidewall 33 and the second sidewall 34 in the Y direction. Furthermore, a third gap S3 is provided between the second lower wall portion 42 and the first sidewall 33 in the Y direction. A fourth gap S4 is provided between the second lower wall portion 42 and the second sidewall 34 in the Y direction.

[0082] Figure 11 This is a bottom view showing a portion of the lower wall 31 of the housing 10. The third gap S3 and the fourth gap S4 communicate with the first gap S1. The length direction of each of the third gap S3 and the fourth gap S4 is along the X direction. The third gap S3 and the fourth gap S4 are exposed outside the housing 10. Air flowing outside the housing 10 can flow into the housing 10 through the third gap S3 and the fourth gap S4.

[0083] like Figure 11 As shown, in this embodiment, a portion of the third connecting portion 61 protrudes towards the -Y direction from the end of the second lower wall portion 42 relative to its -Y direction side. This ensures both a wide receiving space for the substrate unit 20 and sufficient strength of the third connecting portion 61. To prevent the third connecting portion 61 protruding from the second lower wall portion 42 from interfering with the first sidewall 33, a third gap S3 is formed by a recess U3 provided in the first sidewall 33. Similarly, a portion of the fourth connecting portion 62 protrudes towards the +Y direction from the end of the second lower wall portion 42 relative to its +Y direction side. This ensures both a wide receiving space for the substrate unit 20 and sufficient strength of the fourth connecting portion 62. To prevent the fourth connecting portion 62 protruding from the second lower wall portion 42 from interfering with the second sidewall 34, a fourth gap S4 is formed by a recess U4 provided in the second sidewall 34.

[0084] Similarly, the first upper wall portion 51 is disposed in the Y direction between the first side wall 33 and the second side wall 34 (see reference). Figure 5 Furthermore, in the Y direction, a fifth gap S5 is provided between the first upper wall portion 51 and the first side wall 33. In the Y direction, a sixth gap S6 is provided between the first upper wall portion 51 and the second side wall 34. The fifth gap S5 and the sixth gap S6 have, for example, shapes similar to the third gap S3 and the fourth gap S4. That is, the fifth gap S5 and the sixth gap S6 communicate with the second gap S2. The length direction of each of the fifth gap S5 and the sixth gap S6 is along the X direction. The fifth gap S5 and the sixth gap S6 are exposed outside the housing 10. Air flowing outside the housing 10 can flow into the housing 10 through the fifth gap S5 and the sixth gap S6.

[0085] In this embodiment, a portion of the third connecting portion 61 protrudes towards the -Y direction from the end of the first upper wall portion 51 relative to the -Y direction side. This ensures both a wide receiving space for the substrate unit 20 and sufficient strength of the third connecting portion 61. To prevent interference between the third connecting portion 61 protruding from the first upper wall portion 51 and the first sidewall 33, a fifth gap S5 is formed by a recess U5 provided in the first sidewall 33. A portion of the fourth connecting portion 62 protrudes towards the +Y direction from the end of the first upper wall portion 51 relative to the +Y direction side. This ensures both a wide receiving space for the substrate unit 20 and sufficient strength of the fourth connecting portion 62. To prevent interference between the fourth connecting portion 62 protruding from the first upper wall portion 51 and the second sidewall 34, a sixth gap S6 is formed by a recess U6 provided in the second sidewall 34. The shapes of the recesses U5 and U6 are, for example, similar to... Figure 11 The depressions U3 and U4 shown are the same.

[0086] <4. Fixing Components>

[0087] return Figure 1 The following describes a plurality of fixing components 80. The plurality of fixing components 80 fix the first component M1 and the second component M2 described above. In this embodiment, the plurality of fixing components 80 together fasten the fixing base plate 21 relative to the first component M1 and the second component M2. The plurality of fixing components 80 includes, for example, a plurality of first fixing components 80A and a plurality of second fixing components 80B.

[0088] Each of the first fixing components 80A passes through the insertion hole 51h of the support portion 51b of the first upper wall portion 51 and the insertion hole 21ha of the substrate 21, and engages with the engagement hole 41h of the support portion 41b of the first lower wall portion 41. Thus, the first upper wall portion 51 and the first lower wall portion 41 are fixed, and the substrate 21 is clamped and fixed between the support portion 51b of the first upper wall portion 51 and the support portion 41b of the first lower wall portion 41.

[0089] Each of the second fixing components 80B passes through the insertion hole 52h of the support portion 52b of the second upper wall portion 52 and the insertion hole 21ha of the substrate 21, and engages with the engagement hole 42h of the support portion 42b of the second lower wall portion 42. Thus, the second upper wall portion 52 and the second lower wall portion 42 are fixed, and the substrate 21 is clamped and fixed between the support portion 52b of the second upper wall portion 52 and the support portion 42b of the second lower wall portion 42.

[0090] Here, an example of a mounting method for the substrate unit 20 will be described. For example, the substrate unit 20 is inserted into the second component M2 in an oblique position relative to the first component M1. Figure 8 In the state shown, it is inserted between the first component M1 and the second component M2. In the substrate unit 20, for example, the positioning pin 41c (see reference) Figure 6 Insert the through hole 21hb into the substrate 21, and the anti-rotation pin 42c (refer to...) Figure 7 The substrate unit 20 is positioned by inserting it into the through hole 21hc of the substrate 21, thereby suppressing the rotation of the substrate unit 20.

[0091] In this state, by moving the second component M2 relative to the first component M1 towards Figure 8 Rotating in the direction of arrow A, the substrate unit 20 is clamped between the first component M1 and the second component M2. In this embodiment, the first end 21e1 of the substrate 21 is clamped between the support portion 41b of the first lower wall portion 41 and the support portion 51b of the first upper wall portion 51. Furthermore, the second end 21e2 of the substrate 21 is clamped between the support portion 42b of the second lower wall portion 42 and the support portion 52b of the second upper wall portion 52. By mounting the plurality of fixing components 80 to the housing 10 in this state, the substrate unit 20 is fixed to the housing 10. In addition, the mounting method of the substrate unit 20 is not limited to the above example. For example, the second component M2 may be mounted to the first component M1 after the substrate unit 20 is mounted to the second component M2.

[0092] <5. Function>

[0093] As described above, the controller 23 and the power conversion component 24 are connected to the first lower wall portion 41, for example, via thermally conductive components 71A and 71B. Therefore, a portion of the heat generated from the controller 23 and the power conversion component 24 is conducted to the first lower wall portion 41 via the thermally conductive components 71A and 71B. Consequently, the temperature of the first lower wall portion 41 rises. However, since the first lower wall portion 41 and the second lower wall portion 42 are not integrally formed, the heat conducted from the controller 23 and the power conversion component 24 to the first lower wall portion 41 is difficult to conduct from the first lower wall portion 41 to the second lower wall portion 42. Therefore, compared to the case where the first lower wall portion 41 and the second lower wall portion 42 are integrally formed, the temperature of the second lower wall portion 42 is less likely to rise. As a result, it is possible to prevent the semiconductor memory component 27 (e.g., the first semiconductor memory component 27A), whose heat resistance is lower than that of the controller 23 and the power conversion component 24, from reaching high temperatures.

[0094] Here, a portion of the heat conducted from the controller 23 and power conversion component 24 to the first lower wall portion 41 is conducted to the second upper wall portion 52 via the first side wall 33 and the second side wall 34. However, the amount of heat conducted from the first lower wall portion 41 to the second upper wall portion 52 via the first side wall 33 and the second side wall 34 is less than the amount of heat conducted from the wall 31 to the upper wall 32 via the first side wall 33 and the second side wall 34 when the first lower wall portion 41 and the second lower wall portion 42 are integrally formed. Therefore, the semiconductor memory component 27 (e.g., the second semiconductor memory component 27B) can be prevented from reaching high temperatures.

[0095] Similarly, the power circuit component 25 is connected to the first upper wall portion 51, for example, via a thermally conductive component 71D. Therefore, a portion of the heat generated from the power circuit component 25 is conducted to the first upper wall portion 51 via the thermally conductive component 71D. Consequently, the temperature of the first upper wall portion 51 rises. However, since the first upper wall portion 51 and the second upper wall portion 52 are not integrally formed, the heat conducted from the power circuit component 25 to the first upper wall portion 51 is difficult to conduct from the first upper wall portion 51 to the second upper wall portion 52. Therefore, compared to the case where the first upper wall portion 51 and the second upper wall portion 52 are integrally formed, the temperature of the second upper wall portion 52 is less likely to rise. As a result, it is possible to prevent semiconductor memory components 27 (e.g., the second semiconductor memory component 27B), whose heat resistance is lower than that of the power circuit component 25, from reaching high temperatures.

[0096] Here, a portion of the heat conducted from the power circuit component 25 to the first upper wall portion 51 is conducted to the second lower wall portion 42 via the third connection portion 61 and the fourth connection portion 62. However, the amount of heat conducted from the first upper wall portion 51 to the second lower wall portion 42 via the third connection portion 61 and the fourth connection portion 62 is less than the amount of heat conducted from the upper wall 32 to the lower wall 31 via the first side wall 33 and the second side wall 34 when the first upper wall portion 51 and the second upper wall portion 52 are integrally formed. Therefore, it is possible to suppress the semiconductor memory component 27 (e.g., the first semiconductor memory component 27A) from becoming too high.

[0097] <6. Advantages>

[0098] In this embodiment, the housing 10 includes: a first lower wall portion 41 located on the -Z direction side relative to the substrate 21 and facing the substrate 21 in a first region R1; a second lower wall portion 42 located on the -Z direction side relative to the substrate 21 and facing the substrate 21 in a second region R2; a first upper wall portion 51 located on the +Z direction side relative to the substrate 21 and facing the substrate 21 in the first region R1; and a second upper wall portion 52 located on the +Z direction side relative to the substrate 21 and facing the substrate 21 in the second region R2. The first lower wall portion 41 and the second upper wall portion 52 are formed by a first component M1. The second lower wall portion 42 and the first upper wall portion 51 are formed by a second component M2. That is, the first lower wall portion 41 and the second lower wall portion 42 are formed to be separable from each other. In addition, the first upper wall portion 51 and the second upper wall portion 52 are formed to be separable from each other. With this configuration, compared to the case where the first lower wall portion 41 and the second lower wall portion 42 are integral, heat conduction from the first lower wall portion 41 to the second lower wall portion 42 can be suppressed; and compared to the case where the first upper wall portion 51 and the second upper wall portion 52 are integral, heat conduction from the first upper wall portion 51 to the second upper wall portion 52 can be suppressed. Therefore, the temperature rise of the semiconductor memory component 27 can be suppressed. As a result, the reliability of the semiconductor memory device 1 can be improved. Furthermore, with the above configuration, compared to the case where the first lower wall portion 41, the second lower wall portion 42, the first upper wall portion 51, and the second upper wall portion 52 are formed from different components, the number of components can be reduced, and the rigidity of the housing 10 can be improved. From this perspective, the reliability of the semiconductor memory device 1 can also be improved.

[0099] In this embodiment, the housing 10 has a first portion between the first lower wall portion 41 and the second lower wall portion 42, where the thermal conductivity is lower than that of the first lower wall portion 41. With this configuration, heat conduction from the first lower wall portion 41 to the second lower wall portion 42 can be further suppressed.

[0100] In this embodiment, the first portion is the first gap S1 provided between the first lower wall portion 41 and the second lower wall portion 42. With this configuration, heat conduction from the first lower wall portion 41 to the second lower wall portion 42 can be further suppressed. Furthermore, when the semiconductor memory device 1 is placed in an environment where cooling air is supplied around the housing 10, it is expected that a portion of the cooling air will flow into the housing 10 through the first gap S1. Therefore, the temperature rise of the semiconductor memory component 27 can be further suppressed.

[0101] In this embodiment, the housing 10 has a second portion between the first upper wall portion 51 and the second upper wall portion 52, which has a lower thermal conductivity than the first upper wall portion 51. With this configuration, heat conduction from the first upper wall portion 51 to the second upper wall portion 52 can be further suppressed.

[0102] In this embodiment, the first component M1 has a first sidewall 33 and a second sidewall 34, which are separately disposed at both ends of the housing 10 in the Y direction and respectively connect the first lower wall portion 41 and the second upper wall portion 52. The second component M2 has a third connecting portion 61 and a fourth connecting portion 62, which are disposed between the first sidewall 33 and the second sidewall 34 in the Y direction and respectively connect the second lower wall portion 42 and the first upper wall portion 51. With this configuration, the first lower wall portion 41 and the second upper wall portion 52, and the second lower wall portion 42 and the first upper wall portion 51, can be connected with a relatively simple configuration. As a result, it is easy to ensure that the internal space of the housing 10 is relatively wide.

[0103] In this embodiment, the first sidewall 33 and the second sidewall 34 are exposed outside the housing 10. With this configuration, when the semiconductor memory device 1 is placed in an environment where cooling air is supplied around the housing 10, the first sidewall 33 and the second sidewall 34 connecting the first lower wall portion 41 and the second upper wall portion 52 are cooled by the cooling air. Therefore, heat conduction from the first lower wall portion 41 to the second upper wall portion 52 can be further suppressed.

[0104] In this embodiment, the thickness T2 of the first sidewall 33 in the Y direction is thinner than the thickness T1 of the first lower wall portion 41 in the Z direction. With this configuration, heat is less likely to be conducted through the first sidewall 33 compared to a case where the first sidewall 33 is thicker. Therefore, heat conduction from the first lower wall portion 41 to the second upper wall portion 52 can be further suppressed.

[0105] In this embodiment, the length L2 of the third connecting portion 61 in the X direction is shorter than the length L1 of the first sidewall 33 in the X direction. That is, the third connecting portion 61, which is unlikely to be cooled by the surrounding cooling air supplied to the housing 10, is formed to be relatively small. With this configuration, since the third connecting portion 61 is relatively small, heat is difficult to conduct in the third connecting portion 61. Therefore, heat conduction from the first upper wall portion 51 to the second lower wall portion 42 can be further suppressed.

[0106] In this embodiment, the thickness T3 of the third connecting portion 61 in the Y direction is thinner than the thickness T4 of the second lower wall portion 42 in the Z direction. With this configuration, heat is less likely to be conducted within the third connecting portion 61 compared to a thicker third connecting portion 61. Therefore, heat conduction from the first upper wall portion 51 to the second lower wall portion 42 can be further suppressed.

[0107] In this embodiment, the housing 10 has a third gap S3 located in the Y direction between the second component M2 and the first sidewall 33 and exposed on the outside of the housing 10. With this configuration, when the semiconductor memory device 1 is placed in an environment where cooling air is supplied to the surroundings of the housing 10, a portion of the cooling air can be expected to flow into the housing 10 through the third gap S3. This further suppresses the temperature rise of the semiconductor memory component 27.

[0108] In this embodiment, the length direction of the third gap S3 is the X direction. With this configuration, when the semiconductor memory device 1 is placed in an environment where cooling air is supplied to the periphery of the housing 10 along the X direction, it is expected that more cooling air will flow into the housing 10 from the third gap S3.

[0109] In this embodiment, the boundary between the first lower wall portion 41 and the second lower wall portion 42 is located in the X direction closer to the center of the housing 10 than the first end portion 10e1 and the second end portion 10e2 of the housing 10. Similarly, the boundary between the first upper wall portion 51 and the second upper wall portion 52 is located in the X direction closer to the center of the housing 10 than the first end portion 10e1 and the second end portion 10e2 of the housing 10. With this configuration, compared to the case where the boundary portion is located near the first end portion 10e1 or the second end portion 10e2 of the housing 10, for example... Figure 8 As shown, in assembly operations that involve rotation, the stability of the assembly operation can be improved.

[0110] In this embodiment, the inner surface of the housing 10 has a second recess U2 that avoids the capacitor 28. The second recess U2 is provided throughout the first lower wall portion 41 and the second lower wall portion 42. With this configuration, a portion of the adjacent parts of the first lower wall portion 41 and the second lower wall portion 42 is formed thinner, which can further suppress the conduction of heat from the first lower wall portion 41 to the second lower wall portion 42.

[0111] In this embodiment, the substrate 21 is clamped and fixed between the first lower wall portion 41 and the first upper wall portion 51, and is also clamped and fixed between the second lower wall portion 42 and the second upper wall portion 52. With this configuration, the substrate 21 can be stably fixed in a configuration where the first lower wall portion 41 and the second lower wall portion 42 are not integral, and the first upper wall portion 51 and the second upper wall portion 52 are not integral.

[0112] (Second Implementation)

[0113] Next, the second embodiment will be described. In the second embodiment, the configuration is the same as that of the first embodiment, except as described below.

[0114] Figure 12This is an exploded perspective view of the housing 10A according to the second embodiment. In this embodiment, the housing 10A includes a first component M1, a third component M3A, and a fourth component M4A.

[0115] The first component M1 is the same as in the first embodiment, including a first lower wall portion 41, a second upper wall portion 52, a first side wall 33, and a second side wall 34. The third component M3A includes the second lower wall portion 42. The fourth component M4A includes the first upper wall portion 51. That is, in this embodiment, the second lower wall portion 42 and the first upper wall portion 51 are formed by multiple different components. The third component M3A (i.e., the second lower wall portion 42) and the fourth component M4A (i.e., the first upper wall portion 51) are respectively mounted relative to the first component M1. In this embodiment, the first lower wall portion 41 is an example of a "first wall portion". The second lower wall portion 42 is an example of a "second wall portion". The first upper wall portion 51 is an example of a "third wall portion". The second upper wall portion 52 is an example of a "fourth wall portion".

[0116] With this configuration, heat conduction from the first lower wall portion 41 to the second lower wall portion 42 and from the first upper wall portion 51 to the second upper wall portion 52 can be suppressed. As a result, the reliability of the semiconductor memory device 1 can be improved.

[0117] (Third implementation method)

[0118] Next, the third embodiment will be described. In the third embodiment, the configuration is the same as that of the first embodiment, except as described below.

[0119] Figure 13 This is an exploded perspective view of the housing 10B according to the third embodiment. In this embodiment, the housing 10B includes a fifth component M5B, a sixth component M6B, and a second component M2.

[0120] The second component M2 is the same as in the first embodiment, including a first upper wall portion 51, a second lower wall portion 42, a third connecting portion 61, and a fourth connecting portion 62. The fifth component M5B includes the first lower wall portion 41, a first portion 33a that is part of the first side wall 33, and a first portion 34a that is part of the second side wall 34. The sixth component M6B includes the second upper wall portion 52, a second portion 33b that is the remainder of the first side wall 33, and a second portion 34b that is the remainder of the second side wall 34. That is, in this embodiment, the first lower wall portion 41 and the second upper wall portion 52 are formed from multiple different components. The fifth component M5B (i.e., the first lower wall portion 41) and the sixth component M6B (i.e., the second upper wall portion 52) are respectively mounted relative to the second component M2. In this embodiment, the first upper wall portion 51 is an example of a "first wall portion." The second upper wall portion 52 is an example of a "second wall portion." The first lower wall portion 41 is an example of a "third wall portion." The second lower wall portion 42 is an example of the "fourth wall portion".

[0121] With this configuration, heat conduction from the first lower wall portion 41 to the second lower wall portion 42 and from the first upper wall portion 51 to the second upper wall portion 52 can be suppressed. As a result, the reliability of the semiconductor memory device 1 can be improved.

[0122] (Fourth Implementation)

[0123] Next, the fourth embodiment will be described. In the fourth embodiment, the configuration is the same as that of the first embodiment, except as described below.

[0124] Figure 14 This is an exploded perspective view of the housing 10C according to the fourth embodiment. In this embodiment, the housing 10C includes a seventh component M7C, an eighth component M8C, a ninth component M9C, and a tenth component M10C.

[0125] The seventh component M7C includes a first lower wall portion 41, a first portion 33a that is part of a first side wall 33, and a first portion 34a that is part of a second side wall 34. The eighth component M8C includes a second lower wall portion 42. The ninth component M9C includes a first upper wall portion 51. The tenth component M10C includes a second upper wall portion 52, a second portion 33b that is part of the remainder of the first side wall 33, and a second portion 34b that is part of the remainder of the second side wall 34. That is, in this embodiment, the first lower wall portion 41, the second lower wall portion 42, the first upper wall portion 51, and the second upper wall portion 52 are formed by multiple mutually different components. In this embodiment, the first lower wall portion 41 is an example of a "first wall portion." The second lower wall portion 42 is an example of a "second wall portion." The first upper wall portion 51 is an example of a "third wall portion." The second upper wall portion 52 is an example of a "fourth wall portion."

[0126] With this configuration, heat conduction from the first lower wall portion 41 to the second lower wall portion 42 and from the first upper wall portion 51 to the second upper wall portion 52 can be suppressed. As a result, the reliability of the semiconductor memory device 1 can be improved.

[0127] Several embodiments have been described above, but the embodiments are not limited to the examples described above. For example, instead of forming a second recess U2 to avoid electronic components (e.g., capacitor 28) throughout the first lower wall portion 41 and the second lower wall portion 42, the same recess may be formed throughout the first upper wall portion 51 and the second upper wall portion 52. In the above embodiments, a heat-generating component (controller 23, etc.) is mounted in the first region R1 of the substrate 21, and a semiconductor memory component 27 is mounted in the second region R2 of the substrate 21. Alternatively, the semiconductor memory component 27 may be mounted in the first region R1 of the substrate 21, and the heat-generating component (controller 23, etc.) may be mounted in the second region R2 of the substrate 21.

[0128] According to at least one embodiment described above, the housing of a semiconductor memory device includes: a first wall portion located on a first side of the substrate and facing a first region of the substrate in a first direction that is the thickness direction of the substrate; a second wall portion located on the first side of the substrate and facing a second region of the substrate in the first direction; a third wall portion located on a second side of the substrate opposite to the first side in the first direction and facing the first region; and a fourth wall portion located on the second side of the substrate and facing the second region in the first direction. The first wall portion is formed by a first component. The second wall portion is formed by a component different from the first component. The third wall portion is formed by a second component. The fourth wall portion is formed by a component different from the second component. With this configuration, the reliability of the semiconductor memory device can be improved.

[0129] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device, characterized in that, have: case; A substrate, housed in the housing, includes a first region and a second region different from the first region; The controller is installed in one of the first area and the second area; as well as A semiconductor memory component is mounted in one of the first and second regions. The controller is configured to control the semiconductor memory component. The housing has: a first wall portion located on a first side relative to the substrate and facing the first region in a first direction that is the thickness direction of the substrate; a second wall portion located on the first side relative to the substrate and facing the second region in the first direction; and a third wall portion located on a second side opposite to the first side relative to the substrate in the first direction and facing the first region. And a fourth wall portion, which is located on the second side relative to the substrate in the first direction and faces the second region. The first wall portion and the second wall portion are configured to be separable from each other. The third wall portion and the fourth wall portion are configured to be separable from each other. The first wall portion and the second wall portion do not overlap in the first direction. The third wall portion and the fourth wall portion do not overlap in the first direction. The housing includes a first component. The first component includes the first wall portion and the fourth wall portion.

2. The semiconductor memory device as claimed in claim 1, characterized in that, The housing has a first portion between the first wall portion and the second wall portion in a second direction from the first wall portion toward the second wall portion, the thermal conductivity of the first portion being lower than that of the first wall portion.

3. The semiconductor memory device as claimed in claim 1, characterized in that, In a second direction from the first wall portion toward the second wall portion, the second wall portion is configured to have a gap with the first wall portion.

4. The semiconductor memory device as claimed in claim 3, characterized in that, The length direction of the gap is along a third direction that intersects the first direction and the second direction.

5. The semiconductor memory device as claimed in any one of claims 2 to 4, characterized in that, The housing has a second portion in the second direction between the third wall portion and the fourth wall portion, the thermal conductivity of the second portion being lower than that of the third wall portion.

6. The semiconductor memory device as claimed in claim 1, characterized in that, The housing also includes a second component. The second component includes the second wall portion and the third wall portion.

7. The semiconductor memory device as claimed in claim 6, characterized in that, The first component has a first connecting portion and a second connecting portion, which are separately disposed upwards on a third direction intersecting the first direction and intersecting the second direction from the first wall portion toward the second wall portion, and are respectively connected to the first wall portion and the fourth wall portion. The second component has a third connecting portion and a fourth connecting portion, which are separately disposed in the third direction and respectively connect the second wall portion to the third wall portion.

8. The semiconductor memory device as claimed in claim 7, characterized in that, The first connecting portion and the second connecting portion are respectively the fifth wall portion and the sixth wall portion exposed to the outside of the housing.

9. The semiconductor memory device as claimed in claim 8, characterized in that, The thickness of the fifth wall portion in the third direction is thinner than the thickness of the first wall portion in the first direction.

10. The semiconductor memory device as claimed in claim 8 or 9, characterized in that, The length of the third connecting portion in the second direction is shorter than the length of the fifth wall portion in the second direction.

11. The semiconductor memory device as claimed in claim 8 or 9, characterized in that, The thickness of the third connecting portion in the third direction is thinner than the thickness of the second wall portion in the first direction.

12. The semiconductor memory device as claimed in claim 8 or 9, characterized in that, The housing has a gap that is disposed between the second component and the fifth wall portion in the third direction and protrudes to the outside of the housing.

13. The semiconductor memory device as claimed in claim 1, characterized in that, The housing has a first end and a second end in a second direction from the first wall portion toward the second wall portion, the second end being located on the side opposite to the first end portion. The distance between the first boundary portion of the first wall portion and the first end portion is greater than the distance between the first boundary portion and the central portion of the housing in the second direction. The distance between the first boundary portion and the second end portion is greater than the distance between the first boundary portion and the central portion. The distance between the second boundary portion of the third wall portion and the first end portion is greater than the distance between the second boundary portion and the central portion. The distance between the second boundary portion and the second end portion is greater than the distance between the second boundary portion and the central portion.

14. The semiconductor memory device as claimed in claim 1, characterized in that, The semiconductor memory device also includes electronic components mounted on the substrate. The inner surface of the housing has recesses that avoid the electronic components. The recess is provided throughout the first wall portion and the second wall portion, or throughout the third wall portion and the fourth wall portion.

15. The semiconductor memory device as claimed in claim 1, characterized in that, The first wall portion includes a first support portion that protrudes in a direction from the first wall portion toward the third wall portion. The second wall portion includes a second support portion that protrudes in a direction from the second wall portion toward the fourth wall portion. The third wall portion includes a third support portion that protrudes in a direction from the third wall portion toward the first wall portion. The fourth wall portion includes a fourth support portion that protrudes in a direction from the fourth wall portion toward the second wall portion. The substrate is fixed between the first support portion and the third support portion, and is also fixed between the second support portion and the fourth support portion.

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