Package structure and method of manufacturing the same

Abstract

A package structure includes a first / second / third package assembly, a thermal interface material structure overlying the first package assembly and relative to the second package assembly, and a heat dissipation assembly disposed on the third package assembly and thermally coupled to the first package assembly through the thermal interface material structure. The first package assembly includes a plurality of semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies, the second package assembly is interposed between the first and third package assemblies, and the semiconductor dies are electrically coupled to the third package assembly through the second package assembly. The thermal interface material structure includes a dielectric dam and a plurality of thermally conductive members including an electrically conductive material, the thermally conductive members are disposed within an area enclosed by the dielectric dam and overlying the semiconductor dies. A method of fabricating the package structure is also provided.

Description

Technical Field

[0001] The embodiments of the present invention relate to a packaging structure and a method for manufacturing the same, specifically to a packaging structure comprising a thermal interface material structure having a dielectric dam and a method for manufacturing the same. Background Technology

[0002] With the continuous miniaturization of electronic products, heat dissipation in packaging structures has become a crucial issue in packaging technology. In some embodiments, a thermal interface material may be disposed between the back side of the semiconductor die and the heat sink. With such an arrangement, damage may occur depending on the type of thermal interface material used. For example, thermomechanical stress may be generated due to the difference in the coefficient of thermal expansion between the heat sink, the semiconductor die, and the thermal interface material. Furthermore, cracks may appear within the rigid thermal interface material itself or within the semiconductor die, while grease-type thermal interface materials may experience a decrease in thermal performance during temperature cycling. Therefore, continuous efforts are being made to develop new mechanisms for forming packaging structures with better reliability and performance. Summary of the Invention

[0003] According to some embodiments, the packaging structure includes a first packaging component, a second packaging component inserted between the first packaging component and a third packaging component, a thermal interface material structure covering the first packaging component and relative to the second packaging component, and a heat dissipation component disposed on the third packaging component and thermally coupled to the first packaging component through the thermal interface material structure. The first packaging component includes a plurality of semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies. The semiconductor dies are electrically coupled to the third packaging component through the second packaging component. The thermal interface material structure includes a dielectric dam and a plurality of thermally conductive members, the thermally conductive members comprising a conductive material, and the thermally conductive members covering the semiconductor dies are disposed within the area enclosed by the dielectric dam.

[0004] According to some embodiments, the packaging structure includes a packaging substrate, a device package, a thermal interface material structure, and a heat dissipation assembly disposed on the packaging substrate and housing the device therein. The device package includes a plurality of semiconductor dies coupled to an interposer and encapsulated by an insulating encapsulator. The packaging substrate is electrically coupled to the semiconductor dies through the interposer. The thermal interface material structure includes a plurality of thermally conductive members spatially separated from each other and covering the semiconductor dies. The device package is thermally coupled to the heat dissipation assembly through the thermal interface material structure.

[0005] According to some embodiments, a method of manufacturing a package structure includes at least the following steps: Coupling a device package to a package substrate, wherein the device package includes a plurality of semiconductor dies encapsulated by an insulating encapsulator and electrically coupled to the package substrate. Forming a first dielectric pattern on the device package opposite the package substrate, wherein the first dielectric pattern includes a plurality of openings corresponding to the semiconductor dies of the device package. Forming a thermally conductive material on the semiconductor dies of the device package and in the openings of the first dielectric pattern. Placing a heat dissipation assembly on the device package and the package substrate, the heat dissipation assembly contacting the first dielectric pattern and the thermally conductive material. Performing a thermal processing step on the first dielectric pattern and the thermally conductive material to form a thermal interface material structure coupling the heat dissipation assembly to the device package. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A-1E These are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments.

[0008] Figure 1F This is a schematic cross-sectional view of the packaging structure according to some embodiments.

[0009] Figure 2A Based on some embodiments Figure 1B A schematic top view of the structure shown.

[0010] Figure 2B Based on some embodiments Figure 1C A schematic top view of the structure shown.

[0011] Figure 2C Based on some embodiments Figure 1D A schematic enlarged view of the dashed box A shown in the diagram.

[0012] Figure 2D Based on some embodiments Figure 1D A schematic enlarged view of the dashed box B shown in the diagram.

[0013] Figure 3 This is a schematic enlarged view of a portion of another implementation of the packaging structure according to some embodiments.

[0014] Figure 4A Based on some embodiments Figure 1C A schematic top view of another embodiment of the structure shown.

[0015] Figure 4B This is a schematic enlarged view of a portion of another implementation of the packaging structure according to some embodiments.

[0016] Figure 5 Based on some embodiments Figure 1C A schematic top view of another embodiment of the structure shown.

[0017] Figures 6A-6C These are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments.

[0018] Figure 7 Based on some embodiments Figure 6C The diagram shows an enlarged view of the dashed box C.

[0019] Figure 8A This is a schematic cross-sectional view of the packaging structure according to some embodiments.

[0020] Figure 8B Based on some embodiments Figure 8A A schematic enlarged view of the dashed box D shown.

[0021] Figures 9A-9B These are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments.

[0022] Figure 10 This is a schematic cross-sectional view of the packaging structure according to some embodiments.

[0023] [Icon Symbol Explanation]

[0024] 10: Device packaging;

[0025] 10t, 120a, 420s: Upper surface;

[0026] 40: Fourth encapsulation component;

[0027] 45: Device connector;

[0028] 50: Fifth encapsulation component;

[0029] 100: First encapsulation component;

[0030] 110: Semiconductor die;

[0031] 110D, LD: Lateral dimensions;

[0032] 110a, 200a: First side;

[0033] 110b, 200b: Second side;

[0034] 110s, 300s, 410s, 430s, SW: sidewall;

[0035] 112: Core connector;

[0036] 114: Inner interconnect layer;

[0037] 116, 214: Semiconductor substrate;

[0038] 120: Insulating encapsulation;

[0039] 200: Second encapsulation component;

[0040] 211: Conductive terminal;

[0041] 212: Internal interconnect structure;

[0042] 216: Conductive perforation;

[0043] 218, 312a: Conductive patterns;

[0044] 300: Third encapsulation component;

[0045] 300b: Bottom side;

[0046] 300t: Top side;

[0047] 305: Mask layer;

[0048] 311: Contact pad;

[0049] 312: Trace layer;

[0050] 312b: Through hole;

[0051] 312c: Dielectric layer;

[0052] 320: External terminal;

[0053] 400A, 400A', 400B, 400C, 400D, 400E, 400F: Thermal interface material structure;

[0054] 405, 410, 410': Conductive layers;

[0055] 410T, 420T, 420T', 430T, 510T: Thickness;

[0056] 420, 420', 610, 620: First dielectric component;

[0057] 420A, 420B, 420C: First dielectric pattern;

[0058] 420IW, 420IW', 420i: Inner sidewall;

[0059] 420OW, 510s: outer sidewall;

[0060] 420m: Lower surface;

[0061] 420p, 620p: External protrusions;

[0062] 420q: Internal protrusion;

[0063] 430, 430', 630: Thermally conductive components;

[0064] 430A, 430B, 430C, 630A: Conductive material patterns;

[0065] 510: Second dielectric component;

[0066] 510A: Second dielectric pattern;

[0067] 520: Capped;

[0068] 520e: end;

[0069] 620b: Bottom surface;

[0070] 620t: Top surface;

[0071] A, B, C, D: Dashed boxes;

[0072] GP1: Lateral distance;

[0073] GP2, GP3: gaps;

[0074] OP1, OP2, OP3: Openings;

[0075] PS1, PS1', PS2, PS3, PS4, PS5: Packaging structure;

[0076] R1: Zone 1;

[0077] R2: Second Zone;

[0078] R3: Third District;

[0079] U1, U2, U3: Dispensing unit;

[0080] UF1, UF2: Base layer. Detailed Implementation

[0081] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0082] Furthermore, to facilitate the description of the relationship between one element or feature and another element or feature(s) shown in the diagrams, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0083] This disclosure may also include other features and processes. For example, it may include test structures to assist in verification testing of 3D packages or 3DIC devices. For instance, the test structure may include test pads formed in redistribution layers or on a substrate, which can be used to test 3D packages or 3DICs using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0084] Figure 1A-1E These are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments. Figure 2A Based on some embodiments Figure 1B A schematic top view of the structure shown. Figure 2B Based on some embodiments Figure 1C A schematic top view of the structure shown. Figure 2C Based on some embodiments Figure 1D A schematic enlarged view of the dashed box A shown, and Figure 2D Based on some embodiments Figure 1D A schematic enlarged view of the dashed box B shown in the diagram.

[0085] Reference Figure 1A A first packaging component 100 may be disposed on a second packaging component 200. A stack of the first packaging component 100 and the second packaging component 200 may be mounted on a third packaging component 300, with the second packaging component 200 interposed between the first packaging component 100 and the third packaging component 300. In some embodiments, the first packaging component 100 and the second packaging component 200 may be collectively referred to as device package 10. For example, the first packaging component 100 includes a plurality of semiconductor dies 110 arranged side-by-side and encapsulated by an insulating encapsulator 120. In some embodiments, the semiconductor dies 110 are electrically coupled to each other through the second packaging component 200.

[0086] Each semiconductor die 110 may include a first side 110a facing the second package assembly 200, a second side 110b opposite to the first side 110a, and sidewalls 110s connected to the first side 110a and the second side 110b. In some embodiments, the semiconductor die 110 includes die connectors 112 (e.g., micro-bumps, metal pillars with or without a capping layer, controlled collapse chip connection (C4) bumps, or the like) distributed on the first side 110a for electrical connection to the second package assembly 200. Each semiconductor die 110 may include (or may not include) an interconnect layer 114 for connecting active / passive devices (not shown) formed on / in a semiconductor substrate 116 to the die connectors 112. The semiconductor substrate 116 may refer to one or more semiconductor materials, including but not limited to bulk silicon, semiconductor wafers, silicon-germanium substrates, silicon-on-insulator (SOI) substrates, or the like. Other semiconductor materials, including Group 3, Group 4, and Group 5 elements, can be used. In some embodiments, the interconnect layer 114 includes a plurality of dielectric layers, metal lines formed in the dielectric layers, and vias formed between the upper and lower metal lines. It should be noted that the architecture and number of semiconductor dies 110 shown herein are for illustrative purposes only, and any other semiconductor die architecture and number may be used depending on product requirements.

[0087] Continue to refer to Figure 1AIn some embodiments, each semiconductor die 110 may have a single function (e.g., a logic die, a processor die (such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, an application-specific integrated circuit (ASIC) die, etc.), a memory die (such as a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, a stacked memory module, a high-bandwidth memory (HBM) die, etc.), a radio frequency die, a mixed-signal die, an input / output (I / O) die, a combination thereof, and / or the like). For example, the semiconductor die 110 may be formed in a device wafer (not shown) comprising different die regions that are monolithically converted to form multiple device dies. After monolithization, the semiconductor die 110 is mounted at a predetermined location in the second package assembly 200. In some embodiments, semiconductor dies 110 may have different dimensions (e.g., occupied area) and different functions. For example, at least one of the semiconductor dies 110 may be formed as a die stack with multiple functions (e.g., a system-on-chip or the like). For example, semiconductor die 110 includes an interface module that bridges a processor module to a memory module and translates instructions between them. Alternatively, semiconductor dies 110 may have the same / similar dimensions. Other types of semiconductor dies may be used depending on product requirements.

[0088] In some embodiments, the insulating encapsulation 120 extends at least along the sidewalls 110s in the semiconductor die 110 as a protection. The insulating encapsulation 120 may be or may include molding compounds, epoxy resins, molding underfills, and / or the like, and may be applied by compression molding, transfer molding, etc. For example, the insulating encapsulation 120 is formed on the second package assembly 200, and the semiconductor die 110 may be buried or covered by the insulating encapsulation 120. In some embodiments, the insulating encapsulation 120 is thinned to expose the back surface of the semiconductor die 110 (such as the second side 110b). The thinning process may be performed by chemical-mechanical polishing (CMP), grinding, etching, combinations thereof, and / or the like. In some embodiments, after the thinning process, the upper surface 120a of the insulating encapsulation 120 and the back surface of the semiconductor die 110 (such as the second side 110b) may be substantially flush.

[0089] In some embodiments, an undercoat layer UF1 is formed between the gaps of the respective semiconductor dies 110 and the second package assembly 200 to laterally cover the electrical connection between the die connector 116 and the second package assembly 200. In some embodiments, a sufficient amount of undercoat material is applied between the second package assembly 200 and the semiconductor die 110 to which the flip chip has been mounted, and a portion of the undercoat layer UF1 may rise to at least partially cover the sidewalls 110s of the semiconductor die 110. An insulating encapsulation 120 may be formed after the formation of the undercoat layer UF1, such that the remaining portions of the sidewalls 110s of the semiconductor die 110 not covered by the undercoat layer UF1 may be covered by the insulating encapsulation 120. Alternatively, the undercoat layer UF1 may be omitted, and the gap between the semiconductor die 110 and the second package assembly 200 may be covered by the insulating encapsulation 120.

[0090] Continue to refer to Figure 1AA conductive layer 410 may be formed on the back side (e.g., the second side 110b) of the semiconductor die 110. In some embodiments, the conductive layer 410 is formed on the semiconductor die 110 and extends to cover the upper surface 120a of the insulating encapsulation 120. According to some embodiments, the conductive layer 410 may be referred to as a back-side metal layer. In some embodiments, the conductive layer 410 is formed on the first package assembly 100 before a monomerization process is performed to separate the device package 10 from each other. Alternatively, the conductive layer 410 is formed after monomerization into the device package 10. The conductive layer 410 may include titanium (Ti), copper (Cu), nickel (Ni), vanadium (V), aluminum (Al), cobalt (Co), gold (Au), silver (Ag), stainless steel, or other suitable conductive materials having relatively high thermal conductivity. The conductive layer 410 may be or may include one or more layers of conductive material. For example, the conductive layer 410 may optionally include a seed material sublayer (e.g., a titanium / copper thin layer) that allows subsequently deposited conductive material to adhere thereto. In some embodiments, the conductive layer 410 is formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, evaporation, sputtering, and / or other suitable processes. For example, the thickness 410T in the conductive layer 410 is approximately The range is between approximately 5 micrometers (μm). Alternatively, the conductive layer 410 may be formed as a sporadic conductive pattern overlying the semiconductor die 110, or the conductive layer 410 may be omitted as will be described later in other embodiments.

[0091] Continue to refer to Figure 1AThe second package assembly 200 may include (or may not include) active devices and / or passive devices. In some embodiments, the second package assembly 200 serves as an intermediary. For example, the second package assembly 200 includes an interconnect structure 212 on a first side 200a of the second package assembly 200. The interconnect structure 212 may include multiple dielectric layers, conductive patterns embedded in the dielectric layers, and vias connecting the conductive patterns of two vertically adjacent layers. In some other embodiments, the interconnect structure is formed on a second side 200b opposite to the first side 200a for electrical connection to the semiconductor die 110. Alternatively, the interconnect structure is formed on both the first side 200a and the second side 200b. In some embodiments, the second package assembly 200 includes a plurality of conductive terminals 211 distributed on the first side 200a and connecting the interconnect structure 212 and the third package assembly 300. The conductive terminal 211 may be or may include controlled collapse chip connection (C4) bumps, metal pillars, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, solder balls, ball-grid-array (BGA) connectors and / or the like.

[0092] In some embodiments, the interconnect structure 212 is formed on the semiconductor substrate 214. The semiconductor substrate 214 may be made of a material similar to that of the semiconductor substrate 116 or may be formed of other suitable materials. The second package assembly 200 may include a plurality of conductive vias 216 penetrating the semiconductor substrate 214 to provide a vertical electrical connection between opposite sides of the semiconductor substrate 214. For example, the conductive vias 216 are electrically connected to the conductive pattern of the interconnect structure 212 and extend toward the first package assembly 100 to connect to the conductive pattern 218 (such as a contact pad) on a second side 200b of the second package assembly 200. The die connector 112 of the first package assembly 110 may be in physical and electrical contact with one side of the conductive pattern 218, while the conductive vias 216 connect to the other side of the conductive pattern 218. The second packaging assembly 200 may optionally include a dielectric layer formed on a semiconductor substrate 214 to cover a conductive pattern 218 (such as a contact pad) for protection, while an insulating encapsulator 120 (and an undercoat layer UF1, if present) may be formed on the dielectric layer.

[0093] In some other embodiments, the second package assembly 200 is formed as a fan-out redistribution structure, wherein the semiconductor substrate 214 and conductive vias 216 may be omitted or replaced by one or more other interconnect layers. In this case, the first package assembly and the second package assembly are collectively referred to as an integrated fan-out package. It should be noted that the second package assembly 200 shown herein is for illustrative purposes only, and more or fewer components may be arranged in the second package assembly 200. In some embodiments, the second package assembly 200 and the first package assembly 100 disposed thereon are formed in wafer form and then monomerized by a monomerization process, thereby separating the stack of the first package assembly and the second package assembly into a plurality of device packages 10. In this way, the outer sidewalls of the first package assembly 100 and the outer sidewalls of the second package assembly 200 are substantially flush. For example, the device package 10 resulting after monomerization, including the first package assembly 100 and the second package assembly 200, has an edge formed by the continuous sidewalls SW of the interconnect structure 212, the semiconductor substrate 214, and the insulating encapsulation 120.

[0094] Still refer to Figure 1A The third encapsulation component 300 can make physical and electrical contact with the conductive terminals 211 of the second encapsulation component 200. For example, after monomerization, the resulting device package 10 can be mounted onto the top side 300t of the third encapsulation component 300 by a reflow process or other suitable one or more techniques. In some embodiments, an undercoat layer UF2 is formed between the second encapsulation component 200 and the third encapsulation component 300 to surround the conductive terminals 211 for protection. In some embodiments, sufficient amount of undercoat material is applied, and a portion of the undercoat layer UF2 can rise to at least partially cover the sidewall SW of the second encapsulation component 200 or even cover the first encapsulation component 100. Alternatively, the undercoat layer UF2 can be omitted.

[0095] In some embodiments, the third package assembly 300 includes contact pads 311 for abutting conductive terminals 211. Optionally, a mask layer 305 (such as a solder resist or the like) is formed to partially cover the contact pads 311 to prevent bridging and protect the underlying conductive patterns. For example, the contact pads 311 are formed on a trace layer 312, which includes conductive patterns 312a (such as wires and pads) and vias 312b embedded in a dielectric layer 312c. In some embodiments, the third package assembly 300 is a laminated package substrate in which the conductive patterns are embedded in a laminated dielectric layer. In some embodiments, the third package assembly 300 is an add-on package substrate including a core layer (not shown; for example, BT resin, FR-4, ceramic, glass, plastic, tape, add-on film, or other support material), conductive patterns added on opposite sides of the core layer, and vias through the core layer to connect the conductive patterns on opposite sides of the core layer. In some embodiments, depending on the requirements of the product, the packaging substrate is a multilayer circuit board (such as a printed circuit board, PCB) or other types of substrate.

[0096] Still refer to Figure 1A The device package 10, including the second package assembly 200 and the first package assembly 100, can be arranged in a first region R1 of the third package assembly 300. In some embodiments, the fourth package assembly 40 is engaged within a second region R2 of the third package assembly 300, wherein the first region R1 can be surrounded by the second region R2. The fourth package assembly 40 may be or may include an integrated passive device (IPD), an integrated voltage regulator (IVR), an active component, and / or the like. In some embodiments, the fourth package assembly 40 is mounted on the third package assembly 300 via a device connector 45 resting on a contact pad 311 of the third package assembly 300. Other types of connections between the third and fourth package assemblies can be used. It should be noted that... Figure 1A The two fourth encapsulation components 40 shown are for illustrative purposes only, and the number and architecture of the fourth encapsulation components 40 do not constitute a limitation of this disclosure.

[0097] Reference Figure 1B And further refer to Figure 2AA first dielectric pattern 420A with an opening OP1 can be formed on the first encapsulation assembly 100. In some embodiments, the first dielectric pattern 420A is dispensed onto a designated area of ​​the conductive layer 410 by a dispensing unit U1 (such as a printer, syringe, pump, etc.). The material provided by the dispensing unit U1 can be in the form of a solid, paste, gel, etc. In some embodiments, the first dielectric pattern 420A is an adhesive film with an opening OP1 and can be formed by a suitable lamination process to physically adhere to the conductive layer 410. The material of the first dielectric pattern 420A can be or may include one or more polymer materials such as polyimide (PI), polybenzoxazole (PBO), epoxy-based materials, silica-based materials, acrylic-based materials, etc. In some embodiments, the first dielectric pattern 420A can be or may include photosensitive materials, laminated materials, or thermally adhesive materials, etc. It should be noted that any suitable dielectric material, any suitable application method, and any suitable thickness can be used for the first dielectric pattern 420A.

[0098] The conductive layer 410 may be partially covered by the first dielectric pattern 420A and solidly interposed between the insulating encapsulation 120 and the first dielectric pattern 420A. An opening OP1 of the first dielectric pattern 420A may visibly expose a portion of the conductive layer 410. The size of the opening OP1 may correspond to the underlying semiconductor die 110. In some embodiments, each opening OP1 corresponds to any one semiconductor die 110. The opening size (e.g., lateral dimension LD) of each opening OP1 may correspond to the lateral dimension 110D (e.g., length or width) of the underlying semiconductor die 110. In some embodiments, the lateral dimension LD is substantially equal to the lateral dimension 110D of the underlying semiconductor die 110. Alternatively, the lateral dimension LD of each opening OP1 may be substantially greater than or less than the lateral dimension 110D of the underlying semiconductor die 110. In other embodiments, the openings OP1 have the same size. Alternatively, the opening size may be smaller than the semiconductor die and / or at least one of the semiconductor dies may correspond to more than one opening.

[0099] Continue to refer to Figure 1BA second dielectric pattern 510A may be formed on the third encapsulation component 300. The material of the second dielectric pattern 510A may be similar to the material of the first dielectric pattern 420A. For example, the second dielectric pattern 510A comprises a thermal adhesive having a viscous gel or liquid material. Other types of adhesives may be used. In some embodiments, the first dielectric pattern 420A and the second dielectric pattern 510A are formed from the same material in the same step by the dispensing unit U1. Alternatively, the first dielectric pattern 420A and the second dielectric pattern 510A may be formed from different dielectric materials. The second dielectric pattern 510A may be formed before or after the formation of the first dielectric pattern 420A. The thickness 510T of the second dielectric pattern 510A may be substantially the same as (or different from) the thickness 420T of the first dielectric pattern 420A, depending on the requirements of the product and not to be construed as a limitation of this disclosure.

[0100] In some embodiments, a second dielectric pattern 510A is formed on any desired area of ​​the mask layer 305 of the third package assembly 300, the area allowing subsequently mounted components to adhere thereto. For example, the second dielectric pattern 510A is formed within a third region R3, where a first region R1 may be a central region of the third package assembly 300, a third region R3 may be a peripheral region of the third package assembly 300, and a second region R2 may be between the first region R1 and the third region R3. In some embodiments, the outer sidewall 510s of the second dielectric pattern 510A may be laterally offset from the outer sidewall 300s of the third package assembly 300 by a lateral distance GP1. The lateral distance GP1 may be non-zero and may be any suitable value depending on design requirements. The second dielectric pattern 510A may be formed as a loop along the periphery surrounding the top side 300t of the third package assembly 300. For example, the device package 10 and the fourth package assembly 40 may be substantially surrounded by the second dielectric pattern 510A.

[0101] In some embodiments, the second dielectric pattern 510A is formed as a discontinuous ring with a gap GP2, such as Figure 2A As shown. For example, the second dielectric pattern 510A has a plurality of annular sides forming the portion, and the ends of the sides are spaced apart from each other by gap GP2 to allow venting during the subsequent capping connection step. Alternatively, the second dielectric pattern 510A can be formed as a continuous ring. It should be noted that... Figure 1B The shape and structure of the second dielectric pattern 510A shown are for illustrative purposes only and do not constitute a limitation of this disclosure.

[0102] Reference Figure 1C And further refer to Figure 2BA conductive material pattern 430A may be formed within an opening OP1 of the first dielectric pattern 420A to contact the conductive layer 410. The conductive material pattern 430A can be considered as a metal-containing thermal interface material that is in physical and thermal contact with the conductive layer 410. For example, the conductive layer 410 facilitates the attachment of the conductive material pattern 430A to the back surface of each semiconductor die 110 (e.g., ...). Figure 1A The second side 110b shown is illustrated. In some embodiments, the conductive material pattern 430A is a solder-containing layer. For example, the conductive material pattern 430A includes silver, copper, tin, metal alloys, combinations thereof, or any suitable material having a relatively high thermal conductivity. In some embodiments, the conductive material pattern 430A has a thermal conductivity greater than about 40 W / m·K or even greater than 50 W / m·K. For example, the thermal conductivity of the conductive material pattern 430A ranges from approximately 50 W / m·K to 250 W / m·K.

[0103] The conductive material pattern 430A may comprise a viscous gel or liquid material (such as silver paste or solder paste and / or the like) and may be formed using a dispensing process via a dispensing unit U2. In some embodiments, the conductive material pattern 430A, made of conductive paste (such as silver paste, solder paste, etc.), is heated at a temperature for a sufficient time to sinter the conductive particles into a monolithic conductive layer. During sintering, the monolithic conductive layer (such as a silver layer) bonds to the underlying conductive layer 410. The conductive material pattern 430A may be formed by any suitable deposition process or the conductive pattern may be attached to the conductive layer 410.

[0104] In some embodiments, during the formation of the conductive material pattern 430A, the first dielectric pattern 420A acts as a dam structure to prevent the conductive material pattern 430A from diffusing or overflowing. After the conductive material pattern 430A is formed, its thickness 430T may be less than (or approximately equal to) the thickness 420T of the first dielectric pattern 420A. In some embodiments where the conductive layer 410 is a copper-containing layer and the conductive material pattern 430A is a solder-containing layer, an intermetallic compound (IMC) may be formed between the conductive layer 410 and the conductive material pattern 430A. The IMC may or may not be present, depending on the materials and amounts of the conductive layer 410 and the conductive material pattern 430A; therefore, the IMC... Figure 1C The dashed line in the middle indicates that it may or may not form.

[0105] Reference Figure 1D And refer to Figure 1CThe cap 520 may be fitted to the device package 10 and the third package assembly 300. After the cap 520 is placed, the third package assembly 300 and the cap 520 may define a cavity in which the device package 10 is coupled to the third package assembly 300. In some embodiments, the cap 520 is substantially smaller than the third package assembly 300, although in other embodiments, the cap 520 has substantially similar dimensions to the third package assembly 300. It should be noted that the cap 520 may take various shapes and sizes where feasible, depending on the product requirements. The cap 520 may be rigid enough to protect the device package 10 and the third package assembly 300. In some embodiments, the cap 520 may counteract the forces exerted by mismatch caused by the coefficients of thermal expansion (CTE) between the device package 10 and the third package assembly 300.

[0106] In some embodiments, the cover 520 is configured to distribute heat generated from the device package 10 over a larger area and / or dissipate heat from the device package 10. The cover 520 may be a heat dissipation component (such as a heat sink, radiator, or the like) placed on the device package 10 by, for example, a placement process. The material of the cover 520 may be or may include copper, aluminum, gold, steel, stainless steel, metal alloys, combinations thereof, and / or other suitable materials having high thermal conductivity. In some embodiments, the cover 520 is a one-piece component. Alternatively, the cover 520 may include more than one component, which may be made of the same or different materials; for example, the cover may include a reinforcement attached to a third package component and an upper plate attached to the reinforcement.

[0107] In some embodiments, once the cap 520 is placed, a bonding step (e.g., heating) can be performed. Bonding of the cap 520 may require hardening the conductive material pattern 430A, the first dielectric pattern 420A, and the second dielectric pattern 510A in the presence and / or absence of compressive stress and / or suitable mechanical stress, whether by heating and / or other means. For example, a clamp (not shown) is used to apply force between the cap 520 and the third package assembly 300. Alternatively, the clamping force can be replaced depending on how the force is applied to the cap 520. For example, the cap 520 may be pressed toward the conductive material pattern 430A, the first dielectric pattern 420A, and the second dielectric pattern 510A such that the conductive material pattern 430A and the first dielectric pattern 420A physically attach the device package 10 to the cap 520, and the second dielectric pattern 510A physically attaches the third package assembly 300 to the cap 520.

[0108] In some embodiments, during bonding, a heat treatment process (such as curing or the like) is performed at a process temperature between about 150°C and about 200°C for a duration of about 1 hour to about 3 hours. For example, during the application of force to the cap 520, the first dielectric pattern 420A and the second dielectric pattern 510A are cured and solidified to form the first dielectric member 420 and the second dielectric member 510, respectively. In some embodiments, during the same step, a conductive material pattern 430A is cured to form a plurality of thermally conductive members 430. Alternatively, the conductive material pattern 430A is heat-treated individually depending on the type of one or more conductive materials used.

[0109] Continue to refer to Figure 1D And further refer to Figure 2C After bonding is complete, the first encapsulation component 100 of the device package 10 can be thermally coupled to the cap 520 via the thermally conductive members 430. For example, each thermally conductive member 430 metallizes the upper cap 520 to the lower conductive layer 410. In some embodiments, an intermetallic compound (IMC) is formed between the cap 520 and the thermally conductive members 430. The IMC may or may not be present on opposite sides of the thermally conductive members 430, and is therefore depicted here as dashed lines. A first dielectric member 420 may surround the periphery of each thermally conductive member 430 to hold them within a predetermined area. Depending on the material of the first dielectric member 420, the first dielectric member 420 may facilitate thermal coupling between the cap 520 and the first encapsulation component 100. The conductive layer 410, the first dielectric component 420, and the thermally conductive component 430 can be collectively referred to as the thermal interface material (TIM) structure 400A, which is inserted between the cover 520 and the device package 10 to enhance the thermal coupling between the two.

[0110] Still refer to Figure 1D and Figure 2CUnder pressure applied to the cap 520, the first dielectric pattern 420A deforms, and after formation, the first dielectric member 420 may have a thickness 420T' ranging from about 10 μm to about 200 μm. The thickness 420T' of the first dielectric member 420 may be the portion of the first dielectric member 420 interposed between the cap 520 and the conductive layer 410. Other portions of the first dielectric member 420 may have a greater thickness because the periphery of the first dielectric member 420 may extend to cover the device package 10 and even the adhesive layer UF2, as will be described in other embodiments later. For example, the first dielectric member 420 may have an outward protrusion 420p extending beyond the boundary of the conductive layer 410. In some embodiments, under pressure applied to the cap 520, the first dielectric pattern 420A tends to protrude outward beyond the area defined by the device package 10 and / or the conductive layer 410. In some embodiments, the outward protrusion 420p extends downward to cover the sidewalls 410s of the conductive layer 410. The protrusion 420p may (or may not) extend beyond the sidewall 410s of the conductive layer 410 to cover at least a portion of the sidewall SW of the device package 10 (such as the sidewall of the insulating encapsulation 120). The cross-sectional shape of the first dielectric member 420 may include, but is not limited to, an ellipse, an egg-shaped, a rectangle, a rectangle with slightly curved sides, a rectangle with two convex curved sides, or other elongated shapes. For example, the outer sidewall 420OW of the first dielectric member 420 is a surface with an absolute value of curvature greater than 0.

[0111] In some embodiments, a first dielectric pattern 420A protrudes inward to abut a conductive material pattern 430A. For example, the first dielectric member 420 has an inner protrusion 420q opposite to an outer protrusion 420p and extending laterally toward the thermally conductive member 430. The inner sidewall 420IW of the first dielectric member 420, physically connected to the thermally conductive member 430, may include a curved profile with an absolute value greater than 0 for the curvature. In some embodiments, the curvature of the inner sidewall 420IW may differ from the curvature of the outer sidewall 420OW. In a cross-sectional view, the sidewalls 430s of the respective thermally conductive members 430 and the inner sidewalls 420IW of the first dielectric member 420 may be a combination of convex and concave surfaces and may complement each other.

[0112] Still refer to Figure 1D And further refer to Figure 2DAfter bonding is complete, the third encapsulation assembly 300 can be physically coupled to the cap 520 via the second dielectric member 510. Depending on the material of the second dielectric member 510, the cap 520 can be thermally coupled to the third encapsulation assembly 300 via the second dielectric member 510. In some embodiments, the cap 520 is pressed into a second dielectric pattern 510A, and at least an end 520e of the cap 520 can be embedded in the second dielectric member 510. In some embodiments, only the lower surface of the end 520e is attached to the second dielectric member 510. In some embodiments, under pressure applied to the cap 520, the second dielectric member 510 deforms to extend outward beyond the width of the end 520e of the cap 520. The outer sidewall 510s of the second dielectric member 510 can be a curved surface with an absolute value of curvature greater than 0. In some embodiments, the cap 520 and the underlying second dielectric member 510 are located within a boundary defined by the sidewall 300s of the third encapsulation assembly 300.

[0113] Reference Figure 1E Multiple external terminals 320 may be formed on the bottom side 300b of the third package assembly 300. The device package 10 may be electrically coupled to the external terminals 320 via the third package assembly 300. The external terminals 320 may rest on bonding pads distributed on the bottom side 300b of the third package assembly 300. The third package assembly 300 and the external terminals 320 may be collectively referred to as the package substrate. The external terminals 320 may be or may include solder balls, ball grid arrays (BGAs), metal pillars, or other suitable connectors, and may be made of conductive materials such as solder, copper, gold, silver, metal alloys, combinations thereof, or other suitable conductive materials. In some embodiments, the external terminals 320 are configured to be electrically coupled to an external system (not shown) and to / from the external system to transmit signals (and / or power). For example, the external terminals 320 are formed after the cap 520 is attached, so that heat generated by the process used to form the external terminals 320 can be dissipated through the cap 520. Alternatively, the external terminal 320 may be formed before the attachment cover 520, or the external terminal 320 may be omitted.

[0114] In some embodiments, the fifth package component 50 is electrically coupled to the bottom side 300b of the third package component 300 and adjacent to the array of external terminals 320. For example, the fifth package component 50 is mounted on the third package component 300 using surface mount technology (SMT) or one or more other suitable technologies. In some embodiments, the fifth package component 50 is referred to as a surface mount device and includes one or more passive components (such as capacitors, resistors, sensors, etc., or combinations thereof). The fifth package component 50 may not include (or may include) active devices such as transistors. Alternatively, the fifth package component 50 may be omitted. It should be noted that the number and architecture of the fifth package components 50 shown herein are for illustrative purposes only and do not constitute a limitation of this disclosure. The fifth package component 50 may be mounted on the third package component 300 before or after the formation of the external terminals 320. At this point, the fabrication of the package structure PS1 is substantially complete.

[0115] Continue to refer to Figure 1E The package structure PS1 includes a thermal interface material structure 400A for reducing thermal resistance that may occur between the cap 520 and the device package 10. The thermal interface material structure 400A includes a thermally conductive member 430 for connecting the cap 520 and a conductive layer 410 covering the device package 10, and also provides an effective thermal path between the cap 520 and the underlying structure. A first dielectric member 420, laterally surrounding the thermally conductive member 430 and interposed between the cap 520 and the conductive layer 410 covering the device package 10, can serve as a dam structure to isolate the thermally conductive members 430 from each other. The first dielectric member 420 can be a reliable adhesive layer to adhere the cap 520 to the underlying structure. In some embodiments, the first dielectric member 420 serves as a buffer layer to absorb thermomechanical stress between the cap 520 and the device package 10. It is understandable that rigid thermal interface materials (such as solder) may not be able to absorb the thermomechanical stress between the cap 520 and the device package 10. Therefore, during thermal cycling, delamination or cracking may occur in rigid thermal interface materials. By forming the thermally conductive member 430 as a separate component and forming the first dielectric member 420 as a buffer layer to surround the thermally conductive member 430, a package structure PS1 with good heat dissipation efficiency and reliability can be obtained.

[0116] Figure 1F This is a schematic cross-sectional view of the packaging structure according to some embodiments. Figure 1F The package structure PS1' shown can be similar to Figure 1E The encapsulation structure PS1 shown is an example; similar reference numerals are used to denote similar components, and detailed descriptions can be omitted for brevity. (Refer to...) Figure 1F and reference Figure 1EThe difference between the packaging structures PS1 and PS1' includes the first dielectric component 610 of the thermal interface material structure 400A'.

[0117] In some embodiments, the first dielectric member 610 extends from the gap between the cap 520 and the conductive layer 410 and covers at least a portion of the adhesive layer UF2 along the sidewall of the device package 10. For example, when forming such... Figure 1B When the first dielectric pattern is formed, the dielectric material can be applied to the top surface of the base adhesive layer UF2 and the conductive layer 410 via a dispensing unit. In this way, the first dielectric component 610 of the thermal interface material structure 400A' can cover the upper sidewall of the device package 10, while the base adhesive layer UF2 covers the lower sidewall of the device package 10.

[0118] Figure 3 This is a schematic enlarged view of a portion of another implementation of the packaging structure according to some embodiments. Figure 3 The structure shown can be similar to Figure 2C The structure is shown, and the same reference numerals are used to represent the same components. (See also...) Figure 3 And further refer to Figure 2C , Figure 2C and Figure 3 The structural differences shown include a first dielectric member 620 of the thermal interface material structure 400B. For example, the conductive layer 410, the first dielectric member 620, and the thermally conductive member 430 are collectively referred to as the thermal interface material structure 400B, wherein the first dielectric member 620 is made of a sheet with openings. The sheet may be or may include a composite polymer sheet containing additives such as graphite, carbon nanotubes (CNTs), or the like. Other suitable attachment films may be used. In some embodiments, the sheet is attached to the conductive layer 410 to form a first dielectric pattern, and then a conductive material pattern is formed within the openings of the sheet. During the engagement of the cap 520, the sheet may be compressed to protrude outward beyond the underlying structure.

[0119] Continue to refer to Figure 3The first dielectric member 620 includes an external protrusion 620p that extends laterally beyond the sidewall of the underlying conductive layer 410. The external protrusion 620p of the first dielectric member 620 may extend in a direction away from adjacent thermally conductive members 430. For example, the external protrusion 620p may hang downwards without physically contacting the cap 520 and / or the underlying structure. In some embodiments, the periphery of the top surface 620t of the first dielectric member 620 (e.g., the top surface of the external protrusion 620p) is spatially separated from the cap 520. The periphery of the bottom surface 620b of the first dielectric member 620 (e.g., the bottom surface of the external protrusion 620p) may extend from the extent of the underlying structure and may be spatially separated from the sidewall 410s of the conductive layer 410 and the sidewall SW of the device package 10. According to some embodiments, any suitable cross-sectional shape (such as a rectangle with one or more slightly curved sides, a rectangle with two convex curved sides, an ellipse, an egg shape or the like) can be used to implement the first dielectric member 620.

[0120] Figure 4A Based on some embodiments Figure 1C A schematic top view of another embodiment of the structure shown, while Figure 4B This is a schematic enlarged view of a portion of another implementation of the packaging structure according to some embodiments. Figure 4A The structure shown can be similar to Figure 2B The structure shown, Figure 4B The structure shown can be similar to Figure 2C The structures shown are similar, and similar reference numerals are used to denote similar components.

[0121] Reference Figure 4A And further refer to Figure 1C and 2B , Figure 4A and 2B The difference in the structure shown is that the opening size of the first dielectric pattern 420B can be smaller than that of the second dielectric pattern 420B. Figure 2B The dimensions of the first dielectric pattern 420A are shown. In some embodiments, the openings OP2 of the first dielectric pattern 420B are arranged at desired positions within the area defined by the semiconductor die 110, as shown in the top view. Note that the semiconductor dies 110 are shown in dashed lines to indicate those semiconductor dies 110 disposed below the first dielectric pattern 420B. The conductive material pattern 430B disposed within the openings OP2 of the first dielectric pattern 420B may be located directly above each semiconductor die 110. For example, in the top view, the surface area of ​​the conductive material pattern 430B is smaller than the area defined by the extent of the respective semiconductor die 110. The material of the conductive material pattern 430B may be similar to the material of the conductive material pattern 430A described in the preceding paragraphs; details are not repeated for the sake of brevity.

[0122] Reference Figure 4B And further refer to Figure 4A and Figure 2C The cap 520 can be bonded to the device package 10 via a thermal interface material structure 400C. The thermal interface material structure 400C may include a conductive layer 410, a thermally conductive member 430' covering the conductive layer 410, and a first dielectric member 420' adjacent to the thermally conductive member 430'. For example, in forming such... Figure 4A Following the first dielectric pattern 420B and conductive material pattern 430B shown, the cap 520 is disposed thereon using the method described in the preceding paragraphs. During the attachment process of the cap 520, the first dielectric pattern 420B is extruded and deformed to form a first dielectric member 420'. The first dielectric member 420' may be similar to... Figure 2C The first dielectric component 420 described herein will not be described in detail again for the sake of brevity.

[0123] The difference between the first dielectric member 420' and 420 lies in the boundary position of the first dielectric member 420' relative to the sidewall 110 of the semiconductor die 110. For example, the inner sidewall 420' of the first dielectric member 420' lies above and within the area defined by the semiconductor die 110. Alternatively, the inner sidewall of the first dielectric member may be substantially flush with the sidewall of the semiconductor die, or may be laterally offset from the sidewall of the semiconductor die, depending on the product requirements. It should be noted that the opening size of the first dielectric member does not constitute a limitation of this disclosure, as long as the resulting thermally conductive member formed in the opening effectively dissipates heat and reduces the thermal resistance of the device package 10.

[0124] Figure 5 Based on some embodiments Figure 1C A schematic top view of another embodiment of the structure shown. Figure 5 The structure shown can be similar to Figure 4A The structures shown are identical, and the same reference numerals are used to denote the same components. (See also...) Figure 5 And further refer to Figure 4A , Figure 5 and Figure 4A The differences in the illustrated structure include the configuration of the openings in the first dielectric pattern 420C. For example, the first dielectric pattern 420C provides an opening OP3 with a circular top view shape. It should be noted that the openings in the first dielectric pattern 420C can have any top view shape, including, for example, rectangles, squares, circles, ellipses, polygons, and combinations thereof. The openings OP3 and the semiconductor die 110 may or may not correspond one-to-one. For example, forming more than one opening OP3 corresponds to the larger one of the semiconductor dies 110.

[0125] In some embodiments, the opening OP3 is partially or completely positioned over a hot spot area corresponding to the semiconductor die 110. For example, heat may be confined to certain areas of the device package, resulting in localized temperature spikes; these areas are referred to as hot spots. A conductive material pattern 430C may be formed in the opening OP3 directly above the hot spot area of ​​the semiconductor die 110. In this way, the thermally conductive member formed by the conductive material pattern 430C can provide effective thermal conduction between the device package and the cap. The material of the conductive material pattern 430C may be similar to the material of the conductive material pattern 430A described in the preceding paragraphs, and details are not repeated for the sake of brevity. It is understood that the shape, number, and architecture of the openings are for illustrative purposes only, and other shapes, numbers, and architectures may be implemented to meet the design criteria of a particular application.

[0126] Figures 6A-6C These are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments. Figure 7 Based on some embodiments Figure 6C The diagram shows an enlarged schematic view of the dashed box C. Unless otherwise stated, the methods of forming the materials and components in these embodiments are essentially the same as those for components denoted by the same reference numerals in the embodiments in the preceding paragraphs.

[0127] Reference Figure 6A , Figure 6A The structure shown is similar to Figure 1B The structures shown are similar, except that the conductive layer 410' is conformally formed on the first dielectric pattern 420A. For example, the first dielectric pattern 420A is formed before the conductive layer 410' is formed. In some embodiments, the first dielectric pattern 420A is formed directly on the upper surface 10t of the device package 10, wherein the upper surface 10t may be a non-active surface opposite to an active surface (e.g., a first side 200a of the second package assembly 200 marked in the figures). For example, the first dielectric pattern 420A is formed on the upper surface 120a of the insulating encapsulation 120, and the opening OP1 of the first dielectric pattern 420A can expose at least a portion of the back side (e.g., the second side 110b) of each semiconductor die 110 in an accessible manner. It should be understood that the first dielectric pattern 420A may be replaced by other first dielectric patterns described elsewhere in this disclosure. The second dielectric pattern 510A may be formed on the third package assembly 300 in the same steps as forming the first dielectric pattern 420A. Alternatively, the second dielectric pattern 510A can be formed before or after the formation of the first dielectric pattern 420A.

[0128] In some embodiments, after the first dielectric pattern 420A is formed, the conductive layer 410' is formed on the first dielectric pattern 420A using, for example, sputtering or other suitable processes. The material of the conductive layer 410' may be similar to... Figure 1A The conductive layer 410 described herein. For example, the conductive layer 410' may be formed in each opening OP1 to directly contact the back side (e.g., the second side 110b) of each semiconductor die 110. In some embodiments, the conductive layer 410' may blanket the inner sidewall 420i of the first dielectric pattern 420A and may further extend to cover the upper surface 420s of the first dielectric pattern 420A.

[0129] Reference Figure 6B The conductive material pattern 430A can be formed on the conductive layer 410' and within the opening OP1 of the first dielectric pattern 420A. The material and forming process of the conductive material pattern 430A can be compared with... Figure 1C The material and formation process of the conductive material pattern 430A described herein are similar, and will not be described in detail again for the sake of brevity. The conductive layer 410' may be interposed in the thickness direction between the conductive material pattern 430A of the device package 10 and the semiconductor die 110. In some embodiments, the conductive layer 410' is interposed in the length (or width) direction between the conductive material pattern 430A and the first dielectric pattern 420A.

[0130] Reference Figure 6C and Figure 7 This provides the PS2 packaging structure. For example, after forming the conductive material pattern 430A, subsequent processes can be similar to... Figure 1D-1E The process described herein. The cap 520 may be placed on the top side 300t of the third package assembly 300 and bonded to the top side 300t of the third package assembly 300 by a second dielectric member 510 formed by a second dielectric pattern 510A. For example, the thermal interface material structure 400D includes a conductive layer 410', a first dielectric member 420 formed by a first dielectric pattern 420A, and a thermally conductive member 430 formed by a conductive material pattern 430A. The thermally conductive member 430 thermally and physically interfaces both the cap 520 and the device package 10. In some embodiments, the conductive layer 410' and the overlying first dielectric member 420 also provide sufficient adhesion between the cap 520 and the device package 10. After the cap 520 is mounted, external terminals 320 and a fifth package assembly 50 may optionally be formed on the bottom side 300b of the third package assembly 300.

[0131] Continue to refer to Figure 7 During the bonding of the cap 520, the first dielectric pattern 420A is extruded and deformed to form a first dielectric member 420 with protrusions (as shown in...). Figure 2C(as described in 420p and 420q). The conductive layer 410' formed on the inner sidewall 420IW of the first dielectric member 420 may be formed with a curved profile in cross-sectional view and conform to the inner sidewall 420IW of the first dielectric member 420. In some embodiments, after the cover 520 is installed, the conductive layer 410' is inserted between the cover 520 and the upper surface 420s of the first dielectric member 420. In some embodiments, the outer protrusion 420p of the first dielectric member 420 may have a rounded side in cross-sectional view and may extend beyond the conductive layer 4100' to directly contact the cover 520 and cover the sidewall SW of the device package 10. Alternatively, the first dielectric member is made of sheet polymer, and the protrusion of the first dielectric member may hang down due to gravity, such as Figure 3 As shown. In some embodiments, the first dielectric member 420 is replaced with Figure 1F The first dielectric component 610 shown is illustrated.

[0132] Figure 8A This is a schematic cross-sectional view of the packaging structure according to some embodiments. Figure 8B Based on some embodiments Figure 8A A schematic enlarged view of the dashed box D shown. Figure 8A The packaging structure shown for PS3 can be similar to Figure 6C The package structure PS2 shown is... Figure 8B The enlarged view shown can be similar to Figure 7 The enlarged view shown is omitted for brevity; a detailed description will not be repeated. Similar reference numerals are used to denote similar components.

[0133] Reference Figures 8A-8B And further refer to Figure 6C and Figure 7 The difference between package structure PS3 and package structure PS2 includes the architecture of the thermal interface material structure 400E. For example, the thermal interface material structure 400E includes a first dielectric member 420, a thermally conductive member 430 disposed in an opening OP1 of the first dielectric member 420, and a conductive layer 405 conformally disposed in the opening OP1 to separate the respective thermally conductive members 430 from the first dielectric member 420. In some embodiments, when forming the conductive layer 405, the upper surface of the first dielectric pattern is covered by a mask layer (not shown), such that the conductive layer 405 can be conformally formed in the opening of the first dielectric pattern. The mask layer can be removed before the conductive material pattern is formed in the opening of the first dielectric pattern. Alternatively, the mask layer can be removed after the conductive material pattern is formed and before the cap 520 is bonded to the device package 10.

[0134] In some embodiments, the conductive layer 405 of the package structure PS3 is formed only at the opening of the first dielectric member 420, so the inner sidewall 420IW of the first dielectric member 420 and the back side (e.g., the second side 110b) of the semiconductor die 110 are covered by the conductive layer 405. The upper surface 420s of the first dielectric member 420 can directly contact the cap 520, and the lower surface 420m of the first dielectric member 420 can directly contact the insulating encapsulation 120 of the lower first package assembly 100 in the device package 10. In some embodiments, the lower surface of the first dielectric member can further extend to physically contact a portion of the back side of the semiconductor die. In some embodiments, the first dielectric member 420 is replaced by Figure 1F The first dielectric member 610 shown is shown. However, the first dielectric member can be replaced by any first dielectric member described elsewhere in this disclosure.

[0135] Figures 9A-9B These are schematic cross-sectional views illustrating various stages of manufacturing the package structure according to some embodiments. Unless otherwise stated, the methods of forming the materials and components in these embodiments are essentially the same as those for components denoted by the same reference numerals in the embodiments in the preceding paragraphs.

[0136] Reference Figure 9A And further refer to Figure 1B , Figure 9A The structure shown can be similar to Figure 1B The structure shown, except for the omission of... Figure 1B The conductive layer 410 in the middle, and the material of the conductive material pattern 630A is the same as... Figure 1B The conductive material pattern 430A is made of a different material. For example, the first dielectric pattern 420A is formed on the upper surface 10t of the device package 10. In some embodiments, the first dielectric pattern 420A is in direct contact with the upper surface 120a of the insulating encapsulation 120. The first dielectric pattern 420A may further extend to physically contact at least a portion of the back side (e.g., the second side 110b) of the semiconductor die 110. The remaining portion of the back side (e.g., the second side 110b) of the semiconductor die 110 may be accessiblely exposed through the opening OP1 of the first dielectric pattern 420A.

[0137] After the first dielectric pattern 420A is formed, a conductive material pattern 630A may be formed in the opening OP1 of the first dielectric pattern 420A. For example, a cleaning process may be selectively performed on the back side (e.g., the second side 110b) of the semiconductor die 110 exposed by the opening OP1 to prepare for the conductive material pattern 630A. The conductive material pattern 630A may be or may include any suitable thermal interface material to provide a thermal interface. For example, the conductive material pattern 630A may be made of a metal interface composition including gallium, indium, tin, bismuth, silver, lead, and / or alloys thereof. The conductive material pattern 630A may include materials other than metals (or metal alloys), such as graphite or the like. For example, the viscosity of the conductive material pattern 630A may range from 0 to about 10,000 mPa·s. In some embodiments, the conductive material pattern 630A comprises an alloy of a gallium substrate with a viscosity ranging from about 1.75 mPa·s to about 4 mPa·s when measured at 25°C. However, any suitable range and any suitable metal substrate alloy can be used. In some embodiments, the conductive material pattern 630A is composed of a liquid metal eutectic alloy consisting of gallium, indium, and tin. Other one or more metal alloys or low-melting-point alloys can be used. In some embodiments, the conductive material pattern 630A comprises one or more conductive materials in a liquid state at room temperature or the operating temperature of the semiconductor die 110. In some embodiments, the conductive material pattern 630A has superior thermal conductivity and a low melting point. In some embodiments, the thermal conductivity of the conductive material pattern 630A is greater than about 15 W / m·K, for example in the range of about 15 W / m·K to about 100 W / m·K or in the range of about 40 W / m·K to about 100 W / m·K. The melting point of the conductive material pattern 630A may be below room temperature (e.g., 25°C) and / or below the operating temperature of the semiconductor die 110. In some embodiments, the melting point of the conductive material pattern 630A is below 20°C. It should be noted that, depending on the content of conductive material, the conductive material pattern 630A may have other melting point values.

[0138] Continue to refer to Figure 9AThe conductive material pattern 630A is formed in the opening OP1 of the first dielectric pattern 420A by performing a dispensing process using the dispensing unit U3. However, other suitable deposition processes can be used to form the conductive material pattern 630A. The viscosity of the first dielectric pattern 420A can be hundreds or hundreds of thousands of times greater than the viscosity of the conductive material pattern 630A. For example, the viscosity difference between the first dielectric pattern 420A and the conductive material pattern 630A is at least 5000 times. The thickness 420T of the first dielectric pattern 420A can be large enough to prevent the conductive material pattern 630A from overflowing. For example, the first dielectric pattern 420A acts as a dam structure to prevent the liquid conductive material pattern 630A from spreading outside the intended area. It should be noted that the first dielectric member can be replaced by any of the first dielectric members described elsewhere in this disclosure. In some embodiments, the conductive material pattern 630A made of a liquid metal eutectic alloy may not form a permanent bond with the device package 10 below. In some embodiments of semiconductor dies having non-coplanar back sides, a conductive material pattern 630A made of a liquid metal eutectic alloy provides the desired properties to conform to those non-coplanar back sides and to form a reliable connection between the cap and the device package.

[0139] Reference Figure 9B This provides the PS4 packaging structure. For example, after forming the conductive material pattern 630A, subsequent processes can be similar to... Figure 1D-1E The process described herein. The cap 520 can be made from the second dielectric pattern 510A (marked in...). Figure 9A The second dielectric member 510 formed in the middle is engaged with the top side 300t of the third package assembly 300. During engagement, the first dielectric pattern 420A can be extruded and deformed to form the first dielectric member 420 with protrusions (e.g., Figure 2C (as shown in 420p and 420q). Alternatively, the first dielectric member is made of sheet polymer and the protrusions of the first dielectric member may not be in physical contact with the cap and / or device package, such as... Figure 3 As shown. In some embodiments, the first dielectric member 420 is replaced with Figure 1F The first dielectric component 610 shown is illustrated.

[0140] In some embodiments, a curing process is performed during bonding, with the process temperature between about 125°C and about 150°C for a duration of about 1 hour to about 3 hours. Once cured, the third encapsulation component 300 is physically connected and thermally coupled to the cap 520 via the second dielectric member 510. The cap 520 and the device package 10 can be coupled via a thermal interface material structure 400F including a thermally conductive member 630 and a first dielectric member 420. For example, a conductive material pattern 630A (marked on...) Figure 9AThe thermally conductive member 630 formed by the first dielectric member 420 (in the middle) thermally and physically interfaces with the cap 520 and the device package 10, and the thermally conductive member 630 can greatly accelerate the heat dissipation. In some embodiments, the thermally conductive member 630 surrounded by the first dielectric member 420 remains liquid. In this case, the device package 10 will not adhere to the cap 520 through the thermally conductive member 630. In some embodiments, only the first dielectric pattern 420A (marked on the middle) Figure 9A The first dielectric member 420 formed in the middle provides adhesive force between the cover 520 and the device package 10.

[0141] After coupling cap 520, external terminals 320 and fifth package assembly 50 may be selectively formed on the bottom side 300b of third package assembly 300. In some embodiments, package structure PS4 uses a liquid metal eutectic alloy as a thermal interface material layer, thereby facilitating improved thermal coupling between device package 10 and cap 520. First dielectric member 420 of package structure PS4 isolates and confines the respective thermally conductive members 630 to prevent their diffusion. In some embodiments, during operation of package structure PS4, as the temperature of semiconductor die 110 increases, the thermally conductive members 630 may remain liquid.

[0142] Figure 10 This is a schematic cross-sectional view of the packaging structure according to some embodiments. Figure 10 The packaging structure shown for PS5 can be similar to Figure 1E The package structure PS1 shown is not described in detail again for the sake of simplicity; similar reference numerals are used to indicate similar components. See also... Figure 10 And further refer to Figure 1E The differences between the PS5 and PS1 packaging structures include the thermal interface material structure and the 400G architecture.

[0143] In some embodiments, the thermal interface material structure 400G includes a conductive layer 410 and a thermally conductive member 430 disposed on the conductive layer 410, while the thermal interface material structure 400G may not have a first dielectric member. For example, the thermally conductive member 430 is disposed on the semiconductor die 110 of the device package 10, and the conductive layer 410 is interposed between the two. The conductive layer 410 may completely or partially cover the device package 10. For example, the conductive layer 410 extends continuously on the upper surface 10t of the device package 10. Alternatively, the conductive layer extends intermittently on the back side (e.g., the second side 110b) of each semiconductor die 110. In some other embodiments, the conductive layer covers a desired area in the upper surface 10t, which corresponds to a hot spot area on the semiconductor die 110.

[0144] In some embodiments, the individual thermally conductive members 430 have a cross-sectional shape, including but not limited to elliptical, rectangular, or other elongated shapes with convex curved sides. However, the thermally conductive members 430 may have any shape and / or form within the scope of this disclosure. The thermally conductive members 430 may be spatially spaced from each other by a gap GP3. In some embodiments, the gap GP3 is an air gap. Alternatively, additional material may be completely or partially filled in the gap GP3 between adjacent thermally conductive members 430 for physical isolation. The thermally conductive members 430 may be disposed intermittently on the semiconductor die 110 as discrete components rather than continuously. In this way, thermomechanical stress between the cap 520 and the device package 10 can be reduced, thereby eliminating problems of delamination and cracking.

[0145] According to some embodiments, the packaging structure includes a first packaging component, a second packaging component inserted between the first packaging component and a third packaging component, a thermal interface material structure covering the first packaging component and relative to the second packaging component, and a heat dissipation component disposed on the third packaging component and thermally coupled to the first packaging component through the thermal interface material structure. The first packaging component includes a plurality of semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies. The semiconductor dies are electrically coupled to the third packaging component through the second packaging component. The thermal interface material structure includes a dielectric dam and a plurality of thermally conductive members, the thermally conductive members comprising a conductive material, and the thermally conductive members covering the semiconductor dies are disposed within the area enclosed by the dielectric dam.

[0146] In some embodiments, the thermal interface material structure further includes a conductive layer interposed between the semiconductor die of the first package assembly and the thermally conductive member. In some embodiments, the conductive layer separates the thermally conductive member of the thermal interface material structure from the semiconductor die of the first package assembly and conforms to the inner sidewall of the dielectric dam adjacent to the thermally conductive member. In some embodiments, the thermally conductive member in contact with the semiconductor die of the first package assembly has a viscosity less than that of the dielectric dam. In some embodiments, the conductive material of the thermally conductive member includes a solder material or a tin-containing low-melting-point eutectic alloy. In some embodiments, the dielectric dam of the thermal interface material structure includes an outer protrusion and an inner protrusion, the outer protrusion extending beyond the surface of the first package assembly and the inner protrusion protruding toward an adjacent one of the thermally conductive members. In some embodiments, the package structure further includes an adhesive member surrounding a stack of the first package assembly and the second package assembly and coupling a cap to the third package assembly, wherein the material of the adhesive member is substantially the same as the material of the dielectric dam of the thermal interface material structure.

[0147] According to some embodiments, the packaging structure includes a packaging substrate, a device package, a thermal interface material structure, and a heat dissipation assembly disposed on the packaging substrate and housing the device therein. The device package includes a plurality of semiconductor dies coupled to an interposer and encapsulated by an insulating encapsulator. The packaging substrate is electrically coupled to the semiconductor dies through the interposer. The thermal interface material structure includes a plurality of thermally conductive members spatially separated from each other and covering the semiconductor dies. The device package is thermally coupled to the heat dissipation assembly through the thermal interface material structure.

[0148] In some embodiments, the thermal interface material structure further includes a dielectric dam overlying the insulating encapsulation of the device package, the dielectric dam surrounding the thermally conductive member and isolating the thermally conductive members from each other. In some embodiments, the thermally conductive member of the thermal interface material structure includes a liquid metal eutectic alloy that thermally couples the heat dissipation component to the semiconductor die of the device package. In some embodiments, the dielectric dam of the thermal interface material structure includes a protruding edge and an inner sidewall, the protruding edge extending beyond the surface of the device package facing the heat dissipation component, and the inner sidewall having a curved cross-sectional profile and laterally projecting toward an adjacent one of the thermally conductive members. In some embodiments, the thermally conductive member of the thermal interface material structure includes a solder material that metallically bonds the heat dissipation component to a conductive layer overlying the thermal interface material structure of the device package. In some embodiments, the package structure further includes an adhesive member discontinuously disposed along the periphery of the package substrate and bonding the heat dissipation component to the package substrate via the adhesive member.

[0149] According to some embodiments, a method of manufacturing a package structure includes at least the following steps: Coupling a device package to a package substrate, wherein the device package includes a plurality of semiconductor dies encapsulated by an insulating encapsulator and electrically coupled to the package substrate. Forming a first dielectric pattern on the device package opposite the package substrate, wherein the first dielectric pattern includes a plurality of openings corresponding to the semiconductor dies of the device package. Forming a thermally conductive material on the semiconductor dies of the device package and in the openings of the first dielectric pattern. Placing a heat dissipation assembly on the device package and the package substrate, the heat dissipation assembly contacting the first dielectric pattern and the thermally conductive material. Performing a thermal processing step on the first dielectric pattern and the thermally conductive material to form a thermal interface material structure coupling the heat dissipation assembly to the device package.

[0150] In some embodiments, the manufacturing method further includes forming a conductive layer on a non-active surface of the device package, the non-active surface including the surface of the insulating encapsulant and the back surface of the semiconductor die, before forming the first dielectric pattern on the device package, wherein the first dielectric pattern is formed on the conductive layer. In some embodiments, the manufacturing method further includes forming a conductive layer on the back surface of the semiconductor die and conformally formed in the opening of the first dielectric pattern before forming the first dielectric pattern on the semiconductor die, wherein a thermally conductive material is formed on the conductive layer. In some embodiments, forming the thermally conductive material includes performing a dispensing process to form the thermally conductive material in the opening of the first dielectric pattern, wherein the thermally conductive material is liquid. In some embodiments, the thermally conductive material comprises a low-melting-point eutectic alloy, and the thermally conductive material remains liquid after performing the heat treatment process. In some embodiments, the manufacturing method further includes applying a force to the heat dissipation assembly, wherein the first dielectric pattern is deformed to protrude outward beyond the surface of the device package facing the heat dissipation assembly and toward the thermally conductive material. In some embodiments, the manufacturing method further includes forming a second dielectric pattern on the packaging substrate while forming the first dielectric pattern, wherein the heat treatment process is performed on the second dielectric pattern to bond the heat dissipation component disposed on the second dielectric pattern to the packaging substrate.

[0151] The foregoing summary of the features of several embodiments enables those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A packaging structure, comprising: The first packaging assembly includes a plurality of semiconductor dies and an insulating encapsulation body encapsulating the semiconductor dies; The second packaging component is inserted between the first packaging component and the third packaging component, and the semiconductor die is electrically coupled to the third packaging component through the second packaging component; A thermal interface material structure, covering the first encapsulation component and relative to the second encapsulation component, the thermal interface material structure comprising: Dielectric dams; and Multiple thermally conductive components, including conductive materials, are disposed within the area surrounded by the dielectric dam and cover the semiconductor die; and A heat dissipation assembly is disposed on the third encapsulation assembly and thermally coupled to the first encapsulation assembly through the thermal interface material structure, wherein the inner sidewall of the dielectric dam extends between the first encapsulation assembly and the heat dissipation assembly and laterally toward the thermally conductive member, the inner sidewall of the dielectric dam includes a curved profile with an absolute value of curvature greater than 0, the outer sidewall of the dielectric dam opposite to the inner sidewall includes a curved surface with an absolute value of curvature greater than 0, and the curvature of the inner sidewall of the dielectric dam is different from the curvature of the outer sidewall.

2. The packaging structure according to claim 1, wherein the thermal interface material structure further comprises: A conductive layer is inserted between the semiconductor die and the thermally conductive component of the first packaging assembly.

3. The packaging structure of claim 2, wherein the conductive layer separates the thermally conductive member of the thermal interface material structure from the semiconductor die of the first packaging assembly and conforms to the inner sidewall of the dielectric dam adjacent to the thermally conductive member.

4. The packaging structure of claim 1, wherein the thermally conductive member in contact with the semiconductor die of the first packaging assembly has a viscosity less than the viscosity of the dielectric dam.

5. The packaging structure according to claim 1, wherein the conductive material of the thermally conductive component comprises solder material or a tin-containing low-melting-point eutectic alloy.

6. The packaging structure of claim 1, wherein the dielectric dam of the thermal interface material structure includes an outer protrusion and an inner protrusion, the outer protrusion extending beyond the surface of the first packaging assembly, and the inner protrusion protruding toward an adjacent one of the thermally conductive members.

7. The packaging structure according to claim 1, further comprising: An adhesive member surrounds the stack of the first and second encapsulation components and couples the heat dissipation component to the third encapsulation component, wherein the material of the adhesive member is substantially the same as the material of the dielectric dam of the thermal interface material structure.

8. A packaging structure, comprising: Packaging substrate; A device package is disposed on the package substrate and includes a plurality of semiconductor dies coupled to an intermediary and encapsulated by an insulating encapsulator, wherein the package substrate and the plurality of semiconductor dies are electrically coupled through the intermediary; A thermal interface material structure is disposed on the device package relative to the packaging substrate, the thermal interface material structure comprising: Multiple thermally conductive components are spatially separated from each other and cover the multiple semiconductor dies; A dielectric dam, covering the insulating encapsulation of the device and isolating the plurality of thermally conductive members from each other, wherein the inner sidewall of the dielectric dam adjacent to the thermally conductive member includes a curved profile with an absolute value of curvature greater than 0, and the outer sidewall of the dielectric dam opposite the inner sidewall includes a curved surface with an absolute value of curvature greater than 0, and the curvature of the inner sidewall of the dielectric dam is different from that of the outer sidewall; and A heat dissipation component is disposed on the packaging substrate and encapsulates and houses the device therein, and the device package and the heat dissipation component are thermally coupled through the thermal interface material structure.

9. The packaging structure according to claim 8, wherein: The dielectric dam covers the sidewall of the insulating enclosure of the device.

10. The packaging structure of claim 8, wherein the thermally conductive component of the thermal interface material structure comprises a liquid metal eutectic alloy, the liquid metal eutectic alloy thermally coupling the heat dissipation component to the semiconductor die of the device package.

11. The packaging structure of claim 8, wherein the dielectric dam of the thermal interface material structure includes a protruding edge that extends beyond the surface of the device package facing the heat dissipation component.

12. The packaging structure of claim 8, wherein the thermally conductive component of the thermal interface material structure comprises solder material, the solder material metal bonding the heat dissipation component to a conductive layer overlying the thermal interface material structure of the device package.

13. The packaging structure according to claim 8, further comprising: An adhesive member is intermittently disposed along the periphery of the encapsulation substrate, and the heat dissipation assembly is bonded to the encapsulation substrate via the adhesive member.

14. A method for manufacturing a packaging structure, comprising: A device package is coupled to a package substrate, wherein the device package includes a plurality of semiconductor dies encapsulated by an insulating encapsulator and electrically coupled to the package substrate; A first dielectric pattern is formed on the device package opposite to the packaging substrate, wherein the first dielectric pattern includes a plurality of openings corresponding to the semiconductor die of the device package; Thermally conductive material is formed on the semiconductor die of the device package and in the opening of the first dielectric pattern; A heat dissipation component is placed on the device package and the package substrate, and the heat dissipation component contacts the first dielectric pattern and the thermally conductive material; as well as A heat treatment process is performed on the first dielectric pattern and the thermally conductive material to form a thermal interface material structure that couples the heat dissipation component to the device package, such that the inner sidewall of the first dielectric pattern extends between the device package and the heat dissipation component and laterally toward the thermally conductive material, the inner sidewall of the first dielectric pattern includes a curved profile with an absolute value of curvature greater than 0, the outer sidewall of the first dielectric pattern opposite to the inner sidewall includes a curved surface with an absolute value of curvature greater than 0, and the curvature of the inner sidewall of the first dielectric pattern is different from the curvature of the outer sidewall.

15. The method for manufacturing the packaging structure according to claim 14, further comprising: Before forming the first dielectric pattern on the device package, a conductive layer is formed on the non-active surface of the device package, the non-active surface including the surface of the insulating encapsulation and the back side of the semiconductor die, wherein the first dielectric pattern is formed on the conductive layer.

16. The method for manufacturing the packaging structure according to claim 14, further comprising: After the first dielectric pattern is formed on the semiconductor die, a conductive layer is formed on the back side of the semiconductor die and conformally formed in the opening of the first dielectric pattern, wherein the thermally conductive material is formed on the conductive layer.

17. The method of manufacturing the packaging structure according to claim 14, wherein forming the thermally conductive material comprises: A dispensing process is performed to form the thermally conductive material in the opening of the first dielectric pattern, wherein the thermally conductive material is liquid.

18. The method of manufacturing the packaging structure according to claim 14, wherein the thermally conductive material comprises a low-melting-point eutectic alloy, and the thermally conductive material remains in a liquid state after performing the heat treatment process.

19. The method for manufacturing the packaging structure according to claim 14, further comprising: A force is applied to the heat dissipation component, causing the first dielectric pattern to deform and cover the sidewall of the insulating encapsulation of the device package.

20. The method for manufacturing the packaging structure according to claim 14, further comprising: When forming the first dielectric pattern, a second dielectric pattern is formed on the packaging substrate, wherein the heat treatment process is performed on the second dielectric pattern to bond the heat dissipation component disposed on the second dielectric pattern to the packaging substrate.

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