Methods of forming semiconductor structures and semiconductor structures

Abstract

Methods of forming a semiconductor structure include attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, wherein the TIM film is pre-formed prior to the placing, wherein, after the placing, a peripheral portion of the TIM film extends laterally beyond a sidewall of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, wherein, after the attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, wherein the first side of the TIM film distal from the substrate is in contact with the lid. Embodiments of the present application also relate to semiconductor structures.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor structures and semiconductor structures. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this improvement in integration density comes from the repeated reduction in the size of the smallest component, which allows more components to be integrated into a given area.

[0003] With the growing demand for miniaturized electronic devices, there is a corresponding need for smaller and more innovative semiconductor die-packaging technologies. An example of such packaging systems is the PoP (PoS) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide high integration and component density. Another example is a chip-on-a-substrate structure, where a semiconductor chip is attached to a wafer (e.g., an interposer) to form a chip-on-a-substrate structure. The chip-on-a-substrate structure is then attached to a substrate (e.g., a printed circuit board) to form a chip-on-a-substrate structure. These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and small size. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor structure, the method comprising: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device remote from the substrate, wherein the TIM film is pre-formed prior to the placement, and wherein, after the placement, a peripheral portion of the TIM film extends laterally beyond the sidewall of the semiconductor device; and attaching a cover to the first surface of the substrate to form a closed space between the cover and the substrate, wherein, after attaching the cover, the semiconductor device and the TIM film are disposed in the closed space, wherein the first side of the TIM film remote from the substrate is in contact with the cover.

[0005] Some other embodiments of this application provide a method for forming a semiconductor structure, the method comprising: attaching a first semiconductor structure to a first surface of a substrate, wherein the first semiconductor structure includes: an interposer having conductive bumps formed on a first side of the interposer, wherein the conductive bumps are bonded to the first surface of the substrate; a first die attached to a second side of the interposer opposite to the first side; and a molding material located on the second side of the interposer and around the first die; placing a thermal interface material (TIM) film on a first surface of the first semiconductor structure remote from the substrate, wherein the TIM film is pre-formed prior to the placement, wherein after the placement, the first surface of the first semiconductor structure is disposed within the boundary of the TIM film in a plan view; and attaching a cap to the first surface of the substrate above the first semiconductor structure to form a closed space between the cap and the substrate, wherein the first semiconductor structure and the TIM film are disposed in the closed space, wherein the lower side of the cap facing the substrate is in contact with the TIM film.

[0006] Some embodiments of this application provide a semiconductor structure including: a substrate; a semiconductor device located above and electrically coupled to a first surface of the substrate; a molding material located around the semiconductor device; a thermal interface material (TIM) film located above the molding material and the semiconductor device, wherein the TIM film covers an upper surface of the semiconductor device remote from the substrate, wherein a peripheral portion of the TIM film extends laterally beyond the sidewall of the molding material; and a cover attached to the first surface of the substrate, wherein the semiconductor device, the molding material, and the TIM film are disposed in an enclosed space between the cover and the substrate, wherein a first side of the TIM film remote from the substrate contacts the cover. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment is shown.

[0009] Figure 1B Illustrations according to embodiments Figure 1A A top view of a semiconductor device.

[0010] Figure 2 , Figures 3A to 3E and Figures 4 to 7 Various views of a semiconductor device at various stages of manufacturing according to an embodiment are shown.

[0011] Figures 8 to 11 A cross-sectional view of a semiconductor device at various stages of manufacturing according to another embodiment is shown.

[0012] Figures 12 to 14 A cross-sectional view of a semiconductor device at various stages of manufacturing according to another embodiment is shown.

[0013] Figures 15 to 17 Cross-sectional views of a semiconductor device at various stages of manufacturing according to yet another embodiment are shown.

[0014] Figure 18 A flowchart illustrating a method for forming a semiconductor structure in some embodiments is shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. Throughout the specification, unless otherwise stated, the same reference numerals in different figures refer to the same or similar components formed using the same or similar materials and by the same or similar methods. Furthermore, figures with the same numerals but different letters (e.g., Figure 3A and Figure 3B This shows various views (e.g., cross-sectional views, top views) of the same structure at the same stage of the manufacturing process.

[0016] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] This paper discusses embodiments of the invention in the context of forming a chip-on-wafer structure on a substrate having a thermal interface material (TIM) film. The principles of the invention can be applied to other structures or devices, such as integrated fan-out (InFO) packages or system-on-integrated circuit (SoIC) packages.

[0018] In some embodiments, a semiconductor device is attached to a substrate, and then a pre-formed TIM film is placed (e.g., laminated) on the upper surface of the semiconductor device away from the substrate. The TIM film is formed of a material comprising carbon and a polymer. The thermal conductivity of the TIM film can exceed 20 watts per Kelvin meter (W / (m·K)). Next, rollers can be rolled over the TIM film to firmly press the TIM film against the upper surface of the semiconductor device. Next, a cap is attached to the substrate over the TIM film and the semiconductor device, wherein the TIM film and the semiconductor device are disposed in an enclosed space between the cap and the substrate. A clamping curing process is then performed to cure the TIM film. Compared to conventional gel-type TIM materials, the TIM film provides higher heat dissipation efficiency. Furthermore, the shape and thickness of the TIM film are easily controlled, resulting in excellent coverage of the upper surface of the semiconductor device. The ease of manufacturing of the TIM film also increases the throughput of the manufacturing process.

[0019] Figure 1A A cross-sectional view of a semiconductor device 100 according to an embodiment is shown. The semiconductor device 100 has a chip-on-wafer structure. Figure 1A As shown, the semiconductor device 100 includes a wafer 150 (e.g., an interposer), one or more dies 111 (e.g., 111A, 111B, and 111C) attached to the wafer 150, an underfill material 133 between the dies 111 and the wafer 150, and a molding material 135 above the wafer 150 and around the dies 111. The semiconductor device 100 is then attached to a substrate to form a semiconductor device 200 having a chip-on-a-wafer structure on a substrate, the details of which will be described below.

[0020] To form semiconductor device 100, one or more dies 111 (also referred to as semiconductor dies, chips, or integrated circuit (IC) dies) are attached to the upper surface of wafer 150. In the illustrated embodiment, wafer 150 is an interposer, and therefore, in the discussion herein, wafer 150 may also be referred to as an interposer. It should be understood that other suitable types of wafers may also be used as wafer 150. In some embodiments, dies 111 (e.g., 111A, 111B, and 111C) are dies of the same type (e.g., memory dies or logic dies). In other embodiments, dies 111 are of different types; for example, die 111A may be a logic die and dies 111B and 111C may be memory dies. Figure 1AThe number and relative positions of the dies 111 are merely examples; other numbers and positions of dies are also possible and are fully intended to be included within the scope of this invention.

[0021] In some embodiments, die 111A includes a substrate 111AS, electronic components (e.g., transistors, resistors, capacitors, diodes, etc.) formed in / on the substrate 111AS, and an interconnect structure 112 connecting the electronic components above the substrate 111AS to form the functional circuitry of die 111A. Die 111A also includes conductive pads 102 and conductive posts 117 (also referred to as die connectors) formed on the conductive pads 102. The conductive posts 117 provide electrical connections to the circuitry of die 111A.

[0022] The substrate 111AS of die 111A can be a doped or undoped semiconductor substrate, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate typically a silicon or glass substrate. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0023] The electronic components of die 111A include various active components (e.g., transistors) and passive components (e.g., capacitors, resistors, inductors), etc. Any suitable method can be used to form the electronic components of die 111A within or on the substrate 111AS of die 111A. The interconnect structure 112 of die 111A includes one or more metallization layers (e.g., copper layers) formed in one or more dielectric layers and is used to connect various electronic components to form functional circuits. In embodiments, the interconnect structure is formed from alternating layers of dielectric and conductive materials (e.g., copper) and can be formed by any suitable process (such as deposition, damascene, dual damascene, etc.).

[0024] One or more passivation layers (not shown) may be formed over the interconnect structure 112 of die 111A to provide a degree of protection for the structure beneath die 111A. The passivation layers may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations of these materials, etc. The passivation layers may be formed using processes such as chemical vapor deposition (CVD), but any suitable process may be used.

[0025] Conductive pads 102 may be formed over a passivation layer and may extend through the passivation layer to make electrical contact with the interconnect structure 112 of the die 111A. Conductive pads 102 may include aluminum, but may optionally use other materials such as copper.

[0026] Conductive posts 117 of die 111A are formed on conductive pads 102 to provide conductive areas for circuitry electrically connected to die 111A. Conductive posts 117 may be copper posts, contact bumps such as microbumps, or may include materials such as copper, tin, silver, combinations thereof, or other suitable materials.

[0027] Dies 111B and 111C are formed using the same or similar processing steps, but different electrical components and connections can be formed, thus creating circuits with different functions for different dies. Details will not be repeated here.

[0028] Observe wafer 150, which includes substrate 123, through-hole 121 (also referred to as substrate via (TSV)), redistribution structure 131, conductive pad 132 on the upper surface of wafer 150, and external connector 125 (also referred to as conductive bump) on the lower surface of wafer 150. Figure 1A The structure of wafer 150 shown is merely a non-limiting example. Other structures are possible and are fully intended to be included within the scope of this invention.

[0029] The substrate 123 may be, for example, a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate. However, the substrate 123 may optionally be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnect functionality.

[0030] In some embodiments, substrate 123 may include electronic components such as resistors, capacitors, signal distribution circuitry, combinations thereof, etc. These electronic components may be active, passive, or a combination thereof. In other embodiments, substrate 123 does not contain any active or passive electronic components. All such combinations are intended to be included within the scope of this invention.

[0031] A through-hole 121 is formed in the substrate 124 and extends from the upper surface 123U of the substrate 123 to the lower surface 123L of the substrate 123. The through-hole 121 provides electrical connection between the conductive pad 132 and the external connector 125. The through-hole 121 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, alloys, doped polysilicon, or combinations thereof. A barrier layer may be formed between the through-hole 121 and the substrate 123. The barrier layer may include a suitable electrical material, but alternatively, other materials such as tantalum nitride or titanium may be used.

[0032] Once the through-hole 121 is formed, a redistribution structure 131 can be formed on the upper surface 123U of the substrate 123 to provide interconnections between the through-hole 121, the external connector 125, and the dies 111A, 111B, and 111C. The redistribution structure 131 includes conductive components (wires and / or vias) disposed in one or more dielectric layers within the redistribution structure 131. In some embodiments, the one or more dielectric layers are formed of polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layers are formed of nitrides such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The one or more dielectric layers of the redistribution structure 131 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, combinations thereof, etc.

[0033] In some embodiments, the conductive components of the redistribution structure 131 include wires and / or conductive vias formed of suitable conductive materials such as copper, titanium, tungsten, and aluminum. The conductive components can be formed, for example, by: forming an opening in the dielectric layer of the redistribution structure to expose the underlying conductive components; forming a seed layer over the dielectric layer and in the opening; forming a patterned photoresist with a designed pattern over the seed layer; plating (e.g., electroplating or electroless plating) a conductive material in the designed pattern and over the seed layer; and removing portions of the photoresist and seed layer where no conductive material is formed. After forming the redistribution structure 131, any suitable material such as copper, aluminum, gold, tungsten, or combinations thereof can be used to form conductive pads 132 over the redistribution structure 131 and electrically couple these conductive pads to the redistribution structure 131.

[0034] Next, an external connector 125 is formed on the lower surface 123L of the substrate 123. The external connector 125 can be any suitable type of external contact, such as microbumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless nickel-palladium immersion gold (ENEPIG) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb, and combinations thereof.

[0035] like Figure 1A As shown, the conductive posts 117 of die 111 are bonded to the conductive pads 132 of wafer 150 via, for example, solder areas. A reflow process can be performed to bond die 111 to wafer 150.

[0036] After the die 111 is bonded to the wafer 150, an underfill material 133 is formed between the die 111 and the wafer 150. The underfill material 133 may, for example, comprise a liquid epoxy resin, which is dispensed into the gap between the die 111 and the wafer 150, for example using a dispensing needle or other suitable dispensing tool, and then cured to harden. Figure 1A As shown, the bottom filler material 133 fills the gap between the die 111 and the wafer 150, and can also fill the gap between the sidewalls of the die 111.

[0037] Next, a molding material 135 is formed over the wafer 150 and around the die 111. The molding material 135 also surrounds an underfill material 133. For example, the molding material 135 may include an epoxy resin, an organic polymer, a polymer with or without silica-based fillers or glass fillers, or other materials. In some embodiments, the molding material 135 includes a liquid molding compound (LMC) that is a gel-like liquid when applied. The molding material 135 may also include a liquid or a solid when applied. Optionally, the molding material 135 may include other insulating and / or sealing materials. In some embodiments, a wafer-level molding process is used to apply the molding material 135. The molding material 135 may be molded using, for example, compression molding, transfer molding, molding underfill (MUF), or other methods.

[0038] Next, in some embodiments, a curing process is used to cure the molding material 135. The curing process may include heating the molding material 135 to a predetermined temperature for a predetermined time period using an annealing process or other heating process. The curing process may also include ultraviolet (UV) exposure, infrared (IR) energy exposure, combinations thereof, or combinations thereof with heating processes. Optionally, the molding material 135 may be cured using other methods. In some embodiments, a curing process is not included.

[0039] After the molding material 135 is formed, planarization processes, such as chemical and mechanical planarization (CMP), can be performed to remove excess portion of the molding material 135 from above the die 111, so that the molding material 135 and the die 111 have coplanar upper surfaces. Figure 1A As shown, the molding material 135 and the substrate 123 of the wafer 150 share the same end, such that the sidewalls of the molding material 135 are perpendicularly aligned with the corresponding sidewalls of the wafer 150.

[0040] Figure 1B Examples shown Figure 1A A top view of the semiconductor device 100. Figure 1A Show along Figure 1B The image shows a cross-sectional view of semiconductor device 100 at section AA. For simplicity, Figure 1B Not all components are shown. For example, in Figure 1B The bottom filler material 133 is not shown in the diagram. (Example) Figure 1B As shown in the top view, die 111A is located in the central region of semiconductor device 100. A plurality of dies 111B and 111C, which are smaller than die 111A, are located on the opposite side of die 111A. Figure 1B The molding material 135 surrounding the dies 111A / 111B / 111C is also shown. Figure 1B In the top view, the semiconductor device 100 has a first dimension W1 and a second dimension H1, which are measured between the opposing sidewalls of the molding material 135.

[0041] Figure 2 , Figures 3A to 3E and Figures 4 to 7 Various views of the semiconductor device 200 at various stages of manufacturing according to an embodiment are shown. Figure 2 As shown, Figure 1A The semiconductor device 100 is bonded to the upper surface of the substrate 209 (e.g., a printed circuit board) to form a semiconductor device 200 having a chip-on-a-wafer structure on a substrate. Figure 2 A passive component 211 attached to the upper surface of substrate 209 is also shown.

[0042] In some embodiments, substrate 209 is a multilayer circuit board, such as a printed circuit board (PCB). For example, substrate 209 may include one or more dielectric layers 201 formed of bismaleimide triazine (BT) resin, FR-4 (a composite material consisting of woven glass fiber cloth with a flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other support material. Substrate 209 may include conductive components (e.g., wires 202 and vias 204) formed in / on substrate 209. Figure 2 As shown, a solder resist layer 208 is formed on the upper and lower surfaces of the substrate 209. Furthermore, the substrate 209 has conductive pads 203 formed on the upper surface of the substrate 209 and conductive pads 205 formed on the lower surface of the substrate 209, the conductive pads 203 and 205 being electrically coupled to conductive components of the substrate 209.

[0043] exist Figure 2 In this process, the semiconductor device 100 is bonded to the conductive pads 203 of the substrate 209. A reflow process can be performed to electrically and mechanically couple the external connectors 125 of the semiconductor device 100 to the conductive pads 203 of the substrate 209. An underfill material 137 is formed to fill the gap between the semiconductor device 100 and the substrate 209. The underfill material 137 may be the same as or similar to the underfill material 133, so details will not be repeated here.

[0044] Figure 2A passive component 211 is also shown attached to the upper surface of a substrate 209 adjacent to the semiconductor device 100. The passive component 211 may be a discrete component, such as a capacitor, inductor, or resistor. Contact terminals of the passive component 211 are bonded to conductive pads 203. In some embodiments, the passive component 211 is attached to the substrate 209 before the semiconductor device 100 is attached to the substrate 209. In other embodiments, the passive component 211 is attached to the substrate 209 after the semiconductor device 100 is attached to the substrate 209.

[0045] Next, refer to Figure 3A A thermal interface material (TIM) film 141 is placed (e.g., laminated) on the upper surface of the semiconductor device 100, such as the upper surface of the die 111 and the upper surface of the molding material 135. The TIM film 141 is pre-formed before being placed on the semiconductor device 100. For example, the TIM film 141 is pre-formed into a sheet (e.g., in a sheet format like paper) before being placed on the semiconductor device 100.

[0046] In some embodiments, the TIM film 141 is formed of a material consisting of a mixture of carbon and a polymer, wherein the polymer may be, for example, a resin-based polymer or an acrylic-based polymer. In some embodiments, the weight percentage of carbon in the material of the TIM film 141 is between about 40% and about 90%. In some embodiments, the thermal conductivity of the TIM film 141 is between about 20 W / (m·K) and about 80 W / (m·K), such as 23 W / (m·K) or 56 W / (m·K). The range of carbon weight percentages disclosed above is selected to ensure that the physical properties of the TIM film 141 meet performance requirements. For example, if the carbon percentage is less than about 40%, the thermal conductivity of the TIM film 141 may be too low (e.g., <20 W / (m·K)). Conversely, if the carbon percentage is greater than about 90%, the elasticity and / or adhesion of the TIM film 141 may be too low. For example, the thickness of the TIM film 141 may be in the range between about 0.09 mm and about 0.13 mm. Although a mixture of carbon and polymers is used as an example above, other suitable materials, such as graphite, graphene, acrylic resin, resin, gallium, indium, solder, and combinations thereof, can also be used to form TIM film 141.

[0047] like Figure 3A As shown, the TIM film 141 covers (e.g., completely covers) the upper surface of the semiconductor device 100 (e.g., a chip-on-wafer structure). A peripheral portion 141E of the TIM film 141 (also referred to as the edge portion) extends laterally beyond the lateral extent of the semiconductor device 100. In other words, the peripheral portion 141E of the TIM film 141 extends laterally beyond the sidewalls of the semiconductor device 100 (e.g., beyond the sidewalls of the molding material 135).

[0048] After the TIM film 141 is placed on the upper surface of the semiconductor device 100, the peripheral portion 141E of the TIM film 141 can droop down below the upper surface of the molding material 135, such as... Figure 3A As shown, it may extend over the upper surface of the molding material 135, such as Figure 4 As shown. In Figure 3A In the TIM film 141, the dimension T2 (e.g., height) of the peripheral portion 141E is greater than the thickness T1 of the TIM film 141. Similarly, in Figure 4 In this figure, the dimension T3 (e.g., height) of the peripheral portion 141E of the TIM film 141 is greater than the thickness T1 of the TIM film 141. Extending the peripheral portion 141E of the TIM film 141 beyond the boundary (e.g., sidewall) of the semiconductor device 100 ensures that after the TIM film 141 is cured in subsequent processing, the upper surface of the semiconductor device 100 is still completely or almost completely covered by the cured TIM film 141 (e.g., more than 99% of the upper surface area of ​​the semiconductor device 100 is covered). Note that although the TIM film 141 is shown as a single layer in the figure, the TIM film 141 may comprise multiple sublayers stacked together. Additionally or optionally, multiple TIM films 141 may be stacked together above the upper surface of the semiconductor device 100 to achieve a desired total thickness.

[0049] Still referencing Figure 3A After the TIM film 141 is placed on the semiconductor device 100, it is rolled on the TIM film 141 by a roller 147 (e.g., along the roller 147). Figure 3A The TIM film 141 is pressed against the upper surface of the semiconductor device 100 by the rollers 147 (in the direction of arrow 149). The pressing of the rollers 147 ensures that the TIM film 141 is in close contact with the upper surface of the semiconductor device 100, so that there are no gaps (e.g., air bubbles) between the TIM film 141 and the upper surface of the semiconductor device 100. In other words, the contact area between the TIM film 141 and the semiconductor device 100 is maximized, which improves the efficiency of heat transfer (e.g., heat dissipation) from the semiconductor device 100 to the TIM film 141.

[0050] Figure 3B and Figure 3C Show Figure 3A A top view of the semiconductor device 200. It should be noted that, for simplicity, not all components of the semiconductor device 200 are shown. Figure 3B In the diagram, apart from the TIM film 141, the die 111 (e.g., 111A, 111B, and 111C) and the molding material 135 are shown in dashed lines, while... Figure 3C Only TIM film 141 is shown in the image. (Example) Figure 3B As shown in the top view, the dimensions W2 and H2 of the TIM film 141 are larger than the dimensions W1 and H1 of the semiconductor device 100 (see...). Figure 1B (For example, W2>W1, H2>H1), such that the TIM film 141 completely covers the upper surface of the semiconductor device 100. In other words, in the top view, the semiconductor device 100 is completely disposed within the boundary of the TIM film 141.

[0051] Figure 3D The examples shown in the embodiments Figure 3C An enlarged view of region 143 of the TIM film 141. Region 143 is the corner region of the TIM film 141. For example, the radius R1 of the corner region may be less than about 0.2 mm. Figure 3E The examples shown in the embodiments Figure 3C An enlarged view of region 145 of the TIM film 141. Region 145 is the edge region of the TIM film 141, which has a boundary 141B (e.g., an edge) of the TIM film 141. Figure 3E In the illustrated embodiment, the boundary 141B of the TIM film 141 is not a perfectly straight line, and may be, for example, a curve with a maximum lateral offset D1 of less than about 1 mm. Since the rounded or curved boundaries of the TIM material may cause some areas of the underlying semiconductor device 100 to be exposed (e.g., uncovered), the small radius R1 and small maximum lateral offset D1 discussed above (which are made possible by the TIM film 141) improve the coverage of the upper surface of the semiconductor device 100.

[0052] Compared to reference methods that deposit gel-type (or liquid-type) TIM materials on the upper surface of semiconductor device 100, the method of the present invention offers several advantages. For example, gel-type TIM materials typically have low thermal conductivity, such as below 3 W / (m·K). In contrast, TIM film 141 has a much higher thermal conductivity (e.g., greater than 20 W / (m·K)) to improve heat dissipation. Gel-type TIM materials typically need to be stored at lower temperatures (e.g., -40°C), while TIM film 141 can be stored at room temperature. To reduce voids (e.g., bubbles) in the cured gel-type TIM material (or between the cured gel-type TIM material and semiconductor device 100), the gel-type TIM material may have to be deposited with a special pattern. Even with a special pattern, voids may still form in the cured gel-type TIM material. In contrast, no special pattern is required for TIM film 141, and no voids (e.g., bubbles) are formed using the embodiments disclosed herein.

[0053] Furthermore, the shape and size of the deposited gel-type TIM material are difficult to control, which often results in low coverage of the upper surface of the semiconductor device 100 (e.g., the ratio between the area covered by TIM material and the area without TIM material), because some areas of the upper surface of the semiconductor device 100 may not have gel-type TIM material deposited. As a result, the coverage using gel-type TIM material is typically between about 80% and about 90%. In contrast, the TIM film 141 is pre-formed (e.g., in sheet form) and can be cut into any suitable shape and / or size and easily laminated onto the upper surface of the semiconductor device 100. As a result, after curing, the TIM film 141 achieves a coverage greater than 99%, thereby improving the heat dissipation of the semiconductor device 100. Due to the ease with which the TIM film 141 can be laminated onto the semiconductor device 100, the manufacturing yield is much higher than that of the process of depositing gel-type TIM material onto the semiconductor device 100.

[0054] Next, in Figure 5 In this process, a cover 151 is attached to the upper surface of a substrate 209 to form a closed space between the cover 151 and the substrate 209. The cover 151 can be formed of a material suitable for heat dissipation, such as copper, aluminum, steel, ceramics, alloys, dielectric materials, etc. Figure 5 In this embodiment, the cover 151 has a top 151T and a sidewall portion 151S. The sidewall portion 151S is attached to the upper surface of the substrate 209 by, for example, adhesive 153. In one embodiment, the cover 151 is formed of a metallic material and is electrically isolated. In another embodiment, the cover 151 is formed of a metallic material and electrically coupled to a conductive pad 203 configured to be connected to an electrically grounded location (e.g., via a solder area), in which case the cover 151 also serves as an electromagnetic interference (EMI) shield for the semiconductor device 100.

[0055] like Figure 5 As shown, the semiconductor device 100, the TIM film 141, and the passive component 211 are disposed in an enclosed space between the cover 151 and the substrate 209. The TIM film 141 is disposed between the top 151T of the cover 151 and the upper surface of the semiconductor device 100. Specifically, the upper surface of the TIM film 141 contacts (e.g., physically contacts) the top 151T, and the lower surface of the TIM film 141 contacts (e.g., physically contacts) the upper surface of the semiconductor device 100 and the upper surface of the molding material 135.

[0056] Next, in Figure 6In this process, the semiconductor device 200 is clamped between the top clamp 157 and the bottom clamp 159 of the clamp. A rubber pad 155 may be placed between the top clamp 157 and the cover 151 to prevent damage to the semiconductor device 200. Next, while clamped between the top clamp 157 and the bottom clamp 159, the semiconductor device 200 is heated to a predetermined temperature (e.g., between 50°C and 350°C) for a predetermined time period (e.g., about 50 seconds and about 3 hours). In some embodiments, the heating process cures a TIM film 141, and the cured TIM film 141 adheres the upper surface of the semiconductor device 100 to the top 151T of the cover 151.

[0057] Next, in Figure 7 In the process, the semiconductor device 200 is removed from the clamp, and conductive bumps 207 are formed on the conductive pads 205 on the lower surface of the substrate 209. The conductive bumps 207 can be solder balls, copper pillars, or combinations thereof. Thus, the semiconductor device 100, the passive component 211, and the conductive bumps 207 are electrically interconnected through conductive parts (e.g., wires or vias) of the substrate 209.

[0058] Figures 8 to 11 A cross-sectional view of a semiconductor device 200A at various stages of manufacturing according to another embodiment is shown. Figure 8 The semiconductor device 200A in the middle is similar to Figure 2 Semiconductor device 200 is present, but two semiconductor devices 100 (e.g., 100A and 100B) are attached to the upper surface of substrate 209. Each of the two semiconductor devices 100 has a... Figure 1A The semiconductor devices 100 have the same or similar on-chip structure as the wafer. Note that, although Figure 8 Two semiconductor devices 100 are shown, but other numbers (such as three, four or more) of semiconductor devices 100 may be attached to the substrate 209, and these and other variations are fully intended to be included within the scope of the invention.

[0059] Next, in Figure 9 In this process, a TIM film 141 is placed (e.g., laminated) above the upper surfaces of semiconductor devices 100A and 100B. It should be noted that... Figure 9 In this example, a monolithic TIM film 141 is placed on semiconductor devices 100A and 100B. In other words, the TIM film 141 extends continuously from semiconductor device 100A to semiconductor device 100B. Similar to... Figures 3A to 3E The TIM film 141 completely covers the upper surfaces of semiconductor devices 100A and 100B and has an edge portion 141E that extends beyond the lateral extent of semiconductor devices 100A and 100B (e.g., beyond the sidewalls).

[0060] Next, in Figure 10In this process, cover 151 is attached to the upper surface of substrate 209. Semiconductor devices 100A and 100B, TIM film 141, and passive component 211 are disposed in an enclosed space between cover 151 and substrate 209. TIM film 141 contacts (e.g., physically contacts) cover 151 and semiconductor devices 100A and 100B.

[0061] Next, in Figure 11 In the process, semiconductor device 200A is clamped between the top clamp 157 and the bottom clamp 159 of a clamp. Next, a heating process is performed to cure the TIM film 141. After the heating process, semiconductor device 200A is removed from the clamp, and conductive bumps 207 are formed on the lower surface of substrate 209. The process and... Figure 7 The processing is the same or similar, so the details will not be repeated here.

[0062] Figures 12 to 14 A cross-sectional view of a semiconductor device 200B at various stages of manufacturing according to another embodiment is shown. Figure 12 The semiconductor device 200B is similar to Figure 9 The semiconductor device 200A is located in the semiconductor device 100, but two separate TIM films 141 are each placed on the corresponding semiconductor device 100 (e.g., 100A or 100B). The edge portion 141E of each TIM film 141 extends beyond the lateral extent of the underlying semiconductor device 100 (e.g., beyond the sidewall).

[0063] Next, in Figure 13 In this configuration, cover 151 is attached to the upper surface of substrate 209. Semiconductor devices 100A and 100B, TIM film 141, and passive component 211 are disposed in an enclosed space between cover 151 and substrate 209. Each contact (e.g., physical contact) in TIM film 141 is between cover 151 and the underlying semiconductor device 100.

[0064] Next, in Figure 14 In the process, the semiconductor device 200B is clamped between the top clamp 157 and the bottom clamp 159 of the clamp. Next, a heating process is performed to cure the TIM film 141. After the heating process, the semiconductor device 200B is removed from the clamp, and conductive bumps 207 are formed on the lower surface of the substrate 209. The process and... Figure 7 The processing is the same or similar, so the details will not be repeated here.

[0065] Figures 15 to 17 Cross-sectional views of a semiconductor device 200C at various stages of manufacturing according to yet another embodiment are shown. Figure 15 In this process, the TIM film 141 is attached (e.g., laminated) to the lower surface of the top 151T of the cover 151.

[0066] Next, in Figure 16 In this process, for example, adhesive 153 is used to attach the cover 151 with the TIM film 141 attached to it to the upper surface of the substrate 209. Semiconductor devices 100A and 100B, the TIM film 141, and passive component 211 are disposed in an enclosed space between the cover 151 and the substrate 209. The TIM film 141 contacts (e.g., physically contacts) the cover 151 and the underlying semiconductor device 100. Note that although... Figure 16 The diagram shows one TIM film 141, but two TIM films 141 can be used, each TIM film 141 placed on a corresponding semiconductor device 100, and... Figure 13 Same or similar.

[0067] Next, in Figure 17 In the process, the semiconductor device 200C is clamped between the top clamp 157 and the bottom clamp 159 of the clamp. Next, a heating process is performed to cure the TIM film 141. After the heating process, the semiconductor device 200C is removed from the clamp, and conductive bumps 207 are formed on the lower surface of the substrate 209. The process and... Figure 7 The processing is the same or similar, so the details will not be repeated here.

[0068] The embodiments offer advantages. Compared to gel-type TIM materials, using TIM film 141 achieves higher thermal conductivity for more efficient heat dissipation. For example, the disclosed method using TIM film 141 achieves a 50% or greater improvement in heat dissipation efficiency compared to gel-type TIM materials. The shape and thickness of TIM film 141 can be easily controlled to achieve excellent coverage of over 99% on the upper surface of semiconductor device 100 after TIM film 141 has cured. Void problems (e.g., bubbles) caused by using conventional gel-type TIM materials are avoided. Because TIM film 141 is prefabricated, it is easily used in manufacturing processes to achieve higher yields than gel-type or liquid-type TIM materials.

[0069] Figure 18 A flowchart of a method 1000 for forming a semiconductor structure in some embodiments is shown. It should be understood that... Figure 18 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 18 The steps shown.

[0070] refer to Figure 18At frame 1010, a semiconductor device is attached to a first surface of the substrate. At frame 1020, a thermal interface material (TIM) film is placed over a first side of the semiconductor device away from the substrate, wherein the TIM film is pre-formed before placement, and wherein, after placement, the peripheral portion of the TIM film extends laterally beyond the sidewall of the semiconductor device. At frame 1030, a cover is attached to the first surface of the substrate to form a closed space between the cover and the substrate, wherein, after attaching the cover, the semiconductor device and the TIM film are disposed in the closed space, wherein the first side of the TIM film away from the substrate is in contact with the cover.

[0071] According to an embodiment, a method for forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device remote from the substrate, wherein the TIM film is pre-formed prior to the placement, and wherein, after the placement, a peripheral portion of the TIM film extends laterally beyond the sidewall of the semiconductor device; and attaching a cover to the first surface of the substrate to form a closed space between the cover and the substrate, wherein, after attaching the cover, the semiconductor device and the TIM film are disposed in the closed space, and wherein the first side of the TIM film remote from the substrate contacts the cover. In an embodiment, after attaching the cover, a second side of the TIM film facing the substrate contacts the first side of the semiconductor device. In an embodiment, the method further includes: surrounding the semiconductor device with a molding material prior to placing the TIM film, wherein, after placing the TIM film, the peripheral portion of the TIM film extends laterally beyond the sidewall of the molding material. In an embodiment, the second side of the TIM film further contacts the top surface of the molding material remote from the substrate. In one embodiment, attaching the cover is performed after placing the TIM film, wherein the method further includes, after placing the TIM film and before attaching the cover, using rollers to press the TIM film against the first side of the semiconductor device. In another embodiment, the method further includes, before attaching the cover, attaching the TIM film to an inner surface of the cover located between opposing inner sidewalls of the cover, wherein attaching the cover to the first surface of the substrate such that the TIM film is placed on the first side of the semiconductor device. In yet another embodiment, the method further includes, before placing the TIM film, attaching another semiconductor device to the first surface of the substrate, wherein the TIM film is placed above the semiconductor device and above the other semiconductor device, wherein, after placing the TIM film, the TIM film extends continuously from the semiconductor device to the other semiconductor device, wherein, after attaching the cover, the other semiconductor device is disposed within the enclosed space. In one embodiment, the method further includes, before placing the TIM film: attaching another semiconductor device to the first surface of the substrate; and placing another pre-formed TIM film on the other semiconductor device, wherein, after attaching the cover, the other semiconductor device and the other pre-formed TIM film are disposed within the enclosed space. In another embodiment, the method further includes, after attaching the cover: clamping the substrate and the cover between a top clamp and a bottom clamp; and while clamping the substrate and the cover between the top clamp and the bottom clamp, heating the substrate and the cover for a predetermined time period.In one embodiment, the method further includes, after heating: removing the top clamp and the bottom clamp; and forming a conductive connector on a second surface of the substrate opposite to the first surface of the substrate. In one embodiment, the TIM film is a mixture of carbon and a polymer. In one embodiment, the thermal conductivity of the TIM film is greater than about 20 W / (m·K).

[0072] According to an embodiment, a method of forming a semiconductor structure includes: attaching a first semiconductor structure to a first surface of a substrate, wherein the first semiconductor structure includes: an interposer layer, wherein conductive bumps are formed on a first side of the interposer layer, wherein the conductive bumps are bonded to the first surface of the substrate; a first die, attached to a second side of the interposer layer opposite to the first side; and a molding material located on the second side of the interposer layer and around the first die; placing a thermal interface material (TIM) film on the first surface of the first semiconductor structure remote from the substrate, wherein the thermal interface material (TIM) film is pre-formed prior to the placement, wherein after the placement, the first surface of the first semiconductor structure is disposed within the boundary of the TIM film in a plan view; and attaching a cap to the first surface of the substrate above the first semiconductor structure to form a closed space between the cap and the substrate, wherein the first semiconductor structure and the TIM film are disposed in the closed space, wherein the lower side of the cap facing the substrate is in contact with the TIM film. In an embodiment, the TIM film is a mixture of carbon and a polymer, wherein the polymer is a resin-based polymer or an acrylic-based polymer. In an embodiment, the thermal conductivity of the TIM film is between approximately 20 W / (m·K) and approximately 80 W / (m·K). In an embodiment, the method further includes attaching a second semiconductor structure to the first surface of the substrate before placing the TIM film, wherein the TIM film is placed on both the first and second semiconductor structures, and wherein the TIM film extends continuously from the first semiconductor structure to the second semiconductor structure. In an embodiment, the method further includes, after placing the TIM film and before attaching the cover, pressing the TIM film against the first surface of the first semiconductor structure by rolling a roller over the TIM film.

[0073] According to an embodiment, the semiconductor structure includes: a substrate; a semiconductor device located above and electrically coupled to a first surface of the substrate; a molding material located around the semiconductor device; a thermal interface material (TIM) film located above the molding material and the semiconductor device, wherein the TIM film covers an upper surface of the semiconductor device remote from the substrate, wherein a peripheral portion of the TIM film extends laterally beyond the sidewalls of the molding material; and a cap attached to the first surface of the substrate, wherein the semiconductor device, the molding material, and the TIM film are disposed in an enclosed space between the cap and the substrate, wherein a first side of the TIM film remote from the substrate contacts the cap. In an embodiment, a second side of the TIM film facing the substrate contacts the first side of the semiconductor device. In an embodiment, the TIM film is a mixture of carbon and a polymer, and wherein the thermal conductivity of the TIM film is greater than about 20 W / (m·K).

Claims

1. A method for forming a semiconductor structure, the method comprising: Attach the semiconductor device to the first surface of the substrate; A thermal interface material film is placed above a first side of the semiconductor device away from the substrate, wherein the thermal interface material film is pre-formed prior to placement, and wherein, after placement, a peripheral portion of the thermal interface material film extends laterally beyond the sidewall of the semiconductor device, wherein the peripheral portion of the thermal interface material film is closer to the substrate than a central portion disposed above the center of the first side of the semiconductor device, and wherein the peripheral portion of the thermal interface material film and the central portion of the thermal interface material film have the same thickness; and The cover is attached to the first surface of the substrate to form a closed space between the cover and the substrate, wherein, after the cover is attached, the semiconductor device and the thermal interface material film are disposed in the closed space, wherein a first side of the thermal interface material film away from the substrate is in contact with the cover.

2. The method according to claim 1, wherein, After the cover is attached, the second side of the thermal interface material film facing the substrate contacts the first side of the semiconductor device.

3. The method according to claim 2, further comprising: Before the thermal interface material film is placed, the semiconductor device is surrounded by a molding material, wherein, after the thermal interface material film is placed, the peripheral portion of the thermal interface material film extends laterally beyond the sidewall of the molding material.

4. The method according to claim 3, wherein, The second side of the thermal interface material film further contacts the top surface of the molding material away from the substrate.

5. The method according to claim 1, wherein, The attachment of the cover is performed after the thermal interface material film is placed, wherein the method further includes actions performed after the thermal interface material film is placed and before the cover is attached: Rollers are used to press the thermal interface material film against the first side of the semiconductor device.

6. The method according to claim 1, further comprising: Before attaching the cover, the thermal interface material film is attached to the inner surface of the cover located between the opposing inner sidewalls of the cover, wherein attaching the cover to the first surface of the substrate causes the thermal interface material film to be placed on the first side of the semiconductor device.

7. The method of claim 1, further comprising, before placing the thermal interface material film: Another semiconductor device is attached to the first surface of the substrate, wherein... The thermal interface material film is placed above the semiconductor device and above the other semiconductor device, wherein, after the thermal interface material film is placed, the thermal interface material film extends continuously from the semiconductor device to the other semiconductor device, wherein, after the cover is attached, the other semiconductor device is disposed in the enclosed space.

8. The method of claim 1, further comprising, before placing the thermal interface material film: Attaching another semiconductor device to the first surface of the substrate; and Another pre-formed thermal interface material film is placed on the other semiconductor device, wherein, After attaching the cover, the other semiconductor device and the other pre-formed thermal interface material film are disposed within the enclosed space.

9. The method of claim 1, further comprising, after attaching the cover: The substrate and the cover are clamped between the top clamp and the bottom clamp; and While the substrate and the cover are clamped between the top clamp and the bottom clamp, the substrate and the cover are heated for a predetermined period of time.

10. The method of claim 9, further comprising, after the heating: Remove the top clamp and the bottom clamp; and A conductive connector is formed on a second surface of the substrate opposite to the first surface of the substrate.

11. The method according to claim 1, wherein, The thermal interface material film is a mixture of carbon and polymer.

12. The method according to claim 11, wherein, The thermal conductivity of the thermal interface material film is greater than 20 W / (m·K).

13. A method for forming a semiconductor structure, the method comprising: A first semiconductor structure is attached to a first surface of a substrate, wherein the first semiconductor structure comprises: An interposer layer, wherein conductive bumps are formed on a first side of the interposer layer, wherein the conductive bumps are bonded to the first surface of the substrate; A first die is attached to a second side of the interposer opposite to the first side; and Molding material is located on the second side of the intermediate layer and around the first die; A thermal interface material film is placed on a first surface of the first semiconductor structure away from the substrate, wherein the thermal interface material film is pre-formed as a sheet of uniform thickness before placement, wherein after placement, the first surface of the first semiconductor structure is disposed within the boundary of the thermal interface material film in a plan view, wherein the peripheral portion of the thermal interface material film extends beyond the sidewall of the molding material, wherein the peripheral portion of the thermal interface material film is closer to the substrate than the central portion of the thermal interface material film disposed above the center of the first surface of the first semiconductor structure, wherein the peripheral portion of the thermal interface material film and the central portion of the thermal interface material film have the same thickness; and A cover is attached to the first surface of the substrate above the first semiconductor structure to form a closed space between the cover and the substrate, wherein the first semiconductor structure and the thermal interface material film are disposed in the closed space, and wherein the lower side of the cover facing the substrate is in contact with the thermal interface material film.

14. The method according to claim 13, wherein, The thermal interface material film is a mixture of carbon and a polymer, wherein the polymer is a resin-based polymer or an acrylic-based polymer.

15. The method according to claim 14, wherein, The thermal conductivity of the thermal interface material film is between 20 W / (m·K) and 80 W / (m·K).

16. The method of claim 13, further comprising: Before placing the thermal interface material film, a second semiconductor structure is attached to the first surface of the substrate, wherein the thermal interface material film is placed on the first semiconductor structure and the second semiconductor structure, and wherein the thermal interface material film extends continuously from the first semiconductor structure to the second semiconductor structure.

17. The method of claim 13, further comprising, after placing the thermal interface material film and before attaching the cover: The thermal interface material film is pressed against the first surface of the first semiconductor structure by rolling a roller on the thermal interface material film.

18. A semiconductor structure comprising: Substrate; A semiconductor device is located above and electrically coupled to the first surface of the substrate; Molding material is located around the semiconductor device; A thermal interface material film is located above the molding material and the semiconductor device, wherein the thermal interface material film covers the upper surface of the semiconductor device away from the substrate, wherein a peripheral portion of the thermal interface material film extends laterally beyond the sidewalls of the molding material, wherein the peripheral portion of the thermal interface material film is closer to the substrate than a central portion disposed above the center of the upper surface of the semiconductor device, and wherein the peripheral portion of the thermal interface material film and the central portion of the thermal interface material film have the same thickness; and A cover is attached to the first surface of the substrate, wherein the semiconductor device, the molding material, and the thermal interface material film are disposed in an enclosed space between the cover and the substrate, wherein a first side of the thermal interface material film away from the substrate is in contact with the cover.

19. The semiconductor structure according to claim 18, wherein, The second side of the thermal interface material film facing the substrate is in contact with the first side of the semiconductor device.

20. The semiconductor structure according to claim 18, wherein, The thermal interface material film is a mixture of carbon and polymer, and wherein the thermal conductivity of the thermal interface material film is greater than 20 W / (m·K).

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