Semiconductor structure and method of forming the same
By arranging the channel-all-around and source-drain-all-around structures, the manufacturing process of semiconductor structures is simplified, electrical performance is improved, manufacturing costs are reduced, and integration density and current are increased, thus solving the problem of electrical performance degradation in semiconductor structures such as DRAM during the miniaturization process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-09-15
- Publication Date
- 2026-07-24
AI Technical Summary
In the pursuit of faster response rates, lower power consumption, and higher storage density, existing semiconductor structures such as DRAM face increased manufacturing difficulties and increased contact resistance between bit lines and transistors, leading to a decline in electrical performance.
The design employs a channel-encircling structure and a first source-drain region-encircling structure, simplifying the manufacturing process and improving electrical performance through special arrangement and lead connection of word lines and bit lines.
It simplifies the manufacturing process of semiconductor structures, reduces manufacturing costs, and improves electrical performance and integration, increases the internal current of memory cells, and improves electrical performance.
Smart Images
Figure CN115440732B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] DRAM and other semiconductor structures typically employ buried word line or horizontal word line structures, electrically connecting the bit lines to the transistor faces. In pursuit of faster response times, lower power consumption, and higher storage density, the size of DRAM and other semiconductor structures continues to shrink. This increases the manufacturing difficulty of buried or horizontal word line structures, leading to increased contact resistance between the bit lines and transistors, and consequently, a decline in the electrical performance of the semiconductor structure.
[0004] Therefore, how to improve the electrical performance of semiconductor structures while simplifying the semiconductor structure manufacturing process is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to simplify the manufacturing process of the semiconductor structures and improve their electrical performance.
[0006] According to some embodiments, this disclosure provides a semiconductor structure, including:
[0007] Substrate;
[0008] A stacked structure located on the substrate includes a plurality of memory cells spaced apart along a first direction. Each memory cell includes a transistor, and each transistor includes an active structure and a gate structure. The active structure includes a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a second direction. The channel region surrounds the outer periphery of the gate structure. The first direction is perpendicular to the top surface of the substrate, and the second direction is parallel to the top surface of the substrate.
[0009] A word line structure, located on the substrate, includes a plurality of word lines spaced apart along the first direction. Each word line includes a word line body portion extending along the first direction, and the word line body portion is electrically connected to the gate structure.
[0010] Bit line structure, located on the substrate, includes multiple bit lines spaced apart along the first direction. Each bit line includes a bit line body portion extending along the first direction, and the first source / drain region surrounds the outer periphery of the bit line body portion.
[0011] In some embodiments, the stacked structure further includes two memory cells arranged along the second direction, and the two memory cells arranged along the second direction share a first source-drain region, and the two channel regions are located on opposite sides of the shared first source-drain region;
[0012] The first source-drain region shared by the two memory cells arranged along the second direction surrounds the outer periphery of one of the bit line main bodies;
[0013] The word line structure further includes word lines arranged at intervals along the second direction, and the gate structures in two adjacent memory cells along the second direction are respectively connected to two adjacent word lines along the second direction.
[0014] In some embodiments, the memory cell includes a plurality of transistors spaced apart along the first direction;
[0015] The word line body is electrically connected to the gate structure of one of the plurality of transistors arranged at intervals along the first direction within the memory cell.
[0016] The bit line body portion is electrically connected to the first source / drain region of one of the plurality of transistors spaced apart along the first direction in the memory cell, and the first source / drain region of one of the plurality of transistors spaced apart along the first direction in the memory cell surrounds the outer periphery of the bit line body portion.
[0017] In some embodiments, the storage unit further includes a capacitor, the capacitor comprising:
[0018] The lower electrode layer continuously covers at least a portion of the surface of the second source / drain region of a plurality of transistors spaced apart along the first direction;
[0019] A dielectric layer that covers the entire surface of the lower electrode layer;
[0020] The upper electrode layer covers the entire surface of the dielectric layer.
[0021] In some embodiments, the stacked structure includes a plurality of memory cells spaced apart along a third direction, the third direction being parallel to the top surface of the substrate, and the second direction intersecting the third direction;
[0022] Each word line includes a plurality of word line main bodies spaced apart along the third direction, and a word line extension portion extending along the third direction and electrically connected to the plurality of word line main bodies spaced apart along the third direction. The plurality of word line main bodies included in the word line are electrically connected one-to-one with the gate structures in the plurality of memory cells spaced apart along the third direction.
[0023] In some embodiments, the bit line further includes:
[0024] The bit line extension is located above the bit line body and is electrically connected to the bit line body, and the bit line extension extends along the second direction;
[0025] Along the first direction, the bit line extensions electrically connected to the same memory cell are located above the corresponding word line extensions.
[0026] In some embodiments, the stacking structure further includes a plurality of the storage cells spaced apart along the second direction;
[0027] Each bit line includes a plurality of bit line body portions spaced apart along the second direction, and the bit line extension portion is electrically connected to the plurality of bit line body portions spaced apart along the second direction.
[0028] In some embodiments, it also includes:
[0029] The word line lead structure includes multiple word line leads that are electrically connected one-to-one with the ends of the word line extensions of a plurality of word lines spaced apart along the first direction;
[0030] Bit line lead structure includes multiple bit line leads that are electrically connected one-to-one with the ends of the bit line extensions of multiple bit lines spaced apart along the first direction;
[0031] The peripheral circuit is located outside the stacked structure, and the bit line leads and word line leads are electrically connected to the peripheral circuit.
[0032] The extension direction of the bit line lead intersects with the extension direction of the bit line extension; or, the extension direction of the word line lead intersects with the extension direction of the word line extension.
[0033] In some embodiments, the peripheral circuitry is located outside the stacked structure along the second direction, and both the word lines and the bit lines extend along the second direction; or,
[0034] The peripheral circuit is located outside the stacked structure along the third direction, and both the word line lead and the bit line lead extend along the third direction.
[0035] In some embodiments, the peripheral circuitry includes a first peripheral circuitry and a second peripheral circuitry distributed along the second direction on opposite sides of the stacked structure;
[0036] For two adjacent word lines along the second direction, the word line lead electrically connected to the word line extension of one word line closer to the first peripheral circuit is electrically connected to the first peripheral circuit, and the word line lead electrically connected to the word line extension of the other word line is electrically connected to the second peripheral circuit.
[0037] For two adjacent bit lines along the first direction, the bit line lead electrically connected to the bit line extension of one of the bit lines is electrically connected to the first peripheral circuit, and the bit line lead electrically connected to the bit line extension of the other bit line is electrically connected to the second peripheral circuit.
[0038] In some embodiments, the peripheral circuitry includes a first peripheral circuitry and a second peripheral circuitry distributed on different sides of the stacked structure;
[0039] The word line leads are electrically connected to the first peripheral circuit, and the bit line leads are electrically connected to the second peripheral circuit.
[0040] According to other embodiments, this disclosure also provides a method for forming a semiconductor structure, comprising the following steps:
[0041] Provide substrate;
[0042] The following cyclic steps are performed multiple times until a stacked structure comprising a plurality of memory cells spaced apart along a first direction perpendicular to the top surface of the substrate is formed on the substrate, the cyclic steps comprising:
[0043] A plurality of semiconductor layers are formed on the substrate at intervals along the first direction. Each semiconductor layer includes an active structure, which includes a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a second direction, the second direction being parallel to the top surface of the substrate.
[0044] A gate structure, word lines, and bit lines are formed on the substrate. The channel region surrounds the outer periphery of the gate structure. The word line includes a word line body portion extending along the first direction and electrically connected to the gate structure. The bit line includes a bit line body portion extending along the first direction. The first source / drain region surrounds the outer periphery of the bit line body portion. The memory cell includes the active structure and the gate structure.
[0045] An interlayer isolation layer is formed above the memory cell, the word line, and the bit line, and the interlayer isolation layer is used as the substrate for the next cycle step.
[0046] In some embodiments, the semiconductor layer includes a plurality of active structures spaced apart along a third direction, and a plurality of word line bodies penetrate the channel regions of the plurality of active structures one by one along the first direction, the third direction being parallel to the top surface of the substrate, and the second direction intersecting the third direction; the step of forming a gate structure, word lines, and bit lines on the substrate includes:
[0047] A bit line body portion is formed that extends through the first source / drain region of the plurality of semiconductor layers along the first direction;
[0048] A gate structure is formed that penetrates the channel region in the semiconductor layer along the first direction, and a word line body portion is electrically connected to a plurality of the gate structures;
[0049] A character line extension is formed above the character line body portion. The character line extension extends along the third direction and is electrically connected to a plurality of character line bodies arranged at intervals along the third direction. The character line includes the character line body portion and the character line extension portion.
[0050] A bit line extension portion electrically connected to the bit line main body portion is formed above the bit line main body portion. The bit line extension portion extends along the second direction. Along the first direction, the bit line extension portion electrically connected to the same active structure is located above the word line extension portion.
[0051] In some embodiments, before forming an interlayer isolation layer above the memory cell, the word line, and the bit line, the following steps are further included:
[0052] A lower electrode layer is formed that continuously covers the second source / drain regions of the plurality of active structures spaced apart along the first direction, respectively.
[0053] A dielectric layer is formed covering the entire surface of the lower electrode layer;
[0054] An upper electrode layer is formed covering the entire surface of the dielectric layer to form a capacitor comprising the lower electrode layer, the dielectric layer, and the upper electrode layer.
[0055] In some embodiments, the following steps are also included:
[0056] A peripheral circuit located outside the stacked structure is formed on the substrate;
[0057] A word line lead structure and a bit line lead structure are formed. The word line lead structure includes multiple word line leads that are electrically connected to the ends of the word line extensions of multiple word lines arranged at intervals along the first direction. The bit line lead structure includes multiple bit line leads that are electrically connected to the ends of the bit line extensions of multiple bit lines arranged at intervals along the first direction. Both the word line leads and the bit line leads are electrically connected to the peripheral circuit.
[0058] The extension direction of the bit line lead intersects with the extension direction of the bit line extension; or, the extension direction of the word line lead intersects with the extension direction of the word line extension.
[0059] The semiconductor structure and its formation method provided in some embodiments of this disclosure improve the electrical performance of the semiconductor structure by distributing the channel region in the memory cell around the outer periphery of the gate structure to form a channel-all-around structure, and distributing the first source / drain region around the outer periphery of the bit line body to form a first source / drain region-all-around structure. Furthermore, the word line body electrically connecting the gate structure within the memory cell and the bit line body electrically connecting the first source / drain region within the memory cell extend in the same direction (e.g., both extending in a direction perpendicular to the top surface of the substrate), which simplifies the semiconductor structure manufacturing process and reduces manufacturing costs. Additionally, the stacked structure in some embodiments of this disclosure includes multiple memory cells. Word lines electrically connected to the multiple memory cells can be led out through word line leads, and the lead-out direction of the word lines can be adjusted through the word line leads. Bit lines electrically connected to the multiple memory cells can be led out through bit lines, and the lead-out direction of the bit lines can be adjusted through the bit line leads. This not only improves the flexibility of arranging multiple memory cells within the stacked structure but also helps to further improve the integration density of the semiconductor structure. Other embodiments of this disclosure provide a memory cell that includes multiple transistors connected in parallel, which can increase the current inside the memory cell, thereby further improving the electrical performance of the semiconductor structure. Attached Figure Description
[0060] Appendix Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure in one embodiment of a specific implementation of this disclosure;
[0061] Appendix Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure in another embodiment of the specific implementation of this disclosure;
[0062] Appendix Figure 3 It is attached Figure 2 The diagram shows a top view of the semiconductor structure.
[0063] Appendix Figure 4 It is attached Figure 3 Cross-sectional diagrams at positions aa, bb, and cc;
[0064] Appendix Figure 5 This is a schematic diagram of the capacitor structure in a specific embodiment of this disclosure;
[0065] Appendix Figure 6 This is a schematic diagram showing the connection between the word line leads, bit line leads, and peripheral circuits in a specific embodiment of this disclosure;
[0066] Appendix Figure 7 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;
[0067] Appendix Figure 8 - Appendix Figure 13 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to the specific embodiments of this disclosure. Detailed Implementation
[0068] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0069] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure according to one embodiment of the present disclosure, with attached... Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure in another embodiment of the specific implementation of this disclosure, with attached... Figure 3 It is attached Figure 2 The diagram shows a top view of the semiconductor structure, with accompanying illustrations. Figure 4 It is attached Figure 3 Cross-sectional diagrams at positions aa, bb, and cc. (See diagram.) Figures 1-4 As shown, the semiconductor structure includes:
[0070] Substrate 40;
[0071] The stacked structure, located on the substrate 40, includes a plurality of memory cells spaced apart along a first direction D1. Each memory cell includes a transistor, and each transistor includes an active structure and a gate structure. The active structure includes a channel region 11 and a first source / drain region 10 and a second source / drain region 12 located on opposite sides of the channel region 11 along a second direction D2. The channel region 11 is distributed around the outer periphery of the gate structure. The first direction D1 is perpendicular to the top surface of the substrate 40, and the second direction D2 is parallel to the top surface of the substrate 40.
[0072] The word line structure is located on the substrate 40 and includes multiple word lines arranged at intervals along the first direction D1. Each word line includes a word line body portion 13 extending along the first direction D1 and the word line body portion 13 is electrically connected to the gate structure.
[0073] The bit line structure is located on the substrate 40 and includes multiple bit lines arranged at intervals along the first direction D1. Each bit line includes a bit line body portion 15 extending along the first direction D1, and a first source / drain region 10 is distributed around the outer periphery of the bit line body portion 15.
[0074] The semiconductor structure in this specific embodiment can be, but is not limited to, DRAM. This specific embodiment uses DRAM as an example for illustration. Specifically, the substrate 40 can be, but is not limited to, a silicon substrate. This specific embodiment uses silicon as an example for illustration. In other embodiments, the substrate 40 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 40 is used to support the device structure on it. The top surface of the substrate 40 refers to the surface of the substrate 40 facing the memory cell. The stacked structure located on the top surface of the substrate 40 includes at least memory cells and an interlayer isolation layer 18 alternately stacked along the first direction D1. The memory cell includes a transistor, and the transistor includes an active structure and a gate structure. In one example, the material of the interlayer isolation layer 18 can be an insulating dielectric material such as an oxide material (e.g., silicon dioxide) or a nitride material (e.g., silicon nitride). The first source / drain region 10 is used as one of the source and drain regions of the transistor, and the second source / drain region 12 is used as the other of the source and drain regions of the transistor. The gate structure includes a gate conductive structure and a gate dielectric structure. The channel region 11 is separated from the gate conductive structure by the gate dielectric structure, and the gate dielectric structure at least covers the area of the channel region opposite to the gate conductive structure.
[0075] In this specific embodiment, both the word line body portion 13 and the bit line body portion 15 extend along the first direction D1. The channel region 11 in the transistor is distributed around the outer periphery of the gate structure, and the first source / drain region 10 is distributed around the outer periphery of the bit line body portion 15. This allows the semiconductor structure to simultaneously possess both a fully surrounding channel structure and a fully surrounding first source / drain region structure. This not only increases the overlap area between the channel region 11 and the gate structure and the contact area between the first source / drain region 10 and the bit line body portion 15, thereby improving the electrical performance of the semiconductor structure, but also eliminates the need for complex manufacturing processes to form an embedded bit line structure and a single horizontal word line structure, thus simplifying the semiconductor structure manufacturing process and reducing manufacturing costs. Furthermore, since a single horizontal word line structure is not required, the number of memory cells stacked along the first direction D1 in the stacked structure can be increased, and the stability of the semiconductor structure can be improved.
[0076] In some embodiments, the active structure is made of silicon, and the channel region 11, the first source / drain region 10, and the second source / drain region 12 contain the same type of doped ions, and the ion doping concentration of the first source / drain region 10 and the ion doping concentration of the second source / drain region 12 are both greater than the ion doping concentration of the channel region 11.
[0077] In other embodiments, the active structure is made of oxide semiconductor material.
[0078] In one example, the transistors in the memory cell are junctionless transistors. For instance, the channel region 11, the first source / drain region 10, and the second source / drain region 12 in the active structure all contain N-type doped ions, and both the first source / drain region 10 and the second source / drain region 12 are heavily doped, while the channel region 11 is lightly doped. In another example, the active structure is made of an oxide semiconductor material, wherein the oxide semiconductor material is any one or a combination of two or more of In₂O₃ (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxynitride). Preferably, the active structure is made of IGZO.
[0079] In some embodiments, the stacked structure further includes two memory cells arranged along the second direction D2, and the two memory cells arranged along the second direction D2 share a first source-drain region 10, and the two channel regions 11 are located on opposite sides of the shared first source-drain region 10.
[0080] The first source-drain region 10 shared by two memory cells arranged along the second direction D2 surrounds the outer periphery of a bit line body portion 15;
[0081] The word line structure also includes word lines spaced apart along the second direction D2, and the gate structures in two adjacent memory cells along the second direction D2 are respectively connected to the two adjacent word lines along the second direction D2.
[0082] Specifically, such as Figure 1 and Figure 2 As shown, the semiconductor structure includes a semiconductor layer 17 located above the substrate 40. The semiconductor layer 17 includes two active structures arranged along a second direction D2. Each active structure includes a channel region 11 and a first source / drain region 10 and a second source / drain region 12 distributed along the second direction D2 on opposite sides of the channel region 11. The two active structures share a single first source / drain region 10. The shared first source / drain region 10 in the two memory cells arranged along the second direction D2 surrounds the outer periphery of a bit line body portion 15, meaning that a bit line body portion 15 is electrically connected to the two memory cells arranged along the second direction D2, thereby further improving the integration density of the semiconductor structure. The gate structures in the two memory cells arranged along the second direction D2 are respectively electrically connected to the word line body portions 13 of two word lines to facilitate read / write control of different memory cells.
[0083] In some embodiments, the memory cell includes a plurality of transistors spaced apart along a first direction D1;
[0084] The word line body 13 is electrically connected to the gate structure of a plurality of transistors arranged at intervals along the first direction D1 within the memory cell;
[0085] The bit line body portion 15 is electrically connected to the first source / drain region 10 of a plurality of transistors arranged at intervals along the first direction D1 in the memory cell, and the first source / drain region 10 of the plurality of transistors arranged at intervals along the first direction D1 in the memory cell surrounds the outer periphery of the bit line body portion 15.
[0086] For example, such as Figures 2-4 As shown, the memory cell includes a plurality of transistors arranged at intervals along the first direction D1, and the plurality of transistors in the same memory cell are electrically connected to the bit line body portion 15 and the word line body portion 13, so that the memory cell includes a plurality of transistors connected in parallel, thereby increasing the current inside the memory cell and further improving the electrical performance of the semiconductor structure.
[0087] In one example, such as Figures 2-4 As shown, the semiconductor structure includes multiple semiconductor layers 17 arranged at intervals along a first direction D1. Each semiconductor layer 17 includes two active structures arranged along a second direction D2, and the two active structures share a first source-drain region 10. This allows two adjacent memory cells along the second direction D2 to each include multiple transistors connected in parallel, so that the current flowing through the two adjacent memory cells along the second direction D2 is the same after they are selected, thereby further improving the electrical performance of the semiconductor structure.
[0088] Appendix Figure 5 This is a schematic diagram of the capacitor structure in a specific embodiment of this disclosure. In some embodiments, such as Figure 5 As shown, the storage unit also includes a capacitor, which includes:
[0089] The lower electrode layer 50 continuously covers at least a portion of the surface of the second source / drain regions 12 of a plurality of transistors spaced apart along the first direction D1;
[0090] Dielectric layer 51 covers the entire surface of lower electrode layer 50;
[0091] The upper electrode layer 52 covers the entire surface of the dielectric layer 51.
[0092] Specifically, the semiconductor structure also includes a drain isolation layer 32, which is located between adjacent transistor structures along the first direction D1 and covers a portion of the surface of the second source-drain region 12 in the active structure. The drain isolation layer 32 is used to isolate word lines and capacitors. The lower electrode layer 50 continuously covers at least a portion of the surface of the second source-drain region 12 of all transistors in the memory cell and covers the sidewalls of the drain isolation layer 32. The dielectric 51 continuously covers the entire surface of the lower electrode layer 50, and the upper electrode layer 52 continuously covers the entire surface of the dielectric layer 51. In this specific embodiment, only one capacitor is provided in the memory cell, and the capacitor is electrically connected to the second source-drain region 12 of all transistors in the memory cell. On the one hand, the surface area of the capacitor (including the surface area of the lower electrode layer 50, the surface area of the dielectric layer 51, and the surface area of the upper electrode layer 52) can be increased, thereby increasing the capacitance of the capacitor in the memory cell. On the other hand, the length of the capacitor along the second direction D2 can be relatively shortened (i.e., the horizontal length of the capacitor is reduced), thereby helping to reduce the size of the memory cell and the semiconductor structure. In addition, multiple parallel transistors within the memory cell are electrically connected to the same capacitor contact, thereby eliminating the need to form multiple independent capacitors spaced along the first direction D1 within the memory cell, simplifying the semiconductor structure manufacturing process and reducing the manufacturing cost of the semiconductor structure.
[0093] In some embodiments, the stacked structure includes a plurality of memory cells spaced apart along a third direction D3, the third direction D3 being parallel to the top surface of the substrate 40, and the second direction D2 intersecting the third direction D3.
[0094] Each word line includes a plurality of word line body portions 13 spaced apart along a third direction D3, and a word line extension portion 14 extending along a third direction D3 and electrically connected to the plurality of word line body portions 13 spaced apart along a third direction D3. The plurality of word line body portions 13 included in the word line are electrically connected to the gate structures in the plurality of memory cells spaced apart along a third direction D3.
[0095] Specifically, the semiconductor structure includes a plurality of memory cells spaced apart along a third direction D3, and a memory region isolation layer 31 located between adjacent memory cells. The memory region isolation layer 31 is used not only to isolate adjacent memory cells along the third direction D3, but also to support the semiconductor structure. In one example, the material of the memory region isolation layer 31 can be a nitride material (e.g., silicon nitride). Each word line includes a plurality of word line body portions 13 spaced apart along a third direction D3, and the plurality of word line body portions 13 are electrically connected to the gate structure in the plurality of memory cells spaced apart along the third direction D3. A word line extension portion 14 is located on the top surface of the word line body portion 13 and extends along the third direction D3. The word line extension portion 14 is electrically connected to all word line body portions 13 located in the same word line. On the one hand, control signals can be transmitted to multiple memory cells simultaneously through a single word line extension portion 14, simplifying the control operation of the semiconductor structure; on the other hand, it also helps to simplify the specific structure of the semiconductor structure and reduce the manufacturing difficulty of the semiconductor structure (e.g., it eliminates the need to form a single horizontal word line structure).
[0096] In some embodiments, the bit line further includes:
[0097] Bit line extension 16 is located above bit line body 15 and electrically connected to bit line body 15, and bit line extension 16 extends along the second direction D2.
[0098] Along the first direction D1, the bit line extension 16 electrically connected to the same memory cell is located above the corresponding word line extension 14.
[0099] In some embodiments, the stacked structure further includes a plurality of storage cells spaced apart along the second direction D2;
[0100] Each bit line includes a plurality of bit line body portions 15 spaced apart along the second direction D2, and bit line extension portions 16 are electrically connected to the plurality of bit line body portions 15 spaced apart along the second direction D2.
[0101] Specifically, the semiconductor structure includes multiple memory cells spaced apart along a third direction D3, and multiple bit lines spaced apart along the third direction D3, with each bit line electrically connected to one of the multiple memory cells spaced apart along the third direction D3. Each bit line includes a bit line body portion 15, a bit line contact portion 30 located on the top surface of the bit line body portion 15 and electrically connected to the bit line body portion 15, and a bit line extension portion 16 located on the top surface of the bit line contact portion 30 and electrically connected to the bit line contact portion 30. In one example, along the first direction D1, the top surface of the bit line contact portion 30 is located above the top surface of the corresponding word line extension portion 14 to increase the distance between the bit line extension portion 16 and the word line extension portion 14 and reduce the parasitic capacitance effect between the bit line extension portion 16 and the word line extension portion 14. In this specific embodiment, the bit line extension 16 is disposed above the memory cell, and the bit line signal is transmitted to the memory cell through the bit line extension 16. On the one hand, the size of the semiconductor structure can be reduced and the integration of the semiconductor structure can be improved; on the other hand, the circuit routing structure between the peripheral circuit and the bit line can be simplified, thereby reducing the manufacturing process difficulty of the semiconductor structure.
[0102] Appendix Figure 6 This is a schematic diagram illustrating the connection between word line leads, bit line leads, and peripheral circuitry in a specific embodiment of this disclosure. In some embodiments, the semiconductor structure further includes:
[0103] The word line lead structure includes multiple word line leads 61 that are electrically connected one-to-one with the ends of word line extensions 14 in a plurality of word lines spaced apart along the first direction D1.
[0104] The bit line lead structure includes multiple bit line leads 62 that are electrically connected one-to-one with the ends of bit line extensions 16 in a plurality of bit lines spaced apart along the first direction D1.
[0105] The peripheral circuit 60 is located outside the stacked structure, and the bit line lead 62 and word line lead 61 are both electrically connected to the peripheral circuit 60.
[0106] The extension direction of bit line lead 62 intersects the extension direction of bit line extension 16; or, the extension direction of word line lead 61 intersects the extension direction of word line extension 14.
[0107] Specifically, the word line structure includes multiple word lines spaced apart along a first direction D1. Each word line includes a word line extension 14 and a word line body 13. Therefore, the multiple word line extensions 14 are spaced apart along the first direction D1. Correspondingly, the word line lead structure includes multiple word line leads 61 spaced apart along the first direction D1. The multiple word line leads 61 spaced apart along the first direction D1 are electrically connected to the multiple word line extensions spaced apart along the first direction D1. In one example, the lengths of the multiple word line leads 61 spaced apart along the first direction D1 in the word line lead structure can be different to reduce the facing area between adjacent word line leads and reduce the parasitic capacitance effect inside the semiconductor structure.
[0108] The bit line structure includes multiple bit lines spaced apart along a first direction D1. Each bit line includes a bit line extension 16 and a bit line body 15. Therefore, the multiple bit line extensions 16 are also spaced apart along the first direction D1. Correspondingly, the bit line lead structure includes multiple bit line leads 62 spaced apart along the first direction D1. The multiple bit line leads 62 spaced apart along the first direction D1 are electrically connected to the multiple bit line extensions 16 spaced apart along the first direction D1 in a one-to-one correspondence. In one example, the lengths of the multiple bit line leads 62 spaced apart along the first direction D1 in the bit line lead structure can be different to reduce the facing area between adjacent bit line leads and reduce the parasitic capacitance effect inside the semiconductor structure.
[0109] For example, the semiconductor structure also includes a word line plug and a first peripheral plug, both extending along a first direction D1. One end of the word line plug is electrically connected to the word line extension 14, and the other end is electrically connected to the word line lead 61. One end of the first peripheral plug is electrically connected to the peripheral circuit 60, and the other end is electrically connected to the word line lead 61. The semiconductor structure also includes a bit line plug and a second peripheral plug, both extending along the first direction D1. One end of the bit line plug is electrically connected to the bit line extension 16, and the other end is electrically connected to the bit line lead 62. One end of the second peripheral plug is electrically connected to the peripheral circuit 60, and the other end is electrically connected to the bit line lead 62.
[0110] In some embodiments, the peripheral circuitry 60 is located outside the stacked structure along the second direction D2, and both the word line lead 61 and the bit line lead 62 extend along the second direction D2; or,
[0111] The peripheral circuit 60 is located outside the stacked structure along the third direction D3, and both the word line lead 61 and the bit line lead 62 extend along the third direction D3.
[0112] The following explanation uses an example where the peripheral circuit 60 is located outside the stacked structure along the second direction D2. For example, the stacked structure includes multiple memory cells arranged in a three-dimensional array along the first direction D1, the second direction D2, and the third direction D3. The word line structure includes multiple word lines spaced apart along the first direction D1 and the second direction D2, and the bit line structure includes multiple bit lines spaced apart along the first direction D1 and the third direction D3. Figure 6 As shown in (a), the word line lead structure includes a plurality of word line leads 61 spaced apart along a first direction D1. In one example, each word line lead 61 is electrically connected to the end of a word line extension 14 of a plurality of word lines spaced apart along a second direction D2. In another example, each of the plurality of word line leads 61 is electrically connected to the end of a word line extension 14 of a plurality of word lines. The bit line lead structure includes a plurality of bit line leads 62 spaced apart along the first direction D1 and a third direction D3, and each of the bit line leads 62 is electrically connected to the end of a bit line extension 16 of a plurality of bit lines. The extension direction of bit line lead 62 intersects the extension direction of bit line extension 16; or, the extension direction of word line lead 61 intersects the extension direction of word line extension 14. Thus, the lead-out direction of bit line can be adjusted by bit line lead 62, or the lead-out direction of word line can be adjusted by word line lead 61. On the one hand, this helps to improve the utilization rate of internal space of semiconductor structure, thereby improving the integration of semiconductor structure; on the other hand, it also improves the flexibility of the location setting of peripheral circuit 60 to meet different semiconductor structure design requirements.
[0113] To reduce the capacitive coupling effect between adjacent word line leads and adjacent bit line leads, thereby further improving the electrical performance of the semiconductor structure, in other embodiments, such as... Figure 6 As shown in (b), the peripheral circuit 60 includes a first peripheral circuit 601 and a second peripheral circuit 602 distributed along the second direction D2 on opposite sides of the stacked structure;
[0114] For two adjacent word lines along the second direction D2, the word line lead 61 that is electrically connected to the word line extension 14 in one word line that is closer to the first peripheral circuit 601 is electrically connected to the first peripheral circuit 601, and the word line lead 61 that is electrically connected to the word line extension 14 in the other word line is electrically connected to the second peripheral circuit 602.
[0115] For two adjacent bit lines along the first direction D1, the bit line lead 62 electrically connected to the bit line extension 16 in one bit line is electrically connected to the first peripheral circuit 601, and the bit line lead 62 electrically connected to the bit line extension 16 in the other bit line is electrically connected to the second peripheral circuit 602.
[0116] In order to reduce mutual interference between word line leads and bit line leads, so as to apply control signals to word lines and bit lines respectively, thereby realizing 3D read and write, in some embodiments, the peripheral circuit includes a first peripheral circuit and a second peripheral circuit distributed on different sides of the stacked structure.
[0117] The word line leads are electrically connected to the first peripheral circuit, and the bit line leads are electrically connected to the second peripheral circuit.
[0118] This specific embodiment also provides a method for forming a semiconductor structure, attached... Figure 7 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 8 - Appendix Figure 13 This is a schematic diagram of the main process structure during the formation of the semiconductor structure according to the specific embodiments of this disclosure. A schematic diagram of the semiconductor structure formed according to this specific embodiment can be found in [reference needed]. Figures 2-6 .like Figures 2-13 As shown, the method for forming a semiconductor structure includes the following steps:
[0119] Step S71, provide substrate 40;
[0120] The following cyclic steps are performed multiple times until a stacked structure comprising a plurality of memory cells spaced apart along a first direction D1 is formed on the substrate 40. The first direction D1 is perpendicular to the top surface of the substrate 40. The cyclic steps include:
[0121] Step S72: A plurality of semiconductor layers 17 are formed on the substrate 40 at intervals along the first direction D1. Each semiconductor layer 17 includes an active structure, which includes a channel region 11 and a first source / drain region 10 and a second source / drain region 12 located on opposite sides of the channel region 11 along the second direction D2. The second direction D2 is parallel to the top surface of the substrate 40.
[0122] Step S73: A gate structure, word line and bit line are formed on the substrate 40. The channel region 11 is distributed around the outer periphery of the gate structure. The word line includes a word line body portion 13 extending along the first direction D1 and electrically connected to the gate structure. The bit line includes a bit line body portion 15 extending along the first direction D1. The first source and drain regions 10 are distributed around the outer periphery of the bit line body portion 15. The memory cell includes an active structure and a gate structure.
[0123] Step S74: An interlayer isolation layer 18 is formed above the memory cell, word line and bit line, and the interlayer isolation layer 18 is used as the substrate for the next cycle step.
[0124] In some embodiments, the semiconductor layer 17 includes a plurality of active structures spaced apart along a third direction D3, and a plurality of word line bodies 13 penetrating the channel regions 11 in the plurality of active structures along a first direction D1. The third direction D3 is parallel to the top surface of the substrate 40, and the second direction D2 intersects the third direction D3. The step of forming a gate structure, word lines, and bit lines on the substrate 40 includes:
[0125] A bit line body portion 15 is formed that penetrates the first source / drain region 10 in the plurality of semiconductor layers 17 along the first direction D1.
[0126] A gate structure is formed that penetrates the channel region 11 in the semiconductor layer 17 along the first direction D1, and a word line body portion 13 is electrically connected to multiple gate structures;
[0127] A character line extension 14 is formed above the character line body portion 13. The character line extension 14 extends along a third direction D3 and is electrically connected to a plurality of character line body portions 13 arranged at intervals along the third direction D3. The character line includes the character line body portion 13 and the character line extension 14.
[0128] A bit line extension 16, electrically connected to the bit line body 15, is formed above the bit line body 15. The bit line extension 16 extends along the second direction D2. Along the first direction D1, the bit line extension 16, electrically connected to the same active structure, is located above the word line extension 14. Figures 2-6 ,as well as Figure 13 As shown, where, Figure 13 (a) in the diagram is a top view of the structure. Figure 13 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 13 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 13 (d) in the diagram is a cross-sectional view of position cc in (a).
[0129] Specifically, an epitaxial growth process can be used to alternately grow a semiconductor layer 17 and a spacer layer 42 along a first direction D1 on the top surface of the substrate 40 to form a stacked layer. In one example, the semiconductor layer 17 can be made of Si, and the spacer layer 42 can be made of SiGe. Then, the stacked layer is etched to form a plurality of memory region isolation trenches spaced along a third direction D3. The memory region isolation trenches divide the stacked layer into a plurality of memory regions spaced along a third direction, wherein the third direction D3 is parallel to the top surface of the substrate 40, and the second direction D2 intersects the third direction D3. An insulating dielectric material such as a nitride (e.g., silicon nitride) is filled into the memory region isolation trenches to form a memory region isolation layer 31, such as... Figure 3 , Figure 4 and Figure 8 As shown, where, Figure 8 (a) in the diagram is a top view of the structure. Figure 8 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 8 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 8 (d) in the diagram is a cross-sectional view of position cc in (a).
[0130] The stacked layers are etched to form a first trench extending along a first direction D1 and at least penetrating the first source / drain regions 10 of a plurality of semiconductor layers 17 spaced apart along the first direction D1. A conductive material such as TiN, W, Ti, Ru, or Mo is filled into the first trench to form a bit line body 15, such as... Figures 2-4 ,as well as Figure 9 As shown, where, Figure 9 (a) in the diagram is a top view of the structure. Figure 9 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 9 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 9 (d) in the diagram is a cross-sectional view of position cc in (a). Multiple bit line bodies 15 are spaced apart along the third direction D3, and each bit line body 15 is electrically connected to a first source / drain region 10 within a plurality of memory regions. Next, the stacked layers are etched again to form a second trench extending along the first direction D1 and at least penetrating the channel regions 11 of the plurality of semiconductor layers 17 spaced apart along the first direction D1. After forming a gate dielectric layer on the inner wall of the second trench, conductive materials such as TiN, W, Ti, Ru, or Mo are filled into the second trench to form word line bodies 13 and a gate structure covering the surface of the gate dielectric layer, as shown below. Figures 2-4 ,as well as Figure 10 As shown, where, Figure 10 (a) in the diagram is a top view of the structure. Figure 10 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 10 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 10 (d) in the diagram is a cross-sectional view of position cc in (a).
[0131] After forming the word line body 13, a drain isolation layer 32 is formed. The drain isolation layer 32 is located between adjacent semiconductor layers 17 along the first direction D1 and covers the channel region 11 and the second source / drain region 12 in the active structure, such as... Figure 11 As shown, where, Figure 11 (a) in the diagram is a top view of the structure. Figure 11 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 11 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 11(d) in the diagram is a cross-sectional view of the cc position in (a). In one example, the material of the drain isolation layer 32 can be, but is not limited to, a nitride material (e.g., silicon nitride). The drain isolation layer 32 serves two purposes: firstly, to isolate word lines and subsequently pre-formed capacitors, and secondly, to support the stacked layers and prevent them from tipping over or collapsing during subsequent processes.
[0132] Subsequently, a first dielectric layer 44 is deposited on the top surface of the stacked layers, and the first dielectric layer 44 is etched to form a word line extension trench exposing the top surface of the word line body portion 13. A conductive material is filled into the word line extension trench to form word line extension portions 14 extending along a third direction D3 and electrically connected to a plurality of word line body portions 13 spaced apart along the third direction D3, such as... Figures 2-4 ,as well as Figure 12 As shown, where, Figure 12 (a) in the diagram is a top view of the structure. Figure 12 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 12 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 12 (d) in the diagram is a cross-sectional view of the position dd in (a).
[0133] Next, a bitline contact portion 30 extending along the first direction D1 is formed on the top surface of the bitline body portion 15. The bitline contact portion 30 is electrically connected to the bitline body portion 15. Along the first direction D1, the top surface of the bitline contact portion 30 is located above the top surface of the word line extension portion 14. Furthermore, the width of the bitline contact portion 30 along the second direction D2 is at least greater than the width of the bitline body portion 15 along the second direction D2, thereby increasing the contact area between the bitline contact portion 30 and the bitline body portion 15 and reducing the contact resistance inside the bitline. Then, a bitline extension portion 16 is formed on the top surface of the bitline contact portion 30. The bitline extension portion 16 is electrically connected to the bitline contact portion 30, such as... Figure 13 As shown.
[0134] In some embodiments, before forming the interlayer isolation layer 18 located above the memory cells, word lines, and bit lines, the following steps are further included:
[0135] A lower electrode layer 50 is formed to continuously cover the second source / drain regions 12 in the multiple active structures that are spaced apart along the first direction D1, respectively.
[0136] A dielectric layer 51 is formed covering the entire surface of the lower electrode layer 50;
[0137] An upper electrode layer 52 is formed covering the entire surface of the dielectric layer 51 to form a capacitor including a lower electrode layer 50, a dielectric layer 51, and an upper electrode layer 52.
[0138] For example, the substrate 40 includes a plurality of stacked layers (semiconductor layers including a plurality of semiconductor layers 17 spaced apart along a first direction D1) spaced apart along a second direction D2. After forming a gate structure, word line, and bit line in each stacked layer, second source / drain regions 12 of two adjacent stacked layers along the first direction D1 are distributed opposite to each other. Next, a lower electrode material is deposited such that the lower electrode material continuously covers at least a portion of the surface of the plurality of second source / drain regions 12 spaced apart along the second direction D2 in two adjacent stacked layers along the first direction D1. Subsequently, a dielectric material is formed covering the entire surface of the lower electrode material, and an upper electrode material is formed covering the entire surface of the dielectric material and filling the gap between two adjacent stacked layers. Next, the lower electrode material, dielectric material, and upper electrode material are etched along the second direction D2 to form a partition trench that penetrates the lower electrode material, dielectric material, and upper electrode material along the second direction D2, forming two capacitors separated by the partition trench. Each capacitor includes a lower electrode layer 50 covering at least a portion of the surface of a plurality of active regions 12 arranged at intervals along the second direction D2 in a stacked layer, a dielectric layer 51 covering the entire surface of the lower electrode layer 50, and an upper electrode layer 52 covering the entire surface of the dielectric layer 51.
[0139] In some embodiments, the method for forming a semiconductor structure further includes the following steps:
[0140] A peripheral circuit 60 located outside the stacked structure is formed on the substrate 40;
[0141] A word line lead structure and a bit line lead structure are formed. The word line lead structure includes multiple word line leads 61 electrically connected to the ends of word line extensions 14 of multiple word lines spaced apart along the first direction D1. The bit line lead structure includes multiple bit line leads 62 electrically connected to the ends of bit line extensions 16 of multiple bit lines spaced apart along the first direction D1. Both the word line leads 61 and the bit line leads 62 are electrically connected to the peripheral circuit 60, such as... Figure 6 As shown;
[0142] The extension direction of bit line lead 62 intersects the extension direction of bit line extension 16; or, the extension direction of word line lead 61 intersects the extension direction of word line extension 14.
[0143] The semiconductor structure and its formation method provided in some embodiments of this specific embodiment improve the electrical performance of the semiconductor structure by distributing the channel region in the memory cell around the outer periphery of the gate structure to form a channel-all-around structure, and distributing the first source / drain region around the outer periphery of the bit line body to form a first source / drain region-all-around structure. Furthermore, the word line body electrically connected to the gate structure within the memory cell and the bit line body electrically connected to the first source / drain region within the memory cell extend in the same direction (e.g., both extending in a direction perpendicular to the top surface of the substrate), which simplifies the semiconductor structure manufacturing process and reduces the manufacturing cost. In addition, the stacked structure in some embodiments of this specific embodiment includes multiple memory cells. Word lines electrically connected to the multiple memory cells can be led out through word line leads, and the lead-out direction of the word lines can be adjusted through the word line leads. Bit lines electrically connected to the multiple memory cells can be led out through bit lines, and the lead-out direction of the bit lines can be adjusted through the bit line leads. This not only improves the flexibility of arranging multiple memory cells within the stacked structure but also helps to further improve the integration density of the semiconductor structure. In other embodiments of this specific implementation, the memory cell includes multiple transistors connected in parallel, which can increase the current inside the memory cell, thereby further improving the electrical performance of the semiconductor structure.
[0144] The above are merely preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A stacked structure located on the substrate includes a plurality of memory cells spaced apart along a first direction. Each memory cell includes a transistor, and each transistor includes an active structure and a gate structure. The active structure includes a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a second direction. The channel region surrounds the outer periphery of the gate structure. The first direction is perpendicular to the top surface of the substrate, and the second direction is parallel to the top surface of the substrate. A word line structure is located on the substrate and includes a plurality of word lines spaced apart along the first direction. Each word line includes a word line body portion extending along the first direction and the word line body portion is electrically connected to the gate structure. Bit line structure, located on the substrate, includes multiple bit lines spaced apart along the first direction. Each bit line includes a bit line body portion extending along the first direction, and the first source / drain region surrounds the outer periphery of the bit line body portion.
2. The semiconductor structure according to claim 1, characterized in that, The stacked structure further includes two memory cells arranged along the second direction, and the two memory cells arranged along the second direction share a first source-drain region, and the two channel regions are located on opposite sides of the shared first source-drain region; The first source-drain region shared by the two memory cells arranged along the second direction surrounds the outer periphery of one of the bit line main bodies; The word line structure further includes word lines arranged at intervals along the second direction, and the gate structures in two adjacent memory cells along the second direction are respectively connected to two adjacent word lines along the second direction.
3. The semiconductor structure according to claim 2, characterized in that, The storage unit includes a plurality of transistors spaced apart along the first direction; The word line body is electrically connected to the gate structure of one of the plurality of transistors arranged at intervals along the first direction within the memory cell. The bit line body portion is electrically connected to the first source / drain region of one of the plurality of transistors spaced apart along the first direction in the memory cell, and the first source / drain region of one of the plurality of transistors spaced apart along the first direction in the memory cell surrounds the outer periphery of the bit line body portion.
4. The semiconductor structure according to claim 3, characterized in that, The storage unit also includes a capacitor, the capacitor comprising: The lower electrode layer continuously covers at least a portion of the surface of the second source / drain region of a plurality of transistors spaced apart along the first direction; A dielectric layer that covers the entire surface of the lower electrode layer; The upper electrode layer covers the entire surface of the dielectric layer.
5. The semiconductor structure according to claim 3, characterized in that, The stacked structure includes a plurality of memory cells spaced apart along a third direction, the third direction being parallel to the top surface of the substrate, and the second direction intersecting the third direction; Each word line includes a plurality of word line main bodies spaced apart along the third direction, and a word line extension portion extending along the third direction and electrically connected to the plurality of word line main bodies spaced apart along the third direction. The plurality of word line main bodies included in the word line are electrically connected one-to-one with the gate structures in the plurality of memory cells spaced apart along the third direction.
6. The semiconductor structure according to claim 5, characterized in that, The bit line also includes: The bit line extension is located above the bit line body and is electrically connected to the bit line body, and the bit line extension extends along the second direction; Along the first direction, the bit line extensions electrically connected to the same memory cell are located above the corresponding word line extensions.
7. The semiconductor structure according to claim 6, characterized in that, The stacked structure further includes a plurality of the storage cells arranged at intervals along the second direction; Each bit line includes a plurality of bit line body portions spaced apart along the second direction, and the bit line extension portion is electrically connected to the plurality of bit line body portions spaced apart along the second direction.
8. The semiconductor structure according to claim 7, characterized in that, Also includes: The word line lead structure includes multiple word line leads that are electrically connected one-to-one with the ends of the word line extensions of a plurality of word lines spaced apart along the first direction; Bit line lead structure includes multiple bit line leads that are electrically connected one-to-one with the ends of the bit line extensions of multiple bit lines spaced apart along the first direction; The peripheral circuit is located outside the stacked structure, and the bit line leads and word line leads are electrically connected to the peripheral circuit. The extension direction of the bit line lead intersects with the extension direction of the bit line extension; or, the extension direction of the word line lead intersects with the extension direction of the word line extension.
9. The semiconductor structure according to claim 8, characterized in that, The peripheral circuitry is located outside the stacked structure along the second direction, and both the word line leads and the bit line leads extend along the second direction; or, The peripheral circuit is located outside the stacked structure along the third direction, and both the word line lead and the bit line lead extend along the third direction.
10. The semiconductor structure according to claim 8, characterized in that, The peripheral circuit includes a first peripheral circuit and a second peripheral circuit distributed along the second direction on opposite sides of the stacked structure; For two adjacent word lines along the second direction, the word line lead electrically connected to the word line extension of one word line closer to the first peripheral circuit is electrically connected to the first peripheral circuit, and the word line lead electrically connected to the word line extension of the other word line is electrically connected to the second peripheral circuit. For two adjacent bit lines along the first direction, the bit line lead electrically connected to the bit line extension of one of the bit lines is electrically connected to the first peripheral circuit, and the bit line lead electrically connected to the bit line extension of the other bit line is electrically connected to the second peripheral circuit.
11. The semiconductor structure according to claim 8, characterized in that, The peripheral circuit includes a first peripheral circuit and a second peripheral circuit distributed on different sides of the stacked structure; The word line leads are electrically connected to the first peripheral circuit, and the bit line leads are electrically connected to the second peripheral circuit.
12. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; The following cyclic steps are performed multiple times until a stacked structure comprising a plurality of memory cells spaced apart along a first direction perpendicular to the top surface of the substrate is formed on the substrate, the cyclic steps comprising: A plurality of semiconductor layers are formed on the substrate at intervals along the first direction. Each semiconductor layer includes an active structure, which includes a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a second direction, the second direction being parallel to the top surface of the substrate. A gate structure, word lines, and bit lines are formed on the substrate. The channel region surrounds the outer periphery of the gate structure. The word line includes a word line body portion extending along the first direction and electrically connected to the gate structure. The bit line includes a bit line body portion extending along the first direction. The first source / drain region surrounds the outer periphery of the bit line body portion. The memory cell includes the active structure and the gate structure. An interlayer isolation layer is formed above the memory cell, the word line, and the bit line, and the interlayer isolation layer is used as the substrate for the next cycle step.
13. The method for forming a semiconductor structure according to claim 12, characterized in that, The semiconductor layer includes a plurality of active structures spaced apart along a third direction, and a plurality of word line bodies penetrate the channel regions of the plurality of active structures one by one along the first direction. The third direction is parallel to the top surface of the substrate, and the second direction intersects the third direction. The steps of forming a gate structure, word line, and bit line on the substrate include: A bit line body portion is formed that extends through the first source / drain region of the plurality of semiconductor layers along the first direction; A gate structure is formed that penetrates the channel region in the semiconductor layer along the first direction, and a word line body portion is electrically connected to a plurality of the gate structures; A character line extension is formed above the character line body portion. The character line extension extends along the third direction and is electrically connected to a plurality of character line bodies arranged at intervals along the third direction. The character line includes the character line body portion and the character line extension portion. A bit line extension portion electrically connected to the bit line main body portion is formed above the bit line main body portion. The bit line extension portion extends along the second direction. Along the first direction, the bit line extension portion electrically connected to the same active structure is located above the word line extension portion.
14. The method for forming a semiconductor structure according to claim 13, characterized in that, Before forming the interlayer isolation layer located above the memory cell, the word line, and the bit line, the following steps are also included: A lower electrode layer is formed that continuously covers the second source / drain regions of the plurality of active structures spaced apart along the first direction, respectively. A dielectric layer is formed covering the entire surface of the lower electrode layer; An upper electrode layer is formed covering the entire surface of the dielectric layer to form a capacitor comprising the lower electrode layer, the dielectric layer, and the upper electrode layer.
15. The method for forming a semiconductor structure according to claim 13, characterized in that, It also includes the following steps: A peripheral circuit located outside the stacked structure is formed on the substrate; A word line lead structure and a bit line lead structure are formed. The word line lead structure includes multiple word line leads that are electrically connected to the ends of the word line extensions of multiple word lines spaced apart along the first direction. The bit line lead structure includes multiple bit line leads that are electrically connected to the ends of the bit line extensions of multiple bit lines spaced apart along the first direction. Both the word line leads and the bit line leads are electrically connected to the peripheral circuit. The extension direction of the bit line leads intersects the extension direction of the bit line extensions; or, the extension direction of the word line leads intersects the extension direction of the word line extensions.