Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device having different gate structure configurations and a method of manufacturing the same. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interface oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first IO layer, and a first dipole layer disposed at an interface between the first IO layer and the first HK dielectric layer. The first HK dielectric layer includes a rare earth metal dopant or an alkali metal dopant. The second gate structure includes a second IO layer, a second HK dielectric layer disposed on the second IO layer, and a second dipole layer disposed at an interface between the second IO layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and a rare earth metal dopant or an alkali metal dopant.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry is constantly scaling down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and finFETs. This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] According to an embodiment of this application, a semiconductor device is provided, comprising: a first gate structure, the first gate structure comprising: a first interface oxide layer; a first high-k (HK) dielectric layer disposed on the first interface oxide (IO) layer, wherein the high-k dielectric layer comprises a rare-earth metal dopant or an alkali metal dopant; and a first dipole layer disposed at the interface between the first interface oxide layer and the first high-k dielectric layer; the semiconductor device further comprising a second gate structure, the second gate structure comprising: a second interface oxide layer; a second high-k dielectric layer disposed on the second interface oxide layer, wherein the second high-k dielectric layer comprises: a transition metal dopant, and a rare-earth metal dopant or an alkali metal dopant; the second gate structure further comprising a second dipole layer disposed at the interface between the second interface oxide layer and the second high-k dielectric layer.

[0004] According to another embodiment of this application, a semiconductor device is provided, comprising: a substrate; a fin structure disposed on the substrate; a first nanostructured channel region and a second nanostructured channel region disposed on the fin structure; a first gate structure disposed on the first nanostructured channel region, the first gate structure comprising: a first dielectric layer disposed on the first nanostructured channel region, wherein the first dielectric layer comprises a transition metal dopant; and a p-type dipole layer disposed between the first dielectric layer and the first nanostructured channel region; and the semiconductor device comprising a second gate structure disposed on the second nanostructured channel region, the second gate structure comprising: a second dielectric layer disposed on the second nanostructured channel region, wherein the second dielectric layer comprises a transition metal dopant and an alkali metal dopant; and a dipole layer having an n-type dipole and a p-type dipole, the dipole layer being disposed between the second dielectric layer and the second nanostructured channel region.

[0005] According to another embodiment of this application, a method for manufacturing a semiconductor device is provided, comprising: forming a first fin structure and a second fin structure on a substrate; forming a first nanostructured channel region and a second nanostructured channel region on the first fin structure and the second fin structure, respectively; depositing a gate dielectric layer having a first portion and a second portion, the first portion and the second portion of the gate dielectric layer respectively surrounding the first nanostructured channel region and the second nanostructured channel region; depositing a transition metal substrate on the gate dielectric layer; removing a portion of the transition metal substrate on the first portion of the gate dielectric layer; performing a first annealing process on the transition metal substrate; removing the transition metal substrate; depositing an alkali metal substrate on the gate dielectric layer; performing a second annealing process on the alkali metal substrate; removing the alkali metal substrate; depositing a work function metal layer on the gate dielectric layer; and depositing a gate metal fill layer on the work function metal layer.

[0006] Embodiments of this application relate to gate structures in semiconductor devices. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0008] Figure 1A An isometric view of a semiconductor device according to some embodiments is shown.

[0009] Figures 1B-1M Cross-sectional views of semiconductor devices with different gate structures according to some embodiments are shown.

[0010] Figure 1N Device characteristics of semiconductor devices with different gate structures according to some embodiments are shown.

[0011] Figure 2 This is a flowchart of a method for manufacturing semiconductor devices with different gate structures according to some embodiments.

[0012] Figures 3A-15B Cross-sectional views of semiconductor devices with different gate structures at various stages of their manufacturing process are shown according to some embodiments.

[0013] Figure 16 This is a flowchart of another method for manufacturing semiconductor devices with different gate structures, according to some embodiments.

[0014] Figures 17A-25B Cross-sectional views of semiconductor devices with different gate structures at various stages of their manufacturing process are shown according to some embodiments.

[0015] Figure 26This is a flowchart of another method for manufacturing semiconductor devices with different gate structures, according to some embodiments.

[0016] Figures 27A-30B Cross-sectional views of semiconductor devices with different gate structures at various stages of their manufacturing process are shown according to some embodiments.

[0017] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, the process of forming a first component over a second component may include embodiments where the first and second components are in direct contact, or embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means that the first component is formed to be in direct contact with the second component. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition, in itself, does not prescribe a relationship between the various embodiments and / or configurations discussed.

[0019] For ease of description, spatial relation terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein may be interpreted accordingly.

[0020] It should be noted that references to "an embodiment," "embodiment," "example embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific components, structures, or features, but each embodiment may not necessarily include specific components, structures, or features. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific component, structure, or feature is described in connection with an embodiment, whether explicitly described or not, implementing such a component, structure, or feature in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0021] It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology used herein shall be interpreted by those skilled in the art in light of the teachings herein.

[0022] In some embodiments, the terms "about" and "substantially" may refer to a given number of values ​​that vary within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one of skill in the art based on the teachings herein.

[0023] The fin structures disclosed herein can be patterned using any suitable method. For example, the fin structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures.

[0024] The gate voltage—threshold voltage (Vt)—required for a field-effect transistor (FET) can depend on the effective work function (EWF) of the semiconductor material in the FET channel region and / or the FET's gate structure. For example, for an n-type FET (NFET), reducing the difference between the EWF of the NFET gate structure and the conduction band energy of the NFET channel material (e.g., 4.1 eV for Si or 3.8 eV for SiGe) can lower the NFET threshold voltage. For a p-type FET (PFET), reducing the difference between the EWF of the PFET gate structure and the valence band energy of the PFET channel material (e.g., 5.2 eV for Si or 4.8 eV for SiGe) can lower the PFET threshold voltage. The EWF of the FET gate structure can depend on the thickness and / or material composition of the layers of the FET gate structure. In this way, FETs with different threshold voltages can be fabricated by adjusting the thickness and / or material composition of the FET gate structure.

[0025] The increasing demand for versatile, low-power portable devices has led to a corresponding increase in the need for FETs with low threshold voltages, such as threshold voltages between 100mV and 200mV (referred to as "low threshold voltages") and threshold voltages below 100mV (referred to as "ultra-low threshold voltages"). One approach to achieving multi-Vt devices with low and / or ultra-low threshold voltages in FETs is to have different work function metal (WFM) layers with a thickness greater than about 4nm (e.g., about 5nm to about 10nm) in the gate structure. However, the thickness of different WFM layers can be limited by the geometry of the FET gate structure. For example, in a gate-all-around (GAA) FET, the thickness of the WFM layer can be limited by the spacing between the nanostructured channel regions of the GAA FET. Furthermore, depositing different WFM layers can become increasingly challenging as FETs (e.g., GAA FETs, finFETs, and / or MOSFETs) continue to scale down.

[0026] This disclosure provides example structures of FETs (e.g., finFETs or GAA FETs) having different gate structures configured to provide different and / or low threshold voltages, and example methods for forming such multi-Vt FETs on the same substrate. The example methods form NFETs and PFETs with ultra-low, low, and / or different threshold voltages on the same substrate, but with WFM layers of similar thickness. Compared to other methods of forming FETs with similar dimensions and threshold voltages on the same substrate, these example methods are more cost-effective (e.g., reducing costs by about 20% to about 30%) and time-efficient (e.g., reducing time by about 15% to about 20%) in fabricating reliable FET gate structures with different low and / or ultra-low threshold voltages. Furthermore, compared to other methods of forming FETs with similar threshold voltages, these example methods can form FET gate structures with much smaller dimensions (e.g., thinner gate stacks).

[0027] In some embodiments, NFETs and PFETs with different gate structure configurations but similar WFM layer thicknesses can be selectively formed on the same substrate to achieve low, ultra-low, and / or different threshold voltages. Different gate structures may have high-k (HK) gate dielectric layers doped with different types and / or concentrations of metal dopants. Different types and / or concentrations of metal dopants can induce dipoles of different polarities and / or concentrations at the interface between the HK gate dielectric layer and the interface oxide (IO) layer. Different polarities and / or concentrations of dipoles result in gate structures with different EWF values. Since the EWF value of a gate structure corresponds to the threshold voltage of a FET, gate structures with different EWF values ​​result in FETs with different threshold voltages on the same substrate. Therefore, controlling the type and / or concentration of metal dopants in the HK gate dielectric layer can adjust the EWF values ​​of the NFET and PFET gate structures, and thus the threshold voltages of the NFET and PFET can be adjusted without changing the thickness of the WFM layer.

[0028] Figure 1A An isometric view of a semiconductor device 100 having an NFET 102N and a PFET 102P according to some embodiments is shown. Figure 1B The NFET 102N is shown along Figure 1A A cross-sectional view of line AA. Figure 1C The PFET 102P is shown along Figure 1A A cross-sectional view of line BB. Figure 1B and 1C A cross-sectional view of a semiconductor device 100 with additional structures is shown; for simplicity, the additional structures are not shown. Figure 1A It is displayed in the middle. Figure 1D , Figure 1F , Figure 1H , Figure 1J and Figure 1L yes Figure 1B Enlarged views of gate regions 112A1-112A3 are shown, along with different cross-sectional views of gate regions 112A1-112A3. Figure 1E , Figure 1G , Figure 1I , Figure 1K and Figure 1M yes Figure 1C Enlarged views of gate regions 112B1-112B3 are shown, along with different cross-sectional views of gate regions 112B1-112B3. Figure 1D-Figure 1M For simplicity, it is not shown Figures 1B-1C The additional structures shown are as follows. Unless otherwise stated, the discussion of elements with the same annotations applies to each other.

[0029] refer to Figures 1A-1CThe NFET 102N may include an array of gate structures 112N1-112N3 disposed on the fin structure 106N, and the PFET 102P may include an array of gate structures 112P1-112P3 disposed on the fin structure 106P. The NFET 102N may also include a stack of nanostructured channel regions 121 surrounded by the gate structures 112N1-112N3, and an S / D region 110N disposed on the portion of the fin structure 106N not covered by the gate structures 112N1-112N3. Figure 1A An array of S / D regions 110N (visible in the image) and an S / D contact structure 120N disposed on the S / D region 110N. Similarly, the PFET 102P may also include a stack of nanostructured channel regions 121 surrounded by gate structures 112P1-112P3, and an epitaxial S / D region 110P disposed on a portion of the fin structure 106P not covered by the gate structures 112P1-112P3. Figure 1A An array of S / D regions 110P (visible in the image) and S / D contact structures 120P disposed on the S / D regions 110P. As used herein, the term "nanostructured" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the nanostructured channel region 121 may take the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructured shapes.

[0030] The semiconductor device 100 may further include a gate spacer 114, a shallow trench isolation (STI) region 116, an etch stop layer (ESL) 117, and an interlayer dielectric (ILD) layer 118. The ILD layer 118 may be disposed on the ESL 117. The ESL 117 may be configured to protect gate structures 112N and 112P and / or S / D regions 110N and 110P. In some embodiments, the gate spacer 114, the STI region 116, the ESL 117, and the ILD layer 118 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide.

[0031] Semiconductor device 100 may be formed on substrate 104, having NFET 102N and PFET 102P formed on different regions of substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed on substrate 104 between NFET 102N and PFET 102P. Substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Furthermore, substrate 104 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). In some embodiments, fin structures 106N-106P may comprise a material similar to substrate 104 and extend along the X-axis.

[0032] In some embodiments, the S / D region 110N may include an epitaxially grown semiconductor material, such as Si, and an n-type dopant, such as phosphorus and other suitable n-type dopants. In some embodiments, the S / D region 110P may include an epitaxially grown semiconductor material, such as Si and SiGe, and a p-type dopant, such as boron and other suitable p-type dopants. In some embodiments, the S / D contact structure 120N-120P may include a silicide layer 134, a contact plug 136 disposed on the silicide layer 134, and a nitride barrier layer 138 along the sidewalls of the contact plug. In some embodiments, the silicide layer 134 may include titanium silicide (Ti). x Si y ), tantalum silicide (Ta x Si), molybdenum silicide (Mo) x Si y Nickel silicide (Ni) x Si y ), cobalt silicide (Co) x Si y ), Tungsten silicide (W) x Si y (or combinations thereof). In some embodiments, the contact plug 136 may include a conductive material such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and combinations thereof.

[0033] In some embodiments, the nanostructured channel region 121 may comprise a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructured channel region 121 may comprise Si, SiAs, silicon phosphide (SiP), SiC, SiCP, SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. Although a rectangular cross-section of the nanostructured channel region 121 is shown, the nanostructured channel region 121 may have other geometric shapes (e.g., circular, elliptical, triangular, or polygonal cross-sections).

[0034] In some embodiments, gate structures 112N1-112N3 and 112P1-112P3 may be multilayer structures and may surround each of the nanostructured channel regions 121. For the nanostructured channel regions 121, gate structures 112N1-112N3 and 112P1-112P3 may be referred to as a "gate all-around (GAA) structure" or a "horizontal gate all-around (HGAA) structure". NFET 102N may be referred to as "GAA FET 102N" or "GAA NFET 102N", and PFET 102N may be referred to as "GAA FET 102P" or "GAA PFET 102P". A portion of the gate structures 112N1-112N3 and 112P1-112P3 surrounding the nanostructured channel regions 121 may be electrically isolated from the adjacent S / D regions 110N and 110P by internal spacers 113. The internal spacer 113 may include a material similar to the gate spacer 114. In some embodiments, the NFET-PFET 102N-102P may be a finFET and have a fin region (not shown) instead of the nanostructured channel region 121.

[0035] In some embodiments, the gate structures 112N1-112N3 and 112P1-112P3 may include interface oxide (IO) layers 122N1-122N3 and 122P1-122P3, high-k (HK) gate dielectric layers 124N1-124N3 and 124P1-124P3 disposed on the IO layers 122N1-122N3 and 122P1-122P3, a work function metal (WFM) layer 126 disposed on the HK gate dielectric layers 124N1-124N3 and 124P1-124P3, a gate metal fill layer 128 disposed on the WFM layer 126, a conductive capping layer 130 disposed on the HK gate dielectric layers 124N1-124N3 and 124P1-124P3, the WFM layer 126 and the gate metal fill layer 128, and an insulating capping layer 132 disposed on the conductive capping layer 130.

[0036] In some embodiments, the IO layers 122N1-122N3 and 122P1-122P3 may include silicon oxide (SiO2) and silicon germanium oxide (SiGeO2). x or germanium oxide (GeO) x The gate dielectric layers 124N1-124N3 and 124P1-124P3 may have a thickness of about 0.5 nm to about 2 nm. In some embodiments, the HK gate dielectric layers 124N1-124N3 and 124P1-124P3 may include high-k dielectric materials, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2) may have a thickness of about 0.5 nm to about 4 nm. Within these thickness ranges of the IO layers 122N1-122N3 and 122P1-122P3 and the HK gate dielectric layers 124N1-124N3 and 124P1-124P3, sufficient electrical isolation can be provided between the gate structures 112N1-112N3 and 112P1-112P3 and the nanostructured channel region 121 without affecting device size and manufacturing cost. In some embodiments, one or more of the HK gate dielectric layers 124N1-124N3 and 124P1-124P3 may include metal dopants that cause interfaces (i) between IO layer 122N1 and HK gate dielectric layer 124N1 (“interface N1”), (ii) between IO layer 122N2 and HK gate dielectric layer 124N2 (“interface N2”), and (iii) between IO layer 122N3 and HK gate dielectric layer 124N3 (“interface N3”). (v) At the interface between IO layer 122P1 and HK gate dielectric layer 124P1 (“interface P1”), (v) at the interface between IO layer 122P2 and HK gate dielectric layer 124P2 (“interface P2”), and / or (vi) at the interface between IO layer 122P3 and HK gate dielectric layer 124P3 (“interface P3”), dipole layers having n-type dipoles (N-dipoles) and / or p-type dipoles (P-dipoles) are formed, as referenced below. Figure 1D-Figure 1N As described.

[0037] One or more of the HK gate dielectric layers 124N1-124N3 and 124P1-124P3 may have metal dopants of different types and / or concentrations. Different types and / or concentrations of metal dopants can induce dipoles of different polarities (e.g., N-dipoles and P-dipoles) and / or different concentrations of dipoles at interfaces N1-N3 and / or P1-P3, which can result in gate structures 112N1-112N3 and 112P1-112P3 having different EWF values. Since the EWF value corresponds to the threshold voltage, gate structures 112N1-112N3 and 112P1-112P3 with different EWF values ​​result in gate structures 112N1-112N3 and 112P1-112P3 with different threshold voltages on the same substrate. In some embodiments, the type and / or concentration of the metal dopant in the HK gate dielectric layers 124N1-124N3 are configured to form a gate structure 112N1 having a threshold voltage lower than that of the gate structures 112N2-112N3, and a gate structure 112N2 having a threshold voltage lower than that of the gate structures 112N3, as referenced below. Figure 1D , Figure 1F , Figure 1H , Figure 1J and Figure 1L As described. Similarly, in some embodiments, the type and / or concentration of the metal dopant in the HK gate dielectric layers 124P1-124P3 are configured to form a gate structure 112P3 having a threshold voltage lower than that of the gate structures 112P1-112P2, and a gate structure 112P2 having a threshold voltage lower than that of the gate structure 112P1, as referenced below. Figure 1E , Figure 1G , Figure 1I , Figure 1K and Figure 1M As described.

[0038] In some embodiments, the WFM layer 126 of the gate structures 112N1-112N3 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-based materials, or combinations thereof. In some embodiments, the WFM layer 126 of the gate structures 112P1-112P3 may include substantially aluminum-free (e.g., Al-free) Ti-based or Ta-based nitrides or alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, tantalum copper (Ta-Cu), and combinations thereof. The gate metal filling layer 128 may include suitable conductive materials such as tungsten (W), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0039] The insulating capping layer 132 protects the underlying conductive capping layer 130 from structural and / or compositional degradation during subsequent processing of the semiconductor device. In some embodiments, the insulating capping layer 132 may comprise a nitride material, such as silicon nitride, and may have a thickness of about 5 nm to about 10 nm to adequately protect the underlying conductive capping layer 130. The conductive capping layer 130 provides a conductive interface between the gate metal fill layer 128 and a gate contact structure (not shown) to electrically connect the gate metal fill layer 128 to the gate contact structure without forming the gate contact structure directly on or within the gate metal fill layer 128. In some embodiments, the conductive capping layer 130 may comprise a metallic material, such as W, Ru, Ir, Mo, other suitable metallic materials, and combinations thereof.

[0040] Figures 1D-1E , Figures 1F-1G , Figure 1H-Figure 1I , Figure 1J-Figure 1K and Figure 1L-Figure 1MThe diagram illustrates metal dopant configurations in the HK gate dielectric layers 124N1-124N3 and 124P1-124P3 according to some embodiments, which cause dipole configurations at interfaces N1-N3 and P1-P3 to form (i) a gate structure 112N1 having a threshold voltage lower than that of gate structures 112N2-112N3, (ii) a gate structure 112N2 having a threshold voltage lower than that of gate structure 112N3, (iii) a gate structure 112P3 having a threshold voltage lower than that of gate structures 112P1-112P2, and (iv) a gate structure 112P2 having a threshold voltage lower than that of gate structure 112P1.

[0041] refer to Figure 1D In some embodiments, the HK gate dielectric layer 124N3 may be undoped, and the HK gate dielectric layers 124N1-124N2 may include metal dopants 140 of the same type but different concentrations, which can cause dipole layers 142N1-142N2 at interfaces N1-N2 to have N-dipoles 144 of the same type but different concentrations. The metal dopants 140 may include rare earth metals (REM), such as lanthanum (La), yttrium (Y), cerium (Ce), ytterbium (Yb), and erbium (Er), or alkali metals (ALM), such as magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba). In some embodiments, the N-dipoles 144 may include metal ions from the metal dopants 140 and oxygen ions from the IO layers 122N1-122N2. REM dopant 140 can induce REM-based N-dipole 144 and ALM dopant 140 can induce ALM-based N-dipole 144. In some embodiments, N-dipole 144 may include either REM-based N-dipole 144 or ALM-based N-dipole 144. In some embodiments, when metal dopant 140 includes La, REM-based N-dipole 144 may include a La-O dipole. In some embodiments, when metal dopant 140 includes Mg, ALM-based N-dipole 144 may include a Mg-O dipole.

[0042] Since the metal dopant concentration is directly proportional to the N-dipole concentration, and the N-dipole concentration is inversely proportional to the threshold voltage of the NFET gate structure, (i) the HK gate dielectric layer 124N1 has a higher metal dopant concentration than the metal dopant concentration in the HK gate dielectric layers 124N2-124N3, to form a gate structure 112N1 with a lower threshold voltage than the gate structures 112N2-112N3, and (ii) the HK gate dielectric layer 124N2 has a higher metal dopant concentration than the metal dopant concentration in the HK gate dielectric layer 124N3, to form a gate structure 112N2 with a lower threshold voltage than the gate structure 112N3. Therefore, in some embodiments, the threshold voltage across different NFET gate structures (e.g., gate structures 112N1-112N3) can vary with different concentrations of the same polarity dipole (e.g., N-dipole 144).

[0043] In some embodiments, the peak concentration of the metal dopant 140 in the HK gate dielectric layer 124N1 can be at interface N1 or within a distance D1 from interface N1, and the peak concentration of the metal dopant 140 in the HK gate dielectric layer 124N2 can be at interface N2 or within a distance D1 from interface N2, such as Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the distance D1 can be from about 0.1 nm to about 1 nm. If the distance D1 is greater than 1 nm, the concentration of N-dipole 144 may not be proportional to the concentration of metal dopant 140, and therefore, the concentration of N-dipole 144 may not be sufficiently controlled to adjust the threshold voltage. In some embodiments, the peak concentration of metal dopant 140 in HK gate dielectric layer 124N1 can be from about 70 atomic% to about 80 atomic% to form a gate structure 112N1 with an ultra-low threshold voltage. In some embodiments, the peak concentration of metal dopant 140 in HK gate dielectric layer 124N2 can be from about 40 atomic% to about 60 atomic% to form a gate structure 112N2 with a low threshold voltage.

[0044] refer to Figure 1EIn some embodiments, the HK gate dielectric layers 124P1-124P3 may include metal dopants 148 of the same type and substantially equal concentration, which can induce dipole layers 142P1-142P3 with P-dipoles 150 of the same type and substantially equal concentration at interfaces P1-P3. The metal dopants 148 may include Group 13 metals (GTM) of the periodic table, such as gallium (Ga), aluminum (Al), and indium (In), or transition metals (TRM), such as zinc (Zn), niobium (Nb), molybdenum (Mo), tungsten (W), and tantalum (Ta). In some embodiments, the P-dipoles 150 may include metal ions from the metal dopants 148 and oxygen ions from the IO layers 122P1-122P3. The GTM dopants 148 can induce GTM-based P-dipoles 150, and the TRM dopants 148 can induce TRM-based P-dipoles 150. In some embodiments, the P-dipole 150 may include a GTM-based P-dipole 150 or a TRM-based P-dipole 150. In some embodiments, when the metal dopant 148 includes Ga, the GTM-based P-dipole 150 may include a Ga-O dipole. In some embodiments, when the metal dopant 148 includes Zn, the TRM-based P-dipole 150 may include a Zn-O dipole.

[0045] In some embodiments, the HK gate dielectric layers 124P1-124P2 may further include metal dopants 140 of the same type but different concentrations, which can induce N-dipoles 144 of the same type but different concentrations in the dipole layers 142P1-142P2. P-dipoles 150 of the same type and substantially equal concentrations can form gate structures 112P1-112P3 with substantially equal threshold voltages. The presence of N-dipoles 144 at different concentrations, along with the P-dipoles 150, can adjust the threshold voltages to be different from each other. Since the concentration of metal dopant is proportional to the concentration of N-dipole, and the concentration of N-dipole is proportional to the threshold voltage of the PFET gate structure, (i) the HK gate dielectric layer 124P1 has a higher concentration of metal dopant 140 than the concentration of metal dopant 140 in the HK gate dielectric layers 124P2-124P3, so as to form a gate structure 112P1 with a threshold voltage greater than that of the gate structures 112P2-112P3, and (ii) the HK gate dielectric layer 124P2 has a higher concentration of metal dopant 140 than the concentration of metal dopant 140 in the HK gate dielectric layer 124P3, so as to form a gate structure 112P2 with a threshold voltage greater than that of the gate structure 112P3. Therefore, in some embodiments, the threshold voltage across different PFET gate structures (e.g., gate structures 112P1-112P3) can vary with different concentrations of mixed polarity dipoles (e.g., N-dipole 144 and P-dipole 150).

[0046] In some embodiments, the peak concentrations of metal dopants 140 and 148 in the HK gate dielectric layer 124P1 can be at interface P1 or within a distance D1 from interface P1, such as... Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the peak concentrations of metal dopants 140 and 148 in the HK gate dielectric layer 124P2 can be at interface P2 or within a distance D1 from interface P2, such as... Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the peak concentration of the metal dopant 148 in the HK gate dielectric layer 124P3 can be at interface P3 or within a distance D1 from interface P3, such as... Figure 1NThe metal dopant concentration curve 146 is shown in the figure. In some embodiments, the peak concentration of metal dopant 148 in the HK gate dielectric layer 124P3 can be from about 50 atomic% to about 80 atomic% to form a gate structure 112P3 with an ultra-low threshold voltage. In some embodiments, the peak concentration of metal dopant 140 in the HK gate dielectric layer 124P2 can be from about 5 atomic% to about 30 atomic% to form a gate structure 112P2 with a low threshold voltage. In some embodiments, the peak concentration of metal dopant 140 in the HK gate dielectric layer 124P1 can be from about 10 atomic% to about 40 atomic% to form a gate structure 112P1 with a threshold voltage greater than about 200 mV.

[0047] refer to Figure 1F In some embodiments, the HK gate dielectric layers 124N1-124N3 may include metal dopants 140 of the same type and substantially equal concentration, which can cause dipole layers 152N1-152N3 at interfaces N1-N3 having N-dipoles 144 of the same type and substantially equal concentration. In some embodiments, the HK gate dielectric layers 124N2-124N3 may further include metal dopants 148 of the same type but different concentrations, which can cause P-dipoles 150 of the same type but different concentrations in dipole layers 152N2-152N3. The N-dipoles 144 of the same type and substantially equal concentration can form gate structures 112N1-112N3 having substantially equal threshold voltages. The presence of different concentrations of P-dipoles 150, along with N-dipoles 144, can adjust the threshold voltages to be different from each other.

[0048] Since the concentration of metal dopant is proportional to the concentration of P-dipole, and the concentration of P-dipole is proportional to the threshold voltage of the NFET gate structure, (i) the HK gate dielectric layer 124N3 has a higher concentration of metal dopant 148 than the concentration of metal dopant 148 in the HK gate dielectric layers 124N1-124N2, so as to form a gate structure 112N3 with a threshold voltage greater than that of the gate structures 112N1-112N2, and (ii) the HK gate dielectric layer 124N2 has a higher concentration of metal dopant 148 than the concentration of metal dopant 148 in the HK gate dielectric layer 124N1, so as to form a gate structure 112N2 with a threshold voltage greater than that of the gate structure 112N1. Therefore, in some embodiments, the threshold voltage across different NFET gate structures (e.g., gate structures 112N1-112N3) can vary with different concentrations of mixed polarity dipoles (e.g., N-dipole 144 and P-dipole 150).

[0049] In some embodiments, the peak concentration of metal dopant 140 in the HK gate dielectric layer 124N1 can be from about 50 atomic% to about 80 atomic% to form a gate structure 112N1 with an ultra-low threshold voltage. In some embodiments, the peak concentration of metal dopant 148 in the HK gate dielectric layer 124N2 can be from about 5 atomic% to about 30 atomic% to form a gate structure 112N2 with a low threshold voltage. In some embodiments, the peak concentration of metal dopant 148 in the HK gate dielectric layer 124N3 can be from about 10 atomic% to about 40 atomic% to form a gate structure 112N3 with a threshold voltage greater than about 200 mV.

[0050] refer to Figure 1G In some embodiments, the HK gate dielectric layer 124P1 may be undoped, and the HK gate dielectric layers 124P2-124P3 may include metal dopants 148 of the same type but different concentrations, which may cause dipole layers 152P2-152P3 with the same type but different concentrations of P-dipoles 150 at interfaces P2-P3. Since the metal dopant concentration is directly proportional to the P-dipole concentration and inversely proportional to the threshold voltage of the PFET gate structure, (i) the HK gate dielectric layer 124P3 has a higher metal dopant concentration than the HK gate dielectric layers 124P1-124P2, to form a gate structure 112P3 with a lower threshold voltage than the gate structures 112P1-112P2, and (ii) the HK gate dielectric layer 124P2 has a higher metal dopant concentration than the metal dopant concentration in the HK gate dielectric layer 124P1, to form a gate structure 112P2 with a lower threshold voltage than the gate structure 112P1. Therefore, in some embodiments, the threshold voltage across different PFET gate structures (e.g., gate structures 112P1-112P3) can vary with different concentrations of the same polarity dipole (e.g., P-dipole 150).

[0051] In some embodiments, the peak concentration of the metal dopant 148 in the HK gate dielectric layers 124P2-124P3 can be at the interface P2-P3 or within a distance D1 from the interface P2-P3, such as Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the peak concentration of metal dopant 148 in the HK gate dielectric layer 124P3 can be from about 70 atomic% to about 80 atomic% to form a gate structure 112P3 with an ultra-low threshold voltage. In some embodiments, the peak concentration of metal dopant 148 in the HK gate dielectric layer 124P2 can be from about 40 atomic% to about 60 atomic% to form a gate structure 112P2 with a low threshold voltage.

[0052] refer to Figure 1H , Figure 1D The discussion of gate regions 112A1-112A3 applies to Figure 1H The gate regions 112A1-112A3. (Reference) Figure 1I , Figure 1G The discussion of gate regions 112B1-112B3 applies to Figure 1I The gate regions 112B1-112B3.

[0053] refer to Figure 1J , Figure 1D The discussion of gate regions 112A1-112A3 applies to Figure 1J The gate regions 112A1-112A3. (Reference) Figure 1K In some embodiments, the HK gate dielectric layer 124P1 may be undoped, and the HK gate dielectric layers 124P2-124P3 may include different types of metal dopants 149 and 154, which can cause dipole layers 156P2-156P3 with the same type of P-dipoles 151 and 158 at interfaces P2-P3. Metal dopant 149 may include elements of the periodic table GTM, such as Ga, Al, and In. Metal dopant 154 may include TRMs, such as Zn, Nb, Mo, W, and Ta. P-dipole 151 may include metal ions from metal dopant 149 and oxygen ions from IO layers 122P3. P-dipole 158 may include metal ions from metal dopant 154 and oxygen ions from IO layers 122P2-122P3. GTM dopant 149 can induce a GTM-based P-dipole 151 and TRM dopant 154 can induce a TRM-based P-dipole 158. In some embodiments, when metal dopant 149 comprises Ga, the GTM-based P-dipole 151 can comprise a Ga-O dipole. In some embodiments, when metal dopant 154 comprises Zn, the TRM-based P-dipole 158 can comprise a Zn-O dipole.

[0054] and Figure 1G The gate regions 112B1-112B3 are similar, spanning... Figure 1K The threshold voltage of gate regions 112B1-112B3 varies with different concentrations of P-dipoles, and the concentration of P-dipoles in gate region 112B3 (e.g., a combined concentration of P-dipoles 151 and 158) is greater than the concentration of P-dipoles in gate region 112B2. Figure 1G The gate region 112B3 is different. Figure 1K The P-dipoles (e.g., P-dipoles 151 and 158) of the gate region 112B3 are caused by different types of metal dopants (e.g., metal dopants 149 and 154).

[0055] In some embodiments, the peak concentrations of metal dopants 149 and 154 in the HK gate dielectric layers 124P2-124P3 can be at the interface P2-P3 or within a distance D1 from the interface P2-P3, such as in Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the total peak concentration of metal dopants 149 and 154 in the HK gate dielectric layer 124P3 can be from about 70 atomic% to about 80 atomic% to form a gate structure 112P3 with an ultra-low threshold voltage. In some embodiments, the peak concentration of metal dopant 154 in the HK gate dielectric layer 124P2 can be from about 40 atomic% to about 60 atomic% to form a gate structure 112P2 with a low threshold voltage.

[0056] refer to Figure 1L In some embodiments, the HK gate dielectric layer 124N3 may be undoped, and the HK gate dielectric layers 124N1-124N2 may include different types of metal dopants 141 and 160, which can cause dipole layers 156N1-156N2 with the same type of N-dipoles 145 and 162 at interfaces N1-N2. Metal dopant 141 may include REM, such as La, Y, Ce, Yb, and Er. Metal dopant 160 may include ALM, such as Mg, Ca, Sr, and Ba. N-dipole 145 may include metal ions from metal dopant 141 and oxygen ions from IO layers 122N1-122N2. N-dipole 162 may include metal ions from metal dopant 160 and oxygen ions from IO layer 122N1. REM dopant 141 can induce REM-based N-dipole 145 and ALM dopant 160 can induce ALM-based N-dipole 162. In some embodiments, when metal dopant 141 includes La, REM-based N-dipole 145 can include a La-O dipole. In some embodiments, when metal dopant 160 includes Mg, ALM-based N-dipole 162 can include a Mg-O dipole.

[0057] and Figure 1D The gate regions 112A1-112A3 are similar, spanning... Figure 1L The threshold voltage of gate regions 112A1-112A3 varies with different N-dipole concentrations, and the N-dipole concentration in gate region 112N1 (e.g., a combined concentration of N-dipoles 145 and 162) is greater than the N-dipole concentration in gate region 112N2. Figure 1D The gate region 112N1 is different. Figure 1LThe N-dipoles (e.g., N-dipoles 145 and 162) of the gate region 112N1 are caused by different types of metal dopants (e.g., metal dopants 141 and 160).

[0058] In some embodiments, the peak concentrations of metal dopants 141 and 160 in the HK gate dielectric layer 124N1 can be at interface N1 or within a distance D1 from interface N1, such as in Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the peak concentration of metal dopant 141 in the HK gate dielectric layer 124N2 may be at interface N2 or within a distance D1 from interface N2, as shown in the figure. Figure 1N The metal dopant concentration curve 146 is shown in the figure. In some embodiments, the total peak concentration of metal dopants 141 and 160 in the HK gate dielectric layer 124N1 can be from about 70 atomic% to about 80 atomic% to form a gate structure 112N1 with an ultra-low threshold voltage. In some embodiments, the peak concentration of metal dopant 141 in the HK gate dielectric layer 124N2 can be from about 40 atomic% to about 60 atomic% to form a gate structure 112N2 with a low threshold voltage.

[0059] refer to Figure 1M , Figure 1G The discussion of gate regions 112B1-112B3 applies to Figure 1M The gate regions 112B1-112B3.

[0060] Figure 2 It is according to some embodiments for manufacturing having Figure 1D and Figure 1E The flowchart of example method 200 for NFET 102N and PFET 102P, shown in the cross-sectional view, is provided. For illustrative purposes, reference will be made to... Figures 3A-15B The example manufacturing processes for manufacturing NFET 102N and PFET 102P are described in the figure. Figure 2 The operations are shown in the diagram. According to some embodiments, Figures 3A-15A It is along Figure 1A A cross-sectional view of the NFET 102N with line AA, and Figures 3B-15B It is along each stage of manufacturing. Figure 1A A cross-sectional view of the PFET 102P on line BB. Operations may be performed in a different order, or not at all, depending on the specific application. It should be noted that method 200 may not produce complete NFET 102N and PFET 102P. Therefore, it is understood that additional processes may be provided before, during, and after method 200, and only a few of these additional processes may be briefly described herein. Figures 3A-15B The components in have the same characteristics as described above. Figures 1A-1E The same annotations as the components in the text.

[0061] refer to Figure 2 In operation 205, a superlattice structure is formed on the fin structure, and a polycrystalline silicon structure is formed on the superlattice structure used for NFETs and PFETs. For example, as Figures 3A-3B As shown, a superlattice structure 323 is formed on the fin structures 106N-106P, and a polycrystalline silicon structure 312N-312P is formed on the superlattice structure 323. The superlattice structure 323 may include nanostructured layers 121 and 321 arranged in an alternating configuration. In some embodiments, the nanostructured layers 121 and 321 comprise different materials from each other. The nanostructured layer 321 is also referred to as a sacrificial layer 321. During subsequent processing, the polycrystalline silicon structures 312N-312P and the sacrificial layer 321 may be replaced in a gate replacement process to form gate structures 112N1-112N3 and 112P1-112P3.

[0062] refer to Figure 2 In operation 210, an S / D region is formed on the fin structure. For example, as... Figures 3A-3B As shown, S / D regions 110N-110P are formed on the fin structure 106N-106P. In some embodiments, the S / D regions 110N-110P can be epitaxially grown on the fin structure 106N-106P. Before forming the S / D regions 110N-110P, internal spacers 113 can be formed in the superlattice structure 323, such as... Figures 3A-3B As shown in the diagram. After forming the S / D regions 110N-110P, ESL 117 and ILD layer 118 can be formed, as shown in the diagram. Figures 3A-3B As shown in the image.

[0063] refer to Figure 2 In operation 215, a gate opening is formed, an I / O layer is formed within the gate opening, and an HK gate dielectric layer is formed on the I / O layer. For example, as... Figures 4A-4B As shown, gate openings 412N-412P are formed by removing polysilicon structures 312N-312P and sacrificial layer 321. I / O layers 122N1-122N3 and 122P1-122P3 are formed in gate openings 412N-412P, and HK gate dielectric layer 424 is formed on I / O layers 122N1-122N3 and 122P1-122P3.

[0064] refer to Figures 5A-15B Description of operations 220-235 Figures 4A-4B The subsequent processing of the structure. Figures 5A-15A yes Figure 4A Enlarged view of gate regions 112A1-112A3, and Figures 5B-15B yes Figure 4B Enlarged view of the gate regions 112B1-112B3.

[0065] refer to Figure 2 In operation 220, a doping process is performed using a first-type metal dopant that induces a P-dipole to dope the HK gate dielectric layer portion of the PFET. For example, as referenced... Figures 5A-6B As described, a doping process is performed using a metal dopant 148 that induces a P-dipole 150 to dope portions of the HK gate dielectric layer 424 in gate regions 112B1-112B3. The doping process may include the following sequential operations: (i) depositing a dopant source layer 564 on the HK gate dielectric layer 424, as... Figures 5A-5B As shown, (ii) a capping layer 566 is deposited on the dopant source layer 564, as... Figures 5A-5B As shown, (iii) portions of the dopant source layer 564 and capping layer 566 are selectively removed from the gate regions 112A1-112A3 using photolithography patterning and etching processes to form Figures 6A-6B The structure, (iv) in Figures 6A-6B The structure is subjected to a drive-in annealing process to implant metal dopant 148 into portions of the HK gate dielectric layer 424 in the gate regions 112B1-112B3, such as Figure 6B As shown, and (v) from Figure 6B The dopant source layer 564 and capping layer 566 are removed from the structure.

[0066] The deposition of the dopant source layer 564 may include depositing a layer of GTM oxide, such as gallium oxide (Ga2O3), aluminum oxide (Al2O3), and indium oxide (In2O3), or depositing a layer of TRM oxide, such as zinc oxide (ZnO2), niobium oxide (NbO2), molybdenum oxide (MoO2), tungsten oxide (WO3), and tantalum oxide (Ta2O5), using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, the dopant source layer 564 may be deposited with a thickness of about 0.1 nm to about 5 nm to adequately perform the doping process without compromising manufacturing costs.

[0067] The deposition of capping layer 566 may include using a CVD or ALD process to deposit a layer of alumina (Al2O3) or other suitable metal oxide having a thickness of about 0.1 nm to about 5 nm. In some embodiments, capping layer 566 may prevent material of dopant source layer 564 from evaporating during drive-in annealing.

[0068] The drive-in annealing process implants the metal dopant 148 into the HK gate dielectric layer 424 by diffusing metal atoms from the dopant source layer 564 into the HK gate dielectric layer 424. The drive-in annealing process may include a temperature of approximately 500°C to approximately 850°C and a pressure of approximately 1 torr to approximately 50 torr for a period of approximately 0.1 seconds to approximately 3 minutes. Figures 6A-6B The structure is annealed. In some embodiments, the drive-in annealing process may include two annealing processes: (i) a uniform annealing process at a temperature of about 500°C to about 850°C for a period of about 2 seconds to about 60 seconds, and (ii) a spike annealing process at a temperature of about 700°C to about 850°C for a period of about 0.1 seconds to about 2 seconds.

[0069] refer to Figure 2 In operation 225, a doping process is performed using a type-2 metal dopant that induces an N-dipole to dope the HK gate dielectric layer. For example, as referenced... Figures 7A-12B As described, a doping process is performed using a metal dopant 140 that induces an N-dipole 144 to dope portions of the HK gate dielectric layer 424 in gate regions 112A1-112A2 and 112B1-112B2. The doping process may include the following sequential operations: (i) depositing a dopant source layer 768 on the HK gate dielectric layer 424, as... Figures 7A-7B As shown, (ii) a capping layer 566 is deposited on the dopant source layer 768, as... Figures 7A-7B As shown, (iii) portions of the dopant source layer 768 and capping layer 566 are selectively removed from the gate regions 112A2-112A3 and 112B2-112B3 using photolithography patterning and etching processes to form Figures 8A-8B (iv) To form the structure, portions of the capping layer 566 are selectively removed from the gate regions 112A1 and 112B1 using photolithography patterning and etching processes. Figures 9A-9B The structure, (v) in Figures 9A-9B The structure is deposited with a doped source layer 1068, such as Figures 10A-10B As shown, (vi) a capping layer 566 is deposited on the dopant source layer 1068 to form Figures 10A-10B The structure, (vii) involves selectively removing portions of the dopant source layer 1068 and capping layer 566 from gate regions 112A3 and 112B3 using photolithographic patterning and etching processes, such as... Figures 11A-11B As shown in Figure (viii), a portion of the capping layer 566 is removed from the gate regions 112A1-112A2 and 112B1-112B2 to form Figures 11A-11B The structure, (ix) in Figures 11A-11BThe structure is subjected to a drive-in annealing process to implant metal dopant 140 into portions of the HK gate dielectric layer 424 in the gate regions 112A1-112A2 and 112B1-112B2, such as Figures 11A-11B As shown, and (x) from Figures 11A-11B Remove the dopant source layers 768 and 1068 from the structure to form Figures 12A-12B The structure.

[0070] The deposition of the dopant source layer 768 may include depositing a layer of REM oxides, such as lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), cerium oxide (CeO₂), ytterbium oxide (Yb₂O₃), and erbium oxide (Er₂O₃), or depositing a layer of ALM oxides, such as magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), and barium oxide (BaO), using a CVD process or an ALD process. In some embodiments, the dopant source layer 768 may be deposited with a thickness of about 0.1 nm to about 5 nm to adequately perform the doping process without compromising manufacturing costs. In some embodiments, the discussion of the dopant source layer 768 applies to the doped source layer 1068 unless otherwise stated. The concentration of dopant 140 in the portion of the HK gate dielectric layer 424 in the gate region 112A1-112B1 implanted by the two dopant source layers 768 and 1068 is higher than the concentration of dopant 140 in the portion of the HK gate dielectric layer 424 in the gate region 112A2-112B2 implanted from the dopant source layer 1068.

[0071] The drive-in annealing process can implant the metal dopant 140 into the HK gate dielectric layer 424 by diffusing metal atoms from the dopant source layers 768 and 1068 into the HK gate dielectric layer 424. The drive-in annealing process can be similar to the drive-in annealing process described in operation 220.

[0072] refer to Figure 2 In operation 230, a two-stage annealing process is performed on both the NFET and PFET. For example, as referenced... Figures 13A-14B As described, in Figures 12A-12B A two-stage annealing process is performed on the structure to improve the electrical characteristics and / or reliability of the IO layers 122N1-122N3 and 122P1-122P3 and / or the HK gate dielectric layer 424. The first-stage annealing process may include the following sequential operations: (i) depositing a metal nitride capping layer 1370 on the HK gate dielectric layer 424, such as Figures 13A-13B As shown, (ii) an in-situ Si capping layer 1372 is deposited on the metal nitride capping layer 1370, as... Figures 13A-13B As shown in (iii), and in Figures 13A-13B The first peak annealing process is performed on the structure.

[0073] In some embodiments, the metal nitride capping layer 1370 may comprise TiSiN or TiN, and may be deposited using titanium tetrachloride (TiCl4), silane (SiH4), and ammonia (NH3) as precursors at a temperature of about 400°C to about 500°C via an ALD or CVD process. In-situ deposition of the Si capping layer 1372 may include ALD, CVD, or PVD processes. In some embodiments, in-situ deposition of the Si capping layer 1372 may include a homogenization process using TiCl4 and SiH4 gases at a temperature of about 400°C to about 500°C. The homogenization process may include a period of time during which TiCl4 gas is circulated over the metal nitride capping layer 1370 for about 80 seconds to about 100 seconds, followed by a period of time during which SiH4 gas is circulated for about 100 seconds to about 200 seconds. In some embodiments, the Si capping layer 1372 may comprise Si or a compound thereof and / or may comprise amorphous or polycrystalline Si. The Si capping layer 1372 can prevent oxidation of the IO layers 122N1-122N3 and 122P1-122P3 and / or the HK gate dielectric layer 424 during subsequent annealing processes. The first spike annealing process may include performing the annealing process in a nitrogen atmosphere at an annealing temperature of about 600°C to about 1000°C for a period of about 1 second to about 60 seconds.

[0074] The second-stage annealing process may include the following sequential steps: (i) removing the metal nitride layer 1370 and the in-situ Si capping layer 1372 after the first-stage annealing process, such as Figures 14A-14B As shown, and (ii) in Figures 14A-14B A second peak annealing process is performed on the structure. The metal nitride layer 1370 and the in-situ Si capping layer 1372 can be removed by a wet etching process. In some embodiments, the wet etching process may include etching in DHF, KOH solution, SCl solution, or a combination thereof. The second peak annealing process can be performed in an NH3 environment at an annealing temperature of about 600°C to about 1000°C for a period of about 1 second to about 60 seconds. In some embodiments, the annealing temperatures of the first and second peak annealing processes may be similar to or different from each other.

[0075] refer to Figure 2 In operation 235, a WFM layer is deposited on the HK gate dielectric layer and a gate metal fill layer is deposited on the WFM layer. For example, as... Figures 15A-15B As shown, a WFM layer 1526 is deposited on the HK gate dielectric layer 424 and a gate metal fill layer 1528 is deposited on the WFM layer 1526. After depositing the gate metal fill layer 1528, [further details can be added]. Figures 15A-15B Chemical mechanical polishing (CMP) and etching processes are performed on the structure to form such as Figures 1B-1CThe HK gate dielectric layers 124N1-124N2 and 124P1-124P2, WFM layer 126, and gate metal fill layer 128 are shown. A conductive capping layer 130 and an insulating capping layer 132 can be formed after an etching process.

[0076] refer to Figure 2 In operation 240, a contact structure is formed on the S / D region. For example, as... Figures 1B-1C As shown, the contact structure 120 can be formed on the S / D regions 110N-110P.

[0077] Figure 16 It is according to some embodiments for manufacturing having Figure 1H and Figure 1I The flowchart of example method 1600 for the NFET 102N and PFET 102P cross-sectional view shown is illustrated. For illustrative purposes, reference will be made to... Figures 17A-25B The example manufacturing process for manufacturing NFET 102N and PFET 102P is described in the figure. Figure 16 The operations are shown in the diagram. According to some embodiments, Figures 17A-25A It is along Figure 1A A cross-sectional view of the NFET 102N with line AA, and Figures 17B-25B It is along each stage of manufacturing. Figure 1A A cross-sectional view of the PFET 102P on line BB. Operations may be performed in a different order, or not at all, depending on the specific application. It should be noted that method 1600 may not produce complete NFET 102N and PFET 102P. Therefore, it is understood that additional processes may be provided before, during, and after method 1600, and only a few of these additional processes may be briefly described herein. Figures 17A-25B The components in have the same characteristics as described above. Figures 1A-1I The same annotations as the components in the text.

[0078] refer to Figure 16 Operations 1605-1615 and Figure 2 Operations 205-215 are similar. After operation 1615, the structure is... Figures 4A-4B The resulting structures are similar. In operations 1620-1635... Figures 4A-4B Subsequent structural processing, refer to Figures 17A-25B describe. Figures 17A-25A yes Figure 4A Enlarged view of gate regions 112A1-112A3, and Figures 17B-25B yes Figure 4B Enlarged view of the gate regions 112B1-112B3.

[0079] refer to Figure 16In operation 1620, a doping process is performed using a first-type metal dopant that induces N-dipoles to dope the HK gate dielectric layer portion of the NFET. For example, as referenced... Figures 17A-20B As described, a doping process is performed using a metal dopant 140 that induces an N-dipole 144 to dope a portion of the HK gate dielectric layer 424 in the gate regions 112A1-112A2. The doping process may include the following sequential operations: (i) depositing a dopant source layer 768 on the HK gate dielectric layer 424, as... Figures 17A-17B As shown, (ii) a capping layer 566 is deposited on the dopant source layer 768, as... Figures 17A-17B As shown, (iii) portions of the dopant source layer 768 and capping layer 566 are selectively removed from the gate regions 112A2-112A3 and 112B1-112B3 using photolithography patterning and etching processes to form Figures 18A-18B The structure, (iv) in Figures 18A-18B A doped source layer of 1068 is deposited on the structure. For example... Figures 19A-19B As shown in the figure, (v) a capping layer 566 is deposited on the dopant source layer 1068 to form Figures 19A-19B The structure, (vi) involves selectively removing portions of the dopant source layer 1068 and capping layer 566 from gate regions 112A3 and 112B1-112B3 using photolithography patterning and etching processes, such as... Figures 20A-20B As shown, (vii) a portion of the capping layer 566 is removed from the gate regions 112A1-112A2 to form Figures 20A-20B The structure, (viii) in Figures 20A-20B The structure is subjected to a drive-in annealing process to implant metal dopant 140 into portions of the HK gate dielectric layer 424 in the gate regions 112A1-112A2, such as Figure 20A As shown, and (ix) from Figure 20A The dopant source layers 768 and 1068 are removed from the structure.

[0080] The drive-in annealing process can implant the metal dopant 140 into the HK gate dielectric layer 424 by diffusing metal atoms from the dopant source layers 768 and 1068 into the HK gate dielectric layer 424. The drive-in annealing process can be similar to the drive-in annealing process described in operation 220.

[0081] refer to Figure 16 In operation 1625, a doping process is performed using a type-2 metal dopant that induces a P-dipole to dope the HK gate dielectric layer portion of the PFET. For example, as referenced... Figures 21A-24BAs described, a doping process is performed using a metal dopant 148 that induces a P-dipole 150 to dope portions of the HK gate dielectric layer 424 in gate regions 112B2-112B3. The doping process may include the following sequential operations: (i) depositing a dopant source layer 564 on the HK gate dielectric layer 424, as... Figures 21A-21B As shown, (ii) a capping layer 566 is deposited on the dopant source layer 564, as... Figures 21A-21B As shown, (iii) portions of the dopant source layer 564 and capping layer 566 are selectively removed from the gate regions 112A1-112A3 and 112B1-112B2 using photolithography patterning and etching processes to form Figures 22A-22B The structure, (iv) in Figures 22A-22B The structure performs a first implantation annealing process to implant metal dopant 148 into a portion of the HK gate dielectric layer 424 within the gate region 112B3, such as... Figures 22A-22B As shown, (iv) from Figure 22B In the structure, the dopant source layer 564 and capping layer 566 are removed, and (v) operations (i) and (ii) are repeated to form Figures 23A-23B The structure (vi) is formed by selectively removing portions of the dopant source layer 564 and capping layer 566 from the gate regions 112A1-112A3 and 112B1 using photolithography patterning and etching processes. Figures 24A-24B The structure, (vii) in Figures 24A-24B The structure performs a second implantation annealing process to implant metal dopant 148 into portions of the HK gate dielectric layer 424 within gate regions 112B2-112B3, such as... Figure 24B As shown, and (viii) from Figure 24B The dopant source layer 564 and capping layer 566 are removed from the structure to form Figures 25A-25B The structure. The first and second drive-in annealing processes can be similar to the drive-in annealing process described in operation 220.

[0082] refer to Figure 16 Operations at 1630-1640 are similar to... Figure 2 Operations 230-240 and in Figures 25A-25B Executed on the structure, forming Figures 1B-1C The structure.

[0083] Figure 26 It is according to some embodiments for manufacturing having Figure 1J and Figure 1K The flowchart of example method 2600 for NFET 102N and PFET 102P cross-sectional views is shown. For illustrative purposes, reference will be made to... Figures 27A-30BThe example manufacturing processes for manufacturing NFET 102N and PFET 102P are described in the figure. Figure 26 The operations are shown in the diagram. According to some embodiments, Figures 27A-30A It is along Figure 1A A cross-sectional view of the NFET 102N with line AA, and Figure 27B-30B It is along each stage of manufacturing. Figure 1A A cross-sectional view of the PFET 102P on line BB. Operations may be performed in a different order, or not at all, depending on the specific application. It should be noted that method 2600 may not produce complete NFET 102N and PFET 102P. Therefore, it is understood that additional processes may be provided before, during, and after method 2600, and only a few of these additional processes may be briefly described herein. Figures 27A-30B The components in have the same characteristics as described above. Figures 1A-1K The same annotations as the components in the text. Figures 27A-30A yes Figure 4A Enlarged view of gate regions 112A1-112A3, and Figures 27B-30B yes Figure 4B Enlarged view of the gate regions 112B1-112B3.

[0084] refer to Figure 26 Operations 2605-2620 are similar to... Figure 16 Operations 1605-1620. After operation 1620, the structure and... Figures 20A-20B The resulting structures are similar.

[0085] refer to Figure 26 In operation 2625, a doping process is performed using a type-2 metal dopant that induces a P-dipole to dope the HK gate dielectric layer portion of the PFET. For example, as... Figure 27B As shown, a doping process is performed using a metal dopant 148 that induces a P-dipole 150 to dope a portion of the HK gate dielectric layer 424 in the gate region 112B3. Doping process and reference. Figures 21A-22B The doping process is similar to that described in Operation 1625.

[0086] refer to Figure 26 In operation 2630, a doping process is performed using a type III metal dopant that induces a P-dipole to dope the HK gate dielectric layer portion of the PFET. For example, as referenced... Figures 28A-30B As described, a doping process is performed using a metal dopant 154 that induces a P-dipole 158 to dope portions of the HK gate dielectric layer 424 in gate regions 112B2-112B3. The doping process may include the following sequential operations: (i) depositing a dopant source layer 2874 on the HK gate dielectric layer 424, as... Figures 28A-28B As shown, (ii) a capping layer 566 is deposited on the dopant source layer 2874, as... Figures 28A-28B As shown, (iii) portions of the dopant source layer 2874 and capping layer 566 are selectively removed from the gate regions 112A1-112A3 and 112B1 using photolithography patterning and etching processes to form Figures 29A-29B The structure, (iv) in Figures 29A-29B The structure performs a first implantation annealing process to implant metal dopant 154 into portions of the HK gate dielectric layer 424 in gate regions 112B2-112B3, such as Figure 29B As shown, and (v) from Figure 29B The dopant source layer 2874 and capping layer 566 are removed from the structure to form Figures 30A-30B The structure.

[0087] In some embodiments, the dopant source layer 2874 may include a layer of GTM oxide or TRM oxide of a different material than the dopant source layer 564. Deposition of the dopant source layer 2874 may include depositing a layer of GTM oxide or TRM oxide having a thickness of about 0.1 nm to 5 nm to adequately perform the doping process without compromising manufacturing costs.

[0088] refer to Figure 26 Operations 2635-2645 are similar to... Figure 2 Operations 230-240, and... Figures 30A-30B Execution on the structure to form Figures 1B-1C The structure.

[0089] This disclosure provides example structures of FETs (e.g., NFET 102N and PFET 102P) having different gate structures (e.g., gate structures 112N1-112N3 and 112P1-112P3) configured to provide different and / or low threshold voltages, and example methods for forming such multi-Vt FETs on the same substrate. The example methods form NFETs and PFETs with ultra-low, low, and / or different threshold voltages on the same substrate, but with WFM layers of similar thickness. Compared to other methods of forming FETs with similar dimensions and threshold voltages on the same substrate, these example methods are more cost-effective (e.g., reducing cost by about 20% to about 30%) and time-efficient (e.g., reducing time by about 15% to about 20%) in fabricating reliable FET gate structures with different low and / or ultra-low threshold voltages. Furthermore, compared to other methods of forming FETs with similar threshold voltages, these example methods can form FET gate structures with much smaller dimensions (e.g., thinner gate stacks).

[0090] In some embodiments, NFETs and PFETs with different gate structure configurations but similar WFM layer thicknesses can be selectively formed on the same substrate to achieve low, ultra-low, and / or different threshold voltages. Different gate structures may have HK gate dielectric layers (e.g., HK gate dielectric layers 124N1-124N2 and 124P1-124P3) doped with different types and / or concentrations of metal dopants (e.g., metal dopants 140 and 148). Different types and / or concentrations of metal dopants can cause dipoles of different polarities and / or concentrations (e.g., dipoles 144 and 150) at the interface between the HK gate dielectric layer and the IO layer. Different polarities and / or concentrations of dipoles result in gate structures with different EWF values. Since the EWF value of the gate structure corresponds to the threshold voltage of the FET, gate structures with different EWF values ​​result in FETs with different threshold voltages on the same substrate. Therefore, controlling the type and / or concentration of metal dopants in the HK gate dielectric layer can adjust the EWF value of the NFET and PFET gate structures, and thus the threshold voltage of the NFET and PFET can be adjusted without changing the thickness of the WFM layer.

[0091] In some embodiments, the semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interface oxide (IO) layer, a first high-k (HK) dielectric layer disposed on the first interface oxide layer, and a first dipole layer disposed at the interface between the first IO layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IO layer, a second HK dielectric layer disposed on the second IO layer, and a second dipole layer disposed at the interface between the second IO layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and a rare-earth metal dopant or an alkali metal dopant.

[0092] In some embodiments, the semiconductor device includes a substrate, a fin structure disposed on the substrate, first and second nanostructured channel regions disposed on the fin structure, a first gate structure disposed on the first nanostructured channel region, and a second gate structure disposed on the second nanostructured channel region. The first gate structure includes a first dielectric layer disposed on the first nanostructured channel region and a p-type dipole layer disposed between the first dielectric layer and the first nanostructured channel region. The dielectric layer includes a transition metal dopant. The second gate structure includes a second dielectric layer disposed on the second nanostructured channel region and a dipole layer having n-type and p-type dipoles disposed between the second dielectric layer and the second nanostructured channel region. The dielectric layer includes a transition metal dopant and an alkali metal dopant.

[0093] In some embodiments, a method includes forming a first fin structure and a second fin structure on a substrate, forming a first nanostructured channel region and a second nanostructured channel region on the first fin structure and the second fin structure, respectively, depositing a gate dielectric layer having a first portion and a second portion, the first portion and the second portion of the gate dielectric layer surrounding the first nanostructured channel region and the second nanostructured channel region, respectively, depositing a transition metal base layer on the gate dielectric layer, removing a portion of the transition metal base layer on the first portion of the gate dielectric layer, performing a first annealing process on the transition metal base layer to remove the transition metal base layer, depositing an alkali metal base layer on the gate dielectric layer, performing a second annealing process on the alkali metal base layer to remove the alkali metal base layer, depositing a work function metal layer on the gate dielectric layer, and depositing a gate metal fill layer on the work function metal layer.

[0094] According to embodiments of this application, a semiconductor device is provided, comprising: a first gate structure, the first gate structure comprising: a first interface oxide layer; a first high-k dielectric layer disposed on the first interface oxide layer, wherein the high-k dielectric layer comprises a rare-earth metal dopant or an alkali metal dopant; and a first dipole layer disposed at the interface between the first interface oxide layer and the first high-k dielectric layer; the semiconductor device further comprising a second gate structure, the second gate structure comprising: a second interface oxide layer; a second high-k dielectric layer disposed on the second interface oxide layer, wherein the second high-k dielectric layer comprises: a transition metal dopant, and a rare-earth metal dopant or an alkali metal dopant; the second gate structure further comprising a second dipole layer disposed at the interface between the second interface oxide layer and the second high-k dielectric layer. In some embodiments, the first dipole layer comprises a rare-earth metal-based dipole or an alkali metal-based dipole. In some embodiments, the first dipole layer comprises an n-type dipole. In some embodiments, the second dipole layer comprises a transition metal-based dipole and a rare-earth metal-based dipole or an alkali metal-based dipole. In some embodiments, the second dipole layer comprises n-type dipoles and p-type dipoles. In some embodiments, the concentration of rare-earth metal dopants in the first high-k dielectric layer is substantially equal to the concentration of rare-earth metal dopants in the second high-k dielectric layer. In some embodiments, the concentration of rare-earth metal dopants in the first high-k dielectric layer is greater than the concentration of transition metal dopants in the second high-k dielectric layer. In some embodiments, the concentration of rare-earth metal dopants in the second high-k dielectric layer is greater than the concentration of transition metal dopants in the second high-k dielectric layer. In some embodiments, the peak concentration of rare-earth metal dopants or alkali metal dopants in the first high-k dielectric layer is at the interface between the first interface oxide layer and the first high-k dielectric layer. In some embodiments, the second dipole layer comprises zinc-based p-type dipoles and lanthanum-based n-type dipoles.

[0095] According to another embodiment of this application, a semiconductor device is provided, comprising: a substrate; a fin structure disposed on the substrate; a first nanostructured channel region and a second nanostructured channel region disposed on the fin structure; a first gate structure disposed on the first nanostructured channel region, the first gate structure comprising: a first dielectric layer disposed on the first nanostructured channel region, wherein the first dielectric layer comprises a transition metal dopant; and a p-type dipole layer disposed between the first dielectric layer and the first nanostructured channel region; and the semiconductor device comprising a second gate structure disposed on the second nanostructured channel region, the second gate structure comprising: a second dielectric layer disposed on the second nanostructured channel region, wherein the second dielectric layer comprises a transition metal dopant and an alkali metal dopant; and a dipole layer having n-type dipoles and p-type dipoles, the dipole layer being disposed between the second dielectric layer and the second nanostructured channel region. In some embodiments, the concentration of the transition metal dopant in the first dielectric layer is substantially equal to the concentration of the transition metal dopant in the second dielectric layer. In some embodiments, the concentration of the transition metal dopant in the first dielectric layer is greater than the concentration of the alkali metal dopant in the second dielectric layer. In some embodiments, the dipole layer comprises zinc-based p-type dipoles and magnesium-based n-type dipoles. In some embodiments, the concentration of p-type dipoles in the p-type dipole layer is substantially equal to the concentration of p-type dipoles in the dipole layer. In some embodiments, the concentration of p-type dipoles in the dipole layer is greater than the concentration of n-type dipoles in the dipole layer.

[0096] According to another embodiment of this application, a method for manufacturing a semiconductor device is provided, comprising: forming a first fin structure and a second fin structure on a substrate; forming a first nanostructured channel region and a second nanostructured channel region on the first fin structure and the second fin structure, respectively; depositing a gate dielectric layer having a first portion and a second portion, the first portion and the second portion of the gate dielectric layer respectively surrounding the first nanostructured channel region and the second nanostructured channel region; depositing a transition metal substrate on the gate dielectric layer; removing a portion of the transition metal substrate on the first portion of the gate dielectric layer; performing a first annealing process on the transition metal substrate; removing the transition metal substrate; depositing an alkali metal substrate on the gate dielectric layer; performing a second annealing process on the alkali metal substrate; removing the alkali metal substrate; depositing a work function metal layer on the gate dielectric layer; and depositing a gate metal fill layer on the work function metal layer. In some embodiments, the method for manufacturing a semiconductor device further comprises depositing a capping layer on the transition metal substrate. In some embodiments, the method for manufacturing a semiconductor device further comprises depositing a capping layer on an alkali metal substrate. In some embodiments, the method for manufacturing a semiconductor device further comprises depositing another alkali metal substrate on an alkali metal substrate.

[0097] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A first gate structure, comprising: a first interface oxide layer; a first high-k dielectric layer disposed on the first interface oxide layer, wherein the high-k dielectric layer comprises a rare-earth metal dopant or an alkaline-earth metal dopant; and a first dipole layer disposed at the interface between the first interface oxide layer and the first high-k dielectric layer; and The second gate structure includes: a second interface oxide layer, a second high-k dielectric layer disposed on the second interface oxide layer, and a second dipole layer disposed at the interface between the second interface oxide layer and the second high-k dielectric layer. The second high-k dielectric layer includes: a transition metal dopant, and the rare earth metal dopant or the alkaline earth metal dopant; The first dipole layer and the second dipole layer contain dipoles with different polarities and / or concentrations.

2. The semiconductor device according to claim 1, wherein, The first dipole layer includes rare earth metal-based dipoles or alkaline earth metal-based dipoles.

3. The semiconductor device according to claim 1, wherein, The first dipole layer includes n-type dipoles.

4. The semiconductor device according to claim 1, wherein, The second dipole layer includes transition metal-based dipoles and rare earth metal-based dipoles or alkaline earth metal-based dipoles.

5. The semiconductor device according to claim 1, wherein, The second dipole layer includes n-type dipoles and p-type dipoles.

6. The semiconductor device according to claim 1, wherein, The concentration of the rare earth metal dopant in the first high-k dielectric layer is substantially equal to the concentration of the rare earth metal dopant in the second high-k dielectric layer.

7. The semiconductor device according to claim 1, wherein, The concentration of the rare earth metal dopant in the first high-k dielectric layer is greater than the concentration of the transition metal dopant in the second high-k dielectric layer.

8. The semiconductor device according to claim 1, wherein, The concentration of the rare earth metal dopant in the second high-k dielectric layer is greater than the concentration of the transition metal dopant in the second high-k dielectric layer.

9. The semiconductor device according to claim 1, wherein, The peak concentration of the rare earth metal dopant or the alkaline earth metal dopant in the first high-k dielectric layer is at the interface between the first interface oxide layer and the first high-k dielectric layer.

10. The semiconductor device according to claim 1, wherein, The second dipole layer includes zinc-based p-type dipoles and lanthanum-based n-type dipoles.

11. A semiconductor device, comprising: Substrate; A fin structure is disposed on the substrate; The first nanostructured channel region and the second nanostructured channel region are disposed on the fin structure. A first gate structure is disposed on the first nanostructured channel region. The first gate structure includes: a first dielectric layer disposed on the first nanostructured channel region, wherein the first dielectric layer includes a transition metal dopant; and a p-type dipole layer disposed between the first dielectric layer and the first nanostructured channel region; and A second gate structure is disposed on the second nanostructured channel region. The second gate structure includes: a second dielectric layer disposed on the second nanostructured channel region, wherein the second dielectric layer includes the transition metal dopant and the alkaline earth metal dopant; and a dipole layer having n-type dipoles and p-type dipoles, wherein the dipole layer is disposed between the second dielectric layer and the second nanostructured channel region.

12. The semiconductor device of claim 11, wherein the concentration of the transition metal dopant in the first dielectric layer is substantially equal to the concentration of the transition metal dopant in the second dielectric layer.

13. The semiconductor device according to claim 11, wherein, The concentration of the transition metal dopant in the first dielectric layer is greater than the concentration of the alkaline earth metal dopant in the second dielectric layer.

14. The semiconductor device according to claim 11, wherein, The dipole layer includes zinc-based p-type dipoles and magnesium-based n-type dipoles.

15. The semiconductor device according to claim 11, wherein, The concentration of p-type dipoles in the p-type dipole layer is substantially equal to the concentration of p-type dipoles in the dipole layer.

16. The semiconductor device according to claim 11, wherein, The concentration of p-type dipoles in the dipole layer is greater than the concentration of n-type dipoles in the dipole layer.

17. A method for manufacturing a semiconductor device, comprising: A first fin structure and a second fin structure are formed on a substrate; A first nanostructured channel region and a second nanostructured channel region are formed on the first fin structure and the second fin structure, respectively. An interface oxide layer is formed on the first nanostructured channel region and the second nanostructured channel region; A gate dielectric layer having a first portion and a second portion is deposited on the interface oxide layer, wherein the first portion and the second portion of the gate dielectric layer surround the first nanostructured channel region and the second nanostructured channel region, respectively. A transition metal base layer is deposited on the gate dielectric layer; Remove a portion of the transition metal substrate on the first portion of the gate dielectric layer; A first annealing process is performed on the transition metal substrate; Remove the transition metal substrate; An alkaline earth metal substrate is deposited on the gate dielectric layer; A second annealing process is performed on the alkaline earth metal substrate; Remove the alkaline earth metal base layer; A work function metal layer is deposited on the gate dielectric layer; as well as A gate metal fill layer is deposited on the work function metal layer. The gate dielectric layer is a high-K gate dielectric layer, and the interface between the high-K gate dielectric layer and the interface oxide layer contains dipoles with different polarities and / or concentrations.

18. The method of claim 17, further comprising depositing a capping layer on the transition metal substrate.

19. The method of claim 17, further comprising depositing a capping layer on the alkaline earth metal base layer.

20. The method of claim 17 further comprises depositing another alkaline earth metal base layer on the alkaline earth metal base layer.

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