Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a plurality of mutually discrete gate electrodes and a cover structure at least located on the top surface of the gate electrodes within the first dielectric layer, the cover structure including a main layer and a first sidewall located on the sidewall surface of the main layer; forming a second dielectric layer on the first dielectric layer and the cover structure; forming a first conductive opening within the first dielectric layer and the second dielectric layer; forming a first conductive structure within the first conductive opening, the first conductive structure having a second sidewall opening, the bottom of the second sidewall opening exposing at least a portion of the top surface of the first sidewall and the top surface of the first conductive structure; and forming a second sidewall on the sidewall surface within the second sidewall opening. The formation method achieves self-alignment of the etching process, thereby improving the reliability of the semiconductor structure and increasing the process window of the manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits is constantly shrinking, which will effectively improve the operating speed of the entire integrated circuit.

[0003] However, as the size requirements of components become smaller and smaller, the size of the conductive structures formed to connect with semiconductor devices becomes smaller and smaller, resulting in poor reliability of existing semiconductor structures, and small process windows for existing manufacturing processes. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the reliability of the semiconductor structure and increase the process window of the manufacturing process.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a base and a plurality of fins disposed on the base; an isolation layer on the substrate, the isolation layer further being located between adjacent fins, the surface of the isolation layer being lower than the top surface of the fins; a first dielectric layer located on the surface of the isolation layer and on the exposed surfaces of the fins; a plurality of gate electrodes disposed within the first dielectric layer, the surface of the gate electrodes being lower than the surface of the lower dielectric layer, the gate electrodes also being located on the isolation layer, the gate electrodes spanning the surface of the fins, and the fins between adjacent gate electrodes having source / drain doped regions; and a cover structure at least located on the top surface of the gate electrodes, the cover structure including a main body layer and a cover layer located on the main body layer. A first sidewall on the sidewall of the layer; a first conductive structure located within the first dielectric layer, the top surface of the first conductive structure being higher than the top surface of the gate electrode and located between adjacent cover structures, the top surface of the first conductive structure being lower than or flush with the top surface of the first sidewall, and the first conductive structure contacting the surface of the source / drain doped region; a second dielectric layer located on the first dielectric layer and the cover structure; a second sidewall located within the second dielectric layer, the second sidewall also being located on the top surface of the first sidewall; a second conductive structure located within the first dielectric layer and the second dielectric layer, the second conductive structure contacting the top surface of the gate electrode, the second conductive structure being located between adjacent first sidewalls and between adjacent second sidewalls, and the second conductive structure penetrating the cover structure.

[0006] Optionally, the sidewall of the gate electrode has a gate sidewall, with at least a portion of the first sidewall located on the top surface of the gate sidewall.

[0007] Optionally, the sidewalls of the cover structure protrude relative to the sidewalls of the gate electrode.

[0008] Optionally, the sidewall of the second sidewall protrudes relative to the sidewall of the covering structure, and the second sidewall is also located on the top surface of the first conductive structure portion.

[0009] Optionally, the covering structure further includes: a protective layer located between the main body layer and the top surface of the gate electrode, the protective layer being connected to the first sidewalls on both sides of the main body layer, and the second conductive structure penetrating the protective layer.

[0010] Optionally, it further includes: a third conductive structure located within the second dielectric layer, the third conductive structure being located between adjacent second sidewalls, and the third conductive structure being in contact with the top surface of the first conductive structure.

[0011] Optionally, the material of the first dielectric layer includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3; the material of the second dielectric layer includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0012] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a plurality of mutually discrete gate electrodes and a cover structure at least located on the top surface of the gate electrodes within the first dielectric layer, the cover structure including a main layer and a first sidewall located on the sidewall surface of the main layer; forming a second dielectric layer on the first dielectric layer and the cover structure; forming a first conductive opening within the first dielectric layer and the second dielectric layer, the first conductive opening exposing the substrate surface between adjacent gate electrodes and the sidewall surface of the cover structure; forming a first conductive structure within the first conductive opening, the first conductive structure having a second sidewall opening, wherein the first conductive structure is in contact with the substrate between adjacent gate electrodes, the first conductive structure is located between adjacent cover structures, the top surface of the first conductive structure is lower than or flush with the top surface of the first sidewall, the bottom of the second sidewall opening exposes at least a portion of the top surface of the first sidewall and the top surface of the first conductive structure; and forming a second sidewall on the sidewall surface within the second sidewall opening.

[0013] Optionally, the method for forming the first conductive structure and the second sidewall opening includes: forming an initial first conductive structure within the first conductive opening; etching the initial first conductive structure until the top surface of the initial first conductive structure is lower than or flush with the top surface of the first sidewall, forming the first conductive structure and an initial second sidewall opening located on the first conductive structure, the initial second sidewall opening exposing the top surface of the first conductive structure; etching the sidewall within the initial second sidewall opening to expose the top surface of the first sidewall, forming the second sidewall opening.

[0014] Optionally, the etching process for the sidewall within the initial second sidewall opening includes a dry etching process.

[0015] Optionally, the method of forming the second sidewall includes: forming a second sidewall membrane on the surface of the second medium layer and the inner wall surface of the second sidewall opening; forming a third medium layer on the surface of the second sidewall membrane, the surface of the third medium layer being higher than the surface of the second sidewall membrane; and planarizing the third medium layer and the second sidewall membrane until the surface of the second medium layer is exposed.

[0016] Optionally, the method for forming the second sidewall includes: forming a second sidewall film on the surface of the second dielectric layer and the inner wall surface of the second sidewall opening; and etching the second sidewall film using an anisotropic etching process until the second dielectric layer and the surface of the first conductive structure are exposed.

[0017] Optionally, the sidewalls of the cover structure protrude relative to the sidewalls of the gate electrode.

[0018] Optionally, the method of forming a plurality of gate electrodes and a cover structure includes: forming a plurality of mutually discrete initial gate electrodes within the first dielectric layer; etching the initial gate electrodes to form a gate electrode and a first sidewall opening within the first dielectric layer, wherein the bottom of the first sidewall opening exposes the top surface of the gate electrode, and the width of the first sidewall opening is greater than the width of the gate electrode; and forming the cover structure within the first sidewall opening.

[0019] Optionally, the covering structure further includes a protective layer located between the main body layer and the top surface of the gate electrode, the protective layer being connected to the first sidewalls on both sides of the main body layer.

[0020] Optionally, the method of forming the covering structure within the first sidewall opening includes: forming a first sidewall membrane on the first medium layer and the inner wall surface of the first sidewall opening; forming a main material layer on the surface of the first sidewall membrane, wherein the surface of the main material layer is higher than the surface of the first sidewall membrane; and planarizing the main material layer and the first sidewall membrane until the surface of the first medium layer is exposed.

[0021] Optionally, the method for forming the cover structure within the first sidewall opening includes: forming a first sidewall film on the surface of the first dielectric layer and the inner wall surface of the first sidewall opening; etching the first sidewall film using an anisotropic etching process until the first sidewall film on the top surface of the gate electrode and the top surface of the first dielectric layer is removed, thereby forming a first sidewall on the sidewall surface within the first sidewall opening; and forming a main layer within the first sidewall opening after forming the first sidewall.

[0022] Optionally, after forming the first sidewall and the second sidewall, the method further includes: forming a second conductive structure that contacts the top surface of the gate electrode within the first dielectric layer and the second dielectric layer, wherein the second conductive structure is located between adjacent first sidewalls and between adjacent second sidewalls, and the second conductive structure penetrates the cover structure.

[0023] Optionally, the method of forming the second conductive structure includes: forming a second conductive opening within a first dielectric layer and a second dielectric layer, the second conductive opening penetrating the cover structure, and the second conductive opening exposing the top surface of the gate electrode and the sidewalls of the first and second sidewalls on both sides of the gate electrode; and forming the second conductive structure within the second conductive opening.

[0024] Optionally, after forming the first sidewall and the second sidewall, the method further includes: forming a third conductive structure within the second dielectric layer, the third conductive structure being located between adjacent second sidewalls, and the third conductive structure being in contact with the top surface of the first conductive structure.

[0025] Optionally, the method of forming the third conductive structure includes: forming a third conductive opening in the second dielectric layer, the third conductive opening exposing the top surface of the first conductive structure and the sidewalls of the second sidewalls on both sides of the first conductive structure; and forming the third conductive structure in the third conductive opening.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor structure formation method provided by the technical solution of the present invention, since the covering structure is formed at least on the top surface of the gate electrode, and the second sidewall is formed on the sidewall surface inside the second sidewall opening, the self-alignment of the etching process can be achieved through the first sidewall and the second sidewall during the subsequent formation of the conductive structure in contact with the top surface of the gate electrode and the formation of the conductive structure in contact with the top surface of the first conductive structure. This improves the reliability of the semiconductor structure, reduces the overlay accuracy requirements of the manufacturing process, and increases the process window of the manufacturing process. Attached Figure Description

[0028] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0029] Figures 4 to 22 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0030] Figure 23 This is a schematic diagram of the structure in a method for forming a semiconductor structure in another embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, existing semiconductor structures have poor reliability, and existing manufacturing processes have small process windows. The reasons for the complexity of the manufacturing process will now be explained with reference to the accompanying drawings.

[0032] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0033] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0034] Please refer to Figure 1 Substrate 100 is provided.

[0035] Please continue to refer to Figure 1 A first dielectric layer 110, a plurality of gate structures 120 located within the first dielectric layer 110, and a cover structure 130 located on the top surface of the gate structures are formed on the substrate 100.

[0036] Please continue to refer to Figure 1 An initial second dielectric layer (not shown) is formed on the first dielectric layer 110 and the cover structure 130; a first conductive opening (not shown) is formed in the first dielectric layer 110 and the initial second dielectric layer, the first conductive opening being located between adjacent gate structures; a first conductive structure 140 is formed in the first conductive opening, the top surface of the first conductive structure 140 being flush with the surface of the first dielectric layer 110, the first conductive structure 140 being located between adjacent gate structures 120; a dielectric material is filled in the first conductive opening on the first conductive structure 140, and a second dielectric layer 150 is formed on the surfaces of the first dielectric layer 110, the cover structure 130, and the first conductive structure 140.

[0037] Please refer to Figure 2 A second conductive mask material layer (not shown) is formed on the surface of the second dielectric layer 150; a photolithography layer (not shown) is formed on the surface of the second conductive mask material layer, the photolithography layer exposing a portion of the second conductive mask material layer on the gate structure 120; using the photolithography layer as a mask, the second conductive mask material layer is etched until a portion of the surface of the second dielectric layer 150 on the gate structure 120 is exposed, forming a second conductive opening mask layer 160; after forming the second conductive opening mask layer 160, the photolithography layer is removed.

[0038] Please continue to refer to Figure 2 Using the second conductive opening mask layer 160 as a mask, the second dielectric layer 150 and the cover structure 130 are etched until the top surface of the gate structure 120 is exposed, forming the second conductive opening 151; after forming the second conductive opening 151, the second conductive opening mask layer 160 is removed.

[0039] Please refer to Figure 3 A second conductive structure 170 is formed within the second conductive opening 151, and the second conductive structure 170 is in contact with the top surface of the gate structure 120.

[0040] However, in the above method, in order to accurately position the second conductive structure 170 so that the second conductive structure 170 and the gate structure 120 can be electrically interconnected, the overlay accuracy requirements between the patterns of the photolithography layer and the gate structure 120, and between the patterns of the second conductive opening mask layer 160 and the gate structure 120 are high. This results in a small process window and high process difficulty in the process of forming the photolithography layer and the second conductive opening mask layer 160.

[0041] Furthermore, in the above method, in order to expose the top surface of the gate structure 120, it is necessary to etch the second dielectric layer 150 and the cover structure 130 to form the second conductive opening 151. That is, the second conductive opening 151 is relatively deep. Therefore, during the etching process of forming the second conductive opening 151, the second dielectric layer 150 on the first conductive structure is easily over-etched, causing the second conductive opening 151 to expose part of the top surface of the first conductive structure 140. This results in contact between the second conductive structure 170 and the first conductive structure 150, and a short circuit between the gate structure 120 and the first conductive structure 150. As a result, the reliability of the semiconductor structure is poor.

[0042] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure and a method for forming the same. Through the first and second sidewalls, self-alignment of the etching process can be achieved during the formation of a conductive structure in contact with the top surface of the gate electrode and during the formation of a conductive structure in contact with the top surface of the first conductive structure. This improves the reliability of the semiconductor structure, reduces the overlay accuracy requirements of the manufacturing process, and increases the process window of the manufacturing process.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 4 to 22 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0045] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A schematic diagram of the three-dimensional structure. Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure along the X1-X2 direction is provided, with substrate 200.

[0046] In this embodiment, the substrate 200 includes a base 201 and a plurality of fins 202 disposed on the base.

[0047] In other embodiments, the substrate is a planar substrate.

[0048] In this embodiment, the substrate 200 is made of silicon.

[0049] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0050] Please continue to refer to Figure 4 and Figure 5 An isolation layer 203 is formed on the substrate 200.

[0051] The isolation layer 203 is located on the surface of the substrate 201, and the isolation layer 203 is also located between adjacent fins 202. Furthermore, the surface of the isolation layer 203 is lower than the top surface of the fin 202.

[0052] The function of the isolation layer 203 is to provide electrical insulation between adjacent fins 202 and between the semiconductor device and the substrate.

[0053] In this embodiment, the material of the isolation layer 203 includes silicon oxide.

[0054] Please refer to Figure 6 , Figure 6 and Figure 5 With the view direction consistent, after the isolation layer 203 is formed, a plurality of mutually independent pseudo gates 216 are formed on the substrate 200. The sidewalls of the pseudo gates 216 have gate sidewalls 215. The pseudo gates 216 span the fin portion 202 and are located on the isolation layer 203.

[0055] The dummy gate 216 is used to locate the gate structure that will be formed subsequently.

[0056] Please continue to refer to Figure 6 After forming several dummy gates 216, source / drain doped regions 204 are formed in the substrate 200 on both sides of the dummy gates 216.

[0057] In this embodiment, the source / drain doped regions 204 are located within the fins 202 on both sides of the dummy gate 216.

[0058] Please refer to Figure 7 , Figure 7 and Figure 6With the view orientation consistent, after forming the source / drain doped region 204, a first dielectric layer 220 is formed on the substrate 200.

[0059] The first dielectric layer 220 provides support for the subsequent formation of the gate structure.

[0060] In this embodiment, the method for forming the first dielectric layer 220 includes: after forming the source / drain doped region 204, forming an initial first dielectric layer (not shown) on the surface of the dummy gate 216, the surface of the gate sidewall 215, the surface of the source / drain doped region 204, the surface of the exposed fin 202, and the surface of the isolation layer 203, wherein the surface of the initial first dielectric layer is higher than the top surface of the dummy gate 215; planarizing the initial first dielectric layer until the top surface of the dummy gate 215 is exposed, thereby forming the first dielectric layer 220.

[0061] The material of the first dielectric layer 220 is a dielectric material, which includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0062] In this embodiment, the material of the first dielectric layer 220 includes silicon oxide.

[0063] Next, a plurality of mutually discrete gate electrodes and a cover structure located on the top surface of the gate electrodes are formed within the first dielectric layer 220. The cover structure includes a main body layer and a first sidewall located on the side wall of the main body layer. For specific steps in forming the gate electrodes and the cover structure, please refer to [link to documentation]. Figures 8 to 11 .

[0064] Please refer to Figure 8 , Figure 8 and Figure 7 With the same viewing direction, a plurality of initial gate structures 210 are formed in the first dielectric layer 220, which are mutually independent.

[0065] In this embodiment, the method for forming the initial gate structure 210 includes: removing the dummy gate 216, forming a plurality of gate openings (not shown) in the first dielectric layer 220, and forming the initial gate structure 210 in the gate openings.

[0066] In this embodiment, the initial gate structure 210 includes: an initial gate dielectric layer 211, an initial work function layer 212 located on the surface of the initial gate dielectric layer 211, and an initial gate electrode 213 located on the surface of the initial work function layer 212.

[0067] Specifically, the initial gate dielectric layer 211 is located on the inner wall surface of the gate opening.

[0068] The initial gate dielectric layer 211 provides material for the subsequent formation of the gate dielectric layer.

[0069] The initial work function layer 212 provides material for the subsequent formation of the work function layer.

[0070] The initial gate electrode 213 provides material for the subsequent formation of the gate electrode.

[0071] Please refer to Figure 9 , Figure 9 and Figure 8 With the view direction consistent, the initial gate structure 210 and gate sidewall 215 are etched to form a gate structure 230, a gate sidewall 234 and a first sidewall opening 235 within the first dielectric layer 220.

[0072] In this embodiment, the etching process of the initial gate structure 210 and the gate sidewall 215 includes at least one of dry etching process and wet etching process.

[0073] In this embodiment, the gate structure 230 includes: a gate dielectric layer 231, a work function layer 232 located on the surface of the gate dielectric layer 231, and a gate electrode 233 located on the surface of the work function layer 232.

[0074] The material of the gate dielectric layer 231 includes silicon oxide or a high-K dielectric material, wherein the high-K dielectric material refers to a material with a dielectric constant greater than 3.9.

[0075] The material of the work function layer 232 includes one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.

[0076] The material of the gate electrode 233 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0077] The first sidewall opening 235 provides space for the subsequent formation of the covering structure.

[0078] In this embodiment, the first sidewall opening 235 exposes at least the top surface of the gate electrode 233 and the top surface of the work function layer 232.

[0079] In other embodiments, the gate structure includes a gate dielectric layer and a gate electrode, but does not include a work function layer, and the first sidewall opening exposes at least the top surface of the gate electrode.

[0080] Preferably, the bottom of the first sidewall opening 235 also exposes the top surface of the grid dielectric layer 231 to further increase the width of the subsequently formed overlay structure.

[0081] Preferably, the bottom of the first sidewall opening 235 also exposes the top surface of the gate sidewall 234. Thus, the width W1 of the first sidewall opening 235 is greater than the width W2 of the gate structure 230, and the width W1 of the first sidewall opening 235 is greater than the width W3 of the gate electrode 233.

[0082] Next, a covering structure is formed within the first side wall opening 235. For details on the steps of forming the covering structure within the first side wall opening 235, please refer to [link to relevant documentation]. Figures 10 to 11 .

[0083] Please refer to Figure 10 , Figure 10 and Figure 9 With the view direction consistent, a first sidewall membrane 241 is formed on the surface of the first medium layer 220 and the inner wall surface of the first sidewall opening 235; a main material layer 242 is formed on the surface of the first sidewall membrane 241, and the surface of the main material layer 242 is higher than the surface of the first sidewall membrane 241.

[0084] In this embodiment, the first sidewall membrane 241 provides material for the subsequent formation of the first sidewall and the protective layer, and the main material layer 242 provides material for the subsequent formation of the main layer.

[0085] In this embodiment, the process for forming the first sidewall membrane 241 includes atomic layer deposition (ALD).

[0086] The atomic layer deposition process produces materials with high density, resulting in high density of the first sidewall film 241. Consequently, the high density of the subsequently formed first sidewall reduces wear on the first sidewall during subsequent etching processes, such as forming the first conductive opening, the second sidewall opening, the second conductive opening, and the third conductive opening, further ensuring the alignment accuracy of self-alignment during the etching process.

[0087] In other embodiments, the process for forming the first sidewall membrane 241 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD), etc.

[0088] In this embodiment, the process for forming the main material layer 242 includes chemical vapor deposition or physical vapor deposition, etc.

[0089] Please refer to Figure 11 , Figure 11 and Figure 10 With the view direction consistent, the main material layer 242 and the first sidewall membrane 241 are flattened until the surface of the first medium layer 220 is exposed to form a covering structure 240.

[0090] The covering structure 240 includes: a main layer 244, and a first sidewall 243 located on the side wall of the main layer 244.

[0091] The overlay structure 240 is located at least on the top surface of the gate electrode 233 and the work function layer 232. Thus, through the first sidewall 243 and the subsequently formed second sidewall, the position of the second conductive opening can be located during the subsequent etching process to form the second conductive opening, achieving self-alignment of the etching.

[0092] In other embodiments, the gate structure includes a gate dielectric layer and a gate electrode, while the gate structure does not include a work function layer, and the overlay structure is located at least on the top surface of the gate electrode.

[0093] Preferably, the first sidewall 243 in the cover structure 240 is located on the top surface of the gate dielectric layer 231. Therefore, during the subsequent etching process to form the second conductive opening, not only can the position of the second conductive opening be located, but the size of the second conductive opening can also be further enlarged, thereby increasing the process window size for both the etching process for forming the second conductive opening and the process for filling the second conductive structural material.

[0094] Meanwhile, since the first sidewall 243 is located on the top surface of the gate dielectric layer 231, the sidewall of the cover structure 240 protrudes relative to the sidewalls of the gate electrode 233 and the work function layer 232. That is, the sidewall surface of the first sidewall 243 that does not contact the main layer 244 protrudes relative to the sidewalls of the gate electrode 233 and the work function layer 232. Therefore, the first sidewall 243 also enables self-alignment of the etching process during the subsequent etching process to form the first conductive opening, accurately defining the position of the first conductive structure. This further reduces the overlay accuracy requirements of the manufacturing process, increases the process window of the manufacturing process, and improves the reliability of the semiconductor structure.

[0095] In other embodiments, the gate structure includes a gate dielectric layer and a gate electrode, and the gate structure does not include a work function layer. The sidewalls of the cover structure protrude relative to the sidewalls of the gate electrode. Therefore, during the subsequent formation of the first conductive structure, the cover structure can also achieve self-alignment of the etching process during the subsequent etching process to form the first conductive opening, so as to accurately define the position of the first conductive structure. This further reduces the overlay accuracy requirements of the manufacturing process, increases the process window of the manufacturing process, and improves the reliability of the semiconductor structure.

[0096] Preferably, the first sidewall 243 is also located on the top surface of the gate sidewall 234 to increase the thickness of the first sidewall 243. This better avoids the first sidewall 243 being damaged, further reducing the risk of short circuits between the subsequently formed first conductive structure and the gate structure 230, as well as the risk of short circuits between the subsequently formed second conductive structure and the first conductive structure, thereby further improving the reliability of the semiconductor structure.

[0097] In this embodiment, the material of the first sidewall 243 is different from the material of the first dielectric layer 220, and the material of the first sidewall 243 is different from the material of the subsequently formed second dielectric layer. Therefore, during the subsequent etching process to form the second conductive opening, the etching process has a smaller etching rate for the first sidewall 243, while having a larger etching rate for the first dielectric layer 220 and the second dielectric layer, so as to achieve self-alignment of etching in forming the second conductive opening.

[0098] Similarly, when the sidewall of the cover structure 240 protrudes relative to the sidewall of the gate electrode 233 and the work function layer 232, that is, when the etching self-alignment for forming the first conductive opening is achieved through the first sidewall 243, the material of the first sidewall 243 is different from the material of the first dielectric layer 220, and the material of the first sidewall 243 is different from the material of the subsequently formed second dielectric layer. This enables the etching process for forming the first conductive opening to have a smaller etching rate for the first sidewall 243, while having a larger etching rate for the first dielectric layer 220 and the second dielectric layer, so as to achieve etching self-alignment for forming the first conductive opening.

[0099] In this embodiment, the material of the first sidewall 243 includes silicon nitride.

[0100] In this embodiment, the material of the main body layer 244 includes silicon oxide.

[0101] In this embodiment, the covering structure 240 further includes a protective layer 245 located between the main body layer 244 and the top surface of the gate electrode 233, the protective layer 245 being connected to the first sidewalls 243 on both sides of the main body layer 244.

[0102] The protective layer 245 serves to further enhance the protection of the gate electrode 233 during the subsequent formation of the first conductive opening, thereby reducing the risk of short circuit between the first conductive structure and the gate structure 230 and improving the reliability of the semiconductor structure.

[0103] The material of the protective layer 245 is the same as that of the first sidewall 243.

[0104] In another embodiment, please Figure 9 Based on reference Figure 23 The covering structure 340 includes a main layer 341 and a first sidewall 342 located on the side wall of the main layer 341. The covering structure 340 does not include a protective layer.

[0105] Since the covering structure 340 does not include a protective layer, the loss and other effects caused to the first sidewall 342 during the subsequent etching process to remove the protective layer are further reduced, thus improving the accuracy of etching self-alignment when forming the second conductive opening and more accurately defining the position of the second conductive structure.

[0106] Specifically, in another embodiment, the method for forming the cover structure 340 within the first sidewall opening 235 includes: forming a first sidewall film (not shown) on the first dielectric layer 220 and the inner wall surface of the first sidewall opening 235; etching the first sidewall film using an anisotropic etching process until the first sidewall film on the top surface of the gate electrode 233 and the top surface of the first dielectric layer 220 is removed, forming a first sidewall 341 on the sidewall surface within the first sidewall opening 235; and forming a main layer 342 within the first sidewall opening 235 after forming the first sidewall 341. Specifically, the anisotropic etching process includes a plasma etching process.

[0107] In this embodiment, the process of planarizing the main material layer 242 and the first sidewall membrane 241 includes a chemical mechanical polishing process.

[0108] Please refer to Figure 12 , Figure 12 and Figure 11 With the view orientation consistent, a second dielectric layer 250 is formed on the first dielectric layer 220 and the cover structure 240.

[0109] The material of the second dielectric layer 250 is a dielectric material, which includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0110] In this embodiment, the material of the second dielectric layer 250 is the same as the material of the first dielectric layer 220. Specifically, the material of the second dielectric layer 250 includes silicon oxide.

[0111] In other embodiments, the first dielectric layer and the second dielectric layer are made of different materials.

[0112] In this embodiment, the process for forming the second dielectric layer 250 includes at least one of chemical vapor deposition and physical vapor deposition.

[0113] Please continue to refer to Figure 12 A first conductive opening 251 is formed in the first dielectric layer 220 and the second dielectric layer 250. The first conductive opening 251 exposes the surface of the substrate 200 between adjacent gate electrodes 233 and the sidewall surface of the cover structure 240.

[0114] Specifically, the first conductive opening 251 provides space for the subsequent formation of the first conductive structure, and the first conductive opening 251 exposes the surface of the source / drain doped region 204 and the sidewall of the first sidewall 243 in the cover structure 240.

[0115] Specifically, the method for forming the first conductive opening 251 includes: forming a first conductive opening mask layer (not shown) on the surface of the second dielectric layer 250, wherein the first conductive opening mask layer exposes a portion of the surface of the second dielectric layer 250; using the first conductive opening mask layer as a mask, etching the first dielectric layer 220 and the second dielectric layer 250 until the surface of the source / drain doped region 204 is exposed.

[0116] In this embodiment, using the first conductive opening mask layer as a mask, during the etching of the first dielectric layer 220 and the second dielectric layer 250, the first sidewall 243 enables self-alignment of etching during the etching process of forming the first conductive opening 251. Therefore, the pattern accuracy requirements of the first conductive opening mask layer and the process requirements for etching the first dielectric layer 220 and the second dielectric layer 250 are reduced, thereby increasing the process window, reducing the process difficulty, and improving the reliability of the semiconductor structure.

[0117] In this embodiment, the etching process of the first dielectric layer 220 and the second dielectric layer 250 includes a dry etching process.

[0118] In other embodiments, the process of etching the first dielectric layer and the second dielectric layer includes a wet etching process.

[0119] Next, a first conductive structure is formed within the first conductive opening 251. The first conductive structure has a second sidewall opening. The first conductive structure is in contact with the substrate 200 between adjacent gate electrodes 233. The first conductive structure is located between adjacent cover structures 240. The top surface of the first conductive structure is lower than or flush with the top surface of the first sidewall 243. The bottom of the second sidewall opening exposes at least a portion of the top surface of the first sidewall 243 and the top surface of the first conductive structure. For specific steps on forming the first conductive structure and the second sidewall opening, please refer to [link to documentation]. Figures 13 to 15 .

[0120] Please refer to Figure 13 , Figure 13 and Figure 12 With the view orientation consistent, an initial first conductive structure 260 is formed within the first conductive opening 251.

[0121] In this embodiment, the initial first conductive structure 260 includes: an initial first buffer layer (not shown) and an initial first conductive layer (not shown) located on the surface of the initial first buffer layer. The initial first buffer layer provides material for the subsequent formation of the first buffer layer, and the initial first conductive layer provides material for the subsequent formation of the first conductive layer.

[0122] In this embodiment, the method for forming the initial first conductive structure 260 includes: depositing a first conductive structure material layer (not shown) inside the first conductive opening 251 and on the surface of the second dielectric layer 250, wherein the surface of the first conductive structure material layer is higher than the surface of the second dielectric layer 250; planarizing the first conductive structure material layer until the surface of the second dielectric layer 250 is exposed.

[0123] In this embodiment, the process for forming the first conductive structural material layer includes: physical vapor deposition, chemical vapor deposition, or atomic layer deposition. Preferably, chemical vapor deposition is used to form the first conductive structural material layer.

[0124] In this embodiment, the process of planarizing the first conductive structural material layer includes a chemical mechanical polishing process.

[0125] Please refer to Figure 14 , Figure 14 and Figure 13 With the view direction consistent, the initial first conductive structure 260 is etched until the top surface of the initial first conductive structure 260 is lower than or flush with the top surface of the first sidewall 243, forming the first conductive structure 261 and the initial second sidewall opening 262 located on the first conductive structure 261, the initial second sidewall opening 262 exposing the top surface of the first conductive structure 261.

[0126] The first conductive structure 261 is in contact with the substrate 200 between adjacent gate electrodes 233. The first conductive structure 261 is located between adjacent cover structures 240. The top surface of the first conductive structure 261 is lower than or flush with the top surface of the first sidewall 243.

[0127] In this embodiment, the first conductive structure 261 is in contact with the source / drain doped region 204 between the adjacent gate electrode 233.

[0128] In this embodiment, the first conductive structure 261 includes: a first buffer layer (not shown) and a first conductive layer (not shown) located on the surface of the first buffer layer.

[0129] The first buffer layer serves two purposes: firstly, it increases the adhesion of the first conductive layer, thereby improving the performance of the first conductive structure 261; secondly, it blocks atoms or ions in the first conductive layer from diffusing into the first dielectric layer 220 and the second dielectric layer 250, thus preventing leakage and improving the performance of the semiconductor structure.

[0130] The material of the first buffer layer includes: titanium silicide, tantalum silicide, or tungsten nitride.

[0131] The material of the first conductive layer includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0132] Please refer to Figure 15 , Figure 15 and Figure 14 The view direction is consistent with that of the initial second side wall opening 262 (e.g. Figure 14 The sidewalls inside (as shown) are etched to expose the top surface of the first sidewall 243, forming a second sidewall opening 263. The bottom of the second sidewall opening 263 exposes at least a portion of the top surface of the first sidewall 243 and the top surface of the first conductive structure 261.

[0133] By making an initial second sidewall opening 262 (as shown) Figure 14 The sidewall inside (as shown) was etched to enlarge the width of the initial second sidewall opening 262, thus realizing the formation of the second sidewall opening 263.

[0134] In this embodiment, the second sidewall opening 263 exposes a portion of the top surface of the first sidewall 243. Therefore, it is less likely that a second sidewall will be formed on the top surface of the gate electrode 233, preventing the second conductive opening from being occupied by the second sidewall. Consequently, with accurate positioning, the second conductive opening has a larger width. This facilitates filling the second conductive structure with material and ensures that the dimensions of the second conductive structure meet design requirements, reducing the impact on the performance of the second conductive structure caused by the second sidewall occupying space in the second conductive opening.

[0135] In other embodiments, the second sidewall opening exposes the entire top surface of the first sidewall 243, which helps to further ensure that the second sidewall is subsequently formed on the first sidewall 243, so that the second sidewall is connected to the first sidewall 243.

[0136] In this embodiment, the etching process for the sidewall within the initial second sidewall opening 262 includes a dry etching process.

[0137] Specifically, the parameters of the dry etching process include: the gases used are NF3 and NH3, wherein the flow rate of NF3 is in the range of 5 standard milliliters / min to 15 standard milliliters / min, and the flow rate of NH3 is in the range of 15 standard milliliters / min to 45 standard milliliters / min; the pressure range is 5 Torr to 10 Torr; and the power range is 70 watts to 90 watts. Preferably, the power is 80 watts. By using process parameters within the aforementioned range, the etching rate of the dry etching process within the initial second sidewall opening 262 is slower. Therefore, the etching accuracy of the dry etching process is improved, resulting in high accuracy of the stopping position of the etching process. Consequently, a second sidewall opening 263 with better morphology and more accurate sidewall surface position can be formed.

[0138] Next, a second sidewall is formed on the sidewall surface within the opening 263 of the second sidewall. For the specific steps of forming the second sidewall, please refer to [link / reference needed]. Figures 16 to 17 .

[0139] Please refer to Figure 16 , Figure 16 and Figure 15 With the view direction consistent, a second sidewall membrane 264 is formed on the surface of the second medium layer 250 and the inner wall surface of the second sidewall opening 263; a third medium layer 265 is formed on the surface of the second sidewall membrane 264, and the surface of the third medium layer 265 is higher than the surface of the second sidewall membrane 264.

[0140] In this embodiment, the second sidewall membrane 265 provides material for the subsequent formation of the second sidewall.

[0141] In this embodiment, the process for forming the second sidewall membrane 265 includes an atomic layer deposition process.

[0142] The atomic layer deposition process produces materials with high density, resulting in high density of the second sidewall film 265. Consequently, the high density of the subsequently formed second sidewall reduces wear on the second sidewall during subsequent etching processes such as forming the second and third conductive openings, further ensuring the alignment accuracy of self-alignment during the etching process.

[0143] In other embodiments, the process for forming the second sidewall membrane 265 includes chemical vapor deposition or physical vapor deposition, etc.

[0144] The material of the third dielectric layer 265 is a dielectric material, which includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0145] In this embodiment, the material of the third dielectric layer 265 is the same as that of the second dielectric layer 250. Specifically, the material of the third dielectric layer 265 includes silicon oxide.

[0146] In other embodiments, the third dielectric layer is made of a different material than the second dielectric layer.

[0147] In other embodiments, the third dielectric layer is made of a different material than the first dielectric layer.

[0148] In this embodiment, the process for forming the third dielectric layer 265 includes at least one of chemical vapor deposition and physical vapor deposition.

[0149] Please refer to Figure 17 , Figure 17 and Figure 16 With the view direction consistent, flatten the third medium layer 265 and the second sidewall membrane 264 until the surface of the second medium layer 250 is exposed, in the second sidewall opening 263 (e.g. Figure 15 The sidewall surface inside (as shown) forms a second sidewall 266.

[0150] Since the cover structure 240 is formed on the top surface of the gate electrode 233, and the second sidewall 266 is formed on the sidewall surface inside the second sidewall opening 263, the etching process can be self-aligned through the first sidewall and the second sidewall during the subsequent formation of the second conductive structure and the formation of the third conductive structure. This improves the reliability of the semiconductor structure, reduces the overlay accuracy requirements of the manufacturing process, and increases the process window of the manufacturing process.

[0151] Specifically, on the one hand, since the cover structure 240 includes a main layer 244 and a first sidewall 243 located on the sidewall of the main layer 244, and on the other hand, since the second sidewall 266 is located on the first sidewall 243, the first sidewall 243 and the area above the gate electrode 233 and the work function layer 232 are separated by the second sidewall 243 and the area above the first conductive structure 261. Therefore, during the subsequent formation of the second conductive structure and the third conductive structure, the positions of the second and third conductive openings can be accurately defined through a self-aligned etching process, reducing the risk of the second and third conductive openings becoming connected. Thus, the requirements for overlay precision in the manufacturing process are low, the process window is large, and the positions of the second and third conductive structures are accurate, reducing the risk of the second conductive structure not contacting the gate electrode 233 or the third conductive structure not contacting the first conductive structure 261, and minimizing the risk of short circuits between the second and third conductive structures, resulting in high reliability of the semiconductor structure.

[0152] In other embodiments, the gate structure includes a gate dielectric layer and a gate electrode, but does not include a work function layer. Therefore, the region above the gate electrode and the region above the first conductive structure are separated by the first and second sidewalls. This improves the reliability of the semiconductor structure, reduces the overlay accuracy requirements of the manufacturing process, and increases the process window of the manufacturing process.

[0153] In this embodiment, the process of planarizing the third dielectric layer 265 and the second sidewall membrane 264 includes a chemical mechanical polishing process.

[0154] In this embodiment, the material of the second sidewall 266 is the same as the material of the first sidewall 243. Specifically, the material of the second sidewall 266 includes silicon nitride.

[0155] Preferably, the sidewall of the second sidewall 266 protrudes relative to the sidewall of the cover structure 240, and the second sidewall 266 is also located on the top surface of a portion of the first conductive structure 261. Therefore, on the one hand, forming a thicker second sidewall 266 better avoids wear and tear on the second sidewall 266, further reducing the risk of short circuit between the subsequently formed second and third conductive structures. On the other hand, it further reduces the risk of the third conductive structure not making contact with the first conductive structure 261. Thus, the reliability of the semiconductor structure is further improved.

[0156] In this embodiment, while forming the second sidewall 266, a second protective layer 267 is formed on the top surface of the first conductive structure 261. The second protective layer 267 connects the sidewalls 266 on both sides of the first conductive structure 261. The material of the second protective layer 267 is the same as the material of the second sidewall 266.

[0157] The function of the second protective layer 267 is to further enhance the protection capability of the first conductive structure 261 and improve the reliability of the semiconductor structure during the subsequent formation of the second conductive opening.

[0158] In another embodiment, the method for forming the second sidewall includes: forming a second sidewall film on the surface of the second dielectric layer and the inner wall surface of the second sidewall opening; and etching the second sidewall film using an anisotropic etching process until the second dielectric layer and the surface of the first conductive structure are exposed. The anisotropic etching process includes plasma etching. Because the second sidewall film is etched using an anisotropic etching process to expose the surface of the first conductive structure before forming the third dielectric layer, the losses and other effects on the second sidewall caused by removing the second sidewall film from the surface of the first conductive structure during the subsequent etching process for forming the third conductive opening are further reduced. This improves the etching self-alignment accuracy when forming the third conductive opening, allowing for a more accurate definition of the position of the third conductive structure.

[0159] Next, within the first dielectric layer 220 and the second dielectric layer 250, a second conductive structure is formed that contacts the top surface of the gate electrode 233. The second conductive structure is located between adjacent first sidewalls 243 and adjacent second sidewalls 266, and the second conductive structure penetrates the cover structure 240.

[0160] In this embodiment, while forming the second conductive structure, a third conductive structure is formed within the second dielectric layer 220. The third conductive structure is located between adjacent second sidewalls 266 and is in contact with the top surface of the first conductive structure 261.

[0161] In other embodiments, a second conductive structure and a third conductive structure are formed, respectively.

[0162] In this embodiment, please refer to the specific steps for forming the second and third conductive structures. Figures 18 to 22 .

[0163] Please refer to Figures 18 to 20 , Figure 18 yes Figure 19 and Figure 20 Top view, Figure 19 yes Figure 18 A schematic diagram of the cross-sectional structure along the direction X1-X2. Figure 20 yes Figure 18 A cross-sectional structural diagram along direction X3-X4 shows that second conductive openings 271 are formed within the first dielectric layer 220 and the second dielectric layer 250, respectively. The second conductive openings 271 penetrate the covering structure 240 and expose the top surface of the gate electrode 233 and the sidewalls of the first sidewall 243 and the second sidewall 266 on both sides of the gate electrode 233. A third conductive opening 272 is formed within the second dielectric layer 250, exposing the top surface of the first conductive structure 261 and the sidewalls of the second sidewall 266 on both sides of the first conductive structure 261.

[0164] Specifically, the third conductive opening 272 is located in the third dielectric layer 265 within the second dielectric layer 260.

[0165] In this embodiment, the method for forming the second conductive opening 271 and the third conductive opening 272 includes: forming a fourth dielectric layer 280 on the surface of the second dielectric layer 250, the top surface of the second sidewall 266, and the surface of the third dielectric layer 265; forming a conductive opening mask layer (not shown) on the surface of the fourth dielectric layer 280, wherein the conductive opening mask layer has a second mask opening and a third mask opening, the second mask opening exposing a portion of the surface of the fourth dielectric layer 280 on the gate electrode 233, and the third mask opening exposing a portion of the surface of the fourth dielectric layer 280 on the first conductive structure 261; using the conductive opening mask layer as a mask, etching the fourth dielectric layer 280, the third dielectric layer 265, the second dielectric layer 250, the first dielectric layer 220, the overlay structure 240, and the second protective layer 267 (e.g., ...). Figure 17 As shown), until a second conductive opening 271 is formed that exposes the top surface of the gate electrode 233, and a third conductive opening 272 that exposes the top surface of the first conductive structure 261.

[0166] The etching process for the fourth dielectric layer 280, the third dielectric layer 265, the second dielectric layer 250, the first dielectric layer 220, the cover structure 240, and the second protective layer 267 includes at least one of dry etching process and wet etching process.

[0167] In other embodiments, the second conductive opening and the third conductive opening are formed by different mask layers, respectively.

[0168] In this embodiment, after the second conductive opening 271 and the third conductive opening 272 are formed, the conductive opening mask layer is removed.

[0169] Please refer to Figure 21 and Figure 22 , Figure 21 and Figure 19 The view orientation is consistent. Figure 22 and Figure 20 With the view orientation consistent, a second conductive structure 281 is formed in the second conductive opening 271, and a third conductive structure 282 is formed in the third conductive opening 272.

[0170] The second conductive structure 281 is in contact with the top surface of the gate electrode 233. The second conductive structure 281 is also located between adjacent first sidewalls 243 and adjacent second sidewalls 266, and the second conductive structure 281 penetrates the cover structure 240.

[0171] The material of the second conductive structure 281 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0172] In this embodiment, the second conductive structure 281 is a conductive plug.

[0173] The third conductive structure 282 is in contact with the top surface of the first conductive structure 261, and the third conductive structure 282 is located between adjacent second sidewalls 266.

[0174] The material of the third conductive structure 282 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0175] In this embodiment, the third conductive structure 282 is a conductive plug.

[0176] In this embodiment, the method for forming the second conductive structure 281 and the third conductive structure 282 includes: forming a conductive structural material layer (not shown) in the second conductive opening 271, the third conductive opening 272, and on the surface of the fourth dielectric layer 280, wherein the surface of the conductive structural material layer is higher than the surface of the fourth dielectric layer 280; and plateauing the conductive structural material layer until the surface of the fourth dielectric layer 280 is exposed.

[0177] The process for forming the conductive structural material layer includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Preferably, CVD is used to form the conductive structural material layer.

[0178] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [further details]. Figure 21 and Figure 22The system includes: a substrate 200, which includes a base 201 and a plurality of fins 202 disposed on the base 201; an isolation layer 203 disposed on the substrate 200, the isolation layer 203 also being located between adjacent fins 202, the surface of the isolation layer 203 being lower than the top surface of the fins 202; a first dielectric layer 220 disposed on the surface of the isolation layer 203 and the exposed surfaces of the fins 202; a plurality of gate electrodes 233 disposed within the first dielectric layer 220, the surface of the gate electrodes 233 being lower than the surface of the first dielectric layer 220, the gate electrodes 233 also being located on the isolation layer 203, the gate electrodes 233 spanning the surface of the fins 202, and the fins 202 between adjacent gate electrodes 233 having source / drain doped regions 204; and a cover structure 240 at least located on the top surface of the gate electrodes 233, the cover structure 240 including a main layer 244 and a cover structure 240 disposed on the main layer 201. The first sidewall 243 of the 44 sidewalls; the top surface of the first conductive structure 261 is higher than the top surface of the gate electrode 233 and located between adjacent cover structures 240, the top surface of the first conductive structure 261 is lower than or flush with the top surface of the first sidewall 243, and the first conductive structure 261 is in contact with the surface of the source / drain doped region 204; a second dielectric layer 250 is located on the first dielectric layer 220 and the cover structure 240; a second sidewall 266 is located within the second dielectric layer 250, and the second sidewall 266 is also located on the top surface of the first sidewall 243; a second conductive structure 281 is located within the first dielectric layer 220 and the second dielectric layer 250, the second conductive structure 281 is in contact with the top surface of the gate electrode 233, the second conductive structure 281 is located between adjacent first sidewalls 243 and between adjacent second sidewalls 266, and the second conductive structure 281 penetrates the cover structure 240.

[0179] In this embodiment, the substrate 200 is made of silicon.

[0180] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0181] The material of the first dielectric layer 220 is a dielectric material, which includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0182] In this embodiment, the material of the first dielectric layer 220 includes silicon oxide.

[0183] The material of the second dielectric layer 250 is a dielectric material, which includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0184] In this embodiment, the material of the second dielectric layer 250 is the same as the material of the first dielectric layer 220. Specifically, the material of the second dielectric layer 250 includes silicon oxide.

[0185] In other embodiments, the first dielectric layer and the second dielectric layer are made of different materials.

[0186] In this embodiment, the material of the first sidewall 243 is different from the materials of the first dielectric layer 220 and the second dielectric layer 250.

[0187] Specifically, the material of the first sidewall 243 includes silicon nitride.

[0188] In this embodiment, the material of the main body layer 244 includes silicon oxide.

[0189] In this embodiment, the covering structure 240 further includes a protective layer 245 located between the main body layer 244 and the top surface of the gate electrode 233, the protective layer 245 connecting the first sidewalls 243 on both sides of the main body layer 244. The material of the protective layer 245 is the same as the material of the first sidewalls 243, and the second conductive structure 281 penetrates the protective layer 245.

[0190] In another embodiment, the covering structure 340 (e.g.) Figure 23 As shown) includes the main body layer 341 (as shown) Figure 23 (as shown) and the first sidewall 342 located on the side wall of the main layer 341 (as shown) Figure 23 As shown in the figure, the covering structure 340 does not include a protective layer.

[0191] In this embodiment, the material of the second sidewall 266 is the same as the material of the first sidewall 243. Specifically, the material of the second sidewall 266 includes silicon nitride.

[0192] Preferably, the sidewall of the second sidewall 266 protrudes relative to the sidewall of the covering structure 240, and the second sidewall 266 is also located on the top surface of part of the first conductive structure 261.

[0193] In this embodiment, the first conductive structure 261 includes: a first buffer layer (not shown) and a first conductive layer (not shown) located on the surface of the first buffer layer.

[0194] The material of the first buffer layer includes: titanium silicide, tantalum silicide, or tungsten nitride.

[0195] The material of the first conductive layer includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0196] The material of the isolation layer 203 includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0197] In this embodiment, the material of the isolation layer 203 includes silicon oxide.

[0198] In this embodiment, the semiconductor structure further includes a gate dielectric layer 231 and a work function layer 232. The gate dielectric layer 231, the work function layer 232, and the gate electrode 233 constitute a gate structure 230.

[0199] Specifically, the gate structure 230 includes: a gate dielectric layer 231, a work function layer 232 located on the surface of the gate dielectric layer 231, and a gate electrode 233 located on the surface of the work function layer 232.

[0200] The material of the gate dielectric layer 231 includes silicon oxide or a high-K dielectric material, wherein the high-K dielectric material refers to a material with a dielectric constant greater than 3.9.

[0201] The material of the work function layer 232 includes one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.

[0202] The material of the gate electrode 233 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0203] In this embodiment, the covering structure 240 is also located at least on the top surface of the work function layer 232.

[0204] Preferably, the first sidewall 243 in the cover structure 240 is located on the top surface of the grid dielectric layer 231, and the sidewall of the cover structure 240 protrudes relative to the sidewall of the work function layer 232.

[0205] In this embodiment, the sidewall of the gate electrode 233 has a gate sidewall 234, and at least a portion of the first sidewall 243 is located on the top surface of the gate sidewall 234.

[0206] In other embodiments, the gate structure includes a gate dielectric layer and a gate electrode, but does not include a work function layer, and the overlay structure is located at least on the top surface of the gate electrode. Preferably, the sidewalls of the overlay structure protrude relative to the sidewalls of the gate electrode.

[0207] The material of the second conductive structure 281 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0208] In this embodiment, the second conductive structure 281 is a conductive plug.

[0209] In this embodiment, the semiconductor structure further includes a third conductive structure 282 located within the second dielectric layer 250, the third conductive structure 282 being located between adjacent second sidewalls 266, and the third conductive structure 282 being in contact with the top surface of the first conductive structure 261.

[0210] The material of the third conductive structure 282 includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0211] In this embodiment, the third conductive structure 282 is a conductive plug.

[0212] In this embodiment, the semiconductor structure further includes a third dielectric layer 265 located within the second dielectric layer 250 on the first conductive structure 261, the second sidewall 266 being located between the second dielectric layer 250 and the third dielectric layer 265, and the third dielectric layer 265 being located on the sidewall surface of the third conductive structure 282.

[0213] The material of the third dielectric layer 265 is a dielectric material, which includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

[0214] In this embodiment, the material of the third dielectric layer 265 is the same as that of the second dielectric layer 250. Specifically, the material of the third dielectric layer 265 includes silicon oxide.

[0215] In other embodiments, the third dielectric layer and the second dielectric layer are made of different materials.

[0216] In other embodiments, the third dielectric layer and the first dielectric layer are made of different materials.

[0217] In this embodiment, the semiconductor structure further includes: a second protective layer 267 located on the top surface of the first conductive structure 261, the second protective layer 267 connecting the sidewalls 266 on both sides of the first conductive structure 261, the second protective layer 267 also located between the third dielectric layer 265 and the first conductive structure 261, and the material of the second protective layer 267 being the same as the material of the second sidewall 266.

[0218] In yet another embodiment, the semiconductor structure does not include a second protective layer.

[0219] In this embodiment, the semiconductor structure further includes a fourth dielectric layer 280 located on the surface of the second dielectric layer 250, the top surface of the second sidewall 266, and the surface of the third dielectric layer 265. The fourth dielectric layer 280 is also located on the sidewall surfaces of the second conductive structure 281 and the third conductive structure 282.

[0220] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a base and a plurality of fins disposed on the base and separated from each other; An isolation layer is located on the substrate, and the isolation layer is also located between adjacent fins, with the surface of the isolation layer being lower than the top surface of the fin; A first dielectric layer located on the surface of the isolation layer and the exposed surface of the fin; A plurality of gate electrodes are located separately within the first dielectric layer, the surface of the gate electrode is lower than the surface of the dielectric layer, the gate electrode is also located on the isolation layer, the gate electrode spans the surface of the fin, and the fin between adjacent gate electrodes has source and drain doped regions; A covering structure located at least on the top surface of the gate electrode, the covering structure including a main body layer and a first sidewall located on the sidewall of the main body layer; A first conductive opening located within the first dielectric layer, a first conductive structure located within the first conductive opening, the top surface of the first conductive structure being higher than the top surface of the gate electrode and located between adjacent cover structures, the top surface of the first conductive structure being lower than or flush with the top surface of the first sidewall, and the first conductive structure being in contact with the surface of the source / drain doped region. The sidewall of the first conductive structure is in contact with the sidewall of the first sidewall; A second dielectric layer located on the first dielectric layer and the overlay structure; The second sidewall is located within the second medium layer, and the second sidewall is also located on the top surface of the first sidewall; A second conductive opening is located within the first dielectric layer and the second dielectric layer; a second conductive structure is located within the second conductive opening; the second conductive structure is in contact with the top surface of the gate electrode; the second conductive structure is located between adjacent first sidewalls and between adjacent second sidewalls; and the second conductive structure penetrates the cover structure; the sidewall of the second conductive structure is in contact with the first sidewall and the second sidewall. The etching process for forming the first conductive opening has a lower etching rate for the first sidewall but a higher etching rate for the first dielectric layer and the second dielectric layer; the etching process for forming the second conductive opening has a lower etching rate for the second sidewall and the first sidewall but a higher etching rate for the main body layer and the second dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The sidewall of the gate electrode has a gate sidewall, and at least a portion of the first sidewall is located on the top surface of the gate sidewall.

3. The semiconductor structure as described in claim 1, characterized in that, The sidewall of the cover structure protrudes relative to the sidewall of the gate electrode.

4. The semiconductor structure as described in claim 1, characterized in that, The sidewall of the second sidewall protrudes relative to the sidewall of the covering structure, and the second sidewall is also located on the top surface of the first conductive structure portion.

5. The semiconductor structure as described in claim 1, characterized in that, The covering structure further includes: a protective layer located between the main body layer and the top surface of the gate electrode, the protective layer being connected to the first sidewalls on both sides of the main body layer, and the second conductive structure penetrating the protective layer.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: A third conductive structure is located within the second dielectric layer, between adjacent second sidewalls, and in contact with the top surface of the first conductive structure.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3; the material of the second dielectric layer includes one or more combinations of SiO2, SiN, SiOCH, and Al2O3.

8. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first dielectric layer is formed on the substrate; A plurality of gate electrodes, which are mutually independent, and a cover structure at least located on the top surface of the gate electrodes are formed within the first dielectric layer. The cover structure includes a main layer and a first sidewall located on the side wall of the main layer. A second dielectric layer is formed on the first dielectric layer and the cover structure; A first conductive opening is formed within the first dielectric layer and the second dielectric layer, the first conductive opening exposing the substrate surface between adjacent gate electrodes and the sidewall surface of the cover structure; A first conductive structure is formed within the first conductive opening, and the first conductive structure has a second sidewall opening. The first conductive structure is in contact with the substrate between adjacent gate electrodes. The first conductive structure is located between adjacent cover structures. The top surface of the first conductive structure is lower than or flush with the top surface of the first sidewall. The bottom of the second sidewall opening exposes at least a portion of the top surface of the first sidewall and the top surface of the first conductive structure. The sidewall of the first conductive structure is in contact with the sidewall of the first sidewall. A second side wall is formed on the side wall surface inside the opening in the second side wall. A second conductive opening is formed within the first and second dielectric layers, penetrating the cover structure and exposing the top surface of the gate electrode and the sidewalls of the first and second sidewalls on both sides of the gate electrode. A second conductive structure is formed within the second conductive opening. The second conductive structure is located between adjacent first sidewalls and adjacent second sidewalls, and penetrates the cover structure. The second conductive structure is located between adjacent first sidewalls and adjacent second sidewalls and contacts the top surface of the gate electrode. The sidewalls of the second conductive structure contact the first and second sidewalls. The etching process for forming the first conductive opening has a lower etching rate for the first sidewall but a higher etching rate for the first dielectric layer and the second dielectric layer; the etching process for forming the second conductive opening has a lower etching rate for the second sidewall and the first sidewall but a higher etching rate for the main body layer and the second dielectric layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the first conductive structure and the second sidewall opening includes: forming an initial first conductive structure within the first conductive opening; etching the initial first conductive structure until the top surface of the initial first conductive structure is lower than or flush with the top surface of the first sidewall, forming the first conductive structure and an initial second sidewall opening located on the first conductive structure, the initial second sidewall opening exposing the top surface of the first conductive structure; and etching the sidewall within the initial second sidewall opening to expose the top surface of the first sidewall, forming the second sidewall opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The etching process for the sidewall within the initial second sidewall opening includes dry etching.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the second sidewall includes: forming a second sidewall membrane on the surface of the second medium layer and the inner wall surface of the second sidewall opening; forming a third medium layer on the surface of the second sidewall membrane, wherein the surface of the third medium layer is higher than the surface of the second sidewall membrane; and planarizing the third medium layer and the second sidewall membrane until the surface of the second medium layer is exposed.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the second sidewall includes: forming a second sidewall film on the surface of the second dielectric layer and the inner wall surface of the second sidewall opening; and etching the second sidewall film using an anisotropic etching process until the second dielectric layer and the surface of the first conductive structure are exposed.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The sidewall of the cover structure protrudes relative to the sidewall of the gate electrode.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, A method for forming a plurality of gate electrodes and a cover structure includes: forming a plurality of mutually discrete initial gate electrodes within a first dielectric layer; etching the initial gate electrodes to form a gate electrode and a first sidewall opening within the first dielectric layer, wherein the bottom of the first sidewall opening exposes the top surface of the gate electrode, and the width of the first sidewall opening is greater than the width of the gate electrode; and forming the cover structure within the first sidewall opening.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The covering structure further includes a protective layer located between the main body layer and the top surface of the gate electrode, the protective layer being connected to the first sidewalls on both sides of the main body layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method of forming the covering structure within the first sidewall opening includes: forming a first sidewall membrane on the inner wall surface of the first medium layer and the first sidewall opening; forming a main material layer on the surface of the first sidewall membrane, the surface of the main material layer being higher than the surface of the first sidewall membrane; and planarizing the main material layer and the first sidewall membrane until the surface of the first medium layer is exposed.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method of forming the cover structure within the first sidewall opening includes: forming a first sidewall film on the surface of the first dielectric layer and the inner wall surface of the first sidewall opening; etching the first sidewall film using an anisotropic etching process until the first sidewall film on the top surface of the gate electrode and the top surface of the first dielectric layer is removed, thereby forming a first sidewall on the sidewall surface within the first sidewall opening; and forming a main layer within the first sidewall opening after forming the first sidewall.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the first sidewall and the second sidewall, the method further includes: forming a third conductive structure within the second dielectric layer, the third conductive structure being located between adjacent second sidewalls and in contact with the top surface of the first conductive structure.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The method of forming a third conductive structure includes: forming a third conductive opening in a second dielectric layer, the third conductive opening exposing the top surface of a first conductive structure and the sidewalls of the second sidewalls on both sides of the first conductive structure; and forming the third conductive structure within the third conductive opening.

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