A semiconductor device and a manufacturing method thereof

Abstract

Embodiments of the present application provide a semiconductor device, comprising: an active region located in a semiconductor substrate, the active region comprising a central region and a peripheral region surrounding the central region; a first strain layer formed in an embedded manner in the peripheral region; wherein the first strain layer comprises at least a first sub-part, a second sub-part, a third sub-part and a fourth sub-part, the first sub-part and the third sub-part are distributed on two sides of the central region along a first direction, the second sub-part and the fourth sub-part are distributed on the other two sides of the central region along a second direction, the first direction is different from the second direction; a gate located on the active region, the gate extends along the first direction and covers at least part of the central region, at least part of the first sub-part and at least part of the third sub-part.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As the size of microelectronic devices continues to shrink, the low mobility of silicon materials has become a major factor limiting device performance.

[0003] Studies have found that incorporating a strain layer in a semiconductor substrate can improve carrier mobility. However, the carrier mobility varies depending on the location of the strain layer, making the optimal placement of the strain layer a key research area for semiconductor manufacturers. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0006] This invention provides a semiconductor device, including: an active region located in a semiconductor substrate, the active region including a central region and a peripheral region surrounding the central region;

[0007] A first strain layer is embedded in the peripheral region; wherein the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part are distributed at intervals along a first direction on both sides of the central region, and the second sub-part and the fourth sub-part are distributed at intervals along a second direction on the other two sides of the central region, the first direction being different from the second direction;

[0008] A gate is located on the active region, the gate extends along a first direction and covers at least a portion of the central region, at least a portion of the first sub-region, and at least a portion of the third sub-region.

[0009] In the above scheme, the central region is rectangular, and the central region includes a first set of parallel sides and a second set of parallel sides. The first set of parallel sides is parallel to the first direction, and the second set of parallel sides is parallel to the second direction.

[0010] In the above scheme, the first sub-part and the third sub-part are symmetrical along the center line of the first set of parallel sides, and the second sub-part and the fourth sub-part are symmetrical along the center line of the second set of parallel sides.

[0011] In the above scheme, the first sub-part, the second sub-part, the third sub-part, and the fourth sub-part of the first strain layer are connected in sequence to form a ring structure surrounding the central region.

[0012] In the above scheme, the two ends of the first sub-part are respectively connected to one end of the second sub-part and one end of the fourth sub-part, and the two ends of the third sub-part are respectively connected to the other end of the second sub-part and the other end of the fourth sub-part.

[0013] In the above scheme, the second sub-part and the fourth sub-part are symmetrically distributed on both sides of the gate.

[0014] In the above scheme, the first strain layer includes a silicon-germanium layer.

[0015] In the above scheme, the first strain layer is formed by epitaxial growth process.

[0016] In the above scheme, the semiconductor device further includes a second strain layer, which is located in the central region.

[0017] In the above scheme, the thickness of the first strain layer is greater than the thickness of the second strain layer.

[0018] In the above scheme, the thickness of the first strain layer is 5-10 times the thickness of the second strain layer.

[0019] In the above scheme, the semiconductor device includes: a first source / drain region and a second source / drain region; wherein the first source / drain region at least partially overlaps with the fourth sub-part, and the second source / drain region at least partially overlaps with the second sub-part.

[0020] In the above scheme, the semiconductor device further includes: a first source / drain extension region with a doping depth less than the first source / drain region; the first source / drain extension region is located between the channel below the gate and the first source / drain region, and the first source / drain extension region at least partially overlaps with the fourth sub-part.

[0021] In the above scheme, the semiconductor device further includes: a second source / drain extension region with a doping depth less than the second source / drain region; the second source / drain extension region is located between the channel below the gate and the second source / drain region, and the second source / drain extension region at least partially overlaps with the second sub-region.

[0022] In the above scheme, the semiconductor substrate is an n-type substrate, and the semiconductor device is a PMOS transistor.

[0023] In the above scheme, the semiconductor device includes a shallow trench isolation structure located in the semiconductor substrate to define the active region.

[0024] This invention also provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, defining an active region in the semiconductor substrate, the active region including a central region and a peripheral region surrounding the central region;

[0025] A first strain layer is formed in an embedded manner within the peripheral region; wherein the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part are distributed at intervals along a first direction on both sides of the central region, and the second sub-part and the fourth sub-part are distributed at intervals along a second direction on the other side of the central region, the first direction being different from the second direction;

[0026] A gate is formed on the active region, the gate extending along a first direction and covering at least a portion of the central region, at least a portion of the first sub-region, and at least a portion of the third sub-region.

[0027] In the above scheme, the embedding of the first strain layer in the peripheral region includes:

[0028] A first trench is formed in the peripheral region, and the first strain layer is formed in the first trench by an epitaxial growth process.

[0029] In the above scheme, the method for manufacturing the semiconductor device further includes forming a second strain layer in the central region, wherein forming the second strain layer includes:

[0030] A second trench is formed in the central region, and a second strain layer is formed in the second trench by an epitaxial growth process.

[0031] In the above scheme, the method for manufacturing the semiconductor device further includes: doping the active regions on both sides of the gate to form a first source / drain region, a first source / drain extension region, a second source / drain region, and a second source / drain extension region; wherein the first source / drain region and the first source / drain extension region at least partially overlap with the fourth sub-part, and the second source / drain region and the second source / drain extension region at least partially overlap with the second sub-part.

[0032] In the above scheme, defining the active region in the semiconductor substrate includes:

[0033] A shallow trench isolation structure is formed in the semiconductor substrate to define the active region.

[0034] The semiconductor device and its manufacturing method provided in this invention include: an active region located in a semiconductor substrate, the active region including a central region and a peripheral region surrounding the central region; a first strain layer embedded in the peripheral region; wherein the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part being spaced apart on both sides of the central region along a first direction, and the second sub-part and the fourth sub-part being spaced apart on the other side of the central region along a second direction, the first direction being different from the second direction; and a gate located on the active region, the gate extending along the first direction and covering at least a portion of the central region, at least a portion of the first sub-part, and at least a portion of the third sub-part. The first strain layer provided in this invention generates stress in two directions—a first direction and a second direction—on the channel below the gate. Compared to the prior art structure that generates stress in only one direction, the first strain layer of this invention can further improve the channel carrier mobility.

[0035] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0036] Figure 1a and Figure 1b A schematic diagram of a semiconductor device provided in the related technology;

[0037] Figures 2a-2c A schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the central region and the peripheral region provided in an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a semiconductor device having an annular first strain layer provided in an embodiment of the present invention;

[0040] Figures 5a-5b A schematic diagram of a semiconductor device with a second strain layer provided in an embodiment of the present invention;

[0041] Figure 6 A schematic diagram of a semiconductor device having a first source / drain extension region and a second source / drain extension region provided in an embodiment of the present invention;

[0042] Figure 7 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0043] Figures 8a-8eThis is a schematic diagram of the process flow for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0044] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid obscuring the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] It is known that introducing tensile stress into the channel of an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) can improve the electron mobility in the channel, while introducing compressive stress into the channel of a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) can improve the hole mobility in the channel.

[0051] Figure 1a and Figure 1b This is a schematic diagram of a semiconductor device provided in related technologies. Figure 1b for Figure 1a A cross-sectional view along the dashed line A-A'. (See figure) Figures 1a-1b As shown, the semiconductor device includes a semiconductor substrate 1, which includes an active region 11. A gate dielectric layer 16, a gate 12, and a sidewall 17 are formed above the active region 11. The active region 11 includes source / drain regions 131 and 132. The gate 12, the gate dielectric layer 16, the sidewall 17, and the source / drain regions 131 and 132 constitute a MOS transistor.

[0052] Strain portions 141 and 142 are also formed in the active region 11. The strain portions 141 and 142 are located on both sides of the gate 12 to apply stress to the channel below the gate 12 to improve the mobility of channel carriers.

[0053] However, the channel carrier mobility of the semiconductor devices provided in the aforementioned related technologies can no longer meet the needs of modern integrated circuit technology development.

[0054] Based on this, the following technical solutions for embodiments of the present invention are proposed.

[0055] This invention provides a semiconductor device, comprising: an active region located in a semiconductor substrate, the active region including a central region and a peripheral region surrounding the central region; a first strain layer formed embedded in the peripheral region; wherein the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part being spaced apart on both sides of the central region along a first direction, and the second sub-part and the fourth sub-part being spaced apart on the other side of the central region along a second direction, the first direction being different from the second direction; and a gate located on the active region, the gate extending along the first direction and covering at least a portion of the central region, at least a portion of the first sub-part, and at least a portion of the third sub-part.

[0056] The first strain layer provided in this embodiment of the invention generates stress in two directions on the channel below the gate in the first direction and the second direction, respectively. Compared with the structure that generates stress in only one direction in the aforementioned related technologies, the first strain layer in this embodiment of the invention can further improve the mobility of channel carriers.

[0057] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of the present invention, for ease of explanation, the schematic diagrams will be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of the present invention.

[0058] Figures 2a-2c This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention, wherein, Figure 2a This is a top view of a semiconductor device. Figure 2b yes Figure 2a Cross-sectional view along the dashed line A-A' Figure 2c yes Figure 2a A cross-sectional view along the dashed line B-B'. (See diagram below.) Figures 2a-2cAs shown, the semiconductor device includes an active region 21 located in a semiconductor substrate. The active region 21 includes a central region 211 and a peripheral region 212 surrounding the central region 211. A first strain layer 24 is embedded in the peripheral region 212. The first strain layer 24 includes at least a first sub-part 241, a second sub-part 242, a third sub-part 243, and a fourth sub-part 244. The first sub-part 241 and the third sub-part 243 are distributed at intervals along a first direction on both sides of the central region 211, and the second sub-part 242 and the fourth sub-part 244 are distributed at intervals along a second direction on the other two sides of the central region 211. The first direction is different from the second direction.

[0059] The semiconductor device further includes a gate 22 located on the active region 21. The gate 22 extends along a first direction and covers at least a portion of the central region 211, at least a portion of the first sub-region 241, and at least a portion of the third sub-region 243.

[0060] It is understood that the portions of the first sub-portion 241 and the third sub-portion 243 covered by the gate 22 constitute part of the channel; simultaneously, the first sub-portion 241 and the third sub-portion 243 apply stress to the channel region in a first direction. In one embodiment, the first direction is parallel to the channel width direction (B-B' direction).

[0061] The second sub-section 242 and the fourth sub-section 244 apply stress to the channel region in a second direction. In one embodiment, the second direction is parallel to the channel length direction (A-A' direction).

[0062] In some embodiments, the second sub-part 242 and the fourth sub-part 244 are symmetrically distributed on both sides of the gate 22.

[0063] The semiconductor substrate can be made of single-crystal silicon (Si), silicon-on-insulator (SOI), or other materials, such as gallium arsenide or other III-V compounds.

[0064] The semiconductor substrate also includes shallow trench isolation structures (not shown), and there may be multiple shallow trench isolation structures, which define the active region 21 in the semiconductor substrate.

[0065] A gate dielectric layer 26 is included between the gate 22 and the semiconductor substrate. The material of the gate dielectric layer 26 can be, for example, silicon oxide. However, it is not limited to this; any material that can be used as a gate dielectric layer can be applied to the embodiments of the present invention.

[0066] In some embodiments, the gate 22 includes sidewalls 27 on both sides, and the material of the sidewalls 27 can be silicon oxide or silicon nitride. However, it is not limited to this, and any material that can be used as a gate dielectric layer can be applied to the embodiments of the present invention.

[0067] In some embodiments, the central region 211 is rectangular. Figure 3 The figure shows a schematic diagram of the central region and the peripheral region provided in an embodiment of the present invention. The central region 211 includes a first set of parallel side edges 211_1 and a second set of parallel side edges 211_2. The first set of parallel side edges 211_1 is parallel to the first direction, and the second set of parallel side edges 211_2 is parallel to the second direction. It should be noted that in some other embodiments, the central region 211 may also be other shapes, such as a circle, an ellipse, or other polygons other than a rectangle.

[0068] In some specific embodiments, the first sub-part 241 and the third sub-part 243 are symmetrical about the center line of the first set of parallel sides 211_1, and the second sub-part 242 and the fourth sub-part 244 are symmetrical about the center line of the second set of parallel sides 211_2.

[0069] In some embodiments, the first sub-part 241, the second sub-part 242, the third sub-part 243, and the fourth sub-part 244 are sequentially connected to form a ring structure surrounding the central region 211, such as... Figure 4 As shown.

[0070] Specifically, the two ends of the first sub-part 241 are respectively connected to one end of the second sub-part 242, and the two ends of the third sub-part 243 are respectively connected to the other ends of the second sub-part 242 and the fourth sub-part 244. The annular first strain layer 24 can apply stress in two directions to the entire channel region, which can further optimize the performance of the semiconductor device compared to a non-annular first strain layer.

[0071] In one embodiment, the first strain layer 24 comprises a silicon-germanium layer. In this case, the stress generated by the first strain layer 24 on the channel is compressive stress, the semiconductor substrate is an n-type substrate, and the semiconductor device is a PMOS transistor. It is understood that the first strain layer 24 can also be other strain materials, such as silicon carbide.

[0072] In one embodiment, the first strain layer 24 is formed using an epitaxial growth process. However, it is not limited to this; other processes, such as doping the semiconductor substrate, can also be used to form the first strain layer 24.

[0073] In some embodiments, the semiconductor device further includes a second strain layer 29 located within the central region 211. Figures 5a-5b This is a schematic diagram of a semiconductor device with a second strain layer provided in an embodiment of the present invention, wherein, Figure 5b for Figure 5a A cross-sectional view along the dashed line A-A'. (See figure) Figures 5a-5b As shown, a second strain layer 29 is formed within the central region 211. The second strain layer 29 further enhances the mobility of channel carriers, thereby improving the performance of the semiconductor device.

[0074] In one specific embodiment, the thickness of the first strain layer 24 is greater than the thickness of the second strain layer 29. In a more specific embodiment, the thickness of the first strain layer 24 is 5-10 times, for example, 8 times, the thickness of the second strain layer 29.

[0075] In one embodiment, the second strain layer 29 and the first strain layer 24 are formed in the same process step.

[0076] In some embodiments, at least a portion of the boundary of the second strain layer 29 is connected to the boundary of the first strain layer 24. In a more specific embodiment, all boundaries of the second strain layer 29 are connected to the first strain layer 24.

[0077] In one embodiment, the material of the second strain layer 29 is the same as the material of the first strain layer 24. However, it is not limited to this, and the material of the second strain layer 29 may also be different from that of the first strain layer 24.

[0078] In one embodiment, the second strain layer 29 includes a silicon-germanium layer. In this case, the stress generated by the second strain layer 29 on the channel is compressive stress, the semiconductor substrate is an n-type substrate, and the semiconductor device is a PMOS transistor.

[0079] In one embodiment, the second strain layer 29 is formed using an epitaxial growth process. However, it is not limited to this; other processes, such as doping the semiconductor substrate, can also be used to form the second strain layer 29.

[0080] See also Figure 2b The semiconductor device further includes a first source / drain region 231 and a second source / drain region 232, which can be formed in the active region 21 by doping.

[0081] In some embodiments, the first source / drain region 231 at least partially overlaps with the fourth sub-section 244, and the second source / drain region 232 at least partially overlaps with the second sub-section 242. In a specific embodiment, the first source / drain region 231 completely overlaps with the fourth sub-section 244, and the second source / drain region 232 completely overlaps with the second sub-section 242.

[0082] In some embodiments, the semiconductor device further includes a first source / drain extension region 281 with a doping depth smaller than that of the first source / drain region 231, such as... Figure 6 As shown. The first source / drain extension region 281 is located between the channel below the gate 22 and the first source / drain region 231, and the first source / drain extension region 231 at least partially overlaps with the fourth sub-portion 244. The first source / drain extension region 281 can reduce the contact area between the first source / drain region 231 and the channel to reduce the channel leakage current.

[0083] In some embodiments, the semiconductor device further includes a second source / drain extension region 282 with a doping depth smaller than that of the second source / drain region 232, such as... Figure 6 As shown. The second source / drain extension region 282 is located between the channel below the gate 22 and the second source / drain region 232, and the second source / drain extension region 282 at least partially overlaps with the second sub-portion 242. The second source / drain extension region 282 can reduce the contact area between the second source / drain region 232 and the channel to reduce the channel leakage current.

[0084] This invention also provides a method for manufacturing a semiconductor device, such as... Figure 7 As shown, the method includes the following steps:

[0085] Step 701: Provide a semiconductor substrate, and define an active region in the semiconductor substrate, the active region including a central region and a peripheral region surrounding the central region;

[0086] Step 702: An embedded first strain layer is formed in the peripheral region; wherein the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part are distributed at intervals along a first direction on both sides of the central region, and the second sub-part and the fourth sub-part are distributed at intervals along a second direction on the other side of the central region, the first direction being different from the second direction;

[0087] Step 703: A gate is formed on the active region, the gate extending along a first direction and covering at least a portion of the central region, at least a portion of the first sub-region, and at least a portion of the third sub-region.

[0088] Below, in conjunction with Figures 8a-8e The method for manufacturing the semiconductor device according to embodiments of the present invention will be described in further detail.

[0089] First, such as Figure 8a As shown, step 701 is performed by providing a semiconductor substrate and defining an active region 21 in the semiconductor substrate. The active region 21 includes a central region 211 and a peripheral region 212 surrounding the central region 211.

[0090] In one embodiment, defining the active region 21 in the semiconductor substrate includes:

[0091] A shallow trench isolation structure (not shown) is formed in the semiconductor substrate to define the active region 21.

[0092] The semiconductor substrate can be made of single-crystal silicon (Si), silicon-on-insulator (SOI), or other materials, such as gallium arsenide or other III-V compounds.

[0093] In some embodiments, the central region 211 is rectangular. For example... Figure 8a As shown, the central region 211 includes a first set of parallel side edges 211_1 and a second set of parallel side edges 211_2. The first set of parallel side edges 211_1 is parallel to the first direction, and the second set of parallel side edges 211_2 is parallel to the second direction. It should be noted that in some other embodiments, the central region 211 may also be other shapes, such as a circle, an ellipse, or other polygons besides a rectangle.

[0094] Next, as Figure 8b As shown, step 702 is performed to form a first strain layer 24 in an embedded manner within the peripheral region 212.

[0095] In one embodiment, forming the first strain layer 24 includes:

[0096] A first trench is formed in the peripheral region 212, and the first strain layer is formed in the first trench by an epitaxial growth process.

[0097] It is understood that the first strain layer 24 can also be formed in other ways, such as by doping the semiconductor substrate.

[0098] In one embodiment, the first strain layer 24 includes at least a first sub-part 241, a second sub-part 242, a third sub-part 243, and a fourth sub-part 244. The first sub-part 241 and the third sub-part 243 are distributed at intervals along a first direction on both sides of the central region 211, and the second sub-part 242 and the fourth sub-part 244 are distributed at intervals along a second direction on the other two sides of the central region 211. The first direction is different from the second direction.

[0099] In one embodiment, the first sub-part 241 and the third sub-part 243 are symmetrical about the center line of the first set of parallel sides 211_1, and the second sub-part 242 and the fourth sub-part 244 are symmetrical about the center line of the second set of parallel sides 211_2.

[0100] In some embodiments, the first sub-part 241, the second sub-part 242, the third sub-part 243, and the fourth sub-part 244 are sequentially connected to form a ring structure surrounding the central region 211. Specifically, both ends of the first sub-part 241 are respectively connected to one end of the second sub-part 242, and both ends of the third sub-part 243 are respectively connected to the other ends of the second sub-part 242 and the fourth sub-part 244. The ring-shaped first strain layer 24 can apply stress in two directions to the entire channel region, which can further optimize the performance of the semiconductor device compared to a non-ring-shaped first strain layer.

[0101] In one embodiment, the method of manufacturing the semiconductor device further includes forming a second strain layer 29 within the central region 211, such as... Figure 8c As shown.

[0102] In one embodiment, forming the second strain layer 29 includes:

[0103] A second trench is formed in the central region, and a second strain layer is formed in the second trench by an epitaxial growth process.

[0104] It is understood that the second strain layer 29 can also be formed in other ways, for example, by doping the semiconductor substrate.

[0105] Next, as Figure 8d As shown, step 703 is performed, in which a gate 22 is formed on the active region 21, the gate 22 extending along a first direction and covering at least a portion of the central region 211, at least a portion of the first sub-region 241 and at least a portion of the third sub-region 243.

[0106] In one embodiment, the gate 22 also covers at least a portion of the second strain layer 29.

[0107] After forming the gate 22, the method for manufacturing the semiconductor device further includes doping the active regions 21 on both sides of the gate 22 to form a first source / drain region 231, a first source / drain extension region 281, a second source / drain region 232, and a second source / drain extension region 282, as shown below. Figure 8e As shown.

[0108] In one embodiment, the first source / drain region 231 and the first source / drain extension region 28 at least partially overlap with the fourth sub-part 244, and the second source / drain region 232 and the second source / drain extension region 282 at least partially overlap with the second sub-part 242.

[0109] In one embodiment, the method for manufacturing the semiconductor device further includes the step of forming sidewalls 27 on both sides of the gate 22, such as... Figure 8e As shown.

[0110] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: An active region is located in a semiconductor substrate, and the active region includes a central region and a peripheral region surrounding the central region; A first strain layer is embedded in the peripheral region; wherein the first strain layer includes a silicon-germanium layer, and the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part are distributed at intervals along a first direction on both sides of the central region, and the second sub-part and the fourth sub-part are distributed at intervals along a second direction on the other side of the central region, the first direction being different from the second direction; A gate is located on the active region, the gate extends along a first direction and covers at least a portion of the central region, at least a portion of the first sub-region and at least a portion of the third sub-region; A first source / drain region and a second source / drain region, wherein the first source / drain region at least partially overlaps with the fourth sub-part, and the second source / drain region at least partially overlaps with the second sub-part; The first source / drain extension region is located between the channel below the gate and the first source / drain region, and the first source / drain extension region at least partially overlaps with the fourth sub-part. The second source / drain extension region is located between the channel below the gate and the second source / drain region, and the second source / drain extension region at least partially overlaps with the second sub-section.

2. The semiconductor device according to claim 1, characterized in that, The central region is rectangular and includes a first set of parallel sides and a second set of parallel sides. The first set of parallel sides is parallel to the first direction, and the second set of parallel sides is parallel to the second direction.

3. The semiconductor device according to claim 2, characterized in that, The first sub-part and the third sub-part are symmetrical about the center line of the first set of parallel sides, and the second sub-part and the fourth sub-part are symmetrical about the center line of the second set of parallel sides.

4. The semiconductor device according to claim 1, characterized in that, The first sub-section, the second sub-section, the third sub-section, and the fourth sub-section of the first strain layer are connected in sequence to form a ring structure surrounding the central region.

5. The semiconductor device according to claim 4, characterized in that, The two ends of the first sub-part are respectively connected to one end of the second sub-part and one end of the fourth sub-part, and the two ends of the third sub-part are respectively connected to the other end of the second sub-part and the other end of the fourth sub-part.

6. The semiconductor device according to claim 1, characterized in that, The second sub-part and the fourth sub-part are symmetrically distributed on both sides of the gate.

7. The semiconductor device according to claim 1, characterized in that, The first strain layer is formed using an epitaxial growth process.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second strain layer located in the central region.

9. The semiconductor device according to claim 8, characterized in that, The thickness of the first strain layer is greater than the thickness of the second strain layer.

10. The semiconductor device according to claim 9, characterized in that, The thickness of the first strain layer is 5-10 times the thickness of the second strain layer.

11. The semiconductor device according to claim 1, characterized in that, The doping depth of the first source / drain extension region is less than the doping depth of the first source / drain region.

12. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a doping depth of the second source / drain extension region that is less than the doping depth of the second source / drain region.

13. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate is an n-type substrate, and the semiconductor device is a PMOS transistor.

14. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a shallow trench isolation structure located in the semiconductor substrate to define the active region.

15. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, in which an active region is defined, the active region including a central region and a peripheral region surrounding the central region; A first strain layer is formed in an embedded manner within the peripheral region; wherein the first strain layer includes a silicon-germanium layer, and the first strain layer includes at least a first sub-part, a second sub-part, a third sub-part, and a fourth sub-part, the first sub-part and the third sub-part are distributed at intervals along a first direction on both sides of the central region, and the second sub-part and the fourth sub-part are distributed at intervals along a second direction on the other side of the central region, the first direction being different from the second direction; A gate is formed on the active region, the gate extending along a first direction and covering at least a portion of the central region, at least a portion of the first sub-region, and at least a portion of the third sub-region; The active regions on both sides of the gate are doped to form a first source / drain region, a first source / drain extension region, a second source / drain region, and a second source / drain extension region; wherein the first source / drain extension region is located between the channel below the gate and the first source / drain region, the second source / drain extension region is located between the channel below the gate and the second source / drain region, the first source / drain region and the first source / drain extension region at least partially overlap with the fourth sub-part, and the second source / drain region and the second source / drain extension region at least partially overlap with the second sub-part.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The formation of the first strain layer embedded in the peripheral region includes: A first trench is formed in the peripheral region, and the first strain layer is formed in the first trench by an epitaxial growth process.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method for manufacturing the semiconductor device further includes forming a second strain layer in the central region, wherein forming the second strain layer includes: A second trench is formed in the central region, and a second strain layer is formed in the second trench by an epitaxial growth process.

18. The method for manufacturing a semiconductor device according to claim 15, characterized in that, Defining an active region in the semiconductor substrate includes: A shallow trench isolation structure is formed in the semiconductor substrate to define the active region.

Images